2 * driver for ENE KB3926 B/C/D/E/F CIR (pnp id: ENE0XXX)
4 * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * Sami R. <maesesami@gmail.com> for lot of help in debugging and therefore
23 * bringing to life support for transmission & learning mode.
25 * Charlie Andrews <charliethepilot@googlemail.com> for lots of help in
26 * bringing up the support of new firmware buffer that is popular
29 * ENE for partial device documentation
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pnp.h>
37 #include <linux/interrupt.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/input.h>
41 #include <media/ir-core.h>
42 #include <media/ir-common.h>
45 static int sample_period;
46 static bool learning_mode_force;
50 static void ene_set_reg_addr(struct ene_device *dev, u16 reg)
52 outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
53 outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
56 /* read a hardware register */
57 static u8 ene_read_reg(struct ene_device *dev, u16 reg)
60 ene_set_reg_addr(dev, reg);
61 retval = inb(dev->hw_io + ENE_IO);
62 dbg_regs("reg %04x == %02x", reg, retval);
66 /* write a hardware register */
67 static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value)
69 dbg_regs("reg %04x <- %02x", reg, value);
70 ene_set_reg_addr(dev, reg);
71 outb(value, dev->hw_io + ENE_IO);
74 /* Set bits in hardware register */
75 static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
77 dbg_regs("reg %04x |= %02x", reg, mask);
78 ene_set_reg_addr(dev, reg);
79 outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO);
82 /* Clear bits in hardware register */
83 static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
85 dbg_regs("reg %04x &= ~%02x ", reg, mask);
86 ene_set_reg_addr(dev, reg);
87 outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO);
90 /* A helper to set/clear a bit in register according to boolean variable */
91 static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask,
95 ene_set_reg_mask(dev, reg, mask);
97 ene_clear_reg_mask(dev, reg, mask);
100 /* detect hardware features */
101 static int ene_hw_detect(struct ene_device *dev)
103 u8 chip_major, chip_minor;
104 u8 hw_revision, old_ver;
107 ene_clear_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
108 chip_major = ene_read_reg(dev, ENE_ECVER_MAJOR);
109 chip_minor = ene_read_reg(dev, ENE_ECVER_MINOR);
110 ene_set_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
112 hw_revision = ene_read_reg(dev, ENE_ECHV);
113 old_ver = ene_read_reg(dev, ENE_HW_VER_OLD);
115 dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) +
116 (ene_read_reg(dev, ENE_PLLFRL) >> 4);
118 if (sample_period != ENE_DEFAULT_SAMPLE_PERIOD)
119 dev->rx_period_adjust =
120 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 2 : 4;
122 if (hw_revision == 0xFF) {
123 ene_warn("device seems to be disabled");
124 ene_warn("send a mail to lirc-list@lists.sourceforge.net");
125 ene_warn("please attach output of acpidump and dmidecode");
129 ene_notice("chip is 0x%02x%02x - kbver = 0x%02x, rev = 0x%02x",
130 chip_major, chip_minor, old_ver, hw_revision);
132 ene_notice("PLL freq = %d", dev->pll_freq);
134 if (chip_major == 0x33) {
135 ene_warn("chips 0x33xx aren't supported");
139 if (chip_major == 0x39 && chip_minor == 0x26 && hw_revision == 0xC0) {
140 dev->hw_revision = ENE_HW_C;
141 ene_notice("KB3926C detected");
142 } else if (old_ver == 0x24 && hw_revision == 0xC0) {
143 dev->hw_revision = ENE_HW_B;
144 ene_notice("KB3926B detected");
146 dev->hw_revision = ENE_HW_D;
147 ene_notice("KB3926D or higher detected");
150 /* detect features hardware supports */
151 if (dev->hw_revision < ENE_HW_C)
154 fw_reg1 = ene_read_reg(dev, ENE_FW1);
155 fw_reg2 = ene_read_reg(dev, ENE_FW2);
157 ene_notice("Firmware regs: %02x %02x", fw_reg1, fw_reg2);
159 dev->hw_use_gpio_0a = !!(fw_reg2 & ENE_FW2_GP0A);
160 dev->hw_learning_and_tx_capable = !!(fw_reg2 & ENE_FW2_LEARNING);
161 dev->hw_extra_buffer = !!(fw_reg1 & ENE_FW1_HAS_EXTRA_BUF);
163 if (dev->hw_learning_and_tx_capable)
164 dev->hw_fan_input = !!(fw_reg2 & ENE_FW2_FAN_INPUT);
166 ene_notice("Hardware features:");
168 if (dev->hw_learning_and_tx_capable) {
169 ene_notice("* Supports transmitting & learning mode");
170 ene_notice(" This feature is rare and therefore,");
171 ene_notice(" you are welcome to test it,");
172 ene_notice(" and/or contact the author via:");
173 ene_notice(" lirc-list@lists.sourceforge.net");
174 ene_notice(" or maximlevitsky@gmail.com");
176 ene_notice("* Uses GPIO %s for IR raw input",
177 dev->hw_use_gpio_0a ? "40" : "0A");
179 if (dev->hw_fan_input)
180 ene_notice("* Uses unused fan feedback input as source"
181 " of demodulated IR data");
184 if (!dev->hw_fan_input)
185 ene_notice("* Uses GPIO %s for IR demodulated input",
186 dev->hw_use_gpio_0a ? "0A" : "40");
188 if (dev->hw_extra_buffer)
189 ene_notice("* Uses new style input buffer");
193 /* Read properities of hw sample buffer */
194 static void ene_rx_setup_hw_buffer(struct ene_device *dev)
198 ene_rx_read_hw_pointer(dev);
199 dev->r_pointer = dev->w_pointer;
201 if (!dev->hw_extra_buffer) {
202 dev->buffer_len = ENE_FW_PACKET_SIZE * 2;
206 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER);
207 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER+1) << 8;
208 dev->extra_buf1_address = tmp;
210 dev->extra_buf1_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 2);
212 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 3);
213 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 4) << 8;
214 dev->extra_buf2_address = tmp;
216 dev->extra_buf2_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 5);
218 dev->buffer_len = dev->extra_buf1_len + dev->extra_buf2_len + 8;
220 ene_notice("Hardware uses 2 extended buffers:");
221 ene_notice(" 0x%04x - len : %d", dev->extra_buf1_address,
222 dev->extra_buf1_len);
223 ene_notice(" 0x%04x - len : %d", dev->extra_buf2_address,
224 dev->extra_buf2_len);
226 ene_notice("Total buffer len = %d", dev->buffer_len);
228 if (dev->buffer_len > 64 || dev->buffer_len < 16)
231 if (dev->extra_buf1_address > 0xFBFC ||
232 dev->extra_buf1_address < 0xEC00)
235 if (dev->extra_buf2_address > 0xFBFC ||
236 dev->extra_buf2_address < 0xEC00)
239 if (dev->r_pointer > dev->buffer_len)
242 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
245 ene_warn("Error validating extra buffers, device probably won't work");
246 dev->hw_extra_buffer = false;
247 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
251 /* Restore the pointers to extra buffers - to make module reload work*/
252 static void ene_rx_restore_hw_buffer(struct ene_device *dev)
254 if (!dev->hw_extra_buffer)
257 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0,
258 dev->extra_buf1_address & 0xFF);
259 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1,
260 dev->extra_buf1_address >> 8);
261 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len);
263 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3,
264 dev->extra_buf2_address & 0xFF);
265 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4,
266 dev->extra_buf2_address >> 8);
267 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5,
268 dev->extra_buf2_len);
269 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
272 /* Read hardware write pointer */
273 static void ene_rx_read_hw_pointer(struct ene_device *dev)
275 if (dev->hw_extra_buffer)
276 dev->w_pointer = ene_read_reg(dev, ENE_FW_RX_POINTER);
278 dev->w_pointer = ene_read_reg(dev, ENE_FW2)
279 & ENE_FW2_BUF_WPTR ? 0 : ENE_FW_PACKET_SIZE;
281 dbg_verbose("RB: HW write pointer: %02x, driver read pointer: %02x",
282 dev->w_pointer, dev->r_pointer);
285 /* Gets address of next sample from HW ring buffer */
286 static int ene_rx_get_sample_reg(struct ene_device *dev)
290 if (dev->r_pointer == dev->w_pointer) {
291 dbg_verbose("RB: hit end, try update w_pointer");
292 ene_rx_read_hw_pointer(dev);
295 if (dev->r_pointer == dev->w_pointer) {
296 dbg_verbose("RB: end of data at %d", dev->r_pointer);
300 dbg_verbose("RB: reading at offset %d", dev->r_pointer);
301 r_pointer = dev->r_pointer;
304 if (dev->r_pointer == dev->buffer_len)
307 dbg_verbose("RB: next read will be from offset %d", dev->r_pointer);
310 dbg_verbose("RB: read at main buffer at %d", r_pointer);
311 return ENE_FW_SAMPLE_BUFFER + r_pointer;
316 if (r_pointer < dev->extra_buf1_len) {
317 dbg_verbose("RB: read at 1st extra buffer at %d", r_pointer);
318 return dev->extra_buf1_address + r_pointer;
321 r_pointer -= dev->extra_buf1_len;
323 if (r_pointer < dev->extra_buf2_len) {
324 dbg_verbose("RB: read at 2nd extra buffer at %d", r_pointer);
325 return dev->extra_buf2_address + r_pointer;
328 dbg("attempt to read beyong ring bufer end");
332 /* Sense current received carrier */
333 void ene_rx_sense_carrier(struct ene_device *dev)
335 DEFINE_IR_RAW_EVENT(ev);
337 int carrier, duty_cycle;
338 int period = ene_read_reg(dev, ENE_CIRCAR_PRD);
339 int hperiod = ene_read_reg(dev, ENE_CIRCAR_HPRD);
341 if (!(period & ENE_CIRCAR_PRD_VALID))
344 period &= ~ENE_CIRCAR_PRD_VALID;
349 dbg("RX: hardware carrier period = %02x", period);
350 dbg("RX: hardware carrier pulse period = %02x", hperiod);
352 carrier = 2000000 / period;
353 duty_cycle = (hperiod * 100) / period;
354 dbg("RX: sensed carrier = %d Hz, duty cycle %d%%",
355 carrier, duty_cycle);
356 if (dev->carrier_detect_enabled) {
357 ev.carrier_report = true;
358 ev.carrier = carrier;
359 ev.duty_cycle = duty_cycle;
360 ir_raw_event_store(dev->idev, &ev);
364 /* this enables/disables the CIR RX engine */
365 static void ene_rx_enable_cir_engine(struct ene_device *dev, bool enable)
367 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
368 ENE_CIRCFG_RX_EN | ENE_CIRCFG_RX_IRQ, enable);
371 /* this selects input for CIR engine. Ether GPIO 0A or GPIO40*/
372 static void ene_rx_select_input(struct ene_device *dev, bool gpio_0a)
374 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_GPIO0A, gpio_0a);
378 * this enables alternative input via fan tachometer sensor and bypasses
381 static void ene_rx_enable_fan_input(struct ene_device *dev, bool enable)
383 if (!dev->hw_fan_input)
387 ene_write_reg(dev, ENE_FAN_AS_IN1, 0);
389 ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
390 ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
394 /* setup the receiver for RX*/
395 static void ene_rx_setup(struct ene_device *dev)
397 bool learning_mode = dev->learning_mode_enabled ||
398 dev->carrier_detect_enabled;
399 int sample_period_adjust = 0;
401 dbg("RX: setup receiver, learning mode = %d", learning_mode);
404 /* This selects RLC input and clears CFG2 settings */
405 ene_write_reg(dev, ENE_CIRCFG2, 0x00);
407 /* set sample period*/
408 if (sample_period == ENE_DEFAULT_SAMPLE_PERIOD)
409 sample_period_adjust =
410 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 1 : 2;
412 ene_write_reg(dev, ENE_CIRRLC_CFG,
413 (sample_period + sample_period_adjust) |
414 ENE_CIRRLC_CFG_OVERFLOW);
415 /* revB doesn't support inputs */
416 if (dev->hw_revision < ENE_HW_C)
421 WARN_ON(!dev->hw_learning_and_tx_capable);
423 /* Enable the opposite of the normal input
424 That means that if GPIO40 is normally used, use GPIO0A
426 This input will carry non demodulated
427 signal, and we will tell the hw to demodulate it itself */
428 ene_rx_select_input(dev, !dev->hw_use_gpio_0a);
429 dev->rx_fan_input_inuse = false;
431 /* Enable carrier demodulation */
432 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
434 /* Enable carrier detection */
435 ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63);
436 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT,
437 dev->carrier_detect_enabled || debug);
439 if (dev->hw_fan_input)
440 dev->rx_fan_input_inuse = true;
442 ene_rx_select_input(dev, dev->hw_use_gpio_0a);
444 /* Disable carrier detection & demodulation */
445 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
446 ene_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT);
450 if (dev->rx_fan_input_inuse) {
451 dev->props->rx_resolution = MS_TO_NS(ENE_FW_SAMPLE_PERIOD_FAN);
453 /* Fan input doesn't support timeouts, it just ends the
454 input with a maximum sample */
455 dev->props->min_timeout = dev->props->max_timeout =
456 MS_TO_NS(ENE_FW_SMPL_BUF_FAN_MSK *
457 ENE_FW_SAMPLE_PERIOD_FAN);
459 dev->props->rx_resolution = MS_TO_NS(sample_period);
461 /* Theoreticly timeout is unlimited, but we cap it
462 * because it was seen that on one device, it
463 * would stop sending spaces after around 250 msec.
464 * Besides, this is close to 2^32 anyway and timeout is u32.
466 dev->props->min_timeout = MS_TO_NS(127 * sample_period);
467 dev->props->max_timeout = MS_TO_NS(200000);
470 if (dev->hw_learning_and_tx_capable)
471 dev->props->tx_resolution = MS_TO_NS(sample_period);
473 if (dev->props->timeout > dev->props->max_timeout)
474 dev->props->timeout = dev->props->max_timeout;
475 if (dev->props->timeout < dev->props->min_timeout)
476 dev->props->timeout = dev->props->min_timeout;
479 /* Enable the device for receive */
480 static void ene_rx_enable(struct ene_device *dev)
484 /* Enable system interrupt */
485 if (dev->hw_revision < ENE_HW_C) {
486 ene_write_reg(dev, ENEB_IRQ, dev->irq << 1);
487 ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01);
489 reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0;
490 reg_value |= ENE_IRQ_UNK_EN;
491 reg_value &= ~ENE_IRQ_STATUS;
492 reg_value |= (dev->irq & ENE_IRQ_MASK);
493 ene_write_reg(dev, ENE_IRQ, reg_value);
497 ene_rx_enable_fan_input(dev, dev->rx_fan_input_inuse);
498 ene_rx_enable_cir_engine(dev, !dev->rx_fan_input_inuse);
500 /* ack any pending irqs - just in case */
503 /* enable firmware bits */
504 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
506 /* enter idle mode */
507 ir_raw_event_set_idle(dev->idev, true);
508 dev->rx_enabled = true;
511 /* Disable the device receiver */
512 static void ene_rx_disable(struct ene_device *dev)
515 ene_rx_enable_cir_engine(dev, false);
516 ene_rx_enable_fan_input(dev, false);
518 /* disable hardware IRQ and firmware flag */
519 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
521 ir_raw_event_set_idle(dev->idev, true);
522 dev->rx_enabled = false;
525 /* This resets the receiver. Usefull to stop stream of spaces at end of
528 static void ene_rx_reset(struct ene_device *dev)
530 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
531 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
534 /* Set up the TX carrier frequency and duty cycle */
535 static void ene_tx_set_carrier(struct ene_device *dev)
540 spin_lock_irqsave(&dev->hw_lock, flags);
542 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
543 ENE_CIRCFG_TX_CARR, dev->tx_period > 0);
548 BUG_ON(dev->tx_duty_cycle >= 100 || dev->tx_duty_cycle <= 0);
550 tx_puls_width = dev->tx_period / (100 / dev->tx_duty_cycle);
555 dbg("TX: pulse distance = %d * 500 ns", dev->tx_period);
556 dbg("TX: pulse width = %d * 500 ns", tx_puls_width);
558 ene_write_reg(dev, ENE_CIRMOD_PRD, dev->tx_period | ENE_CIRMOD_PRD_POL);
559 ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width);
561 spin_unlock_irqrestore(&dev->hw_lock, flags);
564 /* Enable/disable transmitters */
565 static void ene_tx_set_transmitters(struct ene_device *dev)
569 spin_lock_irqsave(&dev->hw_lock, flags);
570 ene_set_clear_reg_mask(dev, ENE_GPIOFS8, ENE_GPIOFS8_GPIO41,
571 !!(dev->transmitter_mask & 0x01));
572 ene_set_clear_reg_mask(dev, ENE_GPIOFS1, ENE_GPIOFS1_GPIO0D,
573 !!(dev->transmitter_mask & 0x02));
574 spin_unlock_irqrestore(&dev->hw_lock, flags);
577 /* prepare transmission */
578 static void ene_tx_enable(struct ene_device *dev)
580 u8 conf1 = ene_read_reg(dev, ENE_CIRCFG);
581 u8 fwreg2 = ene_read_reg(dev, ENE_FW2);
583 dev->saved_conf1 = conf1;
585 /* Show information about currently connected transmitter jacks */
586 if (fwreg2 & ENE_FW2_EMMITER1_CONN)
587 dbg("TX: Transmitter #1 is connected");
589 if (fwreg2 & ENE_FW2_EMMITER2_CONN)
590 dbg("TX: Transmitter #2 is connected");
592 if (!(fwreg2 & (ENE_FW2_EMMITER1_CONN | ENE_FW2_EMMITER2_CONN)))
593 ene_warn("TX: transmitter cable isn't connected!");
595 /* disable receive on revc */
596 if (dev->hw_revision == ENE_HW_C)
597 conf1 &= ~ENE_CIRCFG_RX_EN;
599 /* Enable TX engine */
600 conf1 |= ENE_CIRCFG_TX_EN | ENE_CIRCFG_TX_IRQ;
601 ene_write_reg(dev, ENE_CIRCFG, conf1);
604 /* end transmission */
605 static void ene_tx_disable(struct ene_device *dev)
607 ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1);
608 dev->tx_buffer = NULL;
612 /* TX one sample - must be called with dev->hw_lock*/
613 static void ene_tx_sample(struct ene_device *dev)
617 bool pulse = dev->tx_sample_pulse;
619 if (!dev->tx_buffer) {
620 ene_warn("TX: BUG: attempt to transmit NULL buffer");
624 /* Grab next TX sample */
625 if (!dev->tx_sample) {
627 if (dev->tx_pos == dev->tx_len) {
629 dbg("TX: no more data to send");
633 dbg("TX: last sample sent by hardware");
635 complete(&dev->tx_complete);
640 sample = dev->tx_buffer[dev->tx_pos++];
641 dev->tx_sample_pulse = !dev->tx_sample_pulse;
643 dev->tx_sample = DIV_ROUND_CLOSEST(sample, sample_period);
649 raw_tx = min(dev->tx_sample , (unsigned int)ENE_CIRRLC_OUT_MASK);
650 dev->tx_sample -= raw_tx;
652 dbg("TX: sample %8d (%s)", raw_tx * sample_period,
653 pulse ? "pulse" : "space");
655 raw_tx |= ENE_CIRRLC_OUT_PULSE;
658 dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx);
660 dev->tx_reg = !dev->tx_reg;
662 /* simulate TX done interrupt */
664 mod_timer(&dev->tx_sim_timer, jiffies + HZ / 500);
667 /* timer to simulate tx done interrupt */
668 static void ene_tx_irqsim(unsigned long data)
670 struct ene_device *dev = (struct ene_device *)data;
673 spin_lock_irqsave(&dev->hw_lock, flags);
675 spin_unlock_irqrestore(&dev->hw_lock, flags);
679 /* read irq status and ack it */
680 static int ene_irq_status(struct ene_device *dev)
683 u8 fw_flags1, fw_flags2;
686 fw_flags2 = ene_read_reg(dev, ENE_FW2);
688 if (dev->hw_revision < ENE_HW_C) {
689 irq_status = ene_read_reg(dev, ENEB_IRQ_STATUS);
691 if (!(irq_status & ENEB_IRQ_STATUS_IR))
694 ene_clear_reg_mask(dev, ENEB_IRQ_STATUS, ENEB_IRQ_STATUS_IR);
698 irq_status = ene_read_reg(dev, ENE_IRQ);
699 if (!(irq_status & ENE_IRQ_STATUS))
702 /* original driver does that twice - a workaround ? */
703 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
704 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
706 /* check RX interrupt */
707 if (fw_flags2 & ENE_FW2_RXIRQ) {
708 retval |= ENE_IRQ_RX;
709 ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ);
712 /* check TX interrupt */
713 fw_flags1 = ene_read_reg(dev, ENE_FW1);
714 if (fw_flags1 & ENE_FW1_TXIRQ) {
715 ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);
716 retval |= ENE_IRQ_TX;
722 /* interrupt handler */
723 static irqreturn_t ene_isr(int irq, void *data)
726 int hw_sample, irq_status;
729 irqreturn_t retval = IRQ_NONE;
730 struct ene_device *dev = (struct ene_device *)data;
731 DEFINE_IR_RAW_EVENT(ev);
733 spin_lock_irqsave(&dev->hw_lock, flags);
735 dbg_verbose("ISR called");
736 ene_rx_read_hw_pointer(dev);
737 irq_status = ene_irq_status(dev);
742 retval = IRQ_HANDLED;
744 if (irq_status & ENE_IRQ_TX) {
745 dbg_verbose("TX interrupt");
746 if (!dev->hw_learning_and_tx_capable) {
747 dbg("TX interrupt on unsupported device!");
753 if (!(irq_status & ENE_IRQ_RX))
756 dbg_verbose("RX interrupt");
758 if (dev->hw_learning_and_tx_capable)
759 ene_rx_sense_carrier(dev);
761 /* On hardware that don't support extra buffer we need to trust
762 the interrupt and not track the read pointer */
763 if (!dev->hw_extra_buffer)
764 dev->r_pointer = dev->w_pointer == 0 ? ENE_FW_PACKET_SIZE : 0;
768 reg = ene_rx_get_sample_reg(dev);
770 dbg_verbose("next sample to read at: %04x", reg);
774 hw_value = ene_read_reg(dev, reg);
776 if (dev->rx_fan_input_inuse) {
778 int offset = ENE_FW_SMPL_BUF_FAN - ENE_FW_SAMPLE_BUFFER;
780 /* read high part of the sample */
781 hw_value |= ene_read_reg(dev, reg + offset) << 8;
782 pulse = hw_value & ENE_FW_SMPL_BUF_FAN_PLS;
784 /* clear space bit, and other unused bits */
785 hw_value &= ENE_FW_SMPL_BUF_FAN_MSK;
786 hw_sample = hw_value * ENE_FW_SAMPLE_PERIOD_FAN;
789 pulse = !(hw_value & ENE_FW_SAMPLE_SPACE);
790 hw_value &= ~ENE_FW_SAMPLE_SPACE;
791 hw_sample = hw_value * sample_period;
793 if (dev->rx_period_adjust) {
795 hw_sample /= (100 + dev->rx_period_adjust);
799 if (!dev->hw_extra_buffer && !hw_sample) {
800 dev->r_pointer = dev->w_pointer;
804 dbg("RX: %d (%s)", hw_sample, pulse ? "pulse" : "space");
806 ev.duration = MS_TO_NS(hw_sample);
808 ir_raw_event_store_with_filter(dev->idev, &ev);
811 ir_raw_event_handle(dev->idev);
813 spin_unlock_irqrestore(&dev->hw_lock, flags);
817 /* Initialize default settings */
818 static void ene_setup_default_settings(struct ene_device *dev)
821 dev->tx_duty_cycle = 50; /*%*/
822 dev->transmitter_mask = 0x03;
823 dev->learning_mode_enabled = learning_mode_force;
825 /* Set reasonable default timeout */
826 dev->props->timeout = MS_TO_NS(150000);
829 /* Upload all hardware settings at once. Used at load and resume time */
830 static void ene_setup_hw_settings(struct ene_device *dev)
832 if (dev->hw_learning_and_tx_capable) {
833 ene_tx_set_carrier(dev);
834 ene_tx_set_transmitters(dev);
840 /* outside interface: called on first open*/
841 static int ene_open(void *data)
843 struct ene_device *dev = (struct ene_device *)data;
846 spin_lock_irqsave(&dev->hw_lock, flags);
848 spin_unlock_irqrestore(&dev->hw_lock, flags);
852 /* outside interface: called on device close*/
853 static void ene_close(void *data)
855 struct ene_device *dev = (struct ene_device *)data;
857 spin_lock_irqsave(&dev->hw_lock, flags);
860 spin_unlock_irqrestore(&dev->hw_lock, flags);
863 /* outside interface: set transmitter mask */
864 static int ene_set_tx_mask(void *data, u32 tx_mask)
866 struct ene_device *dev = (struct ene_device *)data;
867 dbg("TX: attempt to set transmitter mask %02x", tx_mask);
870 if (!tx_mask || tx_mask & ~0x03) {
871 dbg("TX: invalid mask");
872 /* return count of transmitters */
876 dev->transmitter_mask = tx_mask;
877 ene_tx_set_transmitters(dev);
881 /* outside interface : set tx carrier */
882 static int ene_set_tx_carrier(void *data, u32 carrier)
884 struct ene_device *dev = (struct ene_device *)data;
885 u32 period = 2000000 / carrier;
887 dbg("TX: attempt to set tx carrier to %d kHz", carrier);
889 if (period && (period > ENE_CIRMOD_PRD_MAX ||
890 period < ENE_CIRMOD_PRD_MIN)) {
892 dbg("TX: out of range %d-%d kHz carrier",
893 2000 / ENE_CIRMOD_PRD_MIN, 2000 / ENE_CIRMOD_PRD_MAX);
897 dev->tx_period = period;
898 ene_tx_set_carrier(dev);
902 /*outside interface : set tx duty cycle */
903 static int ene_set_tx_duty_cycle(void *data, u32 duty_cycle)
905 struct ene_device *dev = (struct ene_device *)data;
906 dbg("TX: setting duty cycle to %d%%", duty_cycle);
907 dev->tx_duty_cycle = duty_cycle;
908 ene_tx_set_carrier(dev);
912 /* outside interface: enable learning mode */
913 static int ene_set_learning_mode(void *data, int enable)
915 struct ene_device *dev = (struct ene_device *)data;
917 if (enable == dev->learning_mode_enabled)
920 spin_lock_irqsave(&dev->hw_lock, flags);
921 dev->learning_mode_enabled = enable;
925 spin_unlock_irqrestore(&dev->hw_lock, flags);
929 static int ene_set_carrier_report(void *data, int enable)
931 struct ene_device *dev = (struct ene_device *)data;
934 if (enable == dev->carrier_detect_enabled)
937 spin_lock_irqsave(&dev->hw_lock, flags);
938 dev->carrier_detect_enabled = enable;
942 spin_unlock_irqrestore(&dev->hw_lock, flags);
946 /* outside interface: enable or disable idle mode */
947 static void ene_set_idle(void *data, bool idle)
950 ene_rx_reset((struct ene_device *)data);
951 dbg("RX: end of data");
955 /* outside interface: transmit */
956 static int ene_transmit(void *data, int *buf, u32 n)
958 struct ene_device *dev = (struct ene_device *)data;
961 dev->tx_buffer = buf;
962 dev->tx_len = n / sizeof(int);
967 dev->tx_sample_pulse = 0;
969 dbg("TX: %d samples", dev->tx_len);
971 spin_lock_irqsave(&dev->hw_lock, flags);
975 /* Transmit first two samples */
979 spin_unlock_irqrestore(&dev->hw_lock, flags);
981 if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) {
983 spin_lock_irqsave(&dev->hw_lock, flags);
985 spin_unlock_irqrestore(&dev->hw_lock, flags);
992 static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id)
995 struct ir_dev_props *ir_props;
996 struct input_dev *input_dev;
997 struct ene_device *dev;
999 /* allocate memory */
1000 input_dev = input_allocate_device();
1001 ir_props = kzalloc(sizeof(struct ir_dev_props), GFP_KERNEL);
1002 dev = kzalloc(sizeof(struct ene_device), GFP_KERNEL);
1004 if (!input_dev || !ir_props || !dev)
1007 /* validate resources */
1010 if (!pnp_port_valid(pnp_dev, 0) ||
1011 pnp_port_len(pnp_dev, 0) < ENE_IO_SIZE)
1014 if (!pnp_irq_valid(pnp_dev, 0))
1017 spin_lock_init(&dev->hw_lock);
1019 /* claim the resources */
1021 dev->hw_io = pnp_port_start(pnp_dev, 0);
1022 if (!request_region(dev->hw_io, ENE_IO_SIZE, ENE_DRIVER_NAME)) {
1028 dev->irq = pnp_irq(pnp_dev, 0);
1029 if (request_irq(dev->irq, ene_isr,
1030 IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) {
1035 pnp_set_drvdata(pnp_dev, dev);
1036 dev->pnp_dev = pnp_dev;
1038 /* don't allow too short/long sample periods */
1039 if (sample_period < 5 || sample_period > 0x7F)
1040 sample_period = ENE_DEFAULT_SAMPLE_PERIOD;
1042 /* detect hardware version and features */
1043 error = ene_hw_detect(dev);
1047 if (!dev->hw_learning_and_tx_capable && txsim) {
1048 dev->hw_learning_and_tx_capable = true;
1049 setup_timer(&dev->tx_sim_timer, ene_tx_irqsim,
1050 (long unsigned int)dev);
1051 ene_warn("Simulation of TX activated");
1054 if (!dev->hw_learning_and_tx_capable)
1055 learning_mode_force = false;
1057 ir_props->driver_type = RC_DRIVER_IR_RAW;
1058 ir_props->allowed_protos = IR_TYPE_ALL;
1059 ir_props->priv = dev;
1060 ir_props->open = ene_open;
1061 ir_props->close = ene_close;
1062 ir_props->s_idle = ene_set_idle;
1064 dev->props = ir_props;
1065 dev->idev = input_dev;
1067 if (dev->hw_learning_and_tx_capable) {
1068 ir_props->s_learning_mode = ene_set_learning_mode;
1069 init_completion(&dev->tx_complete);
1070 ir_props->tx_ir = ene_transmit;
1071 ir_props->s_tx_mask = ene_set_tx_mask;
1072 ir_props->s_tx_carrier = ene_set_tx_carrier;
1073 ir_props->s_tx_duty_cycle = ene_set_tx_duty_cycle;
1074 ir_props->s_carrier_report = ene_set_carrier_report;
1077 ene_rx_setup_hw_buffer(dev);
1078 ene_setup_default_settings(dev);
1079 ene_setup_hw_settings(dev);
1081 device_set_wakeup_capable(&pnp_dev->dev, true);
1082 device_set_wakeup_enable(&pnp_dev->dev, true);
1084 if (dev->hw_learning_and_tx_capable)
1085 input_dev->name = "ENE eHome Infrared Remote Transceiver";
1087 input_dev->name = "ENE eHome Infrared Remote Receiver";
1090 if (ir_input_register(input_dev, RC_MAP_RC6_MCE, ir_props,
1094 ene_notice("driver has been succesfully loaded");
1097 if (dev && dev->irq >= 0)
1098 free_irq(dev->irq, dev);
1099 if (dev && dev->hw_io >= 0)
1100 release_region(dev->hw_io, ENE_IO_SIZE);
1102 input_free_device(input_dev);
1108 /* main unload function */
1109 static void ene_remove(struct pnp_dev *pnp_dev)
1111 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1112 unsigned long flags;
1114 spin_lock_irqsave(&dev->hw_lock, flags);
1115 ene_rx_disable(dev);
1116 ene_rx_restore_hw_buffer(dev);
1117 spin_unlock_irqrestore(&dev->hw_lock, flags);
1119 free_irq(dev->irq, dev);
1120 release_region(dev->hw_io, ENE_IO_SIZE);
1121 ir_input_unregister(dev->idev);
1126 /* enable wake on IR (wakes on specific button on original remote) */
1127 static void ene_enable_wake(struct ene_device *dev, int enable)
1129 enable = enable && device_may_wakeup(&dev->pnp_dev->dev);
1130 dbg("wake on IR %s", enable ? "enabled" : "disabled");
1131 ene_set_clear_reg_mask(dev, ENE_FW1, ENE_FW1_WAKE, enable);
1135 static int ene_suspend(struct pnp_dev *pnp_dev, pm_message_t state)
1137 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1138 ene_enable_wake(dev, true);
1140 /* TODO: add support for wake pattern */
1144 static int ene_resume(struct pnp_dev *pnp_dev)
1146 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1147 ene_setup_hw_settings(dev);
1149 if (dev->rx_enabled)
1152 ene_enable_wake(dev, false);
1157 static void ene_shutdown(struct pnp_dev *pnp_dev)
1159 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1160 ene_enable_wake(dev, true);
1163 static const struct pnp_device_id ene_ids[] = {
1171 static struct pnp_driver ene_driver = {
1172 .name = ENE_DRIVER_NAME,
1173 .id_table = ene_ids,
1174 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1177 .remove = __devexit_p(ene_remove),
1179 .suspend = ene_suspend,
1180 .resume = ene_resume,
1182 .shutdown = ene_shutdown,
1185 static int __init ene_init(void)
1187 return pnp_register_driver(&ene_driver);
1190 static void ene_exit(void)
1192 pnp_unregister_driver(&ene_driver);
1195 module_param(sample_period, int, S_IRUGO);
1196 MODULE_PARM_DESC(sample_period, "Hardware sample period (50 us default)");
1198 module_param(learning_mode_force, bool, S_IRUGO);
1199 MODULE_PARM_DESC(learning_mode_force, "Enable learning mode by default");
1201 module_param(debug, int, S_IRUGO | S_IWUSR);
1202 MODULE_PARM_DESC(debug, "Debug level");
1204 module_param(txsim, bool, S_IRUGO);
1205 MODULE_PARM_DESC(txsim,
1206 "Simulate TX features on unsupported hardware (dangerous)");
1208 MODULE_DEVICE_TABLE(pnp, ene_ids);
1210 ("Infrared input driver for KB3926B/C/D/E/F "
1211 "(aka ENE0100/ENE0200/ENE0201/ENE0202) CIR port");
1213 MODULE_AUTHOR("Maxim Levitsky");
1214 MODULE_LICENSE("GPL");
1216 module_init(ene_init);
1217 module_exit(ene_exit);