2 * irq.h: in kernel interrupt controller related definitions
3 * Copyright (c) 2007, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
25 #include <linux/mm_types.h>
26 #include <linux/hrtimer.h>
34 typedef void irq_request_func(void *opaque, int level);
36 struct kvm_kpic_state {
37 u8 last_irr; /* edge detection */
38 u8 irr; /* interrupt request register */
39 u8 imr; /* interrupt mask register */
40 u8 isr; /* interrupt service register */
41 u8 priority_add; /* highest irq priority */
48 u8 rotate_on_auto_eoi;
49 u8 special_fully_nested_mode;
50 u8 init4; /* true if 4 byte init */
51 u8 elcr; /* PIIX edge/trigger selection */
53 struct kvm_pic *pics_state;
57 struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */
58 irq_request_func *irq_request;
59 void *irq_request_opaque;
60 int output; /* intr from master PIC */
61 struct kvm_io_device dev;
64 struct kvm_pic *kvm_create_pic(struct kvm *kvm);
65 void kvm_pic_set_irq(void *opaque, int irq, int level);
66 int kvm_pic_read_irq(struct kvm_pic *s);
67 void kvm_pic_update_irq(struct kvm_pic *s);
69 #define IOAPIC_NUM_PINS KVM_IOAPIC_NUM_PINS
70 #define IOAPIC_VERSION_ID 0x11 /* IOAPIC version */
71 #define IOAPIC_EDGE_TRIG 0
72 #define IOAPIC_LEVEL_TRIG 1
74 #define IOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000
75 #define IOAPIC_MEM_LENGTH 0x100
77 /* Direct registers. */
78 #define IOAPIC_REG_SELECT 0x00
79 #define IOAPIC_REG_WINDOW 0x10
80 #define IOAPIC_REG_EOI 0x40 /* IA64 IOSAPIC only */
82 /* Indirect registers. */
83 #define IOAPIC_REG_APIC_ID 0x00 /* x86 IOAPIC only */
84 #define IOAPIC_REG_VERSION 0x01
85 #define IOAPIC_REG_ARB_ID 0x02 /* x86 IOAPIC only */
87 /*ioapic delivery mode*/
88 #define IOAPIC_FIXED 0x0
89 #define IOAPIC_LOWEST_PRIORITY 0x1
90 #define IOAPIC_PMI 0x2
91 #define IOAPIC_NMI 0x4
92 #define IOAPIC_INIT 0x5
93 #define IOAPIC_EXTINT 0x7
101 union ioapic_redir_entry {
107 u8 delivery_status:1;
116 } redirtbl[IOAPIC_NUM_PINS];
117 struct kvm_io_device dev;
122 unsigned long base_address;
123 struct kvm_io_device dev;
126 s64 period; /* unit: ns */
131 struct kvm_vcpu *vcpu;
132 struct page *regs_page;
140 printk(KERN_EMERG "assertion failed %s: %d: %s\n", \
141 __FILE__, __LINE__, #x); \
146 #define ASSERT(x) do { } while (0)
149 static inline struct kvm_pic *pic_irqchip(struct kvm *kvm)
151 return kvm->arch.vpic;
154 static inline struct kvm_ioapic *ioapic_irqchip(struct kvm *kvm)
156 return kvm->arch.vioapic;
159 static inline int irqchip_in_kernel(struct kvm *kvm)
161 return pic_irqchip(kvm) != NULL;
164 void kvm_vcpu_kick(struct kvm_vcpu *vcpu);
165 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
166 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
167 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
168 int kvm_create_lapic(struct kvm_vcpu *vcpu);
169 void kvm_lapic_reset(struct kvm_vcpu *vcpu);
170 void kvm_pic_reset(struct kvm_kpic_state *s);
171 void kvm_ioapic_reset(struct kvm_ioapic *ioapic);
172 void kvm_free_lapic(struct kvm_vcpu *vcpu);
173 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
174 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
175 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
177 struct kvm_vcpu *kvm_get_lowest_prio_vcpu(struct kvm *kvm, u8 vector,
178 unsigned long bitmap);
179 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
180 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
181 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
182 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector);
183 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
184 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, u8 vec, u8 trig);
185 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu);
186 int kvm_ioapic_init(struct kvm *kvm);
187 void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level);
188 int kvm_lapic_enabled(struct kvm_vcpu *vcpu);
189 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
190 void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec);
191 void kvm_timer_intr_post(struct kvm_vcpu *vcpu, int vec);
192 void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu);
193 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu);
194 void kvm_migrate_apic_timer(struct kvm_vcpu *vcpu);