2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/pci.h>
35 #include <linux/netdevice.h>
36 #include <linux/vmalloc.h>
38 #include "ipath_kernel.h"
39 #include "ipath_common.h"
42 * min buffers we want to have per port, after driver
44 #define IPATH_MIN_USER_PORT_BUFCNT 8
47 * Number of ports we are configured to use (to allow for more pio
48 * buffers per port, etc.) Zero means use chip value.
50 static ushort ipath_cfgports;
52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
56 * Number of buffers reserved for driver (verbs and layered drivers.)
57 * Reserved at end of buffer list. Initialized based on
58 * number of PIO buffers if not set via module interface.
59 * The problem with this is that it's global, but we'll use different
60 * numbers for different chip types. So the default value is not
61 * very useful. I've redefined it for the 1.3 release so that it's
62 * zero unless set by the user to something else, in which case we
65 static ushort ipath_kpiobufs;
67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
70 &ipath_kpiobufs, S_IWUSR | S_IRUGO);
71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
74 * create_port0_egr - allocate the eager TID buffers
75 * @dd: the infinipath device
77 * This code is now quite different for user and kernel, because
78 * the kernel uses skb's, for the accelerated network performance.
79 * This is the kernel (port0) version.
81 * Allocate the eager TID buffers and program them into infinipath.
82 * We use the network layer alloc_skb() allocator to allocate the
83 * memory, and either use the buffers as is for things like verbs
84 * packets, or pass the buffers up to the ipath layered driver and
85 * thence the network layer, replacing them as we do so (see
88 static int create_port0_egr(struct ipath_devdata *dd)
91 struct ipath_skbinfo *skbinfo;
94 egrcnt = dd->ipath_rcvegrcnt;
96 skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
97 if (skbinfo == NULL) {
98 ipath_dev_err(dd, "allocation error for eager TID "
103 for (e = 0; e < egrcnt; e++) {
105 * This is a bit tricky in that we allocate extra
106 * space for 2 bytes of the 14 byte ethernet header.
107 * These two bytes are passed in the ipath header so
108 * the rest of the data is word aligned. We allocate
109 * 4 bytes so that the data buffer stays word aligned.
110 * See ipath_kreceive() for more details.
112 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
113 if (!skbinfo[e].skb) {
114 ipath_dev_err(dd, "SKB allocation error for "
115 "eager TID %u\n", e);
117 dev_kfree_skb(skbinfo[--e].skb);
124 * After loop above, so we can test non-NULL to see if ready
125 * to use at receive, etc.
127 dd->ipath_port0_skbinfo = skbinfo;
129 for (e = 0; e < egrcnt; e++) {
130 dd->ipath_port0_skbinfo[e].phys =
131 ipath_map_single(dd->pcidev,
132 dd->ipath_port0_skbinfo[e].skb->data,
133 dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
134 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
135 ((char __iomem *) dd->ipath_kregbase +
136 dd->ipath_rcvegrbase),
137 RCVHQ_RCV_TYPE_EAGER,
138 dd->ipath_port0_skbinfo[e].phys);
147 static int bringup_link(struct ipath_devdata *dd)
152 /* hold IBC in reset */
153 dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
154 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
158 * Note that prior to try 14 or 15 of IB, the credit scaling
159 * wasn't working, because it was swapped for writes with the
160 * 1 bit default linkstate field
163 /* ignore pbc and align word */
164 val = dd->ipath_piosize2k - 2 * sizeof(u32);
166 * for ICRC, which we only send in diag test pkt mode, and we
167 * don't need to worry about that for mtu
171 * Set the IBC maxpktlength to the size of our pio buffers the
172 * maxpktlength is in words. This is *not* the IB data MTU.
174 ibc = (val / sizeof(u32)) << INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
176 ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
178 * How often flowctrl sent. More or less in usecs; balance against
179 * watermark value, so that in theory senders always get a flow
180 * control update in time to not let the IB link go idle.
182 ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
183 /* max error tolerance */
184 ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
185 /* use "real" buffer space for */
186 ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
187 /* IB credit flow control. */
188 ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
189 /* initially come up waiting for TS1, without sending anything. */
190 dd->ipath_ibcctrl = ibc;
192 * Want to start out with both LINKCMD and LINKINITCMD in NOP
193 * (0 and 0). Don't put linkinitcmd in ipath_ibcctrl, want that
196 ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
197 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
198 ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
199 (unsigned long long) ibc);
200 ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
202 // be sure chip saw it
203 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
205 ret = dd->ipath_f_bringup_serdes(dd);
208 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
212 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
213 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
220 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
222 struct ipath_portdata *pd = NULL;
224 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
228 /* The port 0 pkey table is used by the layer interface. */
229 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
234 static int init_chip_first(struct ipath_devdata *dd,
235 struct ipath_portdata **pdp)
237 struct ipath_portdata *pd = NULL;
242 * skip cfgports stuff because we are not allocating memory,
243 * and we don't want problems if the portcnt changed due to
244 * cfgports. We do still check and report a difference, if
245 * not same (should be impossible).
248 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
250 dd->ipath_cfgports = dd->ipath_portcnt;
251 else if (ipath_cfgports <= dd->ipath_portcnt) {
252 dd->ipath_cfgports = ipath_cfgports;
253 ipath_dbg("Configured to use %u ports out of %u in chip\n",
254 dd->ipath_cfgports, dd->ipath_portcnt);
256 dd->ipath_cfgports = dd->ipath_portcnt;
257 ipath_dbg("Tried to configured to use %u ports; chip "
258 "only supports %u\n", ipath_cfgports,
262 * Allocate full portcnt array, rather than just cfgports, because
263 * cleanup iterates across all possible ports.
265 dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
269 ipath_dev_err(dd, "Unable to allocate portdata array, "
275 dd->ipath_lastegrheads = kzalloc(sizeof(*dd->ipath_lastegrheads)
276 * dd->ipath_cfgports,
278 dd->ipath_lastrcvhdrqtails =
279 kzalloc(sizeof(*dd->ipath_lastrcvhdrqtails)
280 * dd->ipath_cfgports, GFP_KERNEL);
282 if (!dd->ipath_lastegrheads || !dd->ipath_lastrcvhdrqtails) {
283 ipath_dev_err(dd, "Unable to allocate head arrays, "
289 pd = create_portdata0(dd);
292 ipath_dev_err(dd, "Unable to allocate portdata for port "
297 dd->ipath_pd[0] = pd;
299 dd->ipath_rcvtidcnt =
300 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
301 dd->ipath_rcvtidbase =
302 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
303 dd->ipath_rcvegrcnt =
304 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
305 dd->ipath_rcvegrbase =
306 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
308 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
309 dd->ipath_piobufbase =
310 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
311 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
312 dd->ipath_piosize2k = val & ~0U;
313 dd->ipath_piosize4k = val >> 32;
315 * Note: the chips support a maximum MTU of 4096, but the driver
316 * hasn't implemented this feature yet, so set the initial value
319 dd->ipath_ibmtu = 2048;
320 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
321 dd->ipath_piobcnt2k = val & ~0U;
322 dd->ipath_piobcnt4k = val >> 32;
323 dd->ipath_pio2kbase =
324 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
325 (dd->ipath_piobufbase & 0xffffffff));
326 if (dd->ipath_piobcnt4k) {
327 dd->ipath_pio4kbase = (u32 __iomem *)
328 (((char __iomem *) dd->ipath_kregbase) +
329 (dd->ipath_piobufbase >> 32));
331 * 4K buffers take 2 pages; we use roundup just to be
332 * paranoid; we calculate it once here, rather than on
335 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
337 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
339 dd->ipath_piobcnt2k, dd->ipath_piosize2k,
340 dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
341 dd->ipath_piosize4k, dd->ipath_pio4kbase,
344 else ipath_dbg("%u 2k piobufs @ %p\n",
345 dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
347 spin_lock_init(&dd->ipath_tid_lock);
348 spin_lock_init(&dd->ipath_sendctrl_lock);
349 spin_lock_init(&dd->ipath_gpio_lock);
350 spin_lock_init(&dd->ipath_eep_st_lock);
351 mutex_init(&dd->ipath_eep_lock);
359 * init_chip_reset - re-initialize after a reset, or enable
360 * @dd: the infinipath device
361 * @pdp: output for port data
363 * sanity check at least some of the values after reset, and
364 * ensure no receive or transmit (explictly, in case reset
367 static int init_chip_reset(struct ipath_devdata *dd,
368 struct ipath_portdata **pdp)
372 *pdp = dd->ipath_pd[0];
373 /* ensure chip does no sends or receives while we re-initialize */
374 dd->ipath_control = dd->ipath_sendctrl = dd->ipath_rcvctrl = 0U;
375 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl, dd->ipath_rcvctrl);
376 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
377 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, dd->ipath_control);
379 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
380 if (dd->ipath_portcnt != rtmp)
381 dev_info(&dd->pcidev->dev, "portcnt was %u before "
382 "reset, now %u, using original\n",
383 dd->ipath_portcnt, rtmp);
384 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
385 if (rtmp != dd->ipath_rcvtidcnt)
386 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
387 "reset, now %u, using original\n",
388 dd->ipath_rcvtidcnt, rtmp);
389 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
390 if (rtmp != dd->ipath_rcvtidbase)
391 dev_info(&dd->pcidev->dev, "tidbase was %u before "
392 "reset, now %u, using original\n",
393 dd->ipath_rcvtidbase, rtmp);
394 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
395 if (rtmp != dd->ipath_rcvegrcnt)
396 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
397 "reset, now %u, using original\n",
398 dd->ipath_rcvegrcnt, rtmp);
399 rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
400 if (rtmp != dd->ipath_rcvegrbase)
401 dev_info(&dd->pcidev->dev, "egrbase was %u before "
402 "reset, now %u, using original\n",
403 dd->ipath_rcvegrbase, rtmp);
408 static int init_pioavailregs(struct ipath_devdata *dd)
412 dd->ipath_pioavailregs_dma = dma_alloc_coherent(
413 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
415 if (!dd->ipath_pioavailregs_dma) {
416 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
423 * we really want L2 cache aligned, but for current CPUs of
424 * interest, they are the same.
426 dd->ipath_statusp = (u64 *)
427 ((char *)dd->ipath_pioavailregs_dma +
428 ((2 * L1_CACHE_BYTES +
429 dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
430 /* copy the current value now that it's really allocated */
431 *dd->ipath_statusp = dd->_ipath_status;
433 * setup buffer to hold freeze msg, accessible to apps,
436 dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
438 dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
447 * init_shadow_tids - allocate the shadow TID array
448 * @dd: the infinipath device
450 * allocate the shadow TID array, so we can ipath_munlock previous
451 * entries. It may make more sense to move the pageshadow to the
452 * port data structure, so we only allocate memory for ports actually
453 * in use, since we at 8k per port, now.
455 static void init_shadow_tids(struct ipath_devdata *dd)
460 pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
461 sizeof(struct page *));
463 ipath_dev_err(dd, "failed to allocate shadow page * "
464 "array, no expected sends!\n");
465 dd->ipath_pageshadow = NULL;
469 addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
472 ipath_dev_err(dd, "failed to allocate shadow dma handle "
473 "array, no expected sends!\n");
474 vfree(dd->ipath_pageshadow);
475 dd->ipath_pageshadow = NULL;
479 memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt *
480 sizeof(struct page *));
482 dd->ipath_pageshadow = pages;
483 dd->ipath_physshadow = addrs;
486 static void enable_chip(struct ipath_devdata *dd,
487 struct ipath_portdata *pd, int reinit)
494 init_waitqueue_head(&ipath_state_wait);
496 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
499 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
500 /* Enable PIO send, and update of PIOavail regs to memory. */
501 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
502 INFINIPATH_S_PIOBUFAVAILUPD;
503 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
504 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
505 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
508 * enable port 0 receive, and receive interrupt. other ports
509 * done as user opens and inits them.
511 dd->ipath_rcvctrl = (1ULL << dd->ipath_r_tailupd_shift) |
512 (1ULL << dd->ipath_r_portenable_shift) |
513 (1ULL << dd->ipath_r_intravail_shift);
514 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
518 * now ready for use. this should be cleared whenever we
519 * detect a reset, or initiate one.
521 dd->ipath_flags |= IPATH_INITTED;
524 * init our shadow copies of head from tail values, and write
525 * head values to match.
527 val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
528 (void)ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
530 /* Initialize so we interrupt on next packet received */
531 (void)ipath_write_ureg(dd, ur_rcvhdrhead,
532 dd->ipath_rhdrhead_intr_off |
533 dd->ipath_pd[0]->port_head, 0);
536 * by now pioavail updates to memory should have occurred, so
537 * copy them into our working/shadow registers; this is in
538 * case something went wrong with abort, but mostly to get the
539 * initial values of the generation bit correct.
541 for (i = 0; i < dd->ipath_pioavregs; i++) {
545 * Chip Errata bug 6641; even and odd qwords>3 are swapped.
549 val = dd->ipath_pioavailregs_dma[i - 1];
551 val = dd->ipath_pioavailregs_dma[i + 1];
554 val = dd->ipath_pioavailregs_dma[i];
555 dd->ipath_pioavailshadow[i] = le64_to_cpu(val);
557 /* can get counters, stats, etc. */
558 dd->ipath_flags |= IPATH_PRESENT;
561 static int init_housekeeping(struct ipath_devdata *dd,
562 struct ipath_portdata **pdp, int reinit)
568 * have to clear shadow copies of registers at init that are
569 * not otherwise set here, or all kinds of bizarre things
570 * happen with driver on chip reset
572 dd->ipath_rcvhdrsize = 0;
575 * Don't clear ipath_flags as 8bit mode was set before
576 * entering this func. However, we do set the linkstate to
577 * unknown, so we can watch for a transition.
578 * PRESENT is set because we want register reads to work,
579 * and the kernel infrastructure saw it in config space;
580 * We clear it if we have failures.
582 dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
583 dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
584 IPATH_LINKDOWN | IPATH_LINKINIT);
586 ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
588 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
591 * set up fundamental info we need to use the chip; we assume
592 * if the revision reg and these regs are OK, we don't need to
593 * special case the rest
596 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
598 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
600 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
601 ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
602 "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
603 dd->ipath_uregbase, dd->ipath_cregbase);
604 if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
605 || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
606 || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
607 || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
608 ipath_dev_err(dd, "Register read failures from chip, "
609 "giving up initialization\n");
610 dd->ipath_flags &= ~IPATH_PRESENT;
616 /* clear diagctrl register, in case diags were running and crashed */
617 ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
619 /* clear the initial reset flag, in case first driver load */
620 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
624 ret = init_chip_reset(dd, pdp);
626 ret = init_chip_first(dd, pdp);
631 ipath_cdbg(VERBOSE, "Revision %llx (PCI %x), %u ports, %u tids, "
632 "%u egrtids\n", (unsigned long long) dd->ipath_revision,
633 dd->ipath_pcirev, dd->ipath_portcnt, dd->ipath_rcvtidcnt,
634 dd->ipath_rcvegrcnt);
636 if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
637 INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
638 ipath_dev_err(dd, "Driver only handles version %d, "
639 "chip swversion is %d (%llx), failng\n",
640 IPATH_CHIP_SWVERSION,
641 (int)(dd->ipath_revision >>
642 INFINIPATH_R_SOFTWARE_SHIFT) &
643 INFINIPATH_R_SOFTWARE_MASK,
644 (unsigned long long) dd->ipath_revision);
648 dd->ipath_majrev = (u8) ((dd->ipath_revision >>
649 INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
650 INFINIPATH_R_CHIPREVMAJOR_MASK);
651 dd->ipath_minrev = (u8) ((dd->ipath_revision >>
652 INFINIPATH_R_CHIPREVMINOR_SHIFT) &
653 INFINIPATH_R_CHIPREVMINOR_MASK);
654 dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
655 INFINIPATH_R_BOARDID_SHIFT) &
656 INFINIPATH_R_BOARDID_MASK);
658 ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
660 snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
661 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
663 IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
664 (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
665 INFINIPATH_R_ARCH_MASK,
666 dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
667 (unsigned)(dd->ipath_revision >>
668 INFINIPATH_R_SOFTWARE_SHIFT) &
669 INFINIPATH_R_SOFTWARE_MASK);
671 ipath_dbg("%s", dd->ipath_boardversion);
679 * ipath_init_chip - do the actual initialization sequence on the chip
680 * @dd: the infinipath device
681 * @reinit: reinitializing, so don't allocate new memory
683 * Do the actual initialization sequence on the chip. This is done
684 * both from the init routine called from the PCI infrastructure, and
685 * when we reset the chip, or detect that it was reset internally,
686 * or it's administratively re-enabled.
688 * Memory allocation here and in called routines is only done in
689 * the first case (reinit == 0). We have to be careful, because even
690 * without memory allocation, we need to re-write all the chip registers
691 * TIDs, etc. after the reset or enable has completed.
693 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
699 struct ipath_portdata *pd = NULL; /* keep gcc4 happy */
700 gfp_t gfp_flags = GFP_USER | __GFP_COMP;
703 ret = init_housekeeping(dd, &pd, reinit);
708 * we ignore most issues after reporting them, but have to specially
709 * handle hardware-disabled chips.
712 /* unique error, known to ipath_init_one */
718 * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
719 * but then it no longer nicely fits power of two, and since
720 * we now use routines that backend onto __get_free_pages, the
721 * rest would be wasted.
723 dd->ipath_rcvhdrcnt = dd->ipath_rcvegrcnt;
724 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
725 dd->ipath_rcvhdrcnt);
728 * Set up the shadow copies of the piobufavail registers,
729 * which we compare against the chip registers for now, and
730 * the in memory DMA'ed copies of the registers. This has to
731 * be done early, before we calculate lastport, etc.
733 piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
735 * calc number of pioavail registers, and save it; we have 2
738 dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
739 / (sizeof(u64) * BITS_PER_BYTE / 2);
740 uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
741 if (ipath_kpiobufs == 0) {
742 /* not set by user (this is default) */
749 kpiobufs = ipath_kpiobufs;
751 if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) {
752 int i = (int) piobufs -
753 (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
756 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
757 "%d for kernel leaves too few for %d user ports "
758 "(%d each); using %u\n", kpiobufs,
759 piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
761 * shouldn't change ipath_kpiobufs, because could be
762 * different for different devices...
766 dd->ipath_lastport_piobuf = piobufs - kpiobufs;
767 dd->ipath_pbufsport =
768 uports ? dd->ipath_lastport_piobuf / uports : 0;
769 val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports);
771 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
772 "add to kernel\n", dd->ipath_pbufsport, val32);
773 dd->ipath_lastport_piobuf -= val32;
774 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
775 dd->ipath_pbufsport, val32);
777 dd->ipath_lastpioindex = dd->ipath_lastport_piobuf;
778 ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
779 "each for %u user ports\n", kpiobufs,
780 piobufs, dd->ipath_pbufsport, uports);
782 dd->ipath_f_early_init(dd);
784 * cancel any possible active sends from early driver load.
785 * Follows early_init because some chips have to initialize
786 * PIO buffers in early_init to avoid false parity errors.
788 ipath_cancel_sends(dd, 0);
790 /* early_init sets rcvhdrentsize and rcvhdrsize, so this must be
791 * done after early_init */
793 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
794 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
795 dd->ipath_rcvhdrentsize);
796 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
797 dd->ipath_rcvhdrsize);
800 ret = init_pioavailregs(dd);
801 init_shadow_tids(dd);
806 (void)ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
807 dd->ipath_pioavailregs_phys);
809 * this is to detect s/w errors, which the h/w works around by
810 * ignoring the low 6 bits of address, if it wasn't aligned.
812 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
813 if (val != dd->ipath_pioavailregs_phys) {
814 ipath_dev_err(dd, "Catastrophic software error, "
815 "SendPIOAvailAddr written as %lx, "
816 "read back as %llx\n",
817 (unsigned long) dd->ipath_pioavailregs_phys,
818 (unsigned long long) val);
823 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
826 * make sure we are not in freeze, and PIO send enabled, so
827 * writes to pbc happen
829 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
830 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
831 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
832 ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
834 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
835 dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE;
836 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
837 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
838 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
841 * before error clears, since we expect serdes pll errors during
842 * this, the first time after reset
844 if (bringup_link(dd)) {
845 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
851 * clear any "expected" hwerrs from reset and/or initialization
852 * clear any that aren't enabled (at least this once), and then
853 * set the enable mask
855 dd->ipath_f_init_hwerrors(dd);
856 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
857 ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
858 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
859 dd->ipath_hwerrmask);
862 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
863 /* enable errors that are masked, at least this first time. */
864 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
865 ~dd->ipath_maskederrs);
866 dd->ipath_errormask = ipath_read_kreg64(dd,
867 dd->ipath_kregs->kr_errormask);
868 /* clear any interrupts up to this point (ints still not enabled) */
869 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
872 * Set up the port 0 (kernel) rcvhdr q and egr TIDs. If doing
873 * re-init, the simplest way to handle this is to free
874 * existing, and re-allocate.
875 * Need to re-create rest of port 0 portdata as well.
878 /* Alloc and init new ipath_portdata for port0,
879 * Then free old pd. Could lead to fragmentation, but also
880 * makes later support for hot-swap easier.
882 struct ipath_portdata *npd;
883 npd = create_portdata0(dd);
885 ipath_free_pddata(dd, pd);
886 dd->ipath_pd[0] = pd = npd;
888 ipath_dev_err(dd, "Unable to allocate portdata for"
889 " port 0, failing\n");
894 dd->ipath_f_tidtemplate(dd);
895 ret = ipath_create_rcvhdrq(dd, pd);
897 dd->ipath_hdrqtailptr =
898 (volatile __le64 *)pd->port_rcvhdrtail_kvaddr;
899 ret = create_port0_egr(dd);
902 ipath_dev_err(dd, "failed to allocate port 0 (kernel) "
903 "rcvhdrq and/or egr bufs\n");
905 enable_chip(dd, pd, reinit);
908 if (!ret && !reinit) {
909 /* used when we close a port, for DMA already in flight at close */
910 dd->ipath_dummy_hdrq = dma_alloc_coherent(
911 &dd->pcidev->dev, pd->port_rcvhdrq_size,
912 &dd->ipath_dummy_hdrq_phys,
914 if (!dd->ipath_dummy_hdrq ) {
915 dev_info(&dd->pcidev->dev,
916 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
917 pd->port_rcvhdrq_size);
918 /* fallback to just 0'ing */
919 dd->ipath_dummy_hdrq_phys = 0UL;
924 * cause retrigger of pending interrupts ignored during init,
925 * even if we had errors
927 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
929 if(!dd->ipath_stats_timer_active) {
931 * first init, or after an admin disable/enable
932 * set up stats retrieval timer, even if we had errors
933 * in last portion of setup
935 init_timer(&dd->ipath_stats_timer);
936 dd->ipath_stats_timer.function = ipath_get_faststats;
937 dd->ipath_stats_timer.data = (unsigned long) dd;
938 /* every 5 seconds; */
939 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
940 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
941 add_timer(&dd->ipath_stats_timer);
942 dd->ipath_stats_timer_active = 1;
947 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
948 if (!dd->ipath_f_intrsetup(dd)) {
949 /* now we can enable all interrupts from the chip */
950 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
952 /* force re-interrupt of any pending interrupts. */
953 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
955 /* chip is usable; mark it as initialized */
956 *dd->ipath_statusp |= IPATH_STATUS_INITTED;
958 ipath_dev_err(dd, "No interrupts enabled, couldn't "
959 "setup interrupt address\n");
961 if (dd->ipath_cfgports > ipath_stats.sps_nports)
963 * sps_nports is a global, so, we set it to
964 * the highest number of ports of any of the
965 * chips we find; we never decrement it, at
966 * least for now. Since this might have changed
967 * over disable/enable or prior to reset, always
968 * do the check and potentially adjust.
970 ipath_stats.sps_nports = dd->ipath_cfgports;
972 ipath_dbg("Failed (%d) to initialize chip\n", ret);
974 /* if ret is non-zero, we probably should do some cleanup
979 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
981 struct ipath_devdata *dd;
986 ret = ipath_parse_ushort(str, &val);
988 spin_lock_irqsave(&ipath_devs_lock, flags);
998 list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
999 if (dd->ipath_kregbase)
1001 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
1002 (dd->ipath_cfgports *
1003 IPATH_MIN_USER_PORT_BUFCNT)))
1007 "Allocating %d PIO bufs for kernel leaves "
1008 "too few for %d user ports (%d each)\n",
1009 val, dd->ipath_cfgports - 1,
1010 IPATH_MIN_USER_PORT_BUFCNT);
1014 dd->ipath_lastport_piobuf =
1015 dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
1018 ipath_kpiobufs = val;
1021 spin_unlock_irqrestore(&ipath_devs_lock, flags);