2 * linux/drivers/ide/pci/serverworks.c Version 0.22 Jun 27 2007
4 * Copyright (C) 1998-2000 Michel Aubry
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * Portions copyright (c) 2001 Sun Microsystems
11 * RCC/ServerWorks IDE driver for Linux
13 * OSB4: `Open South Bridge' IDE Interface (fn 1)
14 * supports UDMA mode 2 (33 MB/s)
16 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
17 * all revisions support UDMA mode 4 (66 MB/s)
18 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
20 * *** The CSB5 does not provide ANY register ***
21 * *** to detect 80-conductor cable presence. ***
23 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
25 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
26 * controller same as the CSB6. Single channel ATA100 only.
29 * Available under NDA only. Errata info very hard to get.
33 #include <linux/types.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/ioport.h>
37 #include <linux/pci.h>
38 #include <linux/hdreg.h>
39 #include <linux/ide.h>
40 #include <linux/init.h>
41 #include <linux/delay.h>
45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
46 #define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
49 * can overrun their FIFOs when used with the CSB5 */
50 static const char *svwks_bad_ata100[] = {
58 static struct pci_dev *isa_dev;
60 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
63 if (!strcmp(*list++, drive->id->model))
68 static u8 svwks_udma_filter(ide_drive_t *drive)
70 struct pci_dev *dev = HWIF(drive)->pci_dev;
73 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
75 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
78 pci_read_config_dword(isa_dev, 0x64, ®);
81 * Don't enable UDMA on disk devices for the moment
83 if(drive->media == ide_disk)
85 /* Check the OSB4 DMA33 enable bit */
86 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
87 } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
89 } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
91 pci_read_config_byte(dev, 0x5A, &btr);
94 /* If someone decides to do UDMA133 on CSB5 the same
95 issue will bite so be inclusive */
96 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
100 case 2: mask = 0x1f; break;
101 case 1: mask = 0x07; break;
102 default: mask = 0x00; break;
105 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
106 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
107 (!(PCI_FUNC(dev->devfn) & 1)))
113 static u8 svwks_csb_check (struct pci_dev *dev)
115 switch (dev->device) {
116 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
117 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
118 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
119 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
127 static void svwks_tune_pio(ide_drive_t *drive, const u8 pio)
129 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
130 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
132 struct pci_dev *dev = drive->hwif->pci_dev;
134 pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
136 if (svwks_csb_check(dev)) {
139 pci_read_config_word(dev, 0x4a, &csb_pio);
141 csb_pio &= ~(0x0f << (4 * drive->dn));
142 csb_pio |= (pio << (4 * drive->dn));
144 pci_write_config_word(dev, 0x4a, csb_pio);
148 static int svwks_tune_chipset(ide_drive_t *drive, const u8 speed)
150 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
151 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
152 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
154 ide_hwif_t *hwif = HWIF(drive);
155 struct pci_dev *dev = hwif->pci_dev;
156 u8 unit = (drive->select.b.unit & 0x01);
158 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
160 if (speed >= XFER_PIO_0 && speed <= XFER_PIO_4) {
161 svwks_tune_pio(drive, speed - XFER_PIO_0);
162 return ide_config_drive_speed(drive, speed);
165 /* If we are about to put a disk into UDMA mode we screwed up.
166 Our code assumes we never _ever_ do this on an OSB4 */
168 if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
169 drive->media == ide_disk && speed >= XFER_UDMA_0)
172 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
173 pci_read_config_byte(dev, 0x54, &ultra_enable);
175 ultra_timing &= ~(0x0F << (4*unit));
176 ultra_enable &= ~(0x01 << drive->dn);
182 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
191 dma_timing |= dma_modes[2];
192 ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
193 ultra_enable |= (0x01 << drive->dn);
198 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
199 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
200 pci_write_config_byte(dev, 0x54, ultra_enable);
202 return (ide_config_drive_speed(drive, speed));
205 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
207 pio = ide_get_best_pio_mode(drive, pio, 4);
208 svwks_tune_pio(drive, pio);
209 (void)ide_config_drive_speed(drive, XFER_PIO_0 + pio);
212 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
214 drive->init_speed = 0;
216 if (ide_tune_dma(drive))
219 if (ide_use_fast_pio(drive))
220 svwks_tune_drive(drive, 255);
225 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
230 /* force Master Latency Timer value to 64 PCICLKs */
231 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
233 /* OSB4 : South Bridge and IDE */
234 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
235 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
236 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
238 pci_read_config_dword(isa_dev, 0x64, ®);
239 reg &= ~0x00002000; /* disable 600ns interrupt mask */
240 if(!(reg & 0x00004000))
241 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
242 reg |= 0x00004000; /* enable UDMA/33 support */
243 pci_write_config_dword(isa_dev, 0x64, reg);
247 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
248 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
249 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
250 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
252 /* Third Channel Test */
253 if (!(PCI_FUNC(dev->devfn) & 1)) {
254 struct pci_dev * findev = NULL;
256 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
257 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
259 pci_read_config_dword(findev, 0x4C, ®4c);
260 reg4c &= ~0x000007FF;
263 pci_write_config_dword(findev, 0x4C, reg4c);
266 outb_p(0x06, 0x0c00);
267 dev->irq = inb_p(0x0c01);
269 struct pci_dev * findev = NULL;
272 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
273 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
275 pci_read_config_byte(findev, 0x41, ®41);
277 pci_write_config_byte(findev, 0x41, reg41);
281 * This is a device pin issue on CSB6.
282 * Since there will be a future raid mode,
283 * early versions of the chipset require the
284 * interrupt pin to be set, and it is a compatibility
287 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
290 // pci_read_config_dword(dev, 0x40, &pioreg)
291 // pci_write_config_dword(dev, 0x40, 0x99999999);
292 // pci_read_config_dword(dev, 0x44, &dmareg);
293 // pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
294 /* setup the UDMA Control register
296 * 1. clear bit 6 to enable DMA
297 * 2. enable DMA modes with bits 0-1
301 * 11 : udma2/udma4/udma5
303 pci_read_config_byte(dev, 0x5A, &btr);
305 if (!(PCI_FUNC(dev->devfn) & 1))
308 btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
309 pci_write_config_byte(dev, 0x5A, btr);
311 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
312 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
313 pci_read_config_byte(dev, 0x5A, &btr);
316 pci_write_config_byte(dev, 0x5A, btr);
322 static u8 __devinit ata66_svwks_svwks(ide_hwif_t *hwif)
324 return ATA_CBL_PATA80;
327 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
328 * of the subsystem device ID indicate presence of an 80-pin cable.
329 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
330 * Bit 15 set = secondary IDE channel has 80-pin cable.
331 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
332 * Bit 14 set = primary IDE channel has 80-pin cable.
334 static u8 __devinit ata66_svwks_dell(ide_hwif_t *hwif)
336 struct pci_dev *dev = hwif->pci_dev;
337 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
338 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
339 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
340 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
341 return ((1 << (hwif->channel + 14)) &
342 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
343 return ATA_CBL_PATA40;
346 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
347 * detect issue by attaching the drives directly to the board.
348 * This check follows the Dell precedent (how scary is that?!)
350 * WARNING: this only works on Alpine hardware!
352 static u8 __devinit ata66_svwks_cobalt(ide_hwif_t *hwif)
354 struct pci_dev *dev = hwif->pci_dev;
355 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
356 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
357 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
358 return ((1 << (hwif->channel + 14)) &
359 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
360 return ATA_CBL_PATA40;
363 static u8 __devinit ata66_svwks(ide_hwif_t *hwif)
365 struct pci_dev *dev = hwif->pci_dev;
368 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
369 return ata66_svwks_svwks (hwif);
372 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
373 return ata66_svwks_dell (hwif);
376 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
377 return ata66_svwks_cobalt (hwif);
379 /* Per Specified Design by OEM, and ASIC Architect */
380 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
381 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
382 return ATA_CBL_PATA80;
384 return ATA_CBL_PATA40;
387 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
390 hwif->irq = hwif->channel ? 15 : 14;
392 hwif->tuneproc = &svwks_tune_drive;
393 hwif->speedproc = &svwks_tune_chipset;
394 hwif->udma_filter = &svwks_udma_filter;
398 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
399 hwif->ultra_mask = 0x3f;
401 hwif->mwdma_mask = 0x07;
405 hwif->drives[0].autotune = 1;
406 hwif->drives[1].autotune = 1;
411 hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
412 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
413 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
414 hwif->cbl = ata66_svwks(hwif);
419 hwif->drives[0].autodma = hwif->drives[1].autodma = 1;
422 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
424 return ide_setup_pci_device(dev, d);
427 static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
429 if (!(PCI_FUNC(dev->devfn) & 1)) {
430 d->bootable = NEVER_BOARD;
431 if (dev->resource[0].start == 0x01f1)
432 d->bootable = ON_BOARD;
435 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
436 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
437 (!(PCI_FUNC(dev->devfn) & 1)))
438 d->host_flags |= IDE_HFLAG_SINGLE;
440 d->host_flags &= ~IDE_HFLAG_SINGLE;
442 return ide_setup_pci_device(dev, d);
445 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
447 .name = "SvrWks OSB4",
448 .init_setup = init_setup_svwks,
449 .init_chipset = init_chipset_svwks,
450 .init_hwif = init_hwif_svwks,
452 .bootable = ON_BOARD,
453 .pio_mask = ATA_PIO4,
455 .name = "SvrWks CSB5",
456 .init_setup = init_setup_svwks,
457 .init_chipset = init_chipset_svwks,
458 .init_hwif = init_hwif_svwks,
460 .bootable = ON_BOARD,
461 .pio_mask = ATA_PIO4,
463 .name = "SvrWks CSB6",
464 .init_setup = init_setup_csb6,
465 .init_chipset = init_chipset_svwks,
466 .init_hwif = init_hwif_svwks,
468 .bootable = ON_BOARD,
469 .pio_mask = ATA_PIO4,
471 .name = "SvrWks CSB6",
472 .init_setup = init_setup_csb6,
473 .init_chipset = init_chipset_svwks,
474 .init_hwif = init_hwif_svwks,
476 .bootable = ON_BOARD,
477 .host_flags = IDE_HFLAG_SINGLE,
478 .pio_mask = ATA_PIO4,
480 .name = "SvrWks HT1000",
481 .init_setup = init_setup_svwks,
482 .init_chipset = init_chipset_svwks,
483 .init_hwif = init_hwif_svwks,
485 .bootable = ON_BOARD,
486 .host_flags = IDE_HFLAG_SINGLE,
487 .pio_mask = ATA_PIO4,
492 * svwks_init_one - called when a OSB/CSB is found
493 * @dev: the svwks device
494 * @id: the matching pci id
496 * Called when the PCI registration layer (or the IDE initialization)
497 * finds a device matching our IDE device tables.
500 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
502 ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
504 return d->init_setup(dev, d);
507 static struct pci_device_id svwks_pci_tbl[] = {
508 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
509 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
510 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
511 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
512 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
515 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
517 static struct pci_driver driver = {
518 .name = "Serverworks_IDE",
519 .id_table = svwks_pci_tbl,
520 .probe = svwks_init_one,
523 static int __init svwks_ide_init(void)
525 return ide_pci_register_driver(&driver);
528 module_init(svwks_ide_init);
530 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
531 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
532 MODULE_LICENSE("GPL");