2 * Support for IDE interfaces on Celleb platform
4 * (C) Copyright 2006 TOSHIBA CORPORATION
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29 #include <linux/hdreg.h>
30 #include <linux/ide.h>
31 #include <linux/init.h>
33 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
35 #define SCC_PATA_NAME "scc IDE"
37 #define TDVHSEL_MASTER 0x00000001
38 #define TDVHSEL_SLAVE 0x00000004
40 #define MODE_JCUSFEN 0x00000080
42 #define CCKCTRL_ATARESET 0x00040000
43 #define CCKCTRL_BUFCNT 0x00020000
44 #define CCKCTRL_CRST 0x00010000
45 #define CCKCTRL_OCLKEN 0x00000100
46 #define CCKCTRL_ATACLKOEN 0x00000002
47 #define CCKCTRL_LCLKEN 0x00000001
49 #define QCHCD_IOS_SS 0x00000001
51 #define QCHSD_STPDIAG 0x00020000
53 #define INTMASK_MSK 0xD1000012
54 #define INTSTS_SERROR 0x80000000
55 #define INTSTS_PRERR 0x40000000
56 #define INTSTS_RERR 0x10000000
57 #define INTSTS_ICERR 0x01000000
58 #define INTSTS_BMSINT 0x00000010
59 #define INTSTS_BMHE 0x00000008
60 #define INTSTS_IOIRQS 0x00000004
61 #define INTSTS_INTRQ 0x00000002
62 #define INTSTS_ACTEINT 0x00000001
64 #define ECMODE_VALUE 0x01
66 static struct scc_ports {
67 unsigned long ctl, dma;
68 ide_hwif_t *hwif; /* for removing port from system */
69 } scc_ports[MAX_HWIFS];
71 /* PIO transfer mode table */
73 static unsigned long JCHSTtbl[2][7] = {
74 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
75 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
79 static unsigned long JCHHTtbl[2][7] = {
80 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
81 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
85 static unsigned long JCHCTtbl[2][7] = {
86 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
87 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
91 /* DMA transfer mode table */
93 static unsigned long JCHDCTxtbl[2][7] = {
94 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
95 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
99 static unsigned long JCSTWTxtbl[2][7] = {
100 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
101 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
105 static unsigned long JCTSStbl[2][7] = {
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
107 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
111 static unsigned long JCENVTtbl[2][7] = {
112 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
113 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
116 /* JCACTSELS/JCACTSELM */
117 static unsigned long JCACTSELtbl[2][7] = {
118 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
123 static u8 scc_ide_inb(unsigned long port)
125 u32 data = in_be32((void*)port);
129 static u16 scc_ide_inw(unsigned long port)
131 u32 data = in_be32((void*)port);
135 static void scc_ide_insw(unsigned long port, void *addr, u32 count)
137 u16 *ptr = (u16 *)addr;
139 *ptr++ = le16_to_cpu(in_be32((void*)port));
143 static void scc_ide_insl(unsigned long port, void *addr, u32 count)
145 u16 *ptr = (u16 *)addr;
147 *ptr++ = le16_to_cpu(in_be32((void*)port));
148 *ptr++ = le16_to_cpu(in_be32((void*)port));
152 static void scc_ide_outb(u8 addr, unsigned long port)
154 out_be32((void*)port, addr);
157 static void scc_ide_outw(u16 addr, unsigned long port)
159 out_be32((void*)port, addr);
163 scc_ide_outbsync(ide_drive_t * drive, u8 addr, unsigned long port)
165 ide_hwif_t *hwif = HWIF(drive);
167 out_be32((void*)port, addr);
169 in_be32((void*)(hwif->dma_base + 0x01c));
174 scc_ide_outsw(unsigned long port, void *addr, u32 count)
176 u16 *ptr = (u16 *)addr;
178 out_be32((void*)port, cpu_to_le16(*ptr++));
183 scc_ide_outsl(unsigned long port, void *addr, u32 count)
185 u16 *ptr = (u16 *)addr;
187 out_be32((void*)port, cpu_to_le16(*ptr++));
188 out_be32((void*)port, cpu_to_le16(*ptr++));
193 * scc_set_pio_mode - set host controller for PIO mode
195 * @pio: PIO mode number
197 * Load the timing settings for this device mode into the
201 static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
203 ide_hwif_t *hwif = HWIF(drive);
204 struct scc_ports *ports = ide_get_hwifdata(hwif);
205 unsigned long ctl_base = ports->ctl;
206 unsigned long cckctrl_port = ctl_base + 0xff0;
207 unsigned long piosht_port = ctl_base + 0x000;
208 unsigned long pioct_port = ctl_base + 0x004;
212 reg = in_be32((void __iomem *)cckctrl_port);
213 if (reg & CCKCTRL_ATACLKOEN) {
214 offset = 1; /* 133MHz */
216 offset = 0; /* 100MHz */
218 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
219 out_be32((void __iomem *)piosht_port, reg);
220 reg = JCHCTtbl[offset][pio];
221 out_be32((void __iomem *)pioct_port, reg);
225 * scc_set_dma_mode - set host controller for DMA mode
229 * Load the timing settings for this device mode into the
233 static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
235 ide_hwif_t *hwif = HWIF(drive);
236 struct scc_ports *ports = ide_get_hwifdata(hwif);
237 unsigned long ctl_base = ports->ctl;
238 unsigned long cckctrl_port = ctl_base + 0xff0;
239 unsigned long mdmact_port = ctl_base + 0x008;
240 unsigned long mcrcst_port = ctl_base + 0x00c;
241 unsigned long sdmact_port = ctl_base + 0x010;
242 unsigned long scrcst_port = ctl_base + 0x014;
243 unsigned long udenvt_port = ctl_base + 0x018;
244 unsigned long tdvhsel_port = ctl_base + 0x020;
245 int is_slave = (&hwif->drives[1] == drive);
248 unsigned long jcactsel;
250 reg = in_be32((void __iomem *)cckctrl_port);
251 if (reg & CCKCTRL_ATACLKOEN) {
252 offset = 1; /* 133MHz */
254 offset = 0; /* 100MHz */
257 idx = speed - XFER_UDMA_0;
259 jcactsel = JCACTSELtbl[offset][idx];
261 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
262 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
263 jcactsel = jcactsel << 2;
264 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
266 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
267 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
268 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
270 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
271 out_be32((void __iomem *)udenvt_port, reg);
275 * scc_ide_dma_setup - begin a DMA phase
276 * @drive: target device
278 * Build an IDE DMA PRD (IDE speak for scatter gather table)
279 * and then set up the DMA transfer registers.
281 * Returns 0 on success. If a PIO fallback is required then 1
285 static int scc_dma_setup(ide_drive_t *drive)
287 ide_hwif_t *hwif = drive->hwif;
288 struct request *rq = HWGROUP(drive)->rq;
289 unsigned int reading;
297 /* fall back to pio! */
298 if (!ide_build_dmatable(drive, rq)) {
299 ide_map_sg(drive, rq);
304 out_be32((void __iomem *)hwif->dma_prdtable, hwif->dmatable_dma);
307 out_be32((void __iomem *)hwif->dma_command, reading);
309 /* read dma_status for INTR & ERROR flags */
310 dma_stat = in_be32((void __iomem *)hwif->dma_status);
312 /* clear INTR & ERROR flags */
313 out_be32((void __iomem *)hwif->dma_status, dma_stat|6);
314 drive->waiting_for_dma = 1;
320 * scc_ide_dma_end - Stop DMA
323 * Check and clear INT Status register.
324 * Then call __ide_dma_end().
327 static int scc_ide_dma_end(ide_drive_t * drive)
329 ide_hwif_t *hwif = HWIF(drive);
330 unsigned long intsts_port = hwif->dma_base + 0x014;
332 int dma_stat, data_loss = 0;
333 static int retry = 0;
335 /* errata A308 workaround: Step5 (check data loss) */
336 /* We don't check non ide_disk because it is limited to UDMA4 */
337 if (!(in_be32((void __iomem *)hwif->io_ports[IDE_ALTSTATUS_OFFSET])
339 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
340 reg = in_be32((void __iomem *)intsts_port);
341 if (!(reg & INTSTS_ACTEINT)) {
342 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
346 struct request *rq = HWGROUP(drive)->rq;
348 /* ERROR_RESET and drive->crc_count are needed
349 * to reduce DMA transfer mode in retry process.
352 rq->errors |= ERROR_RESET;
353 for (unit = 0; unit < MAX_DRIVES; unit++) {
354 ide_drive_t *drive = &hwif->drives[unit];
362 reg = in_be32((void __iomem *)intsts_port);
364 if (reg & INTSTS_SERROR) {
365 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
366 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
368 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
372 if (reg & INTSTS_PRERR) {
374 unsigned long ctl_base = hwif->config_data;
376 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
377 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
379 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
381 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
383 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
387 if (reg & INTSTS_RERR) {
388 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
389 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
391 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
395 if (reg & INTSTS_ICERR) {
396 out_be32((void __iomem *)hwif->dma_command, in_be32((void __iomem *)hwif->dma_command) & ~QCHCD_IOS_SS);
398 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
399 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
403 if (reg & INTSTS_BMSINT) {
404 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
405 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
411 if (reg & INTSTS_BMHE) {
412 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
416 if (reg & INTSTS_ACTEINT) {
417 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
421 if (reg & INTSTS_IOIRQS) {
422 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
428 dma_stat = __ide_dma_end(drive);
430 dma_stat |= 2; /* emulate DMA error (to retry command) */
434 /* returns 1 if dma irq issued, 0 otherwise */
435 static int scc_dma_test_irq(ide_drive_t *drive)
437 ide_hwif_t *hwif = HWIF(drive);
438 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
440 /* SCC errata A252,A308 workaround: Step4 */
441 if ((in_be32((void __iomem *)hwif->io_ports[IDE_ALTSTATUS_OFFSET])
443 (int_stat & INTSTS_INTRQ))
446 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
447 if (int_stat & INTSTS_IOIRQS)
450 if (!drive->waiting_for_dma)
451 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
452 drive->name, __FUNCTION__);
456 static u8 scc_udma_filter(ide_drive_t *drive)
458 ide_hwif_t *hwif = drive->hwif;
459 u8 mask = hwif->ultra_mask;
461 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
462 if ((drive->media != ide_disk) && (mask & 0xE0)) {
463 printk(KERN_INFO "%s: limit %s to UDMA4\n",
464 SCC_PATA_NAME, drive->name);
472 * setup_mmio_scc - map CTRL/BMID region
473 * @dev: PCI device we are configuring
478 static int setup_mmio_scc (struct pci_dev *dev, const char *name)
480 unsigned long ctl_base = pci_resource_start(dev, 0);
481 unsigned long dma_base = pci_resource_start(dev, 1);
482 unsigned long ctl_size = pci_resource_len(dev, 0);
483 unsigned long dma_size = pci_resource_len(dev, 1);
484 void __iomem *ctl_addr;
485 void __iomem *dma_addr;
488 for (i = 0; i < MAX_HWIFS; i++) {
489 if (scc_ports[i].ctl == 0)
495 ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
497 printk(KERN_ERR "%s: can't reserve resources\n", name);
501 if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
504 if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
508 scc_ports[i].ctl = (unsigned long)ctl_addr;
509 scc_ports[i].dma = (unsigned long)dma_addr;
510 pci_set_drvdata(dev, (void *) &scc_ports[i]);
520 static int scc_ide_setup_pci_device(struct pci_dev *dev,
521 const struct ide_port_info *d)
523 struct scc_ports *ports = pci_get_drvdata(dev);
524 ide_hwif_t *hwif = NULL;
526 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
529 hwif = ide_find_port();
531 printk(KERN_ERR "%s: too many IDE interfaces, "
532 "no room in table\n", SCC_PATA_NAME);
536 memset(&hw, 0, sizeof(hw));
537 for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; i++)
538 hw.io_ports[i] = ports->dma + 0x20 + i * 4;
541 hw.chipset = ide_pci;
542 ide_init_port_hw(hwif, &hw);
543 hwif->dev = &dev->dev;
546 idx[0] = hwif->index;
548 ide_device_add(idx, d);
554 * init_setup_scc - set up an SCC PATA Controller
558 * Perform the initial set up for this device.
561 static int __devinit init_setup_scc(struct pci_dev *dev,
562 const struct ide_port_info *d)
564 unsigned long ctl_base;
565 unsigned long dma_base;
566 unsigned long cckctrl_port;
567 unsigned long intmask_port;
568 unsigned long mode_port;
569 unsigned long ecmode_port;
570 unsigned long dma_status_port;
572 struct scc_ports *ports;
575 rc = pci_enable_device(dev);
579 rc = setup_mmio_scc(dev, d->name);
583 ports = pci_get_drvdata(dev);
584 ctl_base = ports->ctl;
585 dma_base = ports->dma;
586 cckctrl_port = ctl_base + 0xff0;
587 intmask_port = dma_base + 0x010;
588 mode_port = ctl_base + 0x024;
589 ecmode_port = ctl_base + 0xf00;
590 dma_status_port = dma_base + 0x004;
592 /* controller initialization */
594 out_be32((void*)cckctrl_port, reg);
595 reg |= CCKCTRL_ATACLKOEN;
596 out_be32((void*)cckctrl_port, reg);
597 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
598 out_be32((void*)cckctrl_port, reg);
600 out_be32((void*)cckctrl_port, reg);
603 reg = in_be32((void*)cckctrl_port);
604 if (reg & CCKCTRL_CRST)
609 reg |= CCKCTRL_ATARESET;
610 out_be32((void*)cckctrl_port, reg);
612 out_be32((void*)ecmode_port, ECMODE_VALUE);
613 out_be32((void*)mode_port, MODE_JCUSFEN);
614 out_be32((void*)intmask_port, INTMASK_MSK);
616 rc = scc_ide_setup_pci_device(dev, d);
623 * init_mmio_iops_scc - set up the iops for MMIO
624 * @hwif: interface to set up
628 static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
630 struct pci_dev *dev = to_pci_dev(hwif->dev);
631 struct scc_ports *ports = pci_get_drvdata(dev);
632 unsigned long dma_base = ports->dma;
634 ide_set_hwifdata(hwif, ports);
636 hwif->INB = scc_ide_inb;
637 hwif->INW = scc_ide_inw;
638 hwif->INSW = scc_ide_insw;
639 hwif->INSL = scc_ide_insl;
640 hwif->OUTB = scc_ide_outb;
641 hwif->OUTBSYNC = scc_ide_outbsync;
642 hwif->OUTW = scc_ide_outw;
643 hwif->OUTSW = scc_ide_outsw;
644 hwif->OUTSL = scc_ide_outsl;
646 hwif->dma_base = dma_base;
647 hwif->config_data = ports->ctl;
652 * init_iops_scc - set up iops
653 * @hwif: interface to set up
655 * Do the basic setup for the SCC hardware interface
656 * and then do the MMIO setup.
659 static void __devinit init_iops_scc(ide_hwif_t *hwif)
661 struct pci_dev *dev = to_pci_dev(hwif->dev);
663 hwif->hwif_data = NULL;
664 if (pci_get_drvdata(dev) == NULL)
666 init_mmio_iops_scc(hwif);
669 static u8 __devinit scc_cable_detect(ide_hwif_t *hwif)
671 return ATA_CBL_PATA80;
675 * init_hwif_scc - set up hwif
676 * @hwif: interface to set up
678 * We do the basic set up of the interface structure. The SCC
679 * requires several custom handlers so we override the default
680 * ide DMA handlers appropriately.
683 static void __devinit init_hwif_scc(ide_hwif_t *hwif)
685 struct scc_ports *ports = ide_get_hwifdata(hwif);
689 hwif->dma_command = hwif->dma_base;
690 hwif->dma_status = hwif->dma_base + 0x04;
691 hwif->dma_prdtable = hwif->dma_base + 0x08;
694 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
696 hwif->dma_setup = scc_dma_setup;
697 hwif->ide_dma_end = scc_ide_dma_end;
698 hwif->ide_dma_test_irq = scc_dma_test_irq;
700 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
701 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
703 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
706 static const struct ide_port_ops scc_port_ops = {
707 .set_pio_mode = scc_set_pio_mode,
708 .set_dma_mode = scc_set_dma_mode,
709 .udma_filter = scc_udma_filter,
710 .cable_detect = scc_cable_detect,
713 #define DECLARE_SCC_DEV(name_str) \
716 .init_iops = init_iops_scc, \
717 .init_hwif = init_hwif_scc, \
718 .port_ops = &scc_port_ops, \
719 .host_flags = IDE_HFLAG_SINGLE, \
720 .pio_mask = ATA_PIO4, \
723 static const struct ide_port_info scc_chipsets[] __devinitdata = {
724 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
728 * scc_init_one - pci layer discovery entry
730 * @id: ident table entry
732 * Called by the PCI code when it finds an SCC PATA controller.
733 * We then use the IDE PCI generic helper to do most of the work.
736 static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
738 return init_setup_scc(dev, &scc_chipsets[id->driver_data]);
742 * scc_remove - pci layer remove entry
745 * Called by the PCI code when it removes an SCC PATA controller.
748 static void __devexit scc_remove(struct pci_dev *dev)
750 struct scc_ports *ports = pci_get_drvdata(dev);
751 ide_hwif_t *hwif = ports->hwif;
753 if (hwif->dmatable_cpu) {
754 pci_free_consistent(dev, PRD_ENTRIES * PRD_BYTES,
755 hwif->dmatable_cpu, hwif->dmatable_dma);
756 hwif->dmatable_cpu = NULL;
759 ide_unregister(hwif->index);
761 hwif->chipset = ide_unknown;
762 iounmap((void*)ports->dma);
763 iounmap((void*)ports->ctl);
764 pci_release_selected_regions(dev, (1 << 2) - 1);
765 memset(ports, 0, sizeof(*ports));
768 static const struct pci_device_id scc_pci_tbl[] = {
769 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
772 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
774 static struct pci_driver driver = {
776 .id_table = scc_pci_tbl,
777 .probe = scc_init_one,
778 .remove = scc_remove,
781 static int scc_ide_init(void)
783 return ide_pci_register_driver(&driver);
786 module_init(scc_ide_init);
788 static void scc_ide_exit(void)
790 ide_pci_unregister_driver(&driver);
792 module_exit(scc_ide_exit);
796 MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
797 MODULE_LICENSE("GPL");