2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * Supports the following Intel I/O Controller Hubs (ICH):
28 * region SMBus Block proc. block
29 * Chip name PCI ID size PEC buffer call read
30 * ---------------------------------------------------------------------------
31 * 82801AA (ICH) 0x2413 16 no no no no
32 * 82801AB (ICH0) 0x2423 16 no no no no
33 * 82801BA (ICH2) 0x2443 16 no no no no
34 * 82801CA (ICH3) 0x2483 32 soft no no no
35 * 82801DB (ICH4) 0x24c3 32 hard yes no no
36 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 * 6300ESB 0x25a4 32 hard yes yes yes
38 * 82801F (ICH6) 0x266a 32 hard yes yes yes
39 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 * 82801G (ICH7) 0x27da 32 hard yes yes yes
41 * 82801H (ICH8) 0x283e 32 hard yes yes yes
42 * 82801I (ICH9) 0x2930 32 hard yes yes yes
43 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 * ICH10 0x3a30 32 hard yes yes yes
45 * ICH10 0x3a60 32 hard yes yes yes
46 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
55 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
56 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
57 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
58 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
59 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
60 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
61 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
62 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
63 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
64 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
65 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
66 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
68 * Features supported by this driver:
72 * Block process call transaction no
73 * I2C block read transaction yes (doesn't use the block buffer)
76 * See the file Documentation/i2c/busses/i2c-i801 for details.
79 #include <linux/module.h>
80 #include <linux/pci.h>
81 #include <linux/kernel.h>
82 #include <linux/stddef.h>
83 #include <linux/delay.h>
84 #include <linux/ioport.h>
85 #include <linux/init.h>
86 #include <linux/i2c.h>
87 #include <linux/acpi.h>
89 #include <linux/dmi.h>
90 #include <linux/slab.h>
92 /* I801 SMBus address offsets */
93 #define SMBHSTSTS(p) (0 + (p)->smba)
94 #define SMBHSTCNT(p) (2 + (p)->smba)
95 #define SMBHSTCMD(p) (3 + (p)->smba)
96 #define SMBHSTADD(p) (4 + (p)->smba)
97 #define SMBHSTDAT0(p) (5 + (p)->smba)
98 #define SMBHSTDAT1(p) (6 + (p)->smba)
99 #define SMBBLKDAT(p) (7 + (p)->smba)
100 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
101 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
102 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
104 /* PCI Address Constants */
106 #define SMBHSTCFG 0x040
108 /* Host configuration bits for SMBHSTCFG */
109 #define SMBHSTCFG_HST_EN 1
110 #define SMBHSTCFG_SMB_SMI_EN 2
111 #define SMBHSTCFG_I2C_EN 4
113 /* Auxiliary control register bits, ICH4+ only */
114 #define SMBAUXCTL_CRC 1
115 #define SMBAUXCTL_E32B 2
117 /* kill bit for SMBHSTCNT */
118 #define SMBHSTCNT_KILL 2
121 #define MAX_TIMEOUT 100
122 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
124 /* I801 command constants */
125 #define I801_QUICK 0x00
126 #define I801_BYTE 0x04
127 #define I801_BYTE_DATA 0x08
128 #define I801_WORD_DATA 0x0C
129 #define I801_PROC_CALL 0x10 /* unimplemented */
130 #define I801_BLOCK_DATA 0x14
131 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
132 #define I801_BLOCK_LAST 0x34
133 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
134 #define I801_START 0x40
135 #define I801_PEC_EN 0x80 /* ICH3 and later */
137 /* I801 Hosts Status register bits */
138 #define SMBHSTSTS_BYTE_DONE 0x80
139 #define SMBHSTSTS_INUSE_STS 0x40
140 #define SMBHSTSTS_SMBALERT_STS 0x20
141 #define SMBHSTSTS_FAILED 0x10
142 #define SMBHSTSTS_BUS_ERR 0x08
143 #define SMBHSTSTS_DEV_ERR 0x04
144 #define SMBHSTSTS_INTR 0x02
145 #define SMBHSTSTS_HOST_BUSY 0x01
147 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
148 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
151 /* Older devices have their ID defined in <linux/pci_ids.h> */
152 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
153 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
154 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
155 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
156 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
157 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
158 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
159 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
160 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
161 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
162 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
163 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
164 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
165 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
166 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
167 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
168 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
169 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
170 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
171 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
172 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
173 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
174 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
177 struct i2c_adapter adapter;
179 unsigned char original_hstcfg;
180 struct pci_dev *pci_dev;
181 unsigned int features;
184 static struct pci_driver i801_driver;
186 #define FEATURE_SMBUS_PEC (1 << 0)
187 #define FEATURE_BLOCK_BUFFER (1 << 1)
188 #define FEATURE_BLOCK_PROC (1 << 2)
189 #define FEATURE_I2C_BLOCK_READ (1 << 3)
190 /* Not really a feature, but it's convenient to handle it as such */
191 #define FEATURE_IDF (1 << 15)
193 static const char *i801_feature_names[] = {
196 "Block process call",
200 static unsigned int disable_features;
201 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
202 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
204 /* Make sure the SMBus host is ready to start transmitting.
205 Return 0 if it is, -EBUSY if it is not. */
206 static int i801_check_pre(struct i801_priv *priv)
210 status = inb_p(SMBHSTSTS(priv));
211 if (status & SMBHSTSTS_HOST_BUSY) {
212 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
216 status &= STATUS_FLAGS;
218 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
220 outb_p(status, SMBHSTSTS(priv));
221 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
223 dev_err(&priv->pci_dev->dev,
224 "Failed clearing status flags (%02x)\n",
233 /* Convert the status register to an error code, and clear it. */
234 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
238 /* If the SMBus is still busy, we give up */
240 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
241 /* try to stop the current command */
242 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
243 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
246 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
249 /* Check if it worked */
250 status = inb_p(SMBHSTSTS(priv));
251 if ((status & SMBHSTSTS_HOST_BUSY) ||
252 !(status & SMBHSTSTS_FAILED))
253 dev_err(&priv->pci_dev->dev,
254 "Failed terminating the transaction\n");
255 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
259 if (status & SMBHSTSTS_FAILED) {
261 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
263 if (status & SMBHSTSTS_DEV_ERR) {
265 dev_dbg(&priv->pci_dev->dev, "No response\n");
267 if (status & SMBHSTSTS_BUS_ERR) {
269 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
273 /* Clear error flags */
274 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
275 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
277 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
278 "flags at end of transaction (%02x)\n",
286 static int i801_transaction(struct i801_priv *priv, int xact)
292 result = i801_check_pre(priv);
296 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
297 * INTREN, SMBSCMD are passed in xact */
298 outb_p(xact | I801_START, SMBHSTCNT(priv));
300 /* We will always wait for a fraction of a second! */
303 status = inb_p(SMBHSTSTS(priv));
304 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
306 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
310 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
314 /* wait for INTR bit as advised by Intel */
315 static void i801_wait_hwpec(struct i801_priv *priv)
322 status = inb_p(SMBHSTSTS(priv));
323 } while ((!(status & SMBHSTSTS_INTR))
324 && (timeout++ < MAX_TIMEOUT));
326 if (timeout > MAX_TIMEOUT)
327 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
329 outb_p(status, SMBHSTSTS(priv));
332 static int i801_block_transaction_by_block(struct i801_priv *priv,
333 union i2c_smbus_data *data,
334 char read_write, int hwpec)
339 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
341 /* Use 32-byte buffer to process this transaction */
342 if (read_write == I2C_SMBUS_WRITE) {
343 len = data->block[0];
344 outb_p(len, SMBHSTDAT0(priv));
345 for (i = 0; i < len; i++)
346 outb_p(data->block[i+1], SMBBLKDAT(priv));
349 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
350 I801_PEC_EN * hwpec);
354 if (read_write == I2C_SMBUS_READ) {
355 len = inb_p(SMBHSTDAT0(priv));
356 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
359 data->block[0] = len;
360 for (i = 0; i < len; i++)
361 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
366 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
367 union i2c_smbus_data *data,
368 char read_write, int command,
377 result = i801_check_pre(priv);
381 len = data->block[0];
383 if (read_write == I2C_SMBUS_WRITE) {
384 outb_p(len, SMBHSTDAT0(priv));
385 outb_p(data->block[1], SMBBLKDAT(priv));
388 for (i = 1; i <= len; i++) {
389 if (i == len && read_write == I2C_SMBUS_READ) {
390 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
391 smbcmd = I801_I2C_BLOCK_LAST;
393 smbcmd = I801_BLOCK_LAST;
395 if (command == I2C_SMBUS_I2C_BLOCK_DATA
396 && read_write == I2C_SMBUS_READ)
397 smbcmd = I801_I2C_BLOCK_DATA;
399 smbcmd = I801_BLOCK_DATA;
401 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
404 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
407 /* We will always wait for a fraction of a second! */
411 status = inb_p(SMBHSTSTS(priv));
412 } while ((!(status & SMBHSTSTS_BYTE_DONE))
413 && (timeout++ < MAX_TIMEOUT));
415 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
419 if (i == 1 && read_write == I2C_SMBUS_READ
420 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
421 len = inb_p(SMBHSTDAT0(priv));
422 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
423 dev_err(&priv->pci_dev->dev,
424 "Illegal SMBus block read size %d\n",
427 while (inb_p(SMBHSTSTS(priv)) &
429 outb_p(SMBHSTSTS_BYTE_DONE,
431 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
434 data->block[0] = len;
437 /* Retrieve/store value in SMBBLKDAT */
438 if (read_write == I2C_SMBUS_READ)
439 data->block[i] = inb_p(SMBBLKDAT(priv));
440 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
441 outb_p(data->block[i+1], SMBBLKDAT(priv));
443 /* signals SMBBLKDAT ready */
444 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
450 static int i801_set_block_buffer_mode(struct i801_priv *priv)
452 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
453 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
458 /* Block transaction function */
459 static int i801_block_transaction(struct i801_priv *priv,
460 union i2c_smbus_data *data, char read_write,
461 int command, int hwpec)
466 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
467 if (read_write == I2C_SMBUS_WRITE) {
468 /* set I2C_EN bit in configuration register */
469 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
470 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
471 hostc | SMBHSTCFG_I2C_EN);
472 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
473 dev_err(&priv->pci_dev->dev,
474 "I2C block read is unsupported!\n");
479 if (read_write == I2C_SMBUS_WRITE
480 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
481 if (data->block[0] < 1)
483 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
484 data->block[0] = I2C_SMBUS_BLOCK_MAX;
486 data->block[0] = 32; /* max for SMBus block reads */
489 /* Experience has shown that the block buffer can only be used for
490 SMBus (not I2C) block transactions, even though the datasheet
491 doesn't mention this limitation. */
492 if ((priv->features & FEATURE_BLOCK_BUFFER)
493 && command != I2C_SMBUS_I2C_BLOCK_DATA
494 && i801_set_block_buffer_mode(priv) == 0)
495 result = i801_block_transaction_by_block(priv, data,
498 result = i801_block_transaction_byte_by_byte(priv, data,
502 if (result == 0 && hwpec)
503 i801_wait_hwpec(priv);
505 if (command == I2C_SMBUS_I2C_BLOCK_DATA
506 && read_write == I2C_SMBUS_WRITE) {
507 /* restore saved configuration register value */
508 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
513 /* Return negative errno on error. */
514 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
515 unsigned short flags, char read_write, u8 command,
516 int size, union i2c_smbus_data *data)
521 struct i801_priv *priv = i2c_get_adapdata(adap);
523 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
524 && size != I2C_SMBUS_QUICK
525 && size != I2C_SMBUS_I2C_BLOCK_DATA;
528 case I2C_SMBUS_QUICK:
529 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
534 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
536 if (read_write == I2C_SMBUS_WRITE)
537 outb_p(command, SMBHSTCMD(priv));
540 case I2C_SMBUS_BYTE_DATA:
541 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
543 outb_p(command, SMBHSTCMD(priv));
544 if (read_write == I2C_SMBUS_WRITE)
545 outb_p(data->byte, SMBHSTDAT0(priv));
546 xact = I801_BYTE_DATA;
548 case I2C_SMBUS_WORD_DATA:
549 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
551 outb_p(command, SMBHSTCMD(priv));
552 if (read_write == I2C_SMBUS_WRITE) {
553 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
554 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
556 xact = I801_WORD_DATA;
558 case I2C_SMBUS_BLOCK_DATA:
559 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
561 outb_p(command, SMBHSTCMD(priv));
564 case I2C_SMBUS_I2C_BLOCK_DATA:
565 /* NB: page 240 of ICH5 datasheet shows that the R/#W
566 * bit should be cleared here, even when reading */
567 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
568 if (read_write == I2C_SMBUS_READ) {
569 /* NB: page 240 of ICH5 datasheet also shows
570 * that DATA1 is the cmd field when reading */
571 outb_p(command, SMBHSTDAT1(priv));
573 outb_p(command, SMBHSTCMD(priv));
577 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
582 if (hwpec) /* enable/disable hardware PEC */
583 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
585 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
589 ret = i801_block_transaction(priv, data, read_write, size,
592 ret = i801_transaction(priv, xact | ENABLE_INT9);
594 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
595 time, so we forcibly disable it after every transaction. Turn off
596 E32B for the same reason. */
598 outb_p(inb_p(SMBAUXCTL(priv)) &
599 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
605 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
608 switch (xact & 0x7f) {
609 case I801_BYTE: /* Result put in SMBHSTDAT0 */
611 data->byte = inb_p(SMBHSTDAT0(priv));
614 data->word = inb_p(SMBHSTDAT0(priv)) +
615 (inb_p(SMBHSTDAT1(priv)) << 8);
622 static u32 i801_func(struct i2c_adapter *adapter)
624 struct i801_priv *priv = i2c_get_adapdata(adapter);
626 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
627 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
628 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
629 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
630 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
631 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
634 static const struct i2c_algorithm smbus_algorithm = {
635 .smbus_xfer = i801_access,
636 .functionality = i801_func,
639 static const struct pci_device_id i801_ids[] = {
640 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
641 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
642 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
643 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
644 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
645 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
646 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
647 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
648 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
649 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
650 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
651 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
652 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
653 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
654 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
655 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
656 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
657 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
658 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
659 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
660 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
661 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
662 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
663 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
664 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
665 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
666 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
667 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
668 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
669 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
670 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
671 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
672 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
673 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
674 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
675 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
676 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
680 MODULE_DEVICE_TABLE(pci, i801_ids);
682 #if defined CONFIG_X86 && defined CONFIG_DMI
683 static unsigned char apanel_addr;
685 /* Scan the system ROM for the signature "FJKEYINF" */
686 static __init const void __iomem *bios_signature(const void __iomem *bios)
689 const unsigned char signature[] = "FJKEYINF";
691 for (offset = 0; offset < 0x10000; offset += 0x10) {
692 if (check_signature(bios + offset, signature,
693 sizeof(signature)-1))
694 return bios + offset;
699 static void __init input_apanel_init(void)
702 const void __iomem *p;
704 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
705 p = bios_signature(bios);
707 /* just use the first address */
708 apanel_addr = readb(p + 8 + 3) >> 1;
713 struct dmi_onboard_device_info {
716 unsigned short i2c_addr;
717 const char *i2c_type;
720 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
721 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
722 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
723 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
726 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
727 struct i2c_adapter *adap)
730 struct i2c_board_info info;
732 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
733 /* & ~0x80, ignore enabled/disabled bit */
734 if ((type & ~0x80) != dmi_devices[i].type)
736 if (strcasecmp(name, dmi_devices[i].name))
739 memset(&info, 0, sizeof(struct i2c_board_info));
740 info.addr = dmi_devices[i].i2c_addr;
741 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
742 i2c_new_device(adap, &info);
747 /* We use our own function to check for onboard devices instead of
748 dmi_find_device() as some buggy BIOS's have the devices we are interested
749 in marked as disabled */
750 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
758 count = (dm->length - sizeof(struct dmi_header)) / 2;
759 for (i = 0; i < count; i++) {
760 const u8 *d = (char *)(dm + 1) + (i * 2);
761 const char *name = ((char *) dm) + dm->length;
768 while (s > 0 && name[0]) {
769 name += strlen(name) + 1;
772 if (name[0] == 0) /* Bogus string reference */
775 dmi_check_onboard_device(type, name, adap);
779 /* Register optional slaves */
780 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
782 /* Only register slaves on main SMBus channel */
783 if (priv->features & FEATURE_IDF)
787 struct i2c_board_info info;
789 memset(&info, 0, sizeof(struct i2c_board_info));
790 info.addr = apanel_addr;
791 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
792 i2c_new_device(&priv->adapter, &info);
795 if (dmi_name_in_vendors("FUJITSU"))
796 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
799 static void __init input_apanel_init(void) {}
800 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
801 #endif /* CONFIG_X86 && CONFIG_DMI */
803 static int __devinit i801_probe(struct pci_dev *dev,
804 const struct pci_device_id *id)
808 struct i801_priv *priv;
810 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
814 i2c_set_adapdata(&priv->adapter, priv);
815 priv->adapter.owner = THIS_MODULE;
816 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
817 priv->adapter.algo = &smbus_algorithm;
820 switch (dev->device) {
821 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
822 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
823 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
824 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
825 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
826 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
827 priv->features |= FEATURE_IDF;
830 priv->features |= FEATURE_I2C_BLOCK_READ;
832 case PCI_DEVICE_ID_INTEL_82801DB_3:
833 priv->features |= FEATURE_SMBUS_PEC;
834 priv->features |= FEATURE_BLOCK_BUFFER;
836 case PCI_DEVICE_ID_INTEL_82801CA_3:
837 case PCI_DEVICE_ID_INTEL_82801BA_2:
838 case PCI_DEVICE_ID_INTEL_82801AB_3:
839 case PCI_DEVICE_ID_INTEL_82801AA_3:
843 /* Disable features on user request */
844 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
845 if (priv->features & disable_features & (1 << i))
846 dev_notice(&dev->dev, "%s disabled by user\n",
847 i801_feature_names[i]);
849 priv->features &= ~disable_features;
851 err = pci_enable_device(dev);
853 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
858 /* Determine the address of the SMBus area */
859 priv->smba = pci_resource_start(dev, SMBBAR);
861 dev_err(&dev->dev, "SMBus base address uninitialized, "
867 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
873 err = pci_request_region(dev, SMBBAR, i801_driver.name);
875 dev_err(&dev->dev, "Failed to request SMBus region "
876 "0x%lx-0x%Lx\n", priv->smba,
877 (unsigned long long)pci_resource_end(dev, SMBBAR));
881 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
882 priv->original_hstcfg = temp;
883 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
884 if (!(temp & SMBHSTCFG_HST_EN)) {
885 dev_info(&dev->dev, "Enabling SMBus device\n");
886 temp |= SMBHSTCFG_HST_EN;
888 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
890 if (temp & SMBHSTCFG_SMB_SMI_EN)
891 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
893 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
895 /* Clear special mode bits */
896 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
897 outb_p(inb_p(SMBAUXCTL(priv)) &
898 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
900 /* set up the sysfs linkage to our parent device */
901 priv->adapter.dev.parent = &dev->dev;
903 /* Retry up to 3 times on lost arbitration */
904 priv->adapter.retries = 3;
906 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
907 "SMBus I801 adapter at %04lx", priv->smba);
908 err = i2c_add_adapter(&priv->adapter);
910 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
914 i801_probe_optional_slaves(priv);
916 pci_set_drvdata(dev, priv);
920 pci_release_region(dev, SMBBAR);
926 static void __devexit i801_remove(struct pci_dev *dev)
928 struct i801_priv *priv = pci_get_drvdata(dev);
930 i2c_del_adapter(&priv->adapter);
931 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
932 pci_release_region(dev, SMBBAR);
933 pci_set_drvdata(dev, NULL);
936 * do not call pci_disable_device(dev) since it can cause hard hangs on
937 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
942 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
944 struct i801_priv *priv = pci_get_drvdata(dev);
947 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
948 pci_set_power_state(dev, pci_choose_state(dev, mesg));
952 static int i801_resume(struct pci_dev *dev)
954 pci_set_power_state(dev, PCI_D0);
955 pci_restore_state(dev);
956 return pci_enable_device(dev);
959 #define i801_suspend NULL
960 #define i801_resume NULL
963 static struct pci_driver i801_driver = {
964 .name = "i801_smbus",
965 .id_table = i801_ids,
967 .remove = __devexit_p(i801_remove),
968 .suspend = i801_suspend,
969 .resume = i801_resume,
972 static int __init i2c_i801_init(void)
974 if (dmi_name_in_vendors("FUJITSU"))
976 return pci_register_driver(&i801_driver);
979 static void __exit i2c_i801_exit(void)
981 pci_unregister_driver(&i801_driver);
984 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
985 "Jean Delvare <khali@linux-fr.org>");
986 MODULE_DESCRIPTION("I801 SMBus driver");
987 MODULE_LICENSE("GPL");
989 module_init(i2c_i801_init);
990 module_exit(i2c_i801_exit);