2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 /* RS600 / Radeon X1250/X1270 integrated GPU
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
40 #include "radeon_asic.h"
44 #include "rs600_reg_safe.h"
46 void rs600_gpu_init(struct radeon_device *rdev);
47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
49 void rs600_pre_page_flip(struct radeon_device *rdev, int crtc)
51 /* enable the pflip int */
52 radeon_irq_kms_pflip_irq_get(rdev, crtc);
55 void rs600_post_page_flip(struct radeon_device *rdev, int crtc)
57 /* disable the pflip int */
58 radeon_irq_kms_pflip_irq_put(rdev, crtc);
61 u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
63 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
64 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
67 /* Lock the graphics update lock */
68 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
69 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
71 /* update the scanout addresses */
72 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
74 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
77 /* Wait for update_pending to go high. */
78 for (i = 0; i < rdev->usec_timeout; i++) {
79 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
83 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
85 /* Unlock the lock, so double-buffering can take place inside vblank */
86 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
87 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
89 /* Return current update_pending status: */
90 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
93 void rs600_pm_misc(struct radeon_device *rdev)
95 int requested_index = rdev->pm.requested_power_state_index;
96 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
97 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
98 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
99 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
101 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
102 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
103 tmp = RREG32(voltage->gpio.reg);
104 if (voltage->active_high)
105 tmp |= voltage->gpio.mask;
107 tmp &= ~(voltage->gpio.mask);
108 WREG32(voltage->gpio.reg, tmp);
110 udelay(voltage->delay);
112 tmp = RREG32(voltage->gpio.reg);
113 if (voltage->active_high)
114 tmp &= ~voltage->gpio.mask;
116 tmp |= voltage->gpio.mask;
117 WREG32(voltage->gpio.reg, tmp);
119 udelay(voltage->delay);
121 } else if (voltage->type == VOLTAGE_VDDC)
122 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
124 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
125 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
126 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
127 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
128 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
129 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
130 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
131 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
132 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
133 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
136 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
137 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
139 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
141 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
142 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
143 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
144 if (voltage->delay) {
145 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
146 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
148 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
150 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
151 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
153 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
154 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
155 hdp_dyn_cntl &= ~HDP_FORCEON;
157 hdp_dyn_cntl |= HDP_FORCEON;
158 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
160 /* mc_host_dyn seems to cause hangs from time to time */
161 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
162 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
163 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
165 mc_host_dyn_cntl |= MC_HOST_FORCEON;
166 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
168 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
169 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
170 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
172 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
173 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
176 if ((rdev->flags & RADEON_IS_PCIE) &&
177 !(rdev->flags & RADEON_IS_IGP) &&
178 rdev->asic->set_pcie_lanes &&
180 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
181 radeon_set_pcie_lanes(rdev,
183 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
187 void rs600_pm_prepare(struct radeon_device *rdev)
189 struct drm_device *ddev = rdev->ddev;
190 struct drm_crtc *crtc;
191 struct radeon_crtc *radeon_crtc;
194 /* disable any active CRTCs */
195 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
196 radeon_crtc = to_radeon_crtc(crtc);
197 if (radeon_crtc->enabled) {
198 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
199 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
200 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
205 void rs600_pm_finish(struct radeon_device *rdev)
207 struct drm_device *ddev = rdev->ddev;
208 struct drm_crtc *crtc;
209 struct radeon_crtc *radeon_crtc;
212 /* enable any active CRTCs */
213 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
214 radeon_crtc = to_radeon_crtc(crtc);
215 if (radeon_crtc->enabled) {
216 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
217 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
218 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
223 /* hpd for digital panel detect/disconnect */
224 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
227 bool connected = false;
231 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
232 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
236 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
237 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
246 void rs600_hpd_set_polarity(struct radeon_device *rdev,
247 enum radeon_hpd_id hpd)
250 bool connected = rs600_hpd_sense(rdev, hpd);
254 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
256 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
258 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
259 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
262 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
264 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
266 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
267 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
274 void rs600_hpd_init(struct radeon_device *rdev)
276 struct drm_device *dev = rdev->ddev;
277 struct drm_connector *connector;
279 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
280 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
281 switch (radeon_connector->hpd.hpd) {
283 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
284 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
285 rdev->irq.hpd[0] = true;
288 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
289 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
290 rdev->irq.hpd[1] = true;
295 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
297 if (rdev->irq.installed)
301 void rs600_hpd_fini(struct radeon_device *rdev)
303 struct drm_device *dev = rdev->ddev;
304 struct drm_connector *connector;
306 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
307 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
308 switch (radeon_connector->hpd.hpd) {
310 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
311 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
312 rdev->irq.hpd[0] = false;
315 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
316 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
317 rdev->irq.hpd[1] = false;
325 void rs600_bm_disable(struct radeon_device *rdev)
329 /* disable bus mastering */
330 pci_read_config_word(rdev->pdev, 0x4, &tmp);
331 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
335 int rs600_asic_reset(struct radeon_device *rdev)
337 struct rv515_mc_save save;
341 status = RREG32(R_000E40_RBBM_STATUS);
342 if (!G_000E40_GUI_ACTIVE(status)) {
345 /* Stops all mc clients */
346 rv515_mc_stop(rdev, &save);
347 status = RREG32(R_000E40_RBBM_STATUS);
348 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
350 WREG32(RADEON_CP_CSQ_CNTL, 0);
351 tmp = RREG32(RADEON_CP_RB_CNTL);
352 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
353 WREG32(RADEON_CP_RB_RPTR_WR, 0);
354 WREG32(RADEON_CP_RB_WPTR, 0);
355 WREG32(RADEON_CP_RB_CNTL, tmp);
356 pci_save_state(rdev->pdev);
357 /* disable bus mastering */
358 rs600_bm_disable(rdev);
360 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
361 S_0000F0_SOFT_RESET_GA(1));
362 RREG32(R_0000F0_RBBM_SOFT_RESET);
364 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
366 status = RREG32(R_000E40_RBBM_STATUS);
367 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
369 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
370 RREG32(R_0000F0_RBBM_SOFT_RESET);
372 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
374 status = RREG32(R_000E40_RBBM_STATUS);
375 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
377 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
378 RREG32(R_0000F0_RBBM_SOFT_RESET);
380 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
382 status = RREG32(R_000E40_RBBM_STATUS);
383 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
384 /* restore PCI & busmastering */
385 pci_restore_state(rdev->pdev);
386 /* Check if GPU is idle */
387 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
388 dev_err(rdev->dev, "failed to reset GPU\n");
389 rdev->gpu_lockup = true;
392 dev_info(rdev->dev, "GPU reset succeed\n");
393 rv515_mc_resume(rdev, &save);
400 void rs600_gart_tlb_flush(struct radeon_device *rdev)
404 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
405 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
406 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
408 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
409 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
410 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
412 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
413 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
414 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
415 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
418 int rs600_gart_init(struct radeon_device *rdev)
422 if (rdev->gart.robj) {
423 WARN(1, "RS600 GART already initialized\n");
426 /* Initialize common gart structure */
427 r = radeon_gart_init(rdev);
431 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
432 return radeon_gart_table_vram_alloc(rdev);
435 static int rs600_gart_enable(struct radeon_device *rdev)
440 if (rdev->gart.robj == NULL) {
441 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
444 r = radeon_gart_table_vram_pin(rdev);
447 radeon_gart_restore(rdev);
448 /* Enable bus master */
449 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
450 WREG32(RADEON_BUS_CNTL, tmp);
451 /* FIXME: setup default page */
452 WREG32_MC(R_000100_MC_PT0_CNTL,
453 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
454 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
456 for (i = 0; i < 19; i++) {
457 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
458 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
459 S_00016C_SYSTEM_ACCESS_MODE_MASK(
460 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
461 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
462 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
463 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
464 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
465 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
467 /* enable first context */
468 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
469 S_000102_ENABLE_PAGE_TABLE(1) |
470 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
472 /* disable all other contexts */
473 for (i = 1; i < 8; i++)
474 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
476 /* setup the page table */
477 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
478 rdev->gart.table_addr);
479 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
480 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
481 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
483 /* System context maps to VRAM space */
484 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
485 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
487 /* enable page tables */
488 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
489 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
490 tmp = RREG32_MC(R_000009_MC_CNTL1);
491 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
492 rs600_gart_tlb_flush(rdev);
493 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
494 (unsigned)(rdev->mc.gtt_size >> 20),
495 (unsigned long long)rdev->gart.table_addr);
496 rdev->gart.ready = true;
500 void rs600_gart_disable(struct radeon_device *rdev)
504 /* FIXME: disable out of gart access */
505 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
506 tmp = RREG32_MC(R_000009_MC_CNTL1);
507 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
508 radeon_gart_table_vram_unpin(rdev);
511 void rs600_gart_fini(struct radeon_device *rdev)
513 radeon_gart_fini(rdev);
514 rs600_gart_disable(rdev);
515 radeon_gart_table_vram_free(rdev);
518 #define R600_PTE_VALID (1 << 0)
519 #define R600_PTE_SYSTEM (1 << 1)
520 #define R600_PTE_SNOOPED (1 << 2)
521 #define R600_PTE_READABLE (1 << 5)
522 #define R600_PTE_WRITEABLE (1 << 6)
524 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
526 void __iomem *ptr = (void *)rdev->gart.ptr;
528 if (i < 0 || i > rdev->gart.num_gpu_pages) {
531 addr = addr & 0xFFFFFFFFFFFFF000ULL;
532 if (addr == rdev->dummy_page.addr)
533 addr |= R600_PTE_SYSTEM | R600_PTE_SNOOPED;
535 addr |= (R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED |
536 R600_PTE_READABLE | R600_PTE_WRITEABLE);
537 writeq(addr, ptr + (i * 8));
541 int rs600_irq_set(struct radeon_device *rdev)
544 uint32_t mode_int = 0;
545 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
546 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
547 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
548 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
550 if (!rdev->irq.installed) {
551 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
552 WREG32(R_000040_GEN_INT_CNTL, 0);
555 if (rdev->irq.sw_int) {
556 tmp |= S_000040_SW_INT_EN(1);
558 if (rdev->irq.gui_idle) {
559 tmp |= S_000040_GUI_IDLE(1);
561 if (rdev->irq.crtc_vblank_int[0] ||
562 rdev->irq.pflip[0]) {
563 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
565 if (rdev->irq.crtc_vblank_int[1] ||
566 rdev->irq.pflip[1]) {
567 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
569 if (rdev->irq.hpd[0]) {
570 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
572 if (rdev->irq.hpd[1]) {
573 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
575 WREG32(R_000040_GEN_INT_CNTL, tmp);
576 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
577 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
578 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
582 static inline u32 rs600_irq_ack(struct radeon_device *rdev)
584 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
585 uint32_t irq_mask = S_000044_SW_INT(1);
588 /* the interrupt works, but the status bit is permanently asserted */
589 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
590 if (!rdev->irq.gui_idle_acked)
591 irq_mask |= S_000044_GUI_IDLE_STAT(1);
594 if (G_000044_DISPLAY_INT_STAT(irqs)) {
595 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
596 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
597 WREG32(R_006534_D1MODE_VBLANK_STATUS,
598 S_006534_D1MODE_VBLANK_ACK(1));
600 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
601 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
602 S_006D34_D2MODE_VBLANK_ACK(1));
604 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
605 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
606 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
607 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
609 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
610 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
611 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
612 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
615 rdev->irq.stat_regs.r500.disp_int = 0;
619 WREG32(R_000044_GEN_INT_STATUS, irqs);
621 return irqs & irq_mask;
624 void rs600_irq_disable(struct radeon_device *rdev)
626 WREG32(R_000040_GEN_INT_CNTL, 0);
627 WREG32(R_006540_DxMODE_INT_MASK, 0);
628 /* Wait and acknowledge irq */
633 int rs600_irq_process(struct radeon_device *rdev)
635 u32 status, msi_rearm;
636 bool queue_hotplug = false;
638 /* reset gui idle ack. the status bit is broken */
639 rdev->irq.gui_idle_acked = false;
641 status = rs600_irq_ack(rdev);
642 if (!status && !rdev->irq.stat_regs.r500.disp_int) {
645 while (status || rdev->irq.stat_regs.r500.disp_int) {
647 if (G_000044_SW_INT(status)) {
648 radeon_fence_process(rdev);
651 if (G_000040_GUI_IDLE(status)) {
652 rdev->irq.gui_idle_acked = true;
653 rdev->pm.gui_idle = true;
654 wake_up(&rdev->irq.idle_queue);
656 /* Vertical blank interrupts */
657 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
658 if (rdev->irq.crtc_vblank_int[0]) {
659 drm_handle_vblank(rdev->ddev, 0);
660 rdev->pm.vblank_sync = true;
661 wake_up(&rdev->irq.vblank_queue);
663 if (rdev->irq.pflip[0])
664 radeon_crtc_handle_flip(rdev, 0);
666 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
667 if (rdev->irq.crtc_vblank_int[1]) {
668 drm_handle_vblank(rdev->ddev, 1);
669 rdev->pm.vblank_sync = true;
670 wake_up(&rdev->irq.vblank_queue);
672 if (rdev->irq.pflip[1])
673 radeon_crtc_handle_flip(rdev, 1);
675 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
676 queue_hotplug = true;
679 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
680 queue_hotplug = true;
683 status = rs600_irq_ack(rdev);
685 /* reset gui idle ack. the status bit is broken */
686 rdev->irq.gui_idle_acked = false;
688 schedule_work(&rdev->hotplug_work);
689 if (rdev->msi_enabled) {
690 switch (rdev->family) {
694 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
695 WREG32(RADEON_BUS_CNTL, msi_rearm);
696 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
699 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
706 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
709 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
711 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
714 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
718 for (i = 0; i < rdev->usec_timeout; i++) {
719 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
726 void rs600_gpu_init(struct radeon_device *rdev)
728 r420_pipes_init(rdev);
729 /* Wait for mc idle */
730 if (rs600_mc_wait_for_idle(rdev))
731 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
734 void rs600_mc_init(struct radeon_device *rdev)
738 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
739 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
740 rdev->mc.vram_is_ddr = true;
741 rdev->mc.vram_width = 128;
742 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
743 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
744 rdev->mc.visible_vram_size = rdev->mc.aper_size;
745 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
746 base = RREG32_MC(R_000004_MC_FB_LOCATION);
747 base = G_000004_MC_FB_START(base) << 16;
748 radeon_vram_location(rdev, &rdev->mc, base);
749 rdev->mc.gtt_base_align = 0;
750 radeon_gtt_location(rdev, &rdev->mc);
751 radeon_update_bandwidth_info(rdev);
754 void rs600_bandwidth_update(struct radeon_device *rdev)
756 struct drm_display_mode *mode0 = NULL;
757 struct drm_display_mode *mode1 = NULL;
758 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
759 /* FIXME: implement full support */
761 radeon_update_display_priority(rdev);
763 if (rdev->mode_info.crtcs[0]->base.enabled)
764 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
765 if (rdev->mode_info.crtcs[1]->base.enabled)
766 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
768 rs690_line_buffer_adjust(rdev, mode0, mode1);
770 if (rdev->disp_priority == 2) {
771 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
772 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
773 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
774 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
775 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
776 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
777 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
778 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
782 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
784 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
785 S_000070_MC_IND_CITF_ARB0(1));
786 return RREG32(R_000074_MC_IND_DATA);
789 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
791 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
792 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
793 WREG32(R_000074_MC_IND_DATA, v);
796 void rs600_debugfs(struct radeon_device *rdev)
798 if (r100_debugfs_rbbm_init(rdev))
799 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
802 void rs600_set_safe_registers(struct radeon_device *rdev)
804 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
805 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
808 static void rs600_mc_program(struct radeon_device *rdev)
810 struct rv515_mc_save save;
812 /* Stops all mc clients */
813 rv515_mc_stop(rdev, &save);
815 /* Wait for mc idle */
816 if (rs600_mc_wait_for_idle(rdev))
817 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
819 /* FIXME: What does AGP means for such chipset ? */
820 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
821 WREG32_MC(R_000006_AGP_BASE, 0);
822 WREG32_MC(R_000007_AGP_BASE_2, 0);
824 WREG32_MC(R_000004_MC_FB_LOCATION,
825 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
826 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
827 WREG32(R_000134_HDP_FB_LOCATION,
828 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
830 rv515_mc_resume(rdev, &save);
833 static int rs600_startup(struct radeon_device *rdev)
837 rs600_mc_program(rdev);
839 rv515_clock_startup(rdev);
840 /* Initialize GPU configuration (# pipes, ...) */
841 rs600_gpu_init(rdev);
842 /* Initialize GART (initialize after TTM so we can allocate
843 * memory through TTM but finalize after TTM) */
844 r = rs600_gart_enable(rdev);
848 /* allocate wb buffer */
849 r = radeon_wb_init(rdev);
854 if (!rdev->irq.installed) {
855 r = radeon_irq_kms_init(rdev);
861 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
863 r = r100_cp_init(rdev, 1024 * 1024);
865 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
868 r = r100_ib_init(rdev);
870 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
874 r = r600_audio_init(rdev);
876 dev_err(rdev->dev, "failed initializing audio\n");
883 int rs600_resume(struct radeon_device *rdev)
885 /* Make sur GART are not working */
886 rs600_gart_disable(rdev);
887 /* Resume clock before doing reset */
888 rv515_clock_startup(rdev);
889 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
890 if (radeon_asic_reset(rdev)) {
891 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
892 RREG32(R_000E40_RBBM_STATUS),
893 RREG32(R_0007C0_CP_STAT));
896 atom_asic_init(rdev->mode_info.atom_context);
897 /* Resume clock after posting */
898 rv515_clock_startup(rdev);
899 /* Initialize surface registers */
900 radeon_surface_init(rdev);
901 return rs600_startup(rdev);
904 int rs600_suspend(struct radeon_device *rdev)
906 r600_audio_fini(rdev);
907 r100_cp_disable(rdev);
908 radeon_wb_disable(rdev);
909 rs600_irq_disable(rdev);
910 rs600_gart_disable(rdev);
914 void rs600_fini(struct radeon_device *rdev)
916 r600_audio_fini(rdev);
918 radeon_wb_fini(rdev);
920 radeon_gem_fini(rdev);
921 rs600_gart_fini(rdev);
922 radeon_irq_kms_fini(rdev);
923 radeon_fence_driver_fini(rdev);
924 radeon_bo_fini(rdev);
925 radeon_atombios_fini(rdev);
930 int rs600_init(struct radeon_device *rdev)
935 rv515_vga_render_disable(rdev);
936 /* Initialize scratch registers */
937 radeon_scratch_init(rdev);
938 /* Initialize surface registers */
939 radeon_surface_init(rdev);
940 /* restore some register to sane defaults */
941 r100_restore_sanity(rdev);
943 if (!radeon_get_bios(rdev)) {
944 if (ASIC_IS_AVIVO(rdev))
947 if (rdev->is_atom_bios) {
948 r = radeon_atombios_init(rdev);
952 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
955 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
956 if (radeon_asic_reset(rdev)) {
958 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
959 RREG32(R_000E40_RBBM_STATUS),
960 RREG32(R_0007C0_CP_STAT));
962 /* check if cards are posted or not */
963 if (radeon_boot_test_post_card(rdev) == false)
966 /* Initialize clocks */
967 radeon_get_clock_info(rdev->ddev);
968 /* initialize memory controller */
972 r = radeon_fence_driver_init(rdev);
976 r = radeon_bo_init(rdev);
979 r = rs600_gart_init(rdev);
982 rs600_set_safe_registers(rdev);
983 rdev->accel_working = true;
984 r = rs600_startup(rdev);
986 /* Somethings want wront with the accel init stop accel */
987 dev_err(rdev->dev, "Disabling GPU acceleration\n");
989 radeon_wb_fini(rdev);
991 rs600_gart_fini(rdev);
992 radeon_irq_kms_fini(rdev);
993 rdev->accel_working = false;