2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #include <linux/acpi.h>
29 #include <linux/power_supply.h>
30 #include <linux/hwmon.h>
31 #include <linux/hwmon-sysfs.h>
33 #define RADEON_IDLE_LOOP_MS 100
34 #define RADEON_RECLOCK_DELAY_MS 200
35 #define RADEON_WAIT_VBLANK_TIMEOUT 200
36 #define RADEON_WAIT_IDLE_TIMEOUT 200
38 static const char *radeon_pm_state_type_name[5] = {
46 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
47 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
48 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
49 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
50 static void radeon_pm_update_profile(struct radeon_device *rdev);
51 static void radeon_pm_set_clocks(struct radeon_device *rdev);
53 #define ACPI_AC_CLASS "ac_adapter"
56 static int radeon_acpi_event(struct notifier_block *nb,
60 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
61 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
63 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
64 if (power_supply_is_system_supplied() > 0)
65 DRM_DEBUG("pm: AC\n");
67 DRM_DEBUG("pm: DC\n");
69 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
70 if (rdev->pm.profile == PM_PROFILE_AUTO) {
71 mutex_lock(&rdev->pm.mutex);
72 radeon_pm_update_profile(rdev);
73 radeon_pm_set_clocks(rdev);
74 mutex_unlock(&rdev->pm.mutex);
83 static void radeon_pm_update_profile(struct radeon_device *rdev)
85 switch (rdev->pm.profile) {
86 case PM_PROFILE_DEFAULT:
87 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
90 if (power_supply_is_system_supplied() > 0) {
91 if (rdev->pm.active_crtc_count > 1)
92 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
94 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
96 if (rdev->pm.active_crtc_count > 1)
97 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
99 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
103 if (rdev->pm.active_crtc_count > 1)
104 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
106 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
109 if (rdev->pm.active_crtc_count > 1)
110 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
112 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
114 case PM_PROFILE_HIGH:
115 if (rdev->pm.active_crtc_count > 1)
116 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
118 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
122 if (rdev->pm.active_crtc_count == 0) {
123 rdev->pm.requested_power_state_index =
124 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
125 rdev->pm.requested_clock_mode_index =
126 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
128 rdev->pm.requested_power_state_index =
129 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
130 rdev->pm.requested_clock_mode_index =
131 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
135 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
137 struct radeon_bo *bo, *n;
139 if (list_empty(&rdev->gem.objects))
142 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
143 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
144 ttm_bo_unmap_virtual(&bo->tbo);
148 static void radeon_sync_with_vblank(struct radeon_device *rdev)
150 if (rdev->pm.active_crtcs) {
151 rdev->pm.vblank_sync = false;
153 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
154 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
158 static void radeon_set_power_state(struct radeon_device *rdev)
161 bool misc_after = false;
163 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
164 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
167 if (radeon_gui_idle(rdev)) {
168 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
169 clock_info[rdev->pm.requested_clock_mode_index].sclk;
170 if (sclk > rdev->clock.default_sclk)
171 sclk = rdev->clock.default_sclk;
173 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
174 clock_info[rdev->pm.requested_clock_mode_index].mclk;
175 if (mclk > rdev->clock.default_mclk)
176 mclk = rdev->clock.default_mclk;
178 /* upvolt before raising clocks, downvolt after lowering clocks */
179 if (sclk < rdev->pm.current_sclk)
182 radeon_sync_with_vblank(rdev);
184 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
185 if (!radeon_pm_in_vbl(rdev))
189 radeon_pm_prepare(rdev);
192 /* voltage, pcie lanes, etc.*/
193 radeon_pm_misc(rdev);
195 /* set engine clock */
196 if (sclk != rdev->pm.current_sclk) {
197 radeon_pm_debug_check_in_vbl(rdev, false);
198 radeon_set_engine_clock(rdev, sclk);
199 radeon_pm_debug_check_in_vbl(rdev, true);
200 rdev->pm.current_sclk = sclk;
201 DRM_DEBUG("Setting: e: %d\n", sclk);
204 /* set memory clock */
205 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
206 radeon_pm_debug_check_in_vbl(rdev, false);
207 radeon_set_memory_clock(rdev, mclk);
208 radeon_pm_debug_check_in_vbl(rdev, true);
209 rdev->pm.current_mclk = mclk;
210 DRM_DEBUG("Setting: m: %d\n", mclk);
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev);
217 radeon_pm_finish(rdev);
219 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
220 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
222 DRM_DEBUG("pm: GUI not idle!!!\n");
225 static void radeon_pm_set_clocks(struct radeon_device *rdev)
229 mutex_lock(&rdev->ddev->struct_mutex);
230 mutex_lock(&rdev->vram_mutex);
231 mutex_lock(&rdev->cp.mutex);
233 /* gui idle int has issues on older chips it seems */
234 if (rdev->family >= CHIP_R600) {
235 if (rdev->irq.installed) {
236 /* wait for GPU idle */
237 rdev->pm.gui_idle = false;
238 rdev->irq.gui_idle = true;
239 radeon_irq_set(rdev);
240 wait_event_interruptible_timeout(
241 rdev->irq.idle_queue, rdev->pm.gui_idle,
242 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
243 rdev->irq.gui_idle = false;
244 radeon_irq_set(rdev);
247 if (rdev->cp.ready) {
248 struct radeon_fence *fence;
249 radeon_ring_alloc(rdev, 64);
250 radeon_fence_create(rdev, &fence);
251 radeon_fence_emit(rdev, fence);
252 radeon_ring_commit(rdev);
253 radeon_fence_wait(fence, false);
254 radeon_fence_unref(&fence);
257 radeon_unmap_vram_bos(rdev);
259 if (rdev->irq.installed) {
260 for (i = 0; i < rdev->num_crtc; i++) {
261 if (rdev->pm.active_crtcs & (1 << i)) {
262 rdev->pm.req_vblank |= (1 << i);
263 drm_vblank_get(rdev->ddev, i);
268 radeon_set_power_state(rdev);
270 if (rdev->irq.installed) {
271 for (i = 0; i < rdev->num_crtc; i++) {
272 if (rdev->pm.req_vblank & (1 << i)) {
273 rdev->pm.req_vblank &= ~(1 << i);
274 drm_vblank_put(rdev->ddev, i);
279 /* update display watermarks based on new power state */
280 radeon_update_bandwidth_info(rdev);
281 if (rdev->pm.active_crtc_count)
282 radeon_bandwidth_update(rdev);
284 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
286 mutex_unlock(&rdev->cp.mutex);
287 mutex_unlock(&rdev->vram_mutex);
288 mutex_unlock(&rdev->ddev->struct_mutex);
291 static void radeon_pm_print_states(struct radeon_device *rdev)
294 struct radeon_power_state *power_state;
295 struct radeon_pm_clock_info *clock_info;
297 DRM_DEBUG("%d Power State(s)\n", rdev->pm.num_power_states);
298 for (i = 0; i < rdev->pm.num_power_states; i++) {
299 power_state = &rdev->pm.power_state[i];
300 DRM_DEBUG("State %d: %s\n", i,
301 radeon_pm_state_type_name[power_state->type]);
302 if (i == rdev->pm.default_power_state_index)
303 DRM_DEBUG("\tDefault");
304 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
305 DRM_DEBUG("\t%d PCIE Lanes\n", power_state->pcie_lanes);
306 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
307 DRM_DEBUG("\tSingle display only\n");
308 DRM_DEBUG("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
309 for (j = 0; j < power_state->num_clock_modes; j++) {
310 clock_info = &(power_state->clock_info[j]);
311 if (rdev->flags & RADEON_IS_IGP)
312 DRM_DEBUG("\t\t%d e: %d%s\n",
314 clock_info->sclk * 10,
315 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
317 DRM_DEBUG("\t\t%d e: %d\tm: %d\tv: %d%s\n",
319 clock_info->sclk * 10,
320 clock_info->mclk * 10,
321 clock_info->voltage.voltage,
322 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
327 static ssize_t radeon_get_pm_profile(struct device *dev,
328 struct device_attribute *attr,
331 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
332 struct radeon_device *rdev = ddev->dev_private;
333 int cp = rdev->pm.profile;
335 return snprintf(buf, PAGE_SIZE, "%s\n",
336 (cp == PM_PROFILE_AUTO) ? "auto" :
337 (cp == PM_PROFILE_LOW) ? "low" :
338 (cp == PM_PROFILE_HIGH) ? "high" : "default");
341 static ssize_t radeon_set_pm_profile(struct device *dev,
342 struct device_attribute *attr,
346 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
347 struct radeon_device *rdev = ddev->dev_private;
349 mutex_lock(&rdev->pm.mutex);
350 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
351 if (strncmp("default", buf, strlen("default")) == 0)
352 rdev->pm.profile = PM_PROFILE_DEFAULT;
353 else if (strncmp("auto", buf, strlen("auto")) == 0)
354 rdev->pm.profile = PM_PROFILE_AUTO;
355 else if (strncmp("low", buf, strlen("low")) == 0)
356 rdev->pm.profile = PM_PROFILE_LOW;
357 else if (strncmp("mid", buf, strlen("mid")) == 0)
358 rdev->pm.profile = PM_PROFILE_MID;
359 else if (strncmp("high", buf, strlen("high")) == 0)
360 rdev->pm.profile = PM_PROFILE_HIGH;
362 DRM_ERROR("invalid power profile!\n");
365 radeon_pm_update_profile(rdev);
366 radeon_pm_set_clocks(rdev);
369 mutex_unlock(&rdev->pm.mutex);
374 static ssize_t radeon_get_pm_method(struct device *dev,
375 struct device_attribute *attr,
378 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
379 struct radeon_device *rdev = ddev->dev_private;
380 int pm = rdev->pm.pm_method;
382 return snprintf(buf, PAGE_SIZE, "%s\n",
383 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
386 static ssize_t radeon_set_pm_method(struct device *dev,
387 struct device_attribute *attr,
391 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
392 struct radeon_device *rdev = ddev->dev_private;
395 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
396 mutex_lock(&rdev->pm.mutex);
397 rdev->pm.pm_method = PM_METHOD_DYNPM;
398 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
399 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
400 mutex_unlock(&rdev->pm.mutex);
401 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
402 bool flush_wq = false;
404 mutex_lock(&rdev->pm.mutex);
405 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
406 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
410 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
411 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
412 rdev->pm.pm_method = PM_METHOD_PROFILE;
413 mutex_unlock(&rdev->pm.mutex);
415 flush_workqueue(rdev->wq);
417 DRM_ERROR("invalid power method!\n");
420 radeon_pm_compute_clocks(rdev);
425 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
426 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
428 static ssize_t radeon_hwmon_show_temp(struct device *dev,
429 struct device_attribute *attr,
432 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
433 struct radeon_device *rdev = ddev->dev_private;
436 switch (rdev->pm.int_thermal_type) {
437 case THERMAL_TYPE_RV6XX:
438 temp = rv6xx_get_temp(rdev);
440 case THERMAL_TYPE_RV770:
441 temp = rv770_get_temp(rdev);
443 case THERMAL_TYPE_EVERGREEN:
444 temp = evergreen_get_temp(rdev);
451 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
454 static ssize_t radeon_hwmon_show_name(struct device *dev,
455 struct device_attribute *attr,
458 return sprintf(buf, "radeon\n");
461 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
462 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
464 static struct attribute *hwmon_attributes[] = {
465 &sensor_dev_attr_temp1_input.dev_attr.attr,
466 &sensor_dev_attr_name.dev_attr.attr,
470 static const struct attribute_group hwmon_attrgroup = {
471 .attrs = hwmon_attributes,
474 static void radeon_hwmon_init(struct radeon_device *rdev)
478 rdev->pm.int_hwmon_dev = NULL;
480 switch (rdev->pm.int_thermal_type) {
481 case THERMAL_TYPE_RV6XX:
482 case THERMAL_TYPE_RV770:
483 case THERMAL_TYPE_EVERGREEN:
484 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
485 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
486 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
489 DRM_ERROR("Unable to create hwmon sysfs file: %d\n", err);
496 static void radeon_hwmon_fini(struct radeon_device *rdev)
498 if (rdev->pm.int_hwmon_dev) {
499 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
500 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
504 void radeon_pm_suspend(struct radeon_device *rdev)
506 bool flush_wq = false;
508 mutex_lock(&rdev->pm.mutex);
509 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
510 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
511 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
512 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
515 mutex_unlock(&rdev->pm.mutex);
517 flush_workqueue(rdev->wq);
520 void radeon_pm_resume(struct radeon_device *rdev)
522 /* asic init will reset the default power state */
523 mutex_lock(&rdev->pm.mutex);
524 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
525 rdev->pm.current_clock_mode_index = 0;
526 rdev->pm.current_sclk = rdev->clock.default_sclk;
527 rdev->pm.current_mclk = rdev->clock.default_mclk;
528 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
529 if (rdev->pm.pm_method == PM_METHOD_DYNPM
530 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
531 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
532 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
533 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
535 mutex_unlock(&rdev->pm.mutex);
536 radeon_pm_compute_clocks(rdev);
539 int radeon_pm_init(struct radeon_device *rdev)
542 /* default to profile method */
543 rdev->pm.pm_method = PM_METHOD_PROFILE;
544 rdev->pm.profile = PM_PROFILE_DEFAULT;
545 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
546 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
547 rdev->pm.dynpm_can_upclock = true;
548 rdev->pm.dynpm_can_downclock = true;
549 rdev->pm.current_sclk = rdev->clock.default_sclk;
550 rdev->pm.current_mclk = rdev->clock.default_mclk;
551 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
554 if (rdev->is_atom_bios)
555 radeon_atombios_get_power_modes(rdev);
557 radeon_combios_get_power_modes(rdev);
558 radeon_pm_print_states(rdev);
559 radeon_pm_init_profile(rdev);
562 /* set up the internal thermal sensor if applicable */
563 radeon_hwmon_init(rdev);
564 if (rdev->pm.num_power_states > 1) {
565 /* where's the best place to put these? */
566 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
568 DRM_ERROR("failed to create device file for power profile\n");
569 ret = device_create_file(rdev->dev, &dev_attr_power_method);
571 DRM_ERROR("failed to create device file for power method\n");
574 rdev->acpi_nb.notifier_call = radeon_acpi_event;
575 register_acpi_notifier(&rdev->acpi_nb);
577 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
579 if (radeon_debugfs_pm_init(rdev)) {
580 DRM_ERROR("Failed to register debugfs file for PM!\n");
583 DRM_INFO("radeon: power management initialized\n");
589 void radeon_pm_fini(struct radeon_device *rdev)
591 if (rdev->pm.num_power_states > 1) {
592 bool flush_wq = false;
594 mutex_lock(&rdev->pm.mutex);
595 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
596 rdev->pm.profile = PM_PROFILE_DEFAULT;
597 radeon_pm_update_profile(rdev);
598 radeon_pm_set_clocks(rdev);
599 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
601 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
603 /* reset default clocks */
604 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
605 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
606 radeon_pm_set_clocks(rdev);
608 mutex_unlock(&rdev->pm.mutex);
610 flush_workqueue(rdev->wq);
612 device_remove_file(rdev->dev, &dev_attr_power_profile);
613 device_remove_file(rdev->dev, &dev_attr_power_method);
615 unregister_acpi_notifier(&rdev->acpi_nb);
619 radeon_hwmon_fini(rdev);
620 if (rdev->pm.i2c_bus)
621 radeon_i2c_destroy(rdev->pm.i2c_bus);
624 void radeon_pm_compute_clocks(struct radeon_device *rdev)
626 struct drm_device *ddev = rdev->ddev;
627 struct drm_crtc *crtc;
628 struct radeon_crtc *radeon_crtc;
630 if (rdev->pm.num_power_states < 2)
633 mutex_lock(&rdev->pm.mutex);
635 rdev->pm.active_crtcs = 0;
636 rdev->pm.active_crtc_count = 0;
637 list_for_each_entry(crtc,
638 &ddev->mode_config.crtc_list, head) {
639 radeon_crtc = to_radeon_crtc(crtc);
640 if (radeon_crtc->enabled) {
641 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
642 rdev->pm.active_crtc_count++;
646 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
647 radeon_pm_update_profile(rdev);
648 radeon_pm_set_clocks(rdev);
649 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
650 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
651 if (rdev->pm.active_crtc_count > 1) {
652 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
653 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
655 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
656 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
657 radeon_pm_get_dynpm_state(rdev);
658 radeon_pm_set_clocks(rdev);
660 DRM_DEBUG("radeon: dynamic power management deactivated\n");
662 } else if (rdev->pm.active_crtc_count == 1) {
663 /* TODO: Increase clocks if needed for current mode */
665 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
666 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
667 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
668 radeon_pm_get_dynpm_state(rdev);
669 radeon_pm_set_clocks(rdev);
671 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
672 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
673 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
674 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
675 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
676 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
677 DRM_DEBUG("radeon: dynamic power management activated\n");
679 } else { /* count == 0 */
680 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
681 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
683 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
684 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
685 radeon_pm_get_dynpm_state(rdev);
686 radeon_pm_set_clocks(rdev);
692 mutex_unlock(&rdev->pm.mutex);
695 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
697 u32 stat_crtc = 0, vbl = 0, position = 0;
700 if (ASIC_IS_DCE4(rdev)) {
701 if (rdev->pm.active_crtcs & (1 << 0)) {
702 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
703 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
704 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
705 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
707 if (rdev->pm.active_crtcs & (1 << 1)) {
708 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
709 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
710 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
711 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
713 if (rdev->pm.active_crtcs & (1 << 2)) {
714 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
715 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
716 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
717 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
719 if (rdev->pm.active_crtcs & (1 << 3)) {
720 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
721 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
722 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
723 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
725 if (rdev->pm.active_crtcs & (1 << 4)) {
726 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
727 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
728 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
729 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
731 if (rdev->pm.active_crtcs & (1 << 5)) {
732 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
733 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
734 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
735 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
737 } else if (ASIC_IS_AVIVO(rdev)) {
738 if (rdev->pm.active_crtcs & (1 << 0)) {
739 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
740 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
742 if (rdev->pm.active_crtcs & (1 << 1)) {
743 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
744 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
746 if (position < vbl && position > 1)
749 if (rdev->pm.active_crtcs & (1 << 0)) {
750 stat_crtc = RREG32(RADEON_CRTC_STATUS);
751 if (!(stat_crtc & 1))
754 if (rdev->pm.active_crtcs & (1 << 1)) {
755 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
756 if (!(stat_crtc & 1))
761 if (position < vbl && position > 1)
767 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
770 bool in_vbl = radeon_pm_in_vbl(rdev);
773 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
774 finish ? "exit" : "entry");
778 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
780 struct radeon_device *rdev;
782 rdev = container_of(work, struct radeon_device,
783 pm.dynpm_idle_work.work);
785 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
786 mutex_lock(&rdev->pm.mutex);
787 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
788 unsigned long irq_flags;
789 int not_processed = 0;
791 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
792 if (!list_empty(&rdev->fence_drv.emited)) {
793 struct list_head *ptr;
794 list_for_each(ptr, &rdev->fence_drv.emited) {
795 /* count up to 3, that's enought info */
796 if (++not_processed >= 3)
800 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
802 if (not_processed >= 3) { /* should upclock */
803 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
804 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
805 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
806 rdev->pm.dynpm_can_upclock) {
807 rdev->pm.dynpm_planned_action =
808 DYNPM_ACTION_UPCLOCK;
809 rdev->pm.dynpm_action_timeout = jiffies +
810 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
812 } else if (not_processed == 0) { /* should downclock */
813 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
814 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
815 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
816 rdev->pm.dynpm_can_downclock) {
817 rdev->pm.dynpm_planned_action =
818 DYNPM_ACTION_DOWNCLOCK;
819 rdev->pm.dynpm_action_timeout = jiffies +
820 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
824 /* Note, radeon_pm_set_clocks is called with static_switch set
825 * to false since we want to wait for vbl to avoid flicker.
827 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
828 jiffies > rdev->pm.dynpm_action_timeout) {
829 radeon_pm_get_dynpm_state(rdev);
830 radeon_pm_set_clocks(rdev);
833 queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
834 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
836 mutex_unlock(&rdev->pm.mutex);
837 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
843 #if defined(CONFIG_DEBUG_FS)
845 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
847 struct drm_info_node *node = (struct drm_info_node *) m->private;
848 struct drm_device *dev = node->minor->dev;
849 struct radeon_device *rdev = dev->dev_private;
851 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
852 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
853 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
854 if (rdev->asic->get_memory_clock)
855 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
856 if (rdev->pm.current_vddc)
857 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
858 if (rdev->asic->get_pcie_lanes)
859 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
864 static struct drm_info_list radeon_pm_info_list[] = {
865 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
869 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
871 #if defined(CONFIG_DEBUG_FS)
872 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));