drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #ifdef CONFIG_ACPI
  27 #include <linux/acpi.h>
  28 #endif
  29 #include <linux/power_supply.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34 #define RADEON_WAIT_IDLE_TIMEOUT 200
  35
  36 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  37 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  38 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  39 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  40 static void radeon_pm_update_profile(struct radeon_device *rdev);
  41 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  42
  43 #define ACPI_AC_CLASS           "ac_adapter"
  44
  45 #ifdef CONFIG_ACPI
  46 static int radeon_acpi_event(struct notifier_block *nb,
  47                              unsigned long val,
  48                              void *data)
  49 {
  50         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  51         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  52
  53         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  54                 if (power_supply_is_system_supplied() > 0)
  55                         DRM_DEBUG("pm: AC\n");
  56                 else
  57                         DRM_DEBUG("pm: DC\n");
  58
  59                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  60                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
  61                                 mutex_lock(&rdev->pm.mutex);
  62                                 radeon_pm_update_profile(rdev);
  63                                 radeon_pm_set_clocks(rdev);
  64                                 mutex_unlock(&rdev->pm.mutex);
  65                         }
  66                 }
  67         }
  68
  69         return NOTIFY_OK;
  70 }
  71 #endif
  72
  73 static void radeon_pm_update_profile(struct radeon_device *rdev)
  74 {
  75         switch (rdev->pm.profile) {
  76         case PM_PROFILE_DEFAULT:
  77                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  78                 break;
  79         case PM_PROFILE_AUTO:
  80                 if (power_supply_is_system_supplied() > 0) {
  81                         if (rdev->pm.active_crtc_count > 1)
  82                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  83                         else
  84                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  85                 } else {
  86                         if (rdev->pm.active_crtc_count > 1)
  87                                 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  88                         else
  89                                 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  90                 }
  91                 break;
  92         case PM_PROFILE_LOW:
  93                 if (rdev->pm.active_crtc_count > 1)
  94                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  95                 else
  96                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  97                 break;
  98         case PM_PROFILE_HIGH:
  99                 if (rdev->pm.active_crtc_count > 1)
 100                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 101                 else
 102                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 103                 break;
 104         }
 105
 106         if (rdev->pm.active_crtc_count == 0) {
 107                 rdev->pm.requested_power_state_index =
 108                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 109                 rdev->pm.requested_clock_mode_index =
 110                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 111         } else {
 112                 rdev->pm.requested_power_state_index =
 113                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 114                 rdev->pm.requested_clock_mode_index =
 115                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 116         }
 117 }
 118
 119 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 120 {
 121         struct radeon_bo *bo, *n;
 122
 123         if (list_empty(&rdev->gem.objects))
 124                 return;
 125
 126         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 127                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 128                         ttm_bo_unmap_virtual(&bo->tbo);
 129         }
 130
 131         if (rdev->gart.table.vram.robj)
 132                 ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
 133
 134         if (rdev->stollen_vga_memory)
 135                 ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
 136
 137         if (rdev->r600_blit.shader_obj)
 138                 ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
 139 }
 140
 141 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 142 {
 143         if (rdev->pm.active_crtcs) {
 144                 rdev->pm.vblank_sync = false;
 145                 wait_event_timeout(
 146                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 147                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 148         }
 149 }
 150
 151 static void radeon_set_power_state(struct radeon_device *rdev)
 152 {
 153         u32 sclk, mclk;
 154
 155         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 156             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 157                 return;
 158
 159         if (radeon_gui_idle(rdev)) {
 160                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 161                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 162                 if (sclk > rdev->clock.default_sclk)
 163                         sclk = rdev->clock.default_sclk;
 164
 165                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 166                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 167                 if (mclk > rdev->clock.default_mclk)
 168                         mclk = rdev->clock.default_mclk;
 169
 170                 /* voltage, pcie lanes, etc.*/
 171                 radeon_pm_misc(rdev);
 172
 173                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 174                         radeon_sync_with_vblank(rdev);
 175
 176                         if (!radeon_pm_in_vbl(rdev))
 177                                 return;
 178
 179                         radeon_pm_prepare(rdev);
 180                         /* set engine clock */
 181                         if (sclk != rdev->pm.current_sclk) {
 182                                 radeon_pm_debug_check_in_vbl(rdev, false);
 183                                 radeon_set_engine_clock(rdev, sclk);
 184                                 radeon_pm_debug_check_in_vbl(rdev, true);
 185                                 rdev->pm.current_sclk = sclk;
 186                                 DRM_DEBUG("Setting: e: %d\n", sclk);
 187                         }
 188
 189                         /* set memory clock */
 190                         if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 191                                 radeon_pm_debug_check_in_vbl(rdev, false);
 192                                 radeon_set_memory_clock(rdev, mclk);
 193                                 radeon_pm_debug_check_in_vbl(rdev, true);
 194                                 rdev->pm.current_mclk = mclk;
 195                                 DRM_DEBUG("Setting: m: %d\n", mclk);
 196                         }
 197                         radeon_pm_finish(rdev);
 198                 } else {
 199                         /* set engine clock */
 200                         if (sclk != rdev->pm.current_sclk) {
 201                                 radeon_sync_with_vblank(rdev);
 202                                 radeon_pm_prepare(rdev);
 203                                 radeon_set_engine_clock(rdev, sclk);
 204                                 radeon_pm_finish(rdev);
 205                                 rdev->pm.current_sclk = sclk;
 206                                 DRM_DEBUG("Setting: e: %d\n", sclk);
 207                         }
 208                         /* set memory clock */
 209                         if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 210                                 radeon_sync_with_vblank(rdev);
 211                                 radeon_pm_prepare(rdev);
 212                                 radeon_set_memory_clock(rdev, mclk);
 213                                 radeon_pm_finish(rdev);
 214                                 rdev->pm.current_mclk = mclk;
 215                                 DRM_DEBUG("Setting: m: %d\n", mclk);
 216                         }
 217                 }
 218
 219                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 220                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 221         } else
 222                 DRM_DEBUG("pm: GUI not idle!!!\n");
 223 }
 224
 225 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 226 {
 227         int i;
 228
 229         mutex_lock(&rdev->ddev->struct_mutex);
 230         mutex_lock(&rdev->vram_mutex);
 231         mutex_lock(&rdev->cp.mutex);
 232
 233         /* gui idle int has issues on older chips it seems */
 234         if (rdev->family >= CHIP_R600) {
 235                 if (rdev->irq.installed) {
 236                         /* wait for GPU idle */
 237                         rdev->pm.gui_idle = false;
 238                         rdev->irq.gui_idle = true;
 239                         radeon_irq_set(rdev);
 240                         wait_event_interruptible_timeout(
 241                                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 242                                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 243                         rdev->irq.gui_idle = false;
 244                         radeon_irq_set(rdev);
 245                 }
 246         } else {
 247                 if (rdev->cp.ready) {
 248                         struct radeon_fence *fence;
 249                         radeon_ring_alloc(rdev, 64);
 250                         radeon_fence_create(rdev, &fence);
 251                         radeon_fence_emit(rdev, fence);
 252                         radeon_ring_commit(rdev);
 253                         radeon_fence_wait(fence, false);
 254                         radeon_fence_unref(&fence);
 255                 }
 256         }
 257         radeon_unmap_vram_bos(rdev);
 258
 259         if (rdev->irq.installed) {
 260                 for (i = 0; i < rdev->num_crtc; i++) {
 261                         if (rdev->pm.active_crtcs & (1 << i)) {
 262                                 rdev->pm.req_vblank |= (1 << i);
 263                                 drm_vblank_get(rdev->ddev, i);
 264                         }
 265                 }
 266         }
 267
 268         radeon_set_power_state(rdev);
 269
 270         if (rdev->irq.installed) {
 271                 for (i = 0; i < rdev->num_crtc; i++) {
 272                         if (rdev->pm.req_vblank & (1 << i)) {
 273                                 rdev->pm.req_vblank &= ~(1 << i);
 274                                 drm_vblank_put(rdev->ddev, i);
 275                         }
 276                 }
 277         }
 278
 279         /* update display watermarks based on new power state */
 280         radeon_update_bandwidth_info(rdev);
 281         if (rdev->pm.active_crtc_count)
 282                 radeon_bandwidth_update(rdev);
 283
 284         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 285
 286         mutex_unlock(&rdev->cp.mutex);
 287         mutex_unlock(&rdev->vram_mutex);
 288         mutex_unlock(&rdev->ddev->struct_mutex);
 289 }
 290
 291 static ssize_t radeon_get_pm_profile(struct device *dev,
 292                                      struct device_attribute *attr,
 293                                      char *buf)
 294 {
 295         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 296         struct radeon_device *rdev = ddev->dev_private;
 297         int cp = rdev->pm.profile;
 298
 299         return snprintf(buf, PAGE_SIZE, "%s\n",
 300                         (cp == PM_PROFILE_AUTO) ? "auto" :
 301                         (cp == PM_PROFILE_LOW) ? "low" :
 302                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 303 }
 304
 305 static ssize_t radeon_set_pm_profile(struct device *dev,
 306                                      struct device_attribute *attr,
 307                                      const char *buf,
 308                                      size_t count)
 309 {
 310         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 311         struct radeon_device *rdev = ddev->dev_private;
 312
 313         mutex_lock(&rdev->pm.mutex);
 314         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 315                 if (strncmp("default", buf, strlen("default")) == 0)
 316                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 317                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 318                         rdev->pm.profile = PM_PROFILE_AUTO;
 319                 else if (strncmp("low", buf, strlen("low")) == 0)
 320                         rdev->pm.profile = PM_PROFILE_LOW;
 321                 else if (strncmp("high", buf, strlen("high")) == 0)
 322                         rdev->pm.profile = PM_PROFILE_HIGH;
 323                 else {
 324                         DRM_ERROR("invalid power profile!\n");
 325                         goto fail;
 326                 }
 327                 radeon_pm_update_profile(rdev);
 328                 radeon_pm_set_clocks(rdev);
 329         }
 330 fail:
 331         mutex_unlock(&rdev->pm.mutex);
 332
 333         return count;
 334 }
 335
 336 static ssize_t radeon_get_pm_method(struct device *dev,
 337                                     struct device_attribute *attr,
 338                                     char *buf)
 339 {
 340         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 341         struct radeon_device *rdev = ddev->dev_private;
 342         int pm = rdev->pm.pm_method;
 343
 344         return snprintf(buf, PAGE_SIZE, "%s\n",
 345                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 346 }
 347
 348 static ssize_t radeon_set_pm_method(struct device *dev,
 349                                     struct device_attribute *attr,
 350                                     const char *buf,
 351                                     size_t count)
 352 {
 353         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 354         struct radeon_device *rdev = ddev->dev_private;
 355
 356
 357         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 358                 mutex_lock(&rdev->pm.mutex);
 359                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 360                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 361                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 362                 mutex_unlock(&rdev->pm.mutex);
 363         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 364                 mutex_lock(&rdev->pm.mutex);
 365                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 366                 /* disable dynpm */
 367                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 368                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 369                 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 370                 mutex_unlock(&rdev->pm.mutex);
 371         } else {
 372                 DRM_ERROR("invalid power method!\n");
 373                 goto fail;
 374         }
 375         radeon_pm_compute_clocks(rdev);
 376 fail:
 377         return count;
 378 }
 379
 380 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 381 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 382
 383 void radeon_pm_suspend(struct radeon_device *rdev)
 384 {
 385         mutex_lock(&rdev->pm.mutex);
 386         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 387         rdev->pm.current_power_state_index = -1;
 388         rdev->pm.current_clock_mode_index = -1;
 389         rdev->pm.current_sclk = 0;
 390         rdev->pm.current_mclk = 0;
 391         mutex_unlock(&rdev->pm.mutex);
 392 }
 393
 394 void radeon_pm_resume(struct radeon_device *rdev)
 395 {
 396         radeon_pm_compute_clocks(rdev);
 397 }
 398
 399 int radeon_pm_init(struct radeon_device *rdev)
 400 {
 401         /* default to profile method */
 402         rdev->pm.pm_method = PM_METHOD_PROFILE;
 403         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 404         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 405         rdev->pm.dynpm_can_upclock = true;
 406         rdev->pm.dynpm_can_downclock = true;
 407         rdev->pm.current_sclk = 0;
 408         rdev->pm.current_mclk = 0;
 409
 410         if (rdev->bios) {
 411                 if (rdev->is_atom_bios)
 412                         radeon_atombios_get_power_modes(rdev);
 413                 else
 414                         radeon_combios_get_power_modes(rdev);
 415                 radeon_pm_init_profile(rdev);
 416                 rdev->pm.current_power_state_index = -1;
 417                 rdev->pm.current_clock_mode_index = -1;
 418         }
 419
 420         if (rdev->pm.num_power_states > 1) {
 421                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 422                         mutex_lock(&rdev->pm.mutex);
 423                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 424                         radeon_pm_update_profile(rdev);
 425                         radeon_pm_set_clocks(rdev);
 426                         mutex_unlock(&rdev->pm.mutex);
 427                 }
 428
 429                 /* where's the best place to put these? */
 430                 device_create_file(rdev->dev, &dev_attr_power_profile);
 431                 device_create_file(rdev->dev, &dev_attr_power_method);
 432
 433 #ifdef CONFIG_ACPI
 434                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
 435                 register_acpi_notifier(&rdev->acpi_nb);
 436 #endif
 437                 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 438
 439                 if (radeon_debugfs_pm_init(rdev)) {
 440                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 441                 }
 442
 443                 DRM_INFO("radeon: power management initialized\n");
 444         }
 445
 446         return 0;
 447 }
 448
 449 void radeon_pm_fini(struct radeon_device *rdev)
 450 {
 451         if (rdev->pm.num_power_states > 1) {
 452                 mutex_lock(&rdev->pm.mutex);
 453                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 454                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 455                         radeon_pm_update_profile(rdev);
 456                         radeon_pm_set_clocks(rdev);
 457                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 458                         /* cancel work */
 459                         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 460                         /* reset default clocks */
 461                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 462                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 463                         radeon_pm_set_clocks(rdev);
 464                 }
 465                 mutex_unlock(&rdev->pm.mutex);
 466
 467                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 468                 device_remove_file(rdev->dev, &dev_attr_power_method);
 469 #ifdef CONFIG_ACPI
 470                 unregister_acpi_notifier(&rdev->acpi_nb);
 471 #endif
 472         }
 473
 474         if (rdev->pm.i2c_bus)
 475                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 476 }
 477
 478 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 479 {
 480         struct drm_device *ddev = rdev->ddev;
 481         struct drm_crtc *crtc;
 482         struct radeon_crtc *radeon_crtc;
 483
 484         if (rdev->pm.num_power_states < 2)
 485                 return;
 486
 487         mutex_lock(&rdev->pm.mutex);
 488
 489         rdev->pm.active_crtcs = 0;
 490         rdev->pm.active_crtc_count = 0;
 491         list_for_each_entry(crtc,
 492                 &ddev->mode_config.crtc_list, head) {
 493                 radeon_crtc = to_radeon_crtc(crtc);
 494                 if (radeon_crtc->enabled) {
 495                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 496                         rdev->pm.active_crtc_count++;
 497                 }
 498         }
 499
 500         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 501                 radeon_pm_update_profile(rdev);
 502                 radeon_pm_set_clocks(rdev);
 503         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 504                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 505                         if (rdev->pm.active_crtc_count > 1) {
 506                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 507                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 508
 509                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 510                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 511                                         radeon_pm_get_dynpm_state(rdev);
 512                                         radeon_pm_set_clocks(rdev);
 513
 514                                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 515                                 }
 516                         } else if (rdev->pm.active_crtc_count == 1) {
 517                                 /* TODO: Increase clocks if needed for current mode */
 518
 519                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 520                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 521                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 522                                         radeon_pm_get_dynpm_state(rdev);
 523                                         radeon_pm_set_clocks(rdev);
 524
 525                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 526                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 527                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 528                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 529                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 530                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 531                                         DRM_DEBUG("radeon: dynamic power management activated\n");
 532                                 }
 533                         } else { /* count == 0 */
 534                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 535                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 536
 537                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 538                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 539                                         radeon_pm_get_dynpm_state(rdev);
 540                                         radeon_pm_set_clocks(rdev);
 541                                 }
 542                         }
 543                 }
 544         }
 545
 546         mutex_unlock(&rdev->pm.mutex);
 547 }
 548
 549 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 550 {
 551         u32 stat_crtc = 0, vbl = 0, position = 0;
 552         bool in_vbl = true;
 553
 554         if (ASIC_IS_DCE4(rdev)) {
 555                 if (rdev->pm.active_crtcs & (1 << 0)) {
 556                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 557                                      EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 558                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 559                                           EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 560                 }
 561                 if (rdev->pm.active_crtcs & (1 << 1)) {
 562                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 563                                      EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 564                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 565                                           EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 566                 }
 567                 if (rdev->pm.active_crtcs & (1 << 2)) {
 568                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 569                                      EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 570                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 571                                           EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 572                 }
 573                 if (rdev->pm.active_crtcs & (1 << 3)) {
 574                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 575                                      EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 576                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 577                                           EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 578                 }
 579                 if (rdev->pm.active_crtcs & (1 << 4)) {
 580                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 581                                      EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 582                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 583                                           EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 584                 }
 585                 if (rdev->pm.active_crtcs & (1 << 5)) {
 586                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 587                                      EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 588                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 589                                           EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 590                 }
 591         } else if (ASIC_IS_AVIVO(rdev)) {
 592                 if (rdev->pm.active_crtcs & (1 << 0)) {
 593                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
 594                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
 595                 }
 596                 if (rdev->pm.active_crtcs & (1 << 1)) {
 597                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
 598                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
 599                 }
 600                 if (position < vbl && position > 1)
 601                         in_vbl = false;
 602         } else {
 603                 if (rdev->pm.active_crtcs & (1 << 0)) {
 604                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 605                         if (!(stat_crtc & 1))
 606                                 in_vbl = false;
 607                 }
 608                 if (rdev->pm.active_crtcs & (1 << 1)) {
 609                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 610                         if (!(stat_crtc & 1))
 611                                 in_vbl = false;
 612                 }
 613         }
 614
 615         if (position < vbl && position > 1)
 616                 in_vbl = false;
 617
 618         return in_vbl;
 619 }
 620
 621 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 622 {
 623         u32 stat_crtc = 0;
 624         bool in_vbl = radeon_pm_in_vbl(rdev);
 625
 626         if (in_vbl == false)
 627                 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
 628                          finish ? "exit" : "entry");
 629         return in_vbl;
 630 }
 631
 632 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 633 {
 634         struct radeon_device *rdev;
 635         int resched;
 636         rdev = container_of(work, struct radeon_device,
 637                                 pm.dynpm_idle_work.work);
 638
 639         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 640         mutex_lock(&rdev->pm.mutex);
 641         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 642                 unsigned long irq_flags;
 643                 int not_processed = 0;
 644
 645                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 646                 if (!list_empty(&rdev->fence_drv.emited)) {
 647                         struct list_head *ptr;
 648                         list_for_each(ptr, &rdev->fence_drv.emited) {
 649                                 /* count up to 3, that's enought info */
 650                                 if (++not_processed >= 3)
 651                                         break;
 652                         }
 653                 }
 654                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 655
 656                 if (not_processed >= 3) { /* should upclock */
 657                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 658                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 659                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 660                                    rdev->pm.dynpm_can_upclock) {
 661                                 rdev->pm.dynpm_planned_action =
 662                                         DYNPM_ACTION_UPCLOCK;
 663                                 rdev->pm.dynpm_action_timeout = jiffies +
 664                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 665                         }
 666                 } else if (not_processed == 0) { /* should downclock */
 667                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 668                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 669                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 670                                    rdev->pm.dynpm_can_downclock) {
 671                                 rdev->pm.dynpm_planned_action =
 672                                         DYNPM_ACTION_DOWNCLOCK;
 673                                 rdev->pm.dynpm_action_timeout = jiffies +
 674                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 675                         }
 676                 }
 677
 678                 /* Note, radeon_pm_set_clocks is called with static_switch set
 679                  * to false since we want to wait for vbl to avoid flicker.
 680                  */
 681                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 682                     jiffies > rdev->pm.dynpm_action_timeout) {
 683                         radeon_pm_get_dynpm_state(rdev);
 684                         radeon_pm_set_clocks(rdev);
 685                 }
 686         }
 687         mutex_unlock(&rdev->pm.mutex);
 688         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 689
 690         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 691                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 692 }
 693
 694 /*
 695  * Debugfs info
 696  */
 697 #if defined(CONFIG_DEBUG_FS)
 698
 699 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 700 {
 701         struct drm_info_node *node = (struct drm_info_node *) m->private;
 702         struct drm_device *dev = node->minor->dev;
 703         struct radeon_device *rdev = dev->dev_private;
 704
 705         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 706         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 707         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 708         if (rdev->asic->get_memory_clock)
 709                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 710         if (rdev->asic->get_pcie_lanes)
 711                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 712
 713         return 0;
 714 }
 715
 716 static struct drm_info_list radeon_pm_info_list[] = {
 717         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 718 };
 719 #endif
 720
 721 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 722 {
 723 #if defined(CONFIG_DEBUG_FS)
 724         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 725 #else
 726         return 0;
 727 #endif
 728 }