2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
27 #define RADEON_IDLE_LOOP_MS 100
28 #define RADEON_RECLOCK_DELAY_MS 200
29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
30 #define RADEON_WAIT_IDLE_TIMEOUT 200
32 static void radeon_pm_idle_work_handler(struct work_struct *work);
33 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
35 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
37 struct radeon_bo *bo, *n;
39 if (list_empty(&rdev->gem.objects))
42 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
43 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
44 ttm_bo_unmap_virtual(&bo->tbo);
47 if (rdev->gart.table.vram.robj)
48 ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
50 if (rdev->stollen_vga_memory)
51 ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
53 if (rdev->r600_blit.shader_obj)
54 ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
57 static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
61 if (rdev->pm.state != PM_STATE_DISABLED)
62 radeon_get_power_state(rdev, rdev->pm.planned_action);
64 mutex_lock(&rdev->ddev->struct_mutex);
65 mutex_lock(&rdev->vram_mutex);
66 mutex_lock(&rdev->cp.mutex);
68 /* gui idle int has issues on older chips it seems */
69 if (rdev->family >= CHIP_R600) {
70 /* wait for GPU idle */
71 rdev->pm.gui_idle = false;
72 rdev->irq.gui_idle = true;
74 wait_event_interruptible_timeout(
75 rdev->irq.idle_queue, rdev->pm.gui_idle,
76 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
77 rdev->irq.gui_idle = false;
80 struct radeon_fence *fence;
81 radeon_ring_alloc(rdev, 64);
82 radeon_fence_create(rdev, &fence);
83 radeon_fence_emit(rdev, fence);
84 radeon_ring_commit(rdev);
85 radeon_fence_wait(fence, false);
86 radeon_fence_unref(&fence);
88 radeon_unmap_vram_bos(rdev);
91 for (i = 0; i < rdev->num_crtc; i++) {
92 if (rdev->pm.active_crtcs & (1 << i)) {
93 rdev->pm.req_vblank |= (1 << i);
94 drm_vblank_get(rdev->ddev, i);
99 radeon_set_power_state(rdev, static_switch);
101 if (!static_switch) {
102 for (i = 0; i < rdev->num_crtc; i++) {
103 if (rdev->pm.req_vblank & (1 << i)) {
104 rdev->pm.req_vblank &= ~(1 << i);
105 drm_vblank_put(rdev->ddev, i);
110 /* update display watermarks based on new power state */
111 radeon_update_bandwidth_info(rdev);
112 if (rdev->pm.active_crtc_count)
113 radeon_bandwidth_update(rdev);
115 rdev->pm.planned_action = PM_ACTION_NONE;
117 mutex_unlock(&rdev->cp.mutex);
118 mutex_unlock(&rdev->vram_mutex);
119 mutex_unlock(&rdev->ddev->struct_mutex);
122 static ssize_t radeon_get_power_state_static(struct device *dev,
123 struct device_attribute *attr,
126 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
127 struct radeon_device *rdev = ddev->dev_private;
129 return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
130 rdev->pm.current_clock_mode_index);
133 static ssize_t radeon_set_power_state_static(struct device *dev,
134 struct device_attribute *attr,
138 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
139 struct radeon_device *rdev = ddev->dev_private;
142 if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
143 DRM_ERROR("Invalid power state!\n");
147 mutex_lock(&rdev->pm.mutex);
148 if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
149 (cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
150 if ((rdev->pm.active_crtc_count > 0) &&
151 (rdev->pm.power_state[ps].clock_info[cm].flags & RADEON_PM_MODE_NO_DISPLAY)) {
152 DRM_ERROR("Invalid power state for display: %d.%d\n", ps, cm);
153 } else if ((rdev->pm.active_crtc_count > 1) &&
154 (rdev->pm.power_state[ps].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)) {
155 DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
158 rdev->pm.state = PM_STATE_DISABLED;
159 rdev->pm.planned_action = PM_ACTION_NONE;
160 rdev->pm.requested_power_state_index = ps;
161 rdev->pm.requested_clock_mode_index = cm;
162 radeon_pm_set_clocks(rdev, true);
165 DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
166 mutex_unlock(&rdev->pm.mutex);
171 static ssize_t radeon_get_dynpm(struct device *dev,
172 struct device_attribute *attr,
175 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
176 struct radeon_device *rdev = ddev->dev_private;
178 return snprintf(buf, PAGE_SIZE, "%s\n",
179 (rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
182 static ssize_t radeon_set_dynpm(struct device *dev,
183 struct device_attribute *attr,
187 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
188 struct radeon_device *rdev = ddev->dev_private;
189 int tmp = simple_strtoul(buf, NULL, 10);
192 /* update power mode info */
193 radeon_pm_compute_clocks(rdev);
195 mutex_lock(&rdev->pm.mutex);
196 rdev->pm.state = PM_STATE_DISABLED;
197 rdev->pm.planned_action = PM_ACTION_NONE;
198 mutex_unlock(&rdev->pm.mutex);
199 DRM_INFO("radeon: dynamic power management disabled\n");
200 } else if (tmp == 1) {
201 if (rdev->pm.num_power_states > 1) {
203 mutex_lock(&rdev->pm.mutex);
204 rdev->pm.state = PM_STATE_PAUSED;
205 rdev->pm.planned_action = PM_ACTION_DEFAULT;
206 radeon_get_power_state(rdev, rdev->pm.planned_action);
207 mutex_unlock(&rdev->pm.mutex);
208 /* update power mode info */
209 radeon_pm_compute_clocks(rdev);
210 DRM_INFO("radeon: dynamic power management enabled\n");
212 DRM_ERROR("dynpm not valid on this system\n");
214 DRM_ERROR("Invalid setting: %d\n", tmp);
219 static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
220 static DEVICE_ATTR(dynpm, S_IRUGO | S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);
223 static const char *pm_state_names[4] = {
230 static const char *pm_state_types[5] = {
238 static void radeon_print_power_mode_info(struct radeon_device *rdev)
243 DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
244 for (i = 0; i < rdev->pm.num_power_states; i++) {
245 if (rdev->pm.default_power_state_index == i)
249 DRM_INFO("State %d %s %s\n", i,
250 pm_state_types[rdev->pm.power_state[i].type],
251 is_default ? "(default)" : "");
252 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
253 DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
254 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
255 DRM_INFO("\tSingle display only\n");
256 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
257 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
258 if (rdev->flags & RADEON_IS_IGP)
259 DRM_INFO("\t\t%d engine: %d\n",
261 rdev->pm.power_state[i].clock_info[j].sclk * 10);
263 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
265 rdev->pm.power_state[i].clock_info[j].sclk * 10,
266 rdev->pm.power_state[i].clock_info[j].mclk * 10);
267 if (rdev->pm.power_state[i].clock_info[j].flags & RADEON_PM_MODE_NO_DISPLAY)
268 DRM_INFO("\t\tNo display only\n");
273 void radeon_sync_with_vblank(struct radeon_device *rdev)
275 if (rdev->pm.active_crtcs) {
276 rdev->pm.vblank_sync = false;
278 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
279 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
283 int radeon_pm_init(struct radeon_device *rdev)
285 rdev->pm.state = PM_STATE_DISABLED;
286 rdev->pm.planned_action = PM_ACTION_NONE;
287 rdev->pm.can_upclock = true;
288 rdev->pm.can_downclock = true;
291 if (rdev->is_atom_bios)
292 radeon_atombios_get_power_modes(rdev);
294 radeon_combios_get_power_modes(rdev);
295 radeon_print_power_mode_info(rdev);
298 if (radeon_debugfs_pm_init(rdev)) {
299 DRM_ERROR("Failed to register debugfs file for PM!\n");
302 /* where's the best place to put this? */
303 device_create_file(rdev->dev, &dev_attr_power_state);
304 device_create_file(rdev->dev, &dev_attr_dynpm);
306 INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
308 if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
309 rdev->pm.state = PM_STATE_PAUSED;
310 DRM_INFO("radeon: dynamic power management enabled\n");
313 DRM_INFO("radeon: power management initialized\n");
318 void radeon_pm_fini(struct radeon_device *rdev)
320 if (rdev->pm.state != PM_STATE_DISABLED) {
322 cancel_delayed_work_sync(&rdev->pm.idle_work);
323 /* reset default clocks */
324 rdev->pm.state = PM_STATE_DISABLED;
325 rdev->pm.planned_action = PM_ACTION_DEFAULT;
326 radeon_pm_set_clocks(rdev, true);
327 } else if ((rdev->pm.current_power_state_index !=
328 rdev->pm.default_power_state_index) ||
329 (rdev->pm.current_clock_mode_index != 0)) {
330 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
331 rdev->pm.requested_clock_mode_index = 0;
332 mutex_lock(&rdev->pm.mutex);
333 radeon_pm_set_clocks(rdev, true);
334 mutex_unlock(&rdev->pm.mutex);
337 device_remove_file(rdev->dev, &dev_attr_power_state);
338 device_remove_file(rdev->dev, &dev_attr_dynpm);
340 if (rdev->pm.i2c_bus)
341 radeon_i2c_destroy(rdev->pm.i2c_bus);
344 void radeon_pm_compute_clocks(struct radeon_device *rdev)
346 struct drm_device *ddev = rdev->ddev;
347 struct drm_crtc *crtc;
348 struct radeon_crtc *radeon_crtc;
350 mutex_lock(&rdev->pm.mutex);
352 rdev->pm.active_crtcs = 0;
353 rdev->pm.active_crtc_count = 0;
354 list_for_each_entry(crtc,
355 &ddev->mode_config.crtc_list, head) {
356 radeon_crtc = to_radeon_crtc(crtc);
357 if (radeon_crtc->enabled) {
358 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
359 rdev->pm.active_crtc_count++;
363 if (rdev->pm.state == PM_STATE_DISABLED) {
364 mutex_unlock(&rdev->pm.mutex);
368 /* Note, radeon_pm_set_clocks is called with static_switch set
369 * to true since we always want to statically set the clocks,
372 if (rdev->pm.active_crtc_count > 1) {
373 if (rdev->pm.state == PM_STATE_ACTIVE) {
374 cancel_delayed_work(&rdev->pm.idle_work);
376 rdev->pm.state = PM_STATE_PAUSED;
377 rdev->pm.planned_action = PM_ACTION_DEFAULT;
378 radeon_pm_set_clocks(rdev, true);
380 DRM_DEBUG("radeon: dynamic power management deactivated\n");
382 } else if (rdev->pm.active_crtc_count == 1) {
383 /* TODO: Increase clocks if needed for current mode */
385 if (rdev->pm.state == PM_STATE_MINIMUM) {
386 rdev->pm.state = PM_STATE_ACTIVE;
387 rdev->pm.planned_action = PM_ACTION_UPCLOCK;
388 radeon_pm_set_clocks(rdev, true);
390 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
391 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
392 } else if (rdev->pm.state == PM_STATE_PAUSED) {
393 rdev->pm.state = PM_STATE_ACTIVE;
394 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
395 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
396 DRM_DEBUG("radeon: dynamic power management activated\n");
398 } else { /* count == 0 */
399 if (rdev->pm.state != PM_STATE_MINIMUM) {
400 cancel_delayed_work(&rdev->pm.idle_work);
402 rdev->pm.state = PM_STATE_MINIMUM;
403 rdev->pm.planned_action = PM_ACTION_MINIMUM;
404 radeon_pm_set_clocks(rdev, true);
408 mutex_unlock(&rdev->pm.mutex);
411 bool radeon_pm_in_vbl(struct radeon_device *rdev)
413 u32 stat_crtc = 0, vbl = 0, position = 0;
416 if (ASIC_IS_DCE4(rdev)) {
417 if (rdev->pm.active_crtcs & (1 << 0)) {
418 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
419 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
420 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
421 EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
423 if (rdev->pm.active_crtcs & (1 << 1)) {
424 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
425 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
426 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
427 EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
429 if (rdev->pm.active_crtcs & (1 << 2)) {
430 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
431 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
432 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
433 EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
435 if (rdev->pm.active_crtcs & (1 << 3)) {
436 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
437 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
438 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
439 EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
441 if (rdev->pm.active_crtcs & (1 << 4)) {
442 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
443 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
444 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
445 EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
447 if (rdev->pm.active_crtcs & (1 << 5)) {
448 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
449 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
450 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
451 EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
453 } else if (ASIC_IS_AVIVO(rdev)) {
454 if (rdev->pm.active_crtcs & (1 << 0)) {
455 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
456 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
458 if (rdev->pm.active_crtcs & (1 << 1)) {
459 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
460 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
462 if (position < vbl && position > 1)
465 if (rdev->pm.active_crtcs & (1 << 0)) {
466 stat_crtc = RREG32(RADEON_CRTC_STATUS);
467 if (!(stat_crtc & 1))
470 if (rdev->pm.active_crtcs & (1 << 1)) {
471 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
472 if (!(stat_crtc & 1))
477 if (position < vbl && position > 1)
483 bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
486 bool in_vbl = radeon_pm_in_vbl(rdev);
489 DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
490 finish ? "exit" : "entry");
494 static void radeon_pm_idle_work_handler(struct work_struct *work)
496 struct radeon_device *rdev;
498 rdev = container_of(work, struct radeon_device,
501 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
502 mutex_lock(&rdev->pm.mutex);
503 if (rdev->pm.state == PM_STATE_ACTIVE) {
504 unsigned long irq_flags;
505 int not_processed = 0;
507 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
508 if (!list_empty(&rdev->fence_drv.emited)) {
509 struct list_head *ptr;
510 list_for_each(ptr, &rdev->fence_drv.emited) {
511 /* count up to 3, that's enought info */
512 if (++not_processed >= 3)
516 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
518 if (not_processed >= 3) { /* should upclock */
519 if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
520 rdev->pm.planned_action = PM_ACTION_NONE;
521 } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
522 rdev->pm.can_upclock) {
523 rdev->pm.planned_action =
525 rdev->pm.action_timeout = jiffies +
526 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
528 } else if (not_processed == 0) { /* should downclock */
529 if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
530 rdev->pm.planned_action = PM_ACTION_NONE;
531 } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
532 rdev->pm.can_downclock) {
533 rdev->pm.planned_action =
535 rdev->pm.action_timeout = jiffies +
536 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
540 /* Note, radeon_pm_set_clocks is called with static_switch set
541 * to false since we want to wait for vbl to avoid flicker.
543 if (rdev->pm.planned_action != PM_ACTION_NONE &&
544 jiffies > rdev->pm.action_timeout) {
545 radeon_pm_set_clocks(rdev, false);
548 mutex_unlock(&rdev->pm.mutex);
549 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
551 queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
552 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
558 #if defined(CONFIG_DEBUG_FS)
560 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
562 struct drm_info_node *node = (struct drm_info_node *) m->private;
563 struct drm_device *dev = node->minor->dev;
564 struct radeon_device *rdev = dev->dev_private;
566 seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
567 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
568 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
569 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
570 if (rdev->asic->get_memory_clock)
571 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
572 if (rdev->asic->get_pcie_lanes)
573 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
578 static struct drm_info_list radeon_pm_info_list[] = {
579 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
583 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
585 #if defined(CONFIG_DEBUG_FS)
586 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));