2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/kernel.h>
32 #include "r600_reg_safe.h"
34 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
35 struct radeon_cs_reloc **cs_reloc);
36 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38 typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39 static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
40 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
43 struct r600_cs_track {
44 /* configuration we miror so that we use same code btw kms/ums */
52 u32 cb_color_base_last[8];
53 struct radeon_bo *cb_color_bo[8];
54 u64 cb_color_bo_mc[8];
55 u64 cb_color_bo_offset[8];
56 struct radeon_bo *cb_color_frag_bo[8];
57 u64 cb_color_frag_offset[8];
58 struct radeon_bo *cb_color_tile_bo[8];
59 u64 cb_color_tile_offset[8];
63 u32 cb_color_size_idx[8]; /* unused */
65 u32 cb_shader_mask; /* unused */
68 u32 vgt_strmout_buffer_en;
69 struct radeon_bo *vgt_strmout_bo[4];
70 u64 vgt_strmout_bo_mc[4]; /* unused */
71 u32 vgt_strmout_bo_offset[4];
72 u32 vgt_strmout_size[4];
75 u32 db_depth_size_idx;
79 struct radeon_bo *db_bo;
81 bool sx_misc_kill_all_prims;
85 struct radeon_bo *htile_bo;
90 #define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
91 #define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
92 #define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }
93 #define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
94 #define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }
95 #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
96 #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
97 #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
101 unsigned blockheight;
103 unsigned valid_color;
104 enum radeon_family min_family;
107 static const struct gpu_formats color_formats_table[] = {
109 FMT_8_BIT(V_038004_COLOR_8, 1),
110 FMT_8_BIT(V_038004_COLOR_4_4, 1),
111 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),
112 FMT_8_BIT(V_038004_FMT_1, 0),
115 FMT_16_BIT(V_038004_COLOR_16, 1),
116 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),
117 FMT_16_BIT(V_038004_COLOR_8_8, 1),
118 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),
119 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),
120 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),
121 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),
122 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),
125 FMT_24_BIT(V_038004_FMT_8_8_8),
128 FMT_32_BIT(V_038004_COLOR_32, 1),
129 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),
130 FMT_32_BIT(V_038004_COLOR_16_16, 1),
131 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),
132 FMT_32_BIT(V_038004_COLOR_8_24, 1),
133 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),
134 FMT_32_BIT(V_038004_COLOR_24_8, 1),
135 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),
136 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),
137 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),
138 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),
139 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),
140 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),
141 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),
142 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),
143 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),
144 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),
145 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),
148 FMT_48_BIT(V_038004_FMT_16_16_16),
149 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),
152 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),
153 FMT_64_BIT(V_038004_COLOR_32_32, 1),
154 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),
155 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),
156 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),
158 FMT_96_BIT(V_038004_FMT_32_32_32),
159 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),
162 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),
163 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),
165 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },
166 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },
168 /* block compressed formats */
169 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },
170 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },
171 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
172 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
173 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
174 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
175 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
177 /* The other Evergreen formats */
178 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
181 bool r600_fmt_is_valid_color(u32 format)
183 if (format >= ARRAY_SIZE(color_formats_table))
186 if (color_formats_table[format].valid_color)
192 bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)
194 if (format >= ARRAY_SIZE(color_formats_table))
197 if (family < color_formats_table[format].min_family)
200 if (color_formats_table[format].blockwidth > 0)
206 int r600_fmt_get_blocksize(u32 format)
208 if (format >= ARRAY_SIZE(color_formats_table))
211 return color_formats_table[format].blocksize;
214 int r600_fmt_get_nblocksx(u32 format, u32 w)
218 if (format >= ARRAY_SIZE(color_formats_table))
221 bw = color_formats_table[format].blockwidth;
225 return (w + bw - 1) / bw;
228 int r600_fmt_get_nblocksy(u32 format, u32 h)
232 if (format >= ARRAY_SIZE(color_formats_table))
235 bh = color_formats_table[format].blockheight;
239 return (h + bh - 1) / bh;
242 struct array_mode_checker {
251 /* returns alignment in pixels for pitch/height/depth and bytes for base */
252 static int r600_get_array_mode_alignment(struct array_mode_checker *values,
260 u32 macro_tile_width = values->nbanks;
261 u32 macro_tile_height = values->npipes;
262 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;
263 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;
265 switch (values->array_mode) {
266 case ARRAY_LINEAR_GENERAL:
267 /* technically tile_width/_height for pitch/height */
268 *pitch_align = 1; /* tile_width */
269 *height_align = 1; /* tile_height */
273 case ARRAY_LINEAR_ALIGNED:
274 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));
277 *base_align = values->group_size;
279 case ARRAY_1D_TILED_THIN1:
280 *pitch_align = max((u32)tile_width,
281 (u32)(values->group_size /
282 (tile_height * values->blocksize * values->nsamples)));
283 *height_align = tile_height;
285 *base_align = values->group_size;
287 case ARRAY_2D_TILED_THIN1:
288 *pitch_align = max((u32)macro_tile_width * tile_width,
289 (u32)((values->group_size * values->nbanks) /
290 (values->blocksize * values->nsamples * tile_width)));
291 *height_align = macro_tile_height * tile_height;
293 *base_align = max(macro_tile_bytes,
294 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);
303 static void r600_cs_track_init(struct r600_cs_track *track)
307 /* assume DX9 mode */
308 track->sq_config = DX9_CONSTS;
309 for (i = 0; i < 8; i++) {
310 track->cb_color_base_last[i] = 0;
311 track->cb_color_size[i] = 0;
312 track->cb_color_size_idx[i] = 0;
313 track->cb_color_info[i] = 0;
314 track->cb_color_view[i] = 0xFFFFFFFF;
315 track->cb_color_bo[i] = NULL;
316 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
317 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
318 track->cb_color_frag_bo[i] = NULL;
319 track->cb_color_frag_offset[i] = 0xFFFFFFFF;
320 track->cb_color_tile_bo[i] = NULL;
321 track->cb_color_tile_offset[i] = 0xFFFFFFFF;
322 track->cb_color_mask[i] = 0xFFFFFFFF;
324 track->nsamples = 16;
325 track->log_nsamples = 4;
326 track->cb_target_mask = 0xFFFFFFFF;
327 track->cb_shader_mask = 0xFFFFFFFF;
328 track->cb_dirty = true;
330 track->db_bo_mc = 0xFFFFFFFF;
331 /* assume the biggest format and that htile is enabled */
332 track->db_depth_info = 7 | (1 << 25);
333 track->db_depth_view = 0xFFFFC000;
334 track->db_depth_size = 0xFFFFFFFF;
335 track->db_depth_size_idx = 0;
336 track->db_depth_control = 0xFFFFFFFF;
337 track->db_dirty = true;
338 track->htile_bo = NULL;
339 track->htile_offset = 0xFFFFFFFF;
340 track->htile_surface = 0;
342 for (i = 0; i < 4; i++) {
343 track->vgt_strmout_size[i] = 0;
344 track->vgt_strmout_bo[i] = NULL;
345 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
346 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
348 track->streamout_dirty = true;
349 track->sx_misc_kill_all_prims = false;
352 static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
354 struct r600_cs_track *track = p->track;
355 u32 slice_tile_max, size, tmp;
356 u32 height, height_align, pitch, pitch_align, depth_align;
357 u64 base_offset, base_align;
358 struct array_mode_checker array_check;
359 volatile u32 *ib = p->ib.ptr;
363 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
364 format = G_0280A0_FORMAT(track->cb_color_info[i]);
365 if (!r600_fmt_is_valid_color(format)) {
366 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",
367 __func__, __LINE__, format,
368 i, track->cb_color_info[i]);
371 /* pitch in pixels */
372 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;
373 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;
374 slice_tile_max *= 64;
375 height = slice_tile_max / pitch;
378 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);
380 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];
381 array_check.array_mode = array_mode;
382 array_check.group_size = track->group_size;
383 array_check.nbanks = track->nbanks;
384 array_check.npipes = track->npipes;
385 array_check.nsamples = track->nsamples;
386 array_check.blocksize = r600_fmt_get_blocksize(format);
387 if (r600_get_array_mode_alignment(&array_check,
388 &pitch_align, &height_align, &depth_align, &base_align)) {
389 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
390 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
391 track->cb_color_info[i]);
394 switch (array_mode) {
395 case V_0280A0_ARRAY_LINEAR_GENERAL:
397 case V_0280A0_ARRAY_LINEAR_ALIGNED:
399 case V_0280A0_ARRAY_1D_TILED_THIN1:
400 /* avoid breaking userspace */
404 case V_0280A0_ARRAY_2D_TILED_THIN1:
407 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,
408 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,
409 track->cb_color_info[i]);
413 if (!IS_ALIGNED(pitch, pitch_align)) {
414 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",
415 __func__, __LINE__, pitch, pitch_align, array_mode);
418 if (!IS_ALIGNED(height, height_align)) {
419 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",
420 __func__, __LINE__, height, height_align, array_mode);
423 if (!IS_ALIGNED(base_offset, base_align)) {
424 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,
425 base_offset, base_align, array_mode);
430 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
431 r600_fmt_get_blocksize(format) * track->nsamples;
432 switch (array_mode) {
434 case V_0280A0_ARRAY_LINEAR_GENERAL:
435 case V_0280A0_ARRAY_LINEAR_ALIGNED:
436 tmp += track->cb_color_view[i] & 0xFF;
438 case V_0280A0_ARRAY_1D_TILED_THIN1:
439 case V_0280A0_ARRAY_2D_TILED_THIN1:
440 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;
443 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {
444 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {
445 /* the initial DDX does bad things with the CB size occasionally */
446 /* it rounds up height too far for slice tile max but the BO is smaller */
447 /* r600c,g also seem to flush at bad times in some apps resulting in
448 * bogus values here. So for linear just allow anything to avoid breaking
452 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
453 __func__, i, array_mode,
454 track->cb_color_bo_offset[i], tmp,
455 radeon_bo_size(track->cb_color_bo[i]),
456 pitch, height, r600_fmt_get_nblocksx(format, pitch),
457 r600_fmt_get_nblocksy(format, height),
458 r600_fmt_get_blocksize(format));
463 tmp = (height * pitch) >> 6;
464 if (tmp < slice_tile_max)
465 slice_tile_max = tmp;
466 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
467 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
468 ib[track->cb_color_size_idx[i]] = tmp;
471 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
472 case V_0280A0_TILE_DISABLE:
474 case V_0280A0_FRAG_ENABLE:
475 if (track->nsamples > 1) {
476 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
477 /* the tile size is 8x8, but the size is in units of bits.
478 * for bytes, do just * 8. */
479 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
481 if (bytes + track->cb_color_frag_offset[i] >
482 radeon_bo_size(track->cb_color_frag_bo[i])) {
483 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
484 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
485 __func__, tile_max, bytes,
486 track->cb_color_frag_offset[i],
487 radeon_bo_size(track->cb_color_frag_bo[i]));
492 case V_0280A0_CLEAR_ENABLE:
494 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
495 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
496 * (128*128) / (8*8) / 2 = 128 bytes per block. */
497 uint32_t bytes = (block_max + 1) * 128;
499 if (bytes + track->cb_color_tile_offset[i] >
500 radeon_bo_size(track->cb_color_tile_bo[i])) {
501 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
502 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
503 __func__, block_max, bytes,
504 track->cb_color_tile_offset[i],
505 radeon_bo_size(track->cb_color_tile_bo[i]));
511 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
517 static int r600_cs_track_validate_db(struct radeon_cs_parser *p)
519 struct r600_cs_track *track = p->track;
520 u32 nviews, bpe, ntiles, size, slice_tile_max, tmp;
521 u32 height_align, pitch_align, depth_align;
524 u64 base_offset, base_align;
525 struct array_mode_checker array_check;
527 volatile u32 *ib = p->ib.ptr;
530 if (track->db_bo == NULL) {
531 dev_warn(p->dev, "z/stencil with no depth buffer\n");
534 switch (G_028010_FORMAT(track->db_depth_info)) {
535 case V_028010_DEPTH_16:
538 case V_028010_DEPTH_X8_24:
539 case V_028010_DEPTH_8_24:
540 case V_028010_DEPTH_X8_24_FLOAT:
541 case V_028010_DEPTH_8_24_FLOAT:
542 case V_028010_DEPTH_32_FLOAT:
545 case V_028010_DEPTH_X24_8_32_FLOAT:
549 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));
552 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
553 if (!track->db_depth_size_idx) {
554 dev_warn(p->dev, "z/stencil buffer size not set\n");
557 tmp = radeon_bo_size(track->db_bo) - track->db_offset;
558 tmp = (tmp / bpe) >> 6;
560 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",
561 track->db_depth_size, bpe, track->db_offset,
562 radeon_bo_size(track->db_bo));
565 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);
567 size = radeon_bo_size(track->db_bo);
568 /* pitch in pixels */
569 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;
570 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
571 slice_tile_max *= 64;
572 height = slice_tile_max / pitch;
575 base_offset = track->db_bo_mc + track->db_offset;
576 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);
577 array_check.array_mode = array_mode;
578 array_check.group_size = track->group_size;
579 array_check.nbanks = track->nbanks;
580 array_check.npipes = track->npipes;
581 array_check.nsamples = track->nsamples;
582 array_check.blocksize = bpe;
583 if (r600_get_array_mode_alignment(&array_check,
584 &pitch_align, &height_align, &depth_align, &base_align)) {
585 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
586 G_028010_ARRAY_MODE(track->db_depth_info),
587 track->db_depth_info);
590 switch (array_mode) {
591 case V_028010_ARRAY_1D_TILED_THIN1:
592 /* don't break userspace */
595 case V_028010_ARRAY_2D_TILED_THIN1:
598 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,
599 G_028010_ARRAY_MODE(track->db_depth_info),
600 track->db_depth_info);
604 if (!IS_ALIGNED(pitch, pitch_align)) {
605 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",
606 __func__, __LINE__, pitch, pitch_align, array_mode);
609 if (!IS_ALIGNED(height, height_align)) {
610 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",
611 __func__, __LINE__, height, height_align, array_mode);
614 if (!IS_ALIGNED(base_offset, base_align)) {
615 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,
616 base_offset, base_align, array_mode);
620 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;
621 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;
622 tmp = ntiles * bpe * 64 * nviews * track->nsamples;
623 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {
624 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",
626 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,
627 radeon_bo_size(track->db_bo));
633 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {
637 if (track->htile_bo == NULL) {
638 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",
639 __func__, __LINE__, track->db_depth_info);
642 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {
643 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",
644 __func__, __LINE__, track->db_depth_size);
650 if (G_028D24_LINEAR(track->htile_surface)) {
651 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */
652 nbx = round_up(nbx, 16 * 8);
653 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */
654 nby = round_up(nby, track->npipes * 8);
656 /* htile widht & nby (8 or 4) make 2 bits number */
657 tmp = track->htile_surface & 3;
658 /* align is htile align * 8, htile align vary according to
659 * number of pipe and tile width and nby
661 switch (track->npipes) {
664 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
665 nbx = round_up(nbx, 64 * 8);
666 nby = round_up(nby, 64 * 8);
668 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
669 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
670 nbx = round_up(nbx, 64 * 8);
671 nby = round_up(nby, 32 * 8);
673 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
674 nbx = round_up(nbx, 32 * 8);
675 nby = round_up(nby, 32 * 8);
683 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
684 nbx = round_up(nbx, 64 * 8);
685 nby = round_up(nby, 32 * 8);
687 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
688 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
689 nbx = round_up(nbx, 32 * 8);
690 nby = round_up(nby, 32 * 8);
692 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
693 nbx = round_up(nbx, 32 * 8);
694 nby = round_up(nby, 16 * 8);
702 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
703 nbx = round_up(nbx, 32 * 8);
704 nby = round_up(nby, 32 * 8);
706 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
707 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
708 nbx = round_up(nbx, 32 * 8);
709 nby = round_up(nby, 16 * 8);
711 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
712 nbx = round_up(nbx, 16 * 8);
713 nby = round_up(nby, 16 * 8);
721 case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
722 nbx = round_up(nbx, 32 * 8);
723 nby = round_up(nby, 16 * 8);
725 case 2: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 8*/
726 case 1: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 4*/
727 nbx = round_up(nbx, 16 * 8);
728 nby = round_up(nby, 16 * 8);
730 case 0: /* HTILE_WIDTH = 4 & HTILE_HEIGHT = 4*/
731 nbx = round_up(nbx, 16 * 8);
732 nby = round_up(nby, 8 * 8);
739 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",
740 __func__, __LINE__, track->npipes);
744 /* compute number of htile */
745 nbx = G_028D24_HTILE_WIDTH(track->htile_surface) ? nbx / 8 : nbx / 4;
746 nby = G_028D24_HTILE_HEIGHT(track->htile_surface) ? nby / 8 : nby / 4;
747 size = nbx * nby * 4;
748 size += track->htile_offset;
750 if (size > radeon_bo_size(track->htile_bo)) {
751 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",
752 __func__, __LINE__, radeon_bo_size(track->htile_bo),
758 track->db_dirty = false;
762 static int r600_cs_track_check(struct radeon_cs_parser *p)
764 struct r600_cs_track *track = p->track;
768 /* on legacy kernel we don't perform advanced check */
772 /* check streamout */
773 if (track->streamout_dirty && track->vgt_strmout_en) {
774 for (i = 0; i < 4; i++) {
775 if (track->vgt_strmout_buffer_en & (1 << i)) {
776 if (track->vgt_strmout_bo[i]) {
777 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
778 (u64)track->vgt_strmout_size[i];
779 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
780 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
782 radeon_bo_size(track->vgt_strmout_bo[i]));
786 dev_warn(p->dev, "No buffer for streamout %d\n", i);
791 track->streamout_dirty = false;
794 if (track->sx_misc_kill_all_prims)
797 /* check that we have a cb for each enabled target, we don't check
798 * shader_mask because it seems mesa isn't always setting it :(
800 if (track->cb_dirty) {
801 tmp = track->cb_target_mask;
802 for (i = 0; i < 8; i++) {
803 if ((tmp >> (i * 4)) & 0xF) {
804 /* at least one component is enabled */
805 if (track->cb_color_bo[i] == NULL) {
806 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
807 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
810 /* perform rewrite of CB_COLOR[0-7]_SIZE */
811 r = r600_cs_track_validate_cb(p, i);
816 track->cb_dirty = false;
819 /* Check depth buffer */
820 if (track->db_dirty &&
821 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&
822 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||
823 G_028800_Z_ENABLE(track->db_depth_control))) {
824 r = r600_cs_track_validate_db(p);
833 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
834 * @parser: parser structure holding parsing context.
835 * @pkt: where to store packet informations
837 * Assume that chunk_ib_index is properly set. Will return -EINVAL
838 * if packet is bigger than remaining ib size. or if packets is unknown.
840 int r600_cs_packet_parse(struct radeon_cs_parser *p,
841 struct radeon_cs_packet *pkt,
844 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
847 if (idx >= ib_chunk->length_dw) {
848 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
849 idx, ib_chunk->length_dw);
852 header = radeon_get_ib_value(p, idx);
854 pkt->type = CP_PACKET_GET_TYPE(header);
855 pkt->count = CP_PACKET_GET_COUNT(header);
859 pkt->reg = CP_PACKET0_GET_REG(header);
862 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
868 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
871 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
872 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
873 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
880 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
881 * @parser: parser structure holding parsing context.
882 * @data: pointer to relocation data
883 * @offset_start: starting offset
884 * @offset_mask: offset mask (to align start offset on)
885 * @reloc: reloc informations
887 * Check next packet is relocation packet3, do bo validation and compute
888 * GPU offset using the provided start.
890 static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
891 struct radeon_cs_reloc **cs_reloc)
893 struct radeon_cs_chunk *relocs_chunk;
894 struct radeon_cs_packet p3reloc;
898 if (p->chunk_relocs_idx == -1) {
899 DRM_ERROR("No relocation chunk !\n");
903 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
904 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
908 p->idx += p3reloc.count + 2;
909 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
910 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
914 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
915 if (idx >= relocs_chunk->length_dw) {
916 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
917 idx, relocs_chunk->length_dw);
920 /* FIXME: we assume reloc size is 4 dwords */
921 *cs_reloc = p->relocs_ptr[(idx / 4)];
926 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
927 * @parser: parser structure holding parsing context.
928 * @data: pointer to relocation data
929 * @offset_start: starting offset
930 * @offset_mask: offset mask (to align start offset on)
931 * @reloc: reloc informations
933 * Check next packet is relocation packet3, do bo validation and compute
934 * GPU offset using the provided start.
936 static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
937 struct radeon_cs_reloc **cs_reloc)
939 struct radeon_cs_chunk *relocs_chunk;
940 struct radeon_cs_packet p3reloc;
944 if (p->chunk_relocs_idx == -1) {
945 DRM_ERROR("No relocation chunk !\n");
949 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
950 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
954 p->idx += p3reloc.count + 2;
955 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
956 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
960 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
961 if (idx >= relocs_chunk->length_dw) {
962 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
963 idx, relocs_chunk->length_dw);
966 *cs_reloc = p->relocs;
967 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
968 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
973 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
974 * @parser: parser structure holding parsing context.
976 * Check next packet is relocation packet3, do bo validation and compute
977 * GPU offset using the provided start.
979 static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
981 struct radeon_cs_packet p3reloc;
984 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
988 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
995 * r600_cs_packet_next_vline() - parse userspace VLINE packet
996 * @parser: parser structure holding parsing context.
998 * Userspace sends a special sequence for VLINE waits.
999 * PACKET0 - VLINE_START_END + value
1000 * PACKET3 - WAIT_REG_MEM poll vline status reg
1001 * RELOC (P3) - crtc_id in reloc.
1003 * This function parses this and relocates the VLINE START END
1004 * and WAIT_REG_MEM packets to the correct crtc.
1005 * It also detects a switched off crtc and nulls out the
1006 * wait in that case.
1008 static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
1010 struct drm_mode_object *obj;
1011 struct drm_crtc *crtc;
1012 struct radeon_crtc *radeon_crtc;
1013 struct radeon_cs_packet p3reloc, wait_reg_mem;
1016 uint32_t header, h_idx, reg, wait_reg_mem_info;
1017 volatile uint32_t *ib;
1021 /* parse the WAIT_REG_MEM */
1022 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx);
1026 /* check its a WAIT_REG_MEM */
1027 if (wait_reg_mem.type != PACKET_TYPE3 ||
1028 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
1029 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
1033 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
1034 /* bit 4 is reg (0) or mem (1) */
1035 if (wait_reg_mem_info & 0x10) {
1036 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
1039 /* waiting for value to be equal */
1040 if ((wait_reg_mem_info & 0x7) != 0x3) {
1041 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
1044 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) {
1045 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1049 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) {
1050 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1054 /* jump over the NOP */
1055 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1060 p->idx += wait_reg_mem.count + 2;
1061 p->idx += p3reloc.count + 2;
1063 header = radeon_get_ib_value(p, h_idx);
1064 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1065 reg = CP_PACKET0_GET_REG(header);
1067 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1069 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1072 crtc = obj_to_crtc(obj);
1073 radeon_crtc = to_radeon_crtc(crtc);
1074 crtc_id = radeon_crtc->crtc_id;
1076 if (!crtc->enabled) {
1077 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1078 ib[h_idx + 2] = PACKET2(0);
1079 ib[h_idx + 3] = PACKET2(0);
1080 ib[h_idx + 4] = PACKET2(0);
1081 ib[h_idx + 5] = PACKET2(0);
1082 ib[h_idx + 6] = PACKET2(0);
1083 ib[h_idx + 7] = PACKET2(0);
1084 ib[h_idx + 8] = PACKET2(0);
1085 } else if (crtc_id == 1) {
1087 case AVIVO_D1MODE_VLINE_START_END:
1088 header &= ~R600_CP_PACKET0_REG_MASK;
1089 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1092 DRM_ERROR("unknown crtc reloc\n");
1096 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
1102 static int r600_packet0_check(struct radeon_cs_parser *p,
1103 struct radeon_cs_packet *pkt,
1104 unsigned idx, unsigned reg)
1109 case AVIVO_D1MODE_VLINE_START_END:
1110 r = r600_cs_packet_parse_vline(p);
1112 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1118 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1125 static int r600_cs_parse_packet0(struct radeon_cs_parser *p,
1126 struct radeon_cs_packet *pkt)
1134 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1135 r = r600_packet0_check(p, pkt, idx, reg);
1144 * r600_cs_check_reg() - check if register is authorized or not
1145 * @parser: parser structure holding parsing context
1146 * @reg: register we are testing
1147 * @idx: index into the cs buffer
1149 * This function will test against r600_reg_safe_bm and return 0
1150 * if register is safe. If register is not flag as safe this function
1151 * will test it against a list of register needind special handling.
1153 static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1155 struct r600_cs_track *track = (struct r600_cs_track *)p->track;
1156 struct radeon_cs_reloc *reloc;
1161 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1162 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1165 m = 1 << ((reg >> 2) & 31);
1166 if (!(r600_reg_safe_bm[i] & m))
1170 /* force following reg to 0 in an attempt to disable out buffer
1171 * which will need us to better understand how it works to perform
1172 * security check on it (Jerome)
1174 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:
1175 case R_008C44_SQ_ESGS_RING_SIZE:
1176 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:
1177 case R_008C54_SQ_ESTMP_RING_SIZE:
1178 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:
1179 case R_008C74_SQ_FBUF_RING_SIZE:
1180 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:
1181 case R_008C5C_SQ_GSTMP_RING_SIZE:
1182 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:
1183 case R_008C4C_SQ_GSVS_RING_SIZE:
1184 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:
1185 case R_008C6C_SQ_PSTMP_RING_SIZE:
1186 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:
1187 case R_008C7C_SQ_REDUC_RING_SIZE:
1188 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:
1189 case R_008C64_SQ_VSTMP_RING_SIZE:
1190 case R_0288C8_SQ_GS_VERT_ITEMSIZE:
1191 /* get value to populate the IB don't remove */
1192 tmp =radeon_get_ib_value(p, idx);
1196 track->sq_config = radeon_get_ib_value(p, idx);
1198 case R_028800_DB_DEPTH_CONTROL:
1199 track->db_depth_control = radeon_get_ib_value(p, idx);
1200 track->db_dirty = true;
1202 case R_028010_DB_DEPTH_INFO:
1203 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1204 r600_cs_packet_next_is_pkt3_nop(p)) {
1205 r = r600_cs_packet_next_reloc(p, &reloc);
1207 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1211 track->db_depth_info = radeon_get_ib_value(p, idx);
1212 ib[idx] &= C_028010_ARRAY_MODE;
1213 track->db_depth_info &= C_028010_ARRAY_MODE;
1214 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1215 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1216 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);
1218 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1219 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);
1222 track->db_depth_info = radeon_get_ib_value(p, idx);
1224 track->db_dirty = true;
1226 case R_028004_DB_DEPTH_VIEW:
1227 track->db_depth_view = radeon_get_ib_value(p, idx);
1228 track->db_dirty = true;
1230 case R_028000_DB_DEPTH_SIZE:
1231 track->db_depth_size = radeon_get_ib_value(p, idx);
1232 track->db_depth_size_idx = idx;
1233 track->db_dirty = true;
1235 case R_028AB0_VGT_STRMOUT_EN:
1236 track->vgt_strmout_en = radeon_get_ib_value(p, idx);
1237 track->streamout_dirty = true;
1239 case R_028B20_VGT_STRMOUT_BUFFER_EN:
1240 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);
1241 track->streamout_dirty = true;
1243 case VGT_STRMOUT_BUFFER_BASE_0:
1244 case VGT_STRMOUT_BUFFER_BASE_1:
1245 case VGT_STRMOUT_BUFFER_BASE_2:
1246 case VGT_STRMOUT_BUFFER_BASE_3:
1247 r = r600_cs_packet_next_reloc(p, &reloc);
1249 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1253 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1254 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1255 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1256 track->vgt_strmout_bo[tmp] = reloc->robj;
1257 track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
1258 track->streamout_dirty = true;
1260 case VGT_STRMOUT_BUFFER_SIZE_0:
1261 case VGT_STRMOUT_BUFFER_SIZE_1:
1262 case VGT_STRMOUT_BUFFER_SIZE_2:
1263 case VGT_STRMOUT_BUFFER_SIZE_3:
1264 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1265 /* size in register is DWs, convert to bytes */
1266 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1267 track->streamout_dirty = true;
1270 r = r600_cs_packet_next_reloc(p, &reloc);
1272 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1276 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1278 case R_028238_CB_TARGET_MASK:
1279 track->cb_target_mask = radeon_get_ib_value(p, idx);
1280 track->cb_dirty = true;
1282 case R_02823C_CB_SHADER_MASK:
1283 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1285 case R_028C04_PA_SC_AA_CONFIG:
1286 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1287 track->log_nsamples = tmp;
1288 track->nsamples = 1 << tmp;
1289 track->cb_dirty = true;
1291 case R_0280A0_CB_COLOR0_INFO:
1292 case R_0280A4_CB_COLOR1_INFO:
1293 case R_0280A8_CB_COLOR2_INFO:
1294 case R_0280AC_CB_COLOR3_INFO:
1295 case R_0280B0_CB_COLOR4_INFO:
1296 case R_0280B4_CB_COLOR5_INFO:
1297 case R_0280B8_CB_COLOR6_INFO:
1298 case R_0280BC_CB_COLOR7_INFO:
1299 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1300 r600_cs_packet_next_is_pkt3_nop(p)) {
1301 r = r600_cs_packet_next_reloc(p, &reloc);
1303 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1306 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1307 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1308 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1309 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1310 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);
1311 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1312 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1313 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);
1316 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;
1317 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1319 track->cb_dirty = true;
1321 case R_028080_CB_COLOR0_VIEW:
1322 case R_028084_CB_COLOR1_VIEW:
1323 case R_028088_CB_COLOR2_VIEW:
1324 case R_02808C_CB_COLOR3_VIEW:
1325 case R_028090_CB_COLOR4_VIEW:
1326 case R_028094_CB_COLOR5_VIEW:
1327 case R_028098_CB_COLOR6_VIEW:
1328 case R_02809C_CB_COLOR7_VIEW:
1329 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;
1330 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1331 track->cb_dirty = true;
1333 case R_028060_CB_COLOR0_SIZE:
1334 case R_028064_CB_COLOR1_SIZE:
1335 case R_028068_CB_COLOR2_SIZE:
1336 case R_02806C_CB_COLOR3_SIZE:
1337 case R_028070_CB_COLOR4_SIZE:
1338 case R_028074_CB_COLOR5_SIZE:
1339 case R_028078_CB_COLOR6_SIZE:
1340 case R_02807C_CB_COLOR7_SIZE:
1341 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;
1342 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);
1343 track->cb_color_size_idx[tmp] = idx;
1344 track->cb_dirty = true;
1346 /* This register were added late, there is userspace
1347 * which does provide relocation for those but set
1348 * 0 offset. In order to avoid breaking old userspace
1349 * we detect this and set address to point to last
1350 * CB_COLOR0_BASE, note that if userspace doesn't set
1351 * CB_COLOR0_BASE before this register we will report
1352 * error. Old userspace always set CB_COLOR0_BASE
1353 * before any of this.
1355 case R_0280E0_CB_COLOR0_FRAG:
1356 case R_0280E4_CB_COLOR1_FRAG:
1357 case R_0280E8_CB_COLOR2_FRAG:
1358 case R_0280EC_CB_COLOR3_FRAG:
1359 case R_0280F0_CB_COLOR4_FRAG:
1360 case R_0280F4_CB_COLOR5_FRAG:
1361 case R_0280F8_CB_COLOR6_FRAG:
1362 case R_0280FC_CB_COLOR7_FRAG:
1363 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1364 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1365 if (!track->cb_color_base_last[tmp]) {
1366 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1369 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1370 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1371 ib[idx] = track->cb_color_base_last[tmp];
1373 r = r600_cs_packet_next_reloc(p, &reloc);
1375 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1378 track->cb_color_frag_bo[tmp] = reloc->robj;
1379 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1380 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1382 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1383 track->cb_dirty = true;
1386 case R_0280C0_CB_COLOR0_TILE:
1387 case R_0280C4_CB_COLOR1_TILE:
1388 case R_0280C8_CB_COLOR2_TILE:
1389 case R_0280CC_CB_COLOR3_TILE:
1390 case R_0280D0_CB_COLOR4_TILE:
1391 case R_0280D4_CB_COLOR5_TILE:
1392 case R_0280D8_CB_COLOR6_TILE:
1393 case R_0280DC_CB_COLOR7_TILE:
1394 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1395 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
1396 if (!track->cb_color_base_last[tmp]) {
1397 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1400 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1401 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1402 ib[idx] = track->cb_color_base_last[tmp];
1404 r = r600_cs_packet_next_reloc(p, &reloc);
1406 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1409 track->cb_color_tile_bo[tmp] = reloc->robj;
1410 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1411 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1413 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1414 track->cb_dirty = true;
1417 case R_028100_CB_COLOR0_MASK:
1418 case R_028104_CB_COLOR1_MASK:
1419 case R_028108_CB_COLOR2_MASK:
1420 case R_02810C_CB_COLOR3_MASK:
1421 case R_028110_CB_COLOR4_MASK:
1422 case R_028114_CB_COLOR5_MASK:
1423 case R_028118_CB_COLOR6_MASK:
1424 case R_02811C_CB_COLOR7_MASK:
1425 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1426 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
1427 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1428 track->cb_dirty = true;
1431 case CB_COLOR0_BASE:
1432 case CB_COLOR1_BASE:
1433 case CB_COLOR2_BASE:
1434 case CB_COLOR3_BASE:
1435 case CB_COLOR4_BASE:
1436 case CB_COLOR5_BASE:
1437 case CB_COLOR6_BASE:
1438 case CB_COLOR7_BASE:
1439 r = r600_cs_packet_next_reloc(p, &reloc);
1441 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1445 tmp = (reg - CB_COLOR0_BASE) / 4;
1446 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1447 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1448 track->cb_color_base_last[tmp] = ib[idx];
1449 track->cb_color_bo[tmp] = reloc->robj;
1450 track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset;
1451 track->cb_dirty = true;
1454 r = r600_cs_packet_next_reloc(p, &reloc);
1456 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1460 track->db_offset = radeon_get_ib_value(p, idx) << 8;
1461 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1462 track->db_bo = reloc->robj;
1463 track->db_bo_mc = reloc->lobj.gpu_offset;
1464 track->db_dirty = true;
1466 case DB_HTILE_DATA_BASE:
1467 r = r600_cs_packet_next_reloc(p, &reloc);
1469 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1473 track->htile_offset = radeon_get_ib_value(p, idx) << 8;
1474 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1475 track->htile_bo = reloc->robj;
1476 track->db_dirty = true;
1478 case DB_HTILE_SURFACE:
1479 track->htile_surface = radeon_get_ib_value(p, idx);
1480 track->db_dirty = true;
1482 case SQ_PGM_START_FS:
1483 case SQ_PGM_START_ES:
1484 case SQ_PGM_START_VS:
1485 case SQ_PGM_START_GS:
1486 case SQ_PGM_START_PS:
1487 case SQ_ALU_CONST_CACHE_GS_0:
1488 case SQ_ALU_CONST_CACHE_GS_1:
1489 case SQ_ALU_CONST_CACHE_GS_2:
1490 case SQ_ALU_CONST_CACHE_GS_3:
1491 case SQ_ALU_CONST_CACHE_GS_4:
1492 case SQ_ALU_CONST_CACHE_GS_5:
1493 case SQ_ALU_CONST_CACHE_GS_6:
1494 case SQ_ALU_CONST_CACHE_GS_7:
1495 case SQ_ALU_CONST_CACHE_GS_8:
1496 case SQ_ALU_CONST_CACHE_GS_9:
1497 case SQ_ALU_CONST_CACHE_GS_10:
1498 case SQ_ALU_CONST_CACHE_GS_11:
1499 case SQ_ALU_CONST_CACHE_GS_12:
1500 case SQ_ALU_CONST_CACHE_GS_13:
1501 case SQ_ALU_CONST_CACHE_GS_14:
1502 case SQ_ALU_CONST_CACHE_GS_15:
1503 case SQ_ALU_CONST_CACHE_PS_0:
1504 case SQ_ALU_CONST_CACHE_PS_1:
1505 case SQ_ALU_CONST_CACHE_PS_2:
1506 case SQ_ALU_CONST_CACHE_PS_3:
1507 case SQ_ALU_CONST_CACHE_PS_4:
1508 case SQ_ALU_CONST_CACHE_PS_5:
1509 case SQ_ALU_CONST_CACHE_PS_6:
1510 case SQ_ALU_CONST_CACHE_PS_7:
1511 case SQ_ALU_CONST_CACHE_PS_8:
1512 case SQ_ALU_CONST_CACHE_PS_9:
1513 case SQ_ALU_CONST_CACHE_PS_10:
1514 case SQ_ALU_CONST_CACHE_PS_11:
1515 case SQ_ALU_CONST_CACHE_PS_12:
1516 case SQ_ALU_CONST_CACHE_PS_13:
1517 case SQ_ALU_CONST_CACHE_PS_14:
1518 case SQ_ALU_CONST_CACHE_PS_15:
1519 case SQ_ALU_CONST_CACHE_VS_0:
1520 case SQ_ALU_CONST_CACHE_VS_1:
1521 case SQ_ALU_CONST_CACHE_VS_2:
1522 case SQ_ALU_CONST_CACHE_VS_3:
1523 case SQ_ALU_CONST_CACHE_VS_4:
1524 case SQ_ALU_CONST_CACHE_VS_5:
1525 case SQ_ALU_CONST_CACHE_VS_6:
1526 case SQ_ALU_CONST_CACHE_VS_7:
1527 case SQ_ALU_CONST_CACHE_VS_8:
1528 case SQ_ALU_CONST_CACHE_VS_9:
1529 case SQ_ALU_CONST_CACHE_VS_10:
1530 case SQ_ALU_CONST_CACHE_VS_11:
1531 case SQ_ALU_CONST_CACHE_VS_12:
1532 case SQ_ALU_CONST_CACHE_VS_13:
1533 case SQ_ALU_CONST_CACHE_VS_14:
1534 case SQ_ALU_CONST_CACHE_VS_15:
1535 r = r600_cs_packet_next_reloc(p, &reloc);
1537 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1541 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1543 case SX_MEMORY_EXPORT_BASE:
1544 r = r600_cs_packet_next_reloc(p, &reloc);
1546 dev_warn(p->dev, "bad SET_CONFIG_REG "
1550 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1553 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1556 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1562 unsigned r600_mip_minify(unsigned size, unsigned level)
1566 val = max(1U, size >> level);
1568 val = roundup_pow_of_two(val);
1572 static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,
1573 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,
1574 unsigned block_align, unsigned height_align, unsigned base_align,
1575 unsigned *l0_size, unsigned *mipmap_size)
1577 unsigned offset, i, level;
1578 unsigned width, height, depth, size;
1581 unsigned nlevels = llevel - blevel + 1;
1584 blocksize = r600_fmt_get_blocksize(format);
1586 w0 = r600_mip_minify(w0, 0);
1587 h0 = r600_mip_minify(h0, 0);
1588 d0 = r600_mip_minify(d0, 0);
1589 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {
1590 width = r600_mip_minify(w0, i);
1591 nbx = r600_fmt_get_nblocksx(format, width);
1593 nbx = round_up(nbx, block_align);
1595 height = r600_mip_minify(h0, i);
1596 nby = r600_fmt_get_nblocksy(format, height);
1597 nby = round_up(nby, height_align);
1599 depth = r600_mip_minify(d0, i);
1601 size = nbx * nby * blocksize * nsamples;
1610 if (i == 0 || i == 1)
1611 offset = round_up(offset, base_align);
1615 *mipmap_size = offset;
1617 *mipmap_size = *l0_size;
1619 *mipmap_size -= *l0_size;
1623 * r600_check_texture_resource() - check if register is authorized or not
1624 * @p: parser structure holding parsing context
1625 * @idx: index into the cs buffer
1626 * @texture: texture's bo structure
1627 * @mipmap: mipmap's bo structure
1629 * This function will check that the resource has valid field and that
1630 * the texture and mipmap bo object are big enough to cover this resource.
1632 static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,
1633 struct radeon_bo *texture,
1634 struct radeon_bo *mipmap,
1639 struct r600_cs_track *track = p->track;
1640 u32 dim, nfaces, llevel, blevel, w0, h0, d0;
1641 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;
1642 u32 height_align, pitch, pitch_align, depth_align;
1645 struct array_mode_checker array_check;
1649 /* on legacy kernel we don't perform advanced check */
1650 if (p->rdev == NULL)
1653 /* convert to bytes */
1657 word0 = radeon_get_ib_value(p, idx + 0);
1658 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1659 if (tiling_flags & RADEON_TILING_MACRO)
1660 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1661 else if (tiling_flags & RADEON_TILING_MICRO)
1662 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1664 word1 = radeon_get_ib_value(p, idx + 1);
1665 word2 = radeon_get_ib_value(p, idx + 2) << 8;
1666 word3 = radeon_get_ib_value(p, idx + 3) << 8;
1667 word4 = radeon_get_ib_value(p, idx + 4);
1668 word5 = radeon_get_ib_value(p, idx + 5);
1669 dim = G_038000_DIM(word0);
1670 w0 = G_038000_TEX_WIDTH(word0) + 1;
1671 pitch = (G_038000_PITCH(word0) + 1) * 8;
1672 h0 = G_038004_TEX_HEIGHT(word1) + 1;
1673 d0 = G_038004_TEX_DEPTH(word1);
1674 format = G_038004_DATA_FORMAT(word1);
1675 blevel = G_038010_BASE_LEVEL(word4);
1676 llevel = G_038014_LAST_LEVEL(word5);
1677 /* pitch in texels */
1678 array_check.array_mode = G_038000_TILE_MODE(word0);
1679 array_check.group_size = track->group_size;
1680 array_check.nbanks = track->nbanks;
1681 array_check.npipes = track->npipes;
1682 array_check.nsamples = 1;
1683 array_check.blocksize = r600_fmt_get_blocksize(format);
1687 case V_038000_SQ_TEX_DIM_1D:
1688 case V_038000_SQ_TEX_DIM_2D:
1689 case V_038000_SQ_TEX_DIM_3D:
1691 case V_038000_SQ_TEX_DIM_CUBEMAP:
1692 if (p->family >= CHIP_RV770)
1697 case V_038000_SQ_TEX_DIM_1D_ARRAY:
1698 case V_038000_SQ_TEX_DIM_2D_ARRAY:
1701 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:
1704 case V_038000_SQ_TEX_DIM_2D_MSAA:
1705 array_check.nsamples = 1 << llevel;
1709 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));
1712 if (!r600_fmt_is_valid_texture(format, p->family)) {
1713 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1714 __func__, __LINE__, format);
1718 if (r600_get_array_mode_alignment(&array_check,
1719 &pitch_align, &height_align, &depth_align, &base_align)) {
1720 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",
1721 __func__, __LINE__, G_038000_TILE_MODE(word0));
1725 /* XXX check height as well... */
1727 if (!IS_ALIGNED(pitch, pitch_align)) {
1728 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",
1729 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));
1732 if (!IS_ALIGNED(base_offset, base_align)) {
1733 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",
1734 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));
1737 if (!IS_ALIGNED(mip_offset, base_align)) {
1738 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",
1739 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));
1743 if (blevel > llevel) {
1744 dev_warn(p->dev, "texture blevel %d > llevel %d\n",
1748 barray = G_038014_BASE_ARRAY(word5);
1749 larray = G_038014_LAST_ARRAY(word5);
1751 nfaces = larray - barray + 1;
1753 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,
1754 pitch_align, height_align, base_align,
1755 &l0_size, &mipmap_size);
1756 /* using get ib will give us the offset into the texture bo */
1757 if ((l0_size + word2) > radeon_bo_size(texture)) {
1758 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",
1759 w0, h0, pitch_align, height_align,
1760 array_check.array_mode, format, word2,
1761 l0_size, radeon_bo_size(texture));
1762 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);
1765 /* using get ib will give us the offset into the mipmap bo */
1766 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {
1767 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",
1768 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/
1773 static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1778 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {
1779 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1782 m = 1 << ((reg >> 2) & 31);
1783 if (!(r600_reg_safe_bm[i] & m))
1785 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1789 static int r600_packet3_check(struct radeon_cs_parser *p,
1790 struct radeon_cs_packet *pkt)
1792 struct radeon_cs_reloc *reloc;
1793 struct r600_cs_track *track;
1797 unsigned start_reg, end_reg, reg;
1801 track = (struct r600_cs_track *)p->track;
1804 idx_value = radeon_get_ib_value(p, idx);
1806 switch (pkt->opcode) {
1807 case PACKET3_SET_PREDICATION:
1813 if (pkt->count != 1) {
1814 DRM_ERROR("bad SET PREDICATION\n");
1818 tmp = radeon_get_ib_value(p, idx + 1);
1819 pred_op = (tmp >> 16) & 0x7;
1821 /* for the clear predicate operation */
1826 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1830 r = r600_cs_packet_next_reloc(p, &reloc);
1832 DRM_ERROR("bad SET PREDICATION\n");
1836 offset = reloc->lobj.gpu_offset +
1837 (idx_value & 0xfffffff0) +
1838 ((u64)(tmp & 0xff) << 32);
1840 ib[idx + 0] = offset;
1841 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1845 case PACKET3_START_3D_CMDBUF:
1846 if (p->family >= CHIP_RV770 || pkt->count) {
1847 DRM_ERROR("bad START_3D\n");
1851 case PACKET3_CONTEXT_CONTROL:
1852 if (pkt->count != 1) {
1853 DRM_ERROR("bad CONTEXT_CONTROL\n");
1857 case PACKET3_INDEX_TYPE:
1858 case PACKET3_NUM_INSTANCES:
1860 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");
1864 case PACKET3_DRAW_INDEX:
1867 if (pkt->count != 3) {
1868 DRM_ERROR("bad DRAW_INDEX\n");
1871 r = r600_cs_packet_next_reloc(p, &reloc);
1873 DRM_ERROR("bad DRAW_INDEX\n");
1877 offset = reloc->lobj.gpu_offset +
1879 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1882 ib[idx+1] = upper_32_bits(offset) & 0xff;
1884 r = r600_cs_track_check(p);
1886 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1891 case PACKET3_DRAW_INDEX_AUTO:
1892 if (pkt->count != 1) {
1893 DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1896 r = r600_cs_track_check(p);
1898 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1902 case PACKET3_DRAW_INDEX_IMMD_BE:
1903 case PACKET3_DRAW_INDEX_IMMD:
1904 if (pkt->count < 2) {
1905 DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1908 r = r600_cs_track_check(p);
1910 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1914 case PACKET3_WAIT_REG_MEM:
1915 if (pkt->count != 5) {
1916 DRM_ERROR("bad WAIT_REG_MEM\n");
1919 /* bit 4 is reg (0) or mem (1) */
1920 if (idx_value & 0x10) {
1923 r = r600_cs_packet_next_reloc(p, &reloc);
1925 DRM_ERROR("bad WAIT_REG_MEM\n");
1929 offset = reloc->lobj.gpu_offset +
1930 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +
1931 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1933 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1934 ib[idx+2] = upper_32_bits(offset) & 0xff;
1937 case PACKET3_SURFACE_SYNC:
1938 if (pkt->count != 3) {
1939 DRM_ERROR("bad SURFACE_SYNC\n");
1942 /* 0xffffffff/0x0 is flush all cache flag */
1943 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1944 radeon_get_ib_value(p, idx + 2) != 0) {
1945 r = r600_cs_packet_next_reloc(p, &reloc);
1947 DRM_ERROR("bad SURFACE_SYNC\n");
1950 ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1953 case PACKET3_EVENT_WRITE:
1954 if (pkt->count != 2 && pkt->count != 0) {
1955 DRM_ERROR("bad EVENT_WRITE\n");
1961 r = r600_cs_packet_next_reloc(p, &reloc);
1963 DRM_ERROR("bad EVENT_WRITE\n");
1966 offset = reloc->lobj.gpu_offset +
1967 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
1968 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1970 ib[idx+1] = offset & 0xfffffff8;
1971 ib[idx+2] = upper_32_bits(offset) & 0xff;
1974 case PACKET3_EVENT_WRITE_EOP:
1978 if (pkt->count != 4) {
1979 DRM_ERROR("bad EVENT_WRITE_EOP\n");
1982 r = r600_cs_packet_next_reloc(p, &reloc);
1984 DRM_ERROR("bad EVENT_WRITE\n");
1988 offset = reloc->lobj.gpu_offset +
1989 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
1990 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1992 ib[idx+1] = offset & 0xfffffffc;
1993 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1996 case PACKET3_SET_CONFIG_REG:
1997 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;
1998 end_reg = 4 * pkt->count + start_reg - 4;
1999 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||
2000 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2001 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2002 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2005 for (i = 0; i < pkt->count; i++) {
2006 reg = start_reg + (4 * i);
2007 r = r600_cs_check_reg(p, reg, idx+1+i);
2012 case PACKET3_SET_CONTEXT_REG:
2013 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;
2014 end_reg = 4 * pkt->count + start_reg - 4;
2015 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||
2016 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2017 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2018 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2021 for (i = 0; i < pkt->count; i++) {
2022 reg = start_reg + (4 * i);
2023 r = r600_cs_check_reg(p, reg, idx+1+i);
2028 case PACKET3_SET_RESOURCE:
2029 if (pkt->count % 7) {
2030 DRM_ERROR("bad SET_RESOURCE\n");
2033 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;
2034 end_reg = 4 * pkt->count + start_reg - 4;
2035 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||
2036 (start_reg >= PACKET3_SET_RESOURCE_END) ||
2037 (end_reg >= PACKET3_SET_RESOURCE_END)) {
2038 DRM_ERROR("bad SET_RESOURCE\n");
2041 for (i = 0; i < (pkt->count / 7); i++) {
2042 struct radeon_bo *texture, *mipmap;
2043 u32 size, offset, base_offset, mip_offset;
2045 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
2046 case SQ_TEX_VTX_VALID_TEXTURE:
2048 r = r600_cs_packet_next_reloc(p, &reloc);
2050 DRM_ERROR("bad SET_RESOURCE\n");
2053 base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2054 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
2055 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
2056 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);
2057 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
2058 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);
2060 texture = reloc->robj;
2062 r = r600_cs_packet_next_reloc(p, &reloc);
2064 DRM_ERROR("bad SET_RESOURCE\n");
2067 mip_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2068 mipmap = reloc->robj;
2069 r = r600_check_texture_resource(p, idx+(i*7)+1,
2071 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),
2072 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),
2073 reloc->lobj.tiling_flags);
2076 ib[idx+1+(i*7)+2] += base_offset;
2077 ib[idx+1+(i*7)+3] += mip_offset;
2079 case SQ_TEX_VTX_VALID_BUFFER:
2083 r = r600_cs_packet_next_reloc(p, &reloc);
2085 DRM_ERROR("bad SET_RESOURCE\n");
2088 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);
2089 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;
2090 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2091 /* force size to size of the buffer */
2092 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",
2093 size + offset, radeon_bo_size(reloc->robj));
2094 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;
2097 offset64 = reloc->lobj.gpu_offset + offset;
2098 ib[idx+1+(i*8)+0] = offset64;
2099 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2100 (upper_32_bits(offset64) & 0xff);
2103 case SQ_TEX_VTX_INVALID_TEXTURE:
2104 case SQ_TEX_VTX_INVALID_BUFFER:
2106 DRM_ERROR("bad SET_RESOURCE\n");
2111 case PACKET3_SET_ALU_CONST:
2112 if (track->sq_config & DX9_CONSTS) {
2113 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
2114 end_reg = 4 * pkt->count + start_reg - 4;
2115 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
2116 (start_reg >= PACKET3_SET_ALU_CONST_END) ||
2117 (end_reg >= PACKET3_SET_ALU_CONST_END)) {
2118 DRM_ERROR("bad SET_ALU_CONST\n");
2123 case PACKET3_SET_BOOL_CONST:
2124 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;
2125 end_reg = 4 * pkt->count + start_reg - 4;
2126 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||
2127 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2128 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2129 DRM_ERROR("bad SET_BOOL_CONST\n");
2133 case PACKET3_SET_LOOP_CONST:
2134 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;
2135 end_reg = 4 * pkt->count + start_reg - 4;
2136 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||
2137 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2138 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2139 DRM_ERROR("bad SET_LOOP_CONST\n");
2143 case PACKET3_SET_CTL_CONST:
2144 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;
2145 end_reg = 4 * pkt->count + start_reg - 4;
2146 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||
2147 (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2148 (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2149 DRM_ERROR("bad SET_CTL_CONST\n");
2153 case PACKET3_SET_SAMPLER:
2154 if (pkt->count % 3) {
2155 DRM_ERROR("bad SET_SAMPLER\n");
2158 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;
2159 end_reg = 4 * pkt->count + start_reg - 4;
2160 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||
2161 (start_reg >= PACKET3_SET_SAMPLER_END) ||
2162 (end_reg >= PACKET3_SET_SAMPLER_END)) {
2163 DRM_ERROR("bad SET_SAMPLER\n");
2167 case PACKET3_STRMOUT_BASE_UPDATE:
2168 if (p->family < CHIP_RV770) {
2169 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");
2172 if (pkt->count != 1) {
2173 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");
2176 if (idx_value > 3) {
2177 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");
2183 r = r600_cs_packet_next_reloc(p, &reloc);
2185 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2189 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {
2190 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");
2194 offset = radeon_get_ib_value(p, idx+1) << 8;
2195 if (offset != track->vgt_strmout_bo_offset[idx_value]) {
2196 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",
2197 offset, track->vgt_strmout_bo_offset[idx_value]);
2201 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2202 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",
2203 offset + 4, radeon_bo_size(reloc->robj));
2206 ib[idx+1] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2209 case PACKET3_SURFACE_BASE_UPDATE:
2210 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {
2211 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2215 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");
2219 case PACKET3_STRMOUT_BUFFER_UPDATE:
2220 if (pkt->count != 4) {
2221 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2224 /* Updating memory at DST_ADDRESS. */
2225 if (idx_value & 0x1) {
2227 r = r600_cs_packet_next_reloc(p, &reloc);
2229 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2232 offset = radeon_get_ib_value(p, idx+1);
2233 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2234 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2235 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2236 offset + 4, radeon_bo_size(reloc->robj));
2239 offset += reloc->lobj.gpu_offset;
2241 ib[idx+2] = upper_32_bits(offset) & 0xff;
2243 /* Reading data from SRC_ADDRESS. */
2244 if (((idx_value >> 1) & 0x3) == 2) {
2246 r = r600_cs_packet_next_reloc(p, &reloc);
2248 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2251 offset = radeon_get_ib_value(p, idx+3);
2252 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2253 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2254 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2255 offset + 4, radeon_bo_size(reloc->robj));
2258 offset += reloc->lobj.gpu_offset;
2260 ib[idx+4] = upper_32_bits(offset) & 0xff;
2263 case PACKET3_COPY_DW:
2264 if (pkt->count != 4) {
2265 DRM_ERROR("bad COPY_DW (invalid count)\n");
2268 if (idx_value & 0x1) {
2270 /* SRC is memory. */
2271 r = r600_cs_packet_next_reloc(p, &reloc);
2273 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2276 offset = radeon_get_ib_value(p, idx+1);
2277 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2278 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2279 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2280 offset + 4, radeon_bo_size(reloc->robj));
2283 offset += reloc->lobj.gpu_offset;
2285 ib[idx+2] = upper_32_bits(offset) & 0xff;
2288 reg = radeon_get_ib_value(p, idx+1) << 2;
2289 if (!r600_is_safe_reg(p, reg, idx+1))
2292 if (idx_value & 0x2) {
2294 /* DST is memory. */
2295 r = r600_cs_packet_next_reloc(p, &reloc);
2297 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2300 offset = radeon_get_ib_value(p, idx+3);
2301 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2302 if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2303 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2304 offset + 4, radeon_bo_size(reloc->robj));
2307 offset += reloc->lobj.gpu_offset;
2309 ib[idx+4] = upper_32_bits(offset) & 0xff;
2312 reg = radeon_get_ib_value(p, idx+3) << 2;
2313 if (!r600_is_safe_reg(p, reg, idx+3))
2320 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2326 int r600_cs_parse(struct radeon_cs_parser *p)
2328 struct radeon_cs_packet pkt;
2329 struct r600_cs_track *track;
2332 if (p->track == NULL) {
2333 /* initialize tracker, we are in kms */
2334 track = kzalloc(sizeof(*track), GFP_KERNEL);
2337 r600_cs_track_init(track);
2338 if (p->rdev->family < CHIP_RV770) {
2339 track->npipes = p->rdev->config.r600.tiling_npipes;
2340 track->nbanks = p->rdev->config.r600.tiling_nbanks;
2341 track->group_size = p->rdev->config.r600.tiling_group_size;
2342 } else if (p->rdev->family <= CHIP_RV740) {
2343 track->npipes = p->rdev->config.rv770.tiling_npipes;
2344 track->nbanks = p->rdev->config.rv770.tiling_nbanks;
2345 track->group_size = p->rdev->config.rv770.tiling_group_size;
2350 r = r600_cs_packet_parse(p, &pkt, p->idx);
2356 p->idx += pkt.count + 2;
2359 r = r600_cs_parse_packet0(p, &pkt);
2364 r = r600_packet3_check(p, &pkt);
2367 DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2377 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2379 for (r = 0; r < p->ib.length_dw; r++) {
2380 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]);
2389 static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2391 if (p->chunk_relocs_idx == -1) {
2394 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
2395 if (p->relocs == NULL) {
2402 * cs_parser_fini() - clean parser states
2403 * @parser: parser structure holding parsing context.
2404 * @error: error number
2406 * If error is set than unvalidate buffer, otherwise just free memory
2407 * used by parsing context.
2409 static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2413 kfree(parser->relocs);
2414 for (i = 0; i < parser->nchunks; i++) {
2415 kfree(parser->chunks[i].kdata);
2416 kfree(parser->chunks[i].kpage[0]);
2417 kfree(parser->chunks[i].kpage[1]);
2419 kfree(parser->chunks);
2420 kfree(parser->chunks_array);
2423 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2424 unsigned family, u32 *ib, int *l)
2426 struct radeon_cs_parser parser;
2427 struct radeon_cs_chunk *ib_chunk;
2428 struct r600_cs_track *track;
2431 /* initialize tracker */
2432 track = kzalloc(sizeof(*track), GFP_KERNEL);
2435 r600_cs_track_init(track);
2436 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
2437 /* initialize parser */
2438 memset(&parser, 0, sizeof(struct radeon_cs_parser));
2440 parser.dev = &dev->pdev->dev;
2442 parser.family = family;
2443 parser.track = track;
2445 r = radeon_cs_parser_init(&parser, data);
2447 DRM_ERROR("Failed to initialize parser !\n");
2448 r600_cs_parser_fini(&parser, r);
2451 r = r600_cs_parser_relocs_legacy(&parser);
2453 DRM_ERROR("Failed to parse relocation !\n");
2454 r600_cs_parser_fini(&parser, r);
2457 /* Copy the packet into the IB, the parser will read from the
2458 * input memory (cached) and write to the IB (which can be
2460 ib_chunk = &parser.chunks[parser.chunk_ib_idx];
2461 parser.ib.length_dw = ib_chunk->length_dw;
2462 *l = parser.ib.length_dw;
2463 r = r600_cs_parse(&parser);
2465 DRM_ERROR("Invalid command stream !\n");
2466 r600_cs_parser_fini(&parser, r);
2469 r = radeon_cs_finish_pages(&parser);
2471 DRM_ERROR("Invalid command stream !\n");
2472 r600_cs_parser_fini(&parser, r);
2475 r600_cs_parser_fini(&parser, r);
2479 void r600_cs_legacy_init(void)
2481 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm;