2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/dma-mapping.h>
28 #include "nouveau_drv.h"
29 #include "nouveau_connector.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_crtc.h"
34 struct nouveau_gpuobj *mem;
41 static struct nvd0_display *
42 nvd0_display(struct drm_device *dev)
44 struct drm_nouveau_private *dev_priv = dev->dev_private;
45 return dev_priv->engine.display.priv;
49 evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
52 nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
53 nv_wr32(dev, 0x610704 + (id * 0x10), data);
54 nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
55 if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
57 nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
62 evo_wait(struct drm_device *dev, int id, int nr)
64 struct nvd0_display *disp = nvd0_display(dev);
65 u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4;
67 if (put + nr >= (PAGE_SIZE / 4)) {
68 disp->evo[id].ptr[put] = 0x20000000;
70 nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000);
71 if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
72 NV_ERROR(dev, "evo %d dma stalled\n", id);
79 return disp->evo[id].ptr + put;
83 evo_kick(u32 *push, struct drm_device *dev, int id)
85 struct nvd0_display *disp = nvd0_display(dev);
86 nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
89 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
90 #define evo_data(p,d) *((p)++) = (d)
92 /******************************************************************************
94 *****************************************************************************/
96 /******************************************************************************
98 *****************************************************************************/
100 /******************************************************************************
102 *****************************************************************************/
104 /******************************************************************************
106 *****************************************************************************/
108 nvd0_display_fini(struct drm_device *dev)
113 for (i = 14; i >= 13; i--) {
114 if (!(nv_rd32(dev, 0x610490 + (i * 0x10)) & 0x00000001))
117 nv_mask(dev, 0x610490 + (i * 0x10), 0x00000001, 0x00000000);
118 nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00000000);
119 nv_mask(dev, 0x610090, 1 << i, 0x00000000);
120 nv_mask(dev, 0x6100a0, 1 << i, 0x00000000);
124 if (nv_rd32(dev, 0x610490) & 0x00000010) {
125 nv_mask(dev, 0x610490, 0x00000010, 0x00000000);
126 nv_mask(dev, 0x610490, 0x00000003, 0x00000000);
127 nv_wait(dev, 0x610490, 0x80000000, 0x00000000);
128 nv_mask(dev, 0x610090, 0x00000001, 0x00000000);
129 nv_mask(dev, 0x6100a0, 0x00000001, 0x00000000);
134 nvd0_display_init(struct drm_device *dev)
136 struct nvd0_display *disp = nvd0_display(dev);
139 if (nv_rd32(dev, 0x6100ac) & 0x00000100) {
140 nv_wr32(dev, 0x6100ac, 0x00000100);
141 nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000);
142 if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) {
143 NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n",
144 nv_rd32(dev, 0x6194e8));
149 nv_wr32(dev, 0x610010, (disp->mem->vinst >> 8) | 9);
152 nv_wr32(dev, 0x610494, (disp->evo[0].handle >> 8) | 3);
153 nv_wr32(dev, 0x610498, 0x00010000);
154 nv_wr32(dev, 0x61049c, 0x00000000);
155 nv_mask(dev, 0x610490, 0x00000010, 0x00000010);
156 nv_wr32(dev, 0x640000, 0x00000000);
157 nv_wr32(dev, 0x610490, 0x01000013);
158 if (!nv_wait(dev, 0x610490, 0x80000000, 0x00000000)) {
159 NV_ERROR(dev, "PDISP: master 0x%08x\n",
160 nv_rd32(dev, 0x610490));
163 nv_mask(dev, 0x610090, 0x00000001, 0x00000001);
164 nv_mask(dev, 0x6100a0, 0x00000001, 0x00000001);
167 for (i = 13; i <= 14; i++) {
168 nv_wr32(dev, 0x610490 + (i * 0x10), 0x00000001);
169 if (!nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00010000)) {
170 NV_ERROR(dev, "PDISP: curs%d 0x%08x\n", i,
171 nv_rd32(dev, 0x610490 + (i * 0x10)));
175 nv_mask(dev, 0x610090, 1 << i, 1 << i);
176 nv_mask(dev, 0x6100a0, 1 << i, 1 << i);
183 nvd0_display_destroy(struct drm_device *dev)
185 struct drm_nouveau_private *dev_priv = dev->dev_private;
186 struct nvd0_display *disp = nvd0_display(dev);
187 struct pci_dev *pdev = dev->pdev;
189 nvd0_display_fini(dev);
191 pci_free_consistent(pdev, PAGE_SIZE, disp->evo[0].ptr, disp->evo[0].handle);
192 nouveau_gpuobj_ref(NULL, &disp->mem);
194 dev_priv->engine.display.priv = NULL;
199 nvd0_display_create(struct drm_device *dev)
201 struct drm_nouveau_private *dev_priv = dev->dev_private;
202 struct pci_dev *pdev = dev->pdev;
203 struct nvd0_display *disp;
206 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
209 dev_priv->engine.display.priv = disp;
211 /* hash table and dma objects for the memory areas we care about */
212 ret = nouveau_gpuobj_new(dev, NULL, 4 * 1024, 0x1000, 0, &disp->mem);
216 /* push buffers for evo channels */
218 pci_alloc_consistent(pdev, PAGE_SIZE, &disp->evo[0].handle);
219 if (!disp->evo[0].ptr) {
224 ret = nvd0_display_init(dev);
230 nvd0_display_destroy(dev);