drivers/gpu/drm/nouveau/nvc0_graph.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/firmware.h>
  26
  27 #include "drmP.h"
  28
  29 #include "nouveau_drv.h"
  30 #include "nouveau_mm.h"
  31 #include "nvc0_graph.h"
  32
  33 static void nvc0_graph_isr(struct drm_device *);
  34 static void nvc0_runk140_isr(struct drm_device *);
  35 static int  nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan);
  36
  37 void
  38 nvc0_graph_fifo_access(struct drm_device *dev, bool enabled)
  39 {
  40 }
  41
  42 struct nouveau_channel *
  43 nvc0_graph_channel(struct drm_device *dev)
  44 {
  45         return NULL;
  46 }
  47
  48 static int
  49 nvc0_graph_construct_context(struct nouveau_channel *chan)
  50 {
  51         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  52         struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
  53         struct nvc0_graph_chan *grch = chan->pgraph_ctx;
  54         struct drm_device *dev = chan->dev;
  55         int ret, i;
  56         u32 *ctx;
  57
  58         ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
  59         if (!ctx)
  60                 return -ENOMEM;
  61
  62         nvc0_graph_load_context(chan);
  63
  64         nv_wo32(grch->grctx, 0x1c, 1);
  65         nv_wo32(grch->grctx, 0x20, 0);
  66         nv_wo32(grch->grctx, 0x28, 0);
  67         nv_wo32(grch->grctx, 0x2c, 0);
  68         dev_priv->engine.instmem.flush(dev);
  69
  70         ret = nvc0_grctx_generate(chan);
  71         if (ret) {
  72                 kfree(ctx);
  73                 return ret;
  74         }
  75
  76         ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
  77         if (ret) {
  78                 kfree(ctx);
  79                 return ret;
  80         }
  81
  82         for (i = 0; i < priv->grctx_size; i += 4)
  83                 ctx[i / 4] = nv_ro32(grch->grctx, i);
  84
  85         priv->grctx_vals = ctx;
  86         return 0;
  87 }
  88
  89 static int
  90 nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
  91 {
  92         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  93         struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
  94         struct nvc0_graph_chan *grch = chan->pgraph_ctx;
  95         struct drm_device *dev = chan->dev;
  96         int i = 0, gpc, tp, ret;
  97         u32 magic;
  98
  99         ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM,
 100                                  &grch->unk408004);
 101         if (ret)
 102                 return ret;
 103
 104         ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM,
 105                                  &grch->unk40800c);
 106         if (ret)
 107                 return ret;
 108
 109         ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096,
 110                                  NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
 111                                  &grch->unk418810);
 112         if (ret)
 113                 return ret;
 114
 115         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM,
 116                                  &grch->mmio);
 117         if (ret)
 118                 return ret;
 119
 120
 121         nv_wo32(grch->mmio, i++ * 4, 0x00408004);
 122         nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
 123         nv_wo32(grch->mmio, i++ * 4, 0x00408008);
 124         nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 125
 126         nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
 127         nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
 128         nv_wo32(grch->mmio, i++ * 4, 0x00408010);
 129         nv_wo32(grch->mmio, i++ * 4, 0x80000000);
 130
 131         nv_wo32(grch->mmio, i++ * 4, 0x00418810);
 132         nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12);
 133         nv_wo32(grch->mmio, i++ * 4, 0x00419848);
 134         nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12);
 135
 136         nv_wo32(grch->mmio, i++ * 4, 0x00419004);
 137         nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
 138         nv_wo32(grch->mmio, i++ * 4, 0x00419008);
 139         nv_wo32(grch->mmio, i++ * 4, 0x00000000);
 140
 141         nv_wo32(grch->mmio, i++ * 4, 0x00418808);
 142         nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
 143         nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
 144         nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 145
 146         magic = 0x02180000;
 147         nv_wo32(grch->mmio, i++ * 4, 0x00405830);
 148         nv_wo32(grch->mmio, i++ * 4, magic);
 149         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 150                 for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x02fc) {
 151                         u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
 152                         nv_wo32(grch->mmio, i++ * 4, reg);
 153                         nv_wo32(grch->mmio, i++ * 4, magic);
 154                 }
 155         }
 156
 157         grch->mmio_nr = i / 2;
 158         return 0;
 159 }
 160
 161 int
 162 nvc0_graph_create_context(struct nouveau_channel *chan)
 163 {
 164         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
 165         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
 166         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 167         struct nvc0_graph_priv *priv = pgraph->priv;
 168         struct nvc0_graph_chan *grch;
 169         struct drm_device *dev = chan->dev;
 170         struct nouveau_gpuobj *grctx;
 171         int ret, i;
 172
 173         chan->pgraph_ctx = kzalloc(sizeof(*grch), GFP_KERNEL);
 174         if (!chan->pgraph_ctx)
 175                 return -ENOMEM;
 176         grch = chan->pgraph_ctx;
 177
 178         ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256,
 179                                  NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
 180                                  &grch->grctx);
 181         if (ret)
 182                 goto error;
 183         chan->ramin_grctx = grch->grctx;
 184         grctx = grch->grctx;
 185
 186         ret = nvc0_graph_create_context_mmio_list(chan);
 187         if (ret)
 188                 goto error;
 189
 190         nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4);
 191         nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst));
 192         pinstmem->flush(dev);
 193
 194         if (!priv->grctx_vals) {
 195                 ret = nvc0_graph_construct_context(chan);
 196                 if (ret)
 197                         goto error;
 198         }
 199
 200         for (i = 0; i < priv->grctx_size; i += 4)
 201                 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
 202
 203         nv_wo32(grctx, 0xf4, 0);
 204         nv_wo32(grctx, 0xf8, 0);
 205         nv_wo32(grctx, 0x10, grch->mmio_nr);
 206         nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));
 207         nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));
 208         nv_wo32(grctx, 0x1c, 1);
 209         nv_wo32(grctx, 0x20, 0);
 210         nv_wo32(grctx, 0x28, 0);
 211         nv_wo32(grctx, 0x2c, 0);
 212         pinstmem->flush(dev);
 213         return 0;
 214
 215 error:
 216         pgraph->destroy_context(chan);
 217         return ret;
 218 }
 219
 220 void
 221 nvc0_graph_destroy_context(struct nouveau_channel *chan)
 222 {
 223         struct nvc0_graph_chan *grch;
 224
 225         grch = chan->pgraph_ctx;
 226         chan->pgraph_ctx = NULL;
 227         if (!grch)
 228                 return;
 229
 230         nouveau_gpuobj_ref(NULL, &grch->mmio);
 231         nouveau_gpuobj_ref(NULL, &grch->unk418810);
 232         nouveau_gpuobj_ref(NULL, &grch->unk40800c);
 233         nouveau_gpuobj_ref(NULL, &grch->unk408004);
 234         nouveau_gpuobj_ref(NULL, &grch->grctx);
 235         chan->ramin_grctx = NULL;
 236 }
 237
 238 int
 239 nvc0_graph_load_context(struct nouveau_channel *chan)
 240 {
 241         struct drm_device *dev = chan->dev;
 242
 243         nv_wr32(dev, 0x409840, 0x00000030);
 244         nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
 245         nv_wr32(dev, 0x409504, 0x00000003);
 246         if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
 247                 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
 248
 249         return 0;
 250 }
 251
 252 static int
 253 nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
 254 {
 255         nv_wr32(dev, 0x409840, 0x00000003);
 256         nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
 257         nv_wr32(dev, 0x409504, 0x00000009);
 258         if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
 259                 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
 260                 return -EBUSY;
 261         }
 262
 263         return 0;
 264 }
 265
 266 int
 267 nvc0_graph_unload_context(struct drm_device *dev)
 268 {
 269         u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
 270         return nvc0_graph_unload_context_to(dev, inst);
 271 }
 272
 273 static void
 274 nvc0_graph_destroy(struct drm_device *dev)
 275 {
 276         struct drm_nouveau_private *dev_priv = dev->dev_private;
 277         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 278         struct nvc0_graph_priv *priv;
 279
 280         priv = pgraph->priv;
 281         if (!priv)
 282                 return;
 283
 284         nouveau_irq_unregister(dev, 12);
 285         nouveau_irq_unregister(dev, 25);
 286
 287         nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
 288         nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
 289
 290         if (priv->grctx_vals)
 291                 kfree(priv->grctx_vals);
 292         kfree(priv);
 293 }
 294
 295 void
 296 nvc0_graph_takedown(struct drm_device *dev)
 297 {
 298         nvc0_graph_destroy(dev);
 299 }
 300
 301 static int
 302 nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
 303                           u32 class, u32 mthd, u32 data)
 304 {
 305         nouveau_finish_page_flip(chan, NULL);
 306         return 0;
 307 }
 308
 309 static int
 310 nvc0_graph_create(struct drm_device *dev)
 311 {
 312         struct drm_nouveau_private *dev_priv = dev->dev_private;
 313         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 314         struct nvc0_graph_priv *priv;
 315         int ret, gpc, i;
 316
 317         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 318         if (!priv)
 319                 return -ENOMEM;
 320         pgraph->priv = priv;
 321
 322         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
 323         if (ret)
 324                 goto error;
 325
 326         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
 327         if (ret)
 328                 goto error;
 329
 330         for (i = 0; i < 0x1000; i += 4) {
 331                 nv_wo32(priv->unk4188b4, i, 0x00000010);
 332                 nv_wo32(priv->unk4188b8, i, 0x00000010);
 333         }
 334
 335         priv->gpc_nr  =  nv_rd32(dev, 0x409604) & 0x0000001f;
 336         priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
 337         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 338                 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
 339                 priv->tp_total += priv->tp_nr[gpc];
 340         }
 341
 342         /*XXX: these need figuring out... */
 343         switch (dev_priv->chipset) {
 344         case 0xc0:
 345                 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
 346                         priv->magic_not_rop_nr = 0x07;
 347                         /* filled values up to tp_total, the rest 0 */
 348                         priv->magicgpc980[0]   = 0x22111000;
 349                         priv->magicgpc980[1]   = 0x00000233;
 350                         priv->magicgpc980[2]   = 0x00000000;
 351                         priv->magicgpc980[3]   = 0x00000000;
 352                         priv->magicgpc918      = 0x000ba2e9;
 353                 } else
 354                 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
 355                         priv->magic_not_rop_nr = 0x05;
 356                         priv->magicgpc980[0]   = 0x11110000;
 357                         priv->magicgpc980[1]   = 0x00233222;
 358                         priv->magicgpc980[2]   = 0x00000000;
 359                         priv->magicgpc980[3]   = 0x00000000;
 360                         priv->magicgpc918      = 0x00092493;
 361                 } else
 362                 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
 363                         priv->magic_not_rop_nr = 0x06;
 364                         priv->magicgpc980[0]   = 0x11110000;
 365                         priv->magicgpc980[1]   = 0x03332222;
 366                         priv->magicgpc980[2]   = 0x00000000;
 367                         priv->magicgpc980[3]   = 0x00000000;
 368                         priv->magicgpc918      = 0x00088889;
 369                 }
 370                 break;
 371         case 0xc3: /* 450, 4/0/0/0, 2 */
 372                 priv->magic_not_rop_nr = 0x03;
 373                 priv->magicgpc980[0]   = 0x00003210;
 374                 priv->magicgpc980[1]   = 0x00000000;
 375                 priv->magicgpc980[2]   = 0x00000000;
 376                 priv->magicgpc980[3]   = 0x00000000;
 377                 priv->magicgpc918      = 0x00200000;
 378                 break;
 379         case 0xc4: /* 460, 3/4/0/0, 4 */
 380                 priv->magic_not_rop_nr = 0x01;
 381                 priv->magicgpc980[0]   = 0x02321100;
 382                 priv->magicgpc980[1]   = 0x00000000;
 383                 priv->magicgpc980[2]   = 0x00000000;
 384                 priv->magicgpc980[3]   = 0x00000000;
 385                 priv->magicgpc918      = 0x00124925;
 386                 break;
 387         }
 388
 389         if (!priv->magic_not_rop_nr) {
 390                 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
 391                          priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
 392                          priv->tp_nr[3], priv->rop_nr);
 393                 /* use 0xc3's values... */
 394                 priv->magic_not_rop_nr = 0x03;
 395                 priv->magicgpc980[0]   = 0x00003210;
 396                 priv->magicgpc980[1]   = 0x00000000;
 397                 priv->magicgpc980[2]   = 0x00000000;
 398                 priv->magicgpc980[3]   = 0x00000000;
 399                 priv->magicgpc918      = 0x00200000;
 400         }
 401
 402         nouveau_irq_register(dev, 12, nvc0_graph_isr);
 403         nouveau_irq_register(dev, 25, nvc0_runk140_isr);
 404         NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
 405         NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
 406         NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
 407         NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
 408         NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
 409         return 0;
 410
 411 error:
 412         nvc0_graph_destroy(dev);
 413         return ret;
 414 }
 415
 416 static void
 417 nvc0_graph_init_obj418880(struct drm_device *dev)
 418 {
 419         struct drm_nouveau_private *dev_priv = dev->dev_private;
 420         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 421         struct nvc0_graph_priv *priv = pgraph->priv;
 422         int i;
 423
 424         nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
 425         nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
 426         for (i = 0; i < 4; i++)
 427                 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
 428         nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
 429         nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
 430 }
 431
 432 static void
 433 nvc0_graph_init_regs(struct drm_device *dev)
 434 {
 435         nv_wr32(dev, 0x400080, 0x003083c2);
 436         nv_wr32(dev, 0x400088, 0x00006fe7);
 437         nv_wr32(dev, 0x40008c, 0x00000000);
 438         nv_wr32(dev, 0x400090, 0x00000030);
 439         nv_wr32(dev, 0x40013c, 0x013901f7);
 440         nv_wr32(dev, 0x400140, 0x00000100);
 441         nv_wr32(dev, 0x400144, 0x00000000);
 442         nv_wr32(dev, 0x400148, 0x00000110);
 443         nv_wr32(dev, 0x400138, 0x00000000);
 444         nv_wr32(dev, 0x400130, 0x00000000);
 445         nv_wr32(dev, 0x400134, 0x00000000);
 446         nv_wr32(dev, 0x400124, 0x00000002);
 447 }
 448
 449 static void
 450 nvc0_graph_init_gpc_0(struct drm_device *dev)
 451 {
 452         struct drm_nouveau_private *dev_priv = dev->dev_private;
 453         struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
 454         int gpc;
 455
 456         //      TP      ROP UNKVAL(magic_not_rop_nr)
 457         // 450: 4/0/0/0 2        3
 458         // 460: 3/4/0/0 4        1
 459         // 465: 3/4/4/0 4        7
 460         // 470: 3/3/4/4 5        5
 461         // 480: 3/4/4/4 6        6
 462
 463         // magicgpc918
 464         // 450: 00200000 00000000001000000000000000000000
 465         // 460: 00124925 00000000000100100100100100100101
 466         // 465: 000ba2e9 00000000000010111010001011101001
 467         // 470: 00092493 00000000000010010010010010010011
 468         // 480: 00088889 00000000000010001000100010001001
 469
 470         /* filled values up to tp_total, remainder 0 */
 471         // 450: 00003210 00000000 00000000 00000000
 472         // 460: 02321100 00000000 00000000 00000000
 473         // 465: 22111000 00000233 00000000 00000000
 474         // 470: 11110000 00233222 00000000 00000000
 475         // 480: 11110000 03332222 00000000 00000000
 476
 477         nv_wr32(dev, GPC_BCAST(0x0980), priv->magicgpc980[0]);
 478         nv_wr32(dev, GPC_BCAST(0x0984), priv->magicgpc980[1]);
 479         nv_wr32(dev, GPC_BCAST(0x0988), priv->magicgpc980[2]);
 480         nv_wr32(dev, GPC_BCAST(0x098c), priv->magicgpc980[3]);
 481
 482         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 483                 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
 484                                                   priv->tp_nr[gpc]);
 485                 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
 486                 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918);
 487         }
 488
 489         nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918);
 490         nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr);
 491 }
 492
 493 static void
 494 nvc0_graph_init_units(struct drm_device *dev)
 495 {
 496         nv_wr32(dev, 0x409c24, 0x000f0000);
 497         nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
 498         nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
 499         nv_wr32(dev, 0x408030, 0xc0000000);
 500         nv_wr32(dev, 0x40601c, 0xc0000000);
 501         nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
 502         nv_wr32(dev, 0x406018, 0xc0000000);
 503         nv_wr32(dev, 0x405840, 0xc0000000);
 504         nv_wr32(dev, 0x405844, 0x00ffffff);
 505         nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
 506         nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
 507 }
 508
 509 static void
 510 nvc0_graph_init_gpc_1(struct drm_device *dev)
 511 {
 512         struct drm_nouveau_private *dev_priv = dev->dev_private;
 513         struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
 514         int gpc, tp;
 515
 516         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 517                 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 518                 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 519                 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 520                 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 521                 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
 522                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
 523                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
 524                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
 525                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
 526                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
 527                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
 528                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
 529                 }
 530                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
 531                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
 532         }
 533 }
 534
 535 static void
 536 nvc0_graph_init_rop(struct drm_device *dev)
 537 {
 538         struct drm_nouveau_private *dev_priv = dev->dev_private;
 539         struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
 540         int rop;
 541
 542         for (rop = 0; rop < priv->rop_nr; rop++) {
 543                 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
 544                 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
 545                 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
 546                 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
 547         }
 548 }
 549
 550 static int
 551 nvc0_fuc_load_fw(struct drm_device *dev, u32 fuc_base,
 552                  const char *code_fw, const char *data_fw)
 553 {
 554         const struct firmware *fw;
 555         char name[32];
 556         int ret, i;
 557
 558         snprintf(name, sizeof(name), "nouveau/%s", data_fw);
 559         ret = request_firmware(&fw, name, &dev->pdev->dev);
 560         if (ret) {
 561                 NV_ERROR(dev, "failed to load %s\n", data_fw);
 562                 return ret;
 563         }
 564
 565         nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
 566         for (i = 0; i < fw->size / 4; i++)
 567                 nv_wr32(dev, fuc_base + 0x01c4, ((u32 *)fw->data)[i]);
 568         release_firmware(fw);
 569
 570         snprintf(name, sizeof(name), "nouveau/%s", code_fw);
 571         ret = request_firmware(&fw, name, &dev->pdev->dev);
 572         if (ret) {
 573                 NV_ERROR(dev, "failed to load %s\n", code_fw);
 574                 return ret;
 575         }
 576
 577         nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
 578         for (i = 0; i < fw->size / 4; i++) {
 579                 if ((i & 0x3f) == 0)
 580                         nv_wr32(dev, fuc_base + 0x0188, i >> 6);
 581                 nv_wr32(dev, fuc_base + 0x0184, ((u32 *)fw->data)[i]);
 582         }
 583         release_firmware(fw);
 584
 585         return 0;
 586 }
 587
 588 static int
 589 nvc0_graph_init_ctxctl(struct drm_device *dev)
 590 {
 591         struct drm_nouveau_private *dev_priv = dev->dev_private;
 592         struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
 593         u32 r000260;
 594         int ret;
 595
 596         /* load fuc microcode */
 597         r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
 598         ret = nvc0_fuc_load_fw(dev, 0x409000, "fuc409c", "fuc409d");
 599         if (ret == 0)
 600                 ret = nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad");
 601         nv_wr32(dev, 0x000260, r000260);
 602
 603         if (ret)
 604                 return ret;
 605
 606         /* start both of them running */
 607         nv_wr32(dev, 0x409840, 0xffffffff);
 608         nv_wr32(dev, 0x41a10c, 0x00000000);
 609         nv_wr32(dev, 0x40910c, 0x00000000);
 610         nv_wr32(dev, 0x41a100, 0x00000002);
 611         nv_wr32(dev, 0x409100, 0x00000002);
 612         if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
 613                 NV_INFO(dev, "0x409800 wait failed\n");
 614
 615         nv_wr32(dev, 0x409840, 0xffffffff);
 616         nv_wr32(dev, 0x409500, 0x7fffffff);
 617         nv_wr32(dev, 0x409504, 0x00000021);
 618
 619         nv_wr32(dev, 0x409840, 0xffffffff);
 620         nv_wr32(dev, 0x409500, 0x00000000);
 621         nv_wr32(dev, 0x409504, 0x00000010);
 622         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 623                 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
 624                 return -EBUSY;
 625         }
 626         priv->grctx_size = nv_rd32(dev, 0x409800);
 627
 628         nv_wr32(dev, 0x409840, 0xffffffff);
 629         nv_wr32(dev, 0x409500, 0x00000000);
 630         nv_wr32(dev, 0x409504, 0x00000016);
 631         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 632                 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
 633                 return -EBUSY;
 634         }
 635
 636         nv_wr32(dev, 0x409840, 0xffffffff);
 637         nv_wr32(dev, 0x409500, 0x00000000);
 638         nv_wr32(dev, 0x409504, 0x00000025);
 639         if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 640                 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
 641                 return -EBUSY;
 642         }
 643
 644         return 0;
 645 }
 646
 647 int
 648 nvc0_graph_init(struct drm_device *dev)
 649 {
 650         struct drm_nouveau_private *dev_priv = dev->dev_private;
 651         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
 652         int ret;
 653
 654         dev_priv->engine.graph.accel_blocked = true;
 655
 656         switch (dev_priv->chipset) {
 657         case 0xc0:
 658         case 0xc3:
 659         case 0xc4:
 660                 break;
 661         default:
 662                 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
 663                 if (nouveau_noaccel != 0)
 664                         return 0;
 665                 break;
 666         }
 667
 668         nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
 669         nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
 670
 671         if (!pgraph->priv) {
 672                 ret = nvc0_graph_create(dev);
 673                 if (ret)
 674                         return ret;
 675         }
 676
 677         nvc0_graph_init_obj418880(dev);
 678         nvc0_graph_init_regs(dev);
 679         //nvc0_graph_init_unitplemented_magics(dev);
 680         nvc0_graph_init_gpc_0(dev);
 681         //nvc0_graph_init_unitplemented_c242(dev);
 682
 683         nv_wr32(dev, 0x400500, 0x00010001);
 684         nv_wr32(dev, 0x400100, 0xffffffff);
 685         nv_wr32(dev, 0x40013c, 0xffffffff);
 686
 687         nvc0_graph_init_units(dev);
 688         nvc0_graph_init_gpc_1(dev);
 689         nvc0_graph_init_rop(dev);
 690
 691         nv_wr32(dev, 0x400108, 0xffffffff);
 692         nv_wr32(dev, 0x400138, 0xffffffff);
 693         nv_wr32(dev, 0x400118, 0xffffffff);
 694         nv_wr32(dev, 0x400130, 0xffffffff);
 695         nv_wr32(dev, 0x40011c, 0xffffffff);
 696         nv_wr32(dev, 0x400134, 0xffffffff);
 697         nv_wr32(dev, 0x400054, 0x34ce3464);
 698
 699         ret = nvc0_graph_init_ctxctl(dev);
 700         if (ret == 0)
 701                 dev_priv->engine.graph.accel_blocked = false;
 702         return 0;
 703 }
 704
 705 static int
 706 nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
 707 {
 708         struct drm_nouveau_private *dev_priv = dev->dev_private;
 709         struct nouveau_channel *chan;
 710         unsigned long flags;
 711         int i;
 712
 713         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 714         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 715                 chan = dev_priv->channels.ptr[i];
 716                 if (!chan || !chan->ramin)
 717                         continue;
 718
 719                 if (inst == chan->ramin->vinst)
 720                         break;
 721         }
 722         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 723         return i;
 724 }
 725
 726 static void
 727 nvc0_graph_isr(struct drm_device *dev)
 728 {
 729         u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
 730         u32 chid = nvc0_graph_isr_chid(dev, inst);
 731         u32 stat = nv_rd32(dev, 0x400100);
 732         u32 addr = nv_rd32(dev, 0x400704);
 733         u32 mthd = (addr & 0x00003ffc);
 734         u32 subc = (addr & 0x00070000) >> 16;
 735         u32 data = nv_rd32(dev, 0x400708);
 736         u32 code = nv_rd32(dev, 0x400110);
 737         u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
 738
 739         if (stat & 0x00000010) {
 740                 if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
 741                         NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
 742                                      "subc %d class 0x%04x mthd 0x%04x "
 743                                      "data 0x%08x\n",
 744                                 chid, inst, subc, class, mthd, data);
 745                 }
 746                 nv_wr32(dev, 0x400100, 0x00000010);
 747                 stat &= ~0x00000010;
 748         }
 749
 750         if (stat & 0x00000020) {
 751                 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
 752                              "class 0x%04x mthd 0x%04x data 0x%08x\n",
 753                         chid, inst, subc, class, mthd, data);
 754                 nv_wr32(dev, 0x400100, 0x00000020);
 755                 stat &= ~0x00000020;
 756         }
 757
 758         if (stat & 0x00100000) {
 759                 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
 760                 nouveau_enum_print(nv50_data_error_names, code);
 761                 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
 762                        "mthd 0x%04x data 0x%08x\n",
 763                        chid, inst, subc, class, mthd, data);
 764                 nv_wr32(dev, 0x400100, 0x00100000);
 765                 stat &= ~0x00100000;
 766         }
 767
 768         if (stat & 0x00200000) {
 769                 u32 trap = nv_rd32(dev, 0x400108);
 770                 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
 771                 nv_wr32(dev, 0x400108, trap);
 772                 nv_wr32(dev, 0x400100, 0x00200000);
 773                 stat &= ~0x00200000;
 774         }
 775
 776         if (stat & 0x00080000) {
 777                 u32 ustat = nv_rd32(dev, 0x409c18);
 778
 779                 NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat);
 780
 781                 nv_wr32(dev, 0x409c20, ustat);
 782                 nv_wr32(dev, 0x400100, 0x00080000);
 783                 stat &= ~0x00080000;
 784         }
 785
 786         if (stat) {
 787                 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
 788                 nv_wr32(dev, 0x400100, stat);
 789         }
 790
 791         nv_wr32(dev, 0x400500, 0x00010001);
 792 }
 793
 794 static void
 795 nvc0_runk140_isr(struct drm_device *dev)
 796 {
 797         u32 units = nv_rd32(dev, 0x00017c) & 0x1f;
 798
 799         while (units) {
 800                 u32 unit = ffs(units) - 1;
 801                 u32 reg = 0x140000 + unit * 0x2000;
 802                 u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0);
 803                 u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0);
 804
 805                 NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1);
 806                 units &= ~(1 << unit);
 807         }
 808 }