drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nouveau_drm.h"
  28 #include "nouveau_dma.h"
  29
  30 #include "nv50_display.h"
  31 #include "nouveau_crtc.h"
  32 #include "nouveau_encoder.h"
  33 #include "nouveau_connector.h"
  34 #include "nouveau_fbcon.h"
  35 #include <drm/drm_crtc_helper.h>
  36 #include "nouveau_fence.h"
  37
  38 #include <core/gpuobj.h>
  39 #include <subdev/timer.h>
  40
  41 static void nv50_display_bh(unsigned long);
  42
  43 static inline int
  44 nv50_sor_nr(struct drm_device *dev)
  45 {
  46         struct nouveau_device *device = nouveau_dev(dev);
  47
  48         if (device->chipset  < 0x90 ||
  49             device->chipset == 0x92 ||
  50             device->chipset == 0xa0)
  51                 return 2;
  52
  53         return 4;
  54 }
  55
  56 u32
  57 nv50_display_active_crtcs(struct drm_device *dev)
  58 {
  59         struct nouveau_device *device = nouveau_dev(dev);
  60         u32 mask = 0;
  61         int i;
  62
  63         if (device->chipset  < 0x90 ||
  64             device->chipset == 0x92 ||
  65             device->chipset == 0xa0) {
  66                 for (i = 0; i < 2; i++)
  67                         mask |= nv_rd32(device, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
  68         } else {
  69                 for (i = 0; i < 4; i++)
  70                         mask |= nv_rd32(device, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
  71         }
  72
  73         for (i = 0; i < 3; i++)
  74                 mask |= nv_rd32(device, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
  75
  76         return mask & 3;
  77 }
  78
  79 int
  80 nv50_display_early_init(struct drm_device *dev)
  81 {
  82         return 0;
  83 }
  84
  85 void
  86 nv50_display_late_takedown(struct drm_device *dev)
  87 {
  88 }
  89
  90 int
  91 nv50_display_sync(struct drm_device *dev)
  92 {
  93         struct nv50_display *disp = nv50_display(dev);
  94         struct nouveau_channel *evo = disp->master;
  95         int ret;
  96
  97         ret = RING_SPACE(evo, 6);
  98         if (ret == 0) {
  99                 BEGIN_NV04(evo, 0, 0x0084, 1);
 100                 OUT_RING  (evo, 0x80000000);
 101                 BEGIN_NV04(evo, 0, 0x0080, 1);
 102                 OUT_RING  (evo, 0);
 103                 BEGIN_NV04(evo, 0, 0x0084, 1);
 104                 OUT_RING  (evo, 0x00000000);
 105
 106                 nv_wo32(disp->ramin, 0x2000, 0x00000000);
 107                 FIRE_RING (evo);
 108
 109                 if (nv_wait_ne(disp->ramin, 0x2000, 0xffffffff, 0x00000000))
 110                         return 0;
 111         }
 112
 113         return 0;
 114 }
 115
 116 int
 117 nv50_display_init(struct drm_device *dev)
 118 {
 119         struct nouveau_drm *drm = nouveau_drm(dev);
 120         struct nouveau_device *device = nouveau_dev(dev);
 121         struct nouveau_channel *evo;
 122         int ret, i;
 123         u32 val;
 124
 125         NV_DEBUG(drm, "\n");
 126
 127         nv_wr32(device, 0x00610184, nv_rd32(device, 0x00614004));
 128
 129         /*
 130          * I think the 0x006101XX range is some kind of main control area
 131          * that enables things.
 132          */
 133         /* CRTC? */
 134         for (i = 0; i < 2; i++) {
 135                 val = nv_rd32(device, 0x00616100 + (i * 0x800));
 136                 nv_wr32(device, 0x00610190 + (i * 0x10), val);
 137                 val = nv_rd32(device, 0x00616104 + (i * 0x800));
 138                 nv_wr32(device, 0x00610194 + (i * 0x10), val);
 139                 val = nv_rd32(device, 0x00616108 + (i * 0x800));
 140                 nv_wr32(device, 0x00610198 + (i * 0x10), val);
 141                 val = nv_rd32(device, 0x0061610c + (i * 0x800));
 142                 nv_wr32(device, 0x0061019c + (i * 0x10), val);
 143         }
 144
 145         /* DAC */
 146         for (i = 0; i < 3; i++) {
 147                 val = nv_rd32(device, 0x0061a000 + (i * 0x800));
 148                 nv_wr32(device, 0x006101d0 + (i * 0x04), val);
 149         }
 150
 151         /* SOR */
 152         for (i = 0; i < nv50_sor_nr(dev); i++) {
 153                 val = nv_rd32(device, 0x0061c000 + (i * 0x800));
 154                 nv_wr32(device, 0x006101e0 + (i * 0x04), val);
 155         }
 156
 157         /* EXT */
 158         for (i = 0; i < 3; i++) {
 159                 val = nv_rd32(device, 0x0061e000 + (i * 0x800));
 160                 nv_wr32(device, 0x006101f0 + (i * 0x04), val);
 161         }
 162
 163         for (i = 0; i < 3; i++) {
 164                 nv_wr32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 165                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 166                 nv_wr32(device, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 167         }
 168
 169         /* The precise purpose is unknown, i suspect it has something to do
 170          * with text mode.
 171          */
 172         if (nv_rd32(device, NV50_PDISPLAY_INTR_1) & 0x100) {
 173                 nv_wr32(device, NV50_PDISPLAY_INTR_1, 0x100);
 174                 nv_wr32(device, 0x006194e8, nv_rd32(device, 0x006194e8) & ~1);
 175                 if (!nv_wait(device, 0x006194e8, 2, 0)) {
 176                         NV_ERROR(drm, "timeout: (0x6194e8 & 2) != 0\n");
 177                         NV_ERROR(drm, "0x6194e8 = 0x%08x\n",
 178                                                 nv_rd32(device, 0x6194e8));
 179                         return -EBUSY;
 180                 }
 181         }
 182
 183         for (i = 0; i < 2; i++) {
 184                 nv_wr32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 185                 if (!nv_wait(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 186                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 187                         NV_ERROR(drm, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 188                         NV_ERROR(drm, "CURSOR_CTRL2 = 0x%08x\n",
 189                                  nv_rd32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 190                         return -EBUSY;
 191                 }
 192
 193                 nv_wr32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 194                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 195                 if (!nv_wait(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 196                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 197                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 198                         NV_ERROR(drm, "timeout: "
 199                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 200                         NV_ERROR(drm, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 201                                  nv_rd32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 202                         return -EBUSY;
 203                 }
 204         }
 205
 206         nv_wr32(device, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
 207         nv_mask(device, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
 208         nv_wr32(device, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
 209         nv_mask(device, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
 210         nv_wr32(device, NV50_PDISPLAY_INTR_EN_1,
 211                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
 212                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
 213                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
 214
 215         ret = nv50_evo_init(dev);
 216         if (ret)
 217                 return ret;
 218         evo = nv50_display(dev)->master;
 219
 220         nv_wr32(device, NV50_PDISPLAY_OBJECTS, (nv50_display(dev)->ramin->addr >> 8) | 9);
 221
 222         ret = RING_SPACE(evo, 3);
 223         if (ret)
 224                 return ret;
 225         BEGIN_NV04(evo, 0, NV50_EVO_UNK84, 2);
 226         OUT_RING  (evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 227         OUT_RING  (evo, NvEvoSync);
 228
 229         return nv50_display_sync(dev);
 230 }
 231
 232 void
 233 nv50_display_fini(struct drm_device *dev)
 234 {
 235         struct nouveau_drm *drm = nouveau_drm(dev);
 236         struct nouveau_device *device = nouveau_dev(dev);
 237         struct nv50_display *disp = nv50_display(dev);
 238         struct nouveau_channel *evo = disp->master;
 239         struct drm_crtc *drm_crtc;
 240         int ret, i;
 241
 242         NV_DEBUG(drm, "\n");
 243
 244         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 245                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 246
 247                 nv50_crtc_blank(crtc, true);
 248         }
 249
 250         ret = RING_SPACE(evo, 2);
 251         if (ret == 0) {
 252                 BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1);
 253                 OUT_RING(evo, 0);
 254         }
 255         FIRE_RING(evo);
 256
 257         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 258          * cleaning up?
 259          */
 260         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 261                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 262                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 263
 264                 if (!crtc->base.enabled)
 265                         continue;
 266
 267                 nv_wr32(device, NV50_PDISPLAY_INTR_1, mask);
 268                 if (!nv_wait(device, NV50_PDISPLAY_INTR_1, mask, mask)) {
 269                         NV_ERROR(drm, "timeout: (0x610024 & 0x%08x) == "
 270                                       "0x%08x\n", mask, mask);
 271                         NV_ERROR(drm, "0x610024 = 0x%08x\n",
 272                                  nv_rd32(device, NV50_PDISPLAY_INTR_1));
 273                 }
 274         }
 275
 276         for (i = 0; i < 2; i++) {
 277                 nv_wr32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0);
 278                 if (!nv_wait(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 279                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 280                         NV_ERROR(drm, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 281                         NV_ERROR(drm, "CURSOR_CTRL2 = 0x%08x\n",
 282                                  nv_rd32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 283                 }
 284         }
 285
 286         nv50_evo_fini(dev);
 287
 288         for (i = 0; i < 3; i++) {
 289                 if (!nv_wait(device, NV50_PDISPLAY_SOR_DPMS_STATE(i),
 290                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 291                         NV_ERROR(drm, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 292                         NV_ERROR(drm, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 293                                   nv_rd32(device, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 294                 }
 295         }
 296
 297         /* disable interrupts. */
 298         nv_wr32(device, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
 299 }
 300
 301 int
 302 nv50_display_create(struct drm_device *dev)
 303 {
 304         struct nouveau_drm *drm = nouveau_drm(dev);
 305         struct dcb_table *dcb = &drm->vbios.dcb;
 306         struct drm_connector *connector, *ct;
 307         struct nv50_display *priv;
 308         int ret, i;
 309
 310         NV_DEBUG(drm, "\n");
 311
 312         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 313         if (!priv)
 314                 return -ENOMEM;
 315
 316         nouveau_display(dev)->priv = priv;
 317         nouveau_display(dev)->dtor = nv50_display_destroy;
 318         nouveau_display(dev)->init = nv50_display_init;
 319         nouveau_display(dev)->fini = nv50_display_fini;
 320
 321         /* Create CRTC objects */
 322         for (i = 0; i < 2; i++) {
 323                 ret = nv50_crtc_create(dev, i);
 324                 if (ret)
 325                         return ret;
 326         }
 327
 328         /* We setup the encoders from the BIOS table */
 329         for (i = 0 ; i < dcb->entries; i++) {
 330                 struct dcb_output *entry = &dcb->entry[i];
 331
 332                 if (entry->location != DCB_LOC_ON_CHIP) {
 333                         NV_WARN(drm, "Off-chip encoder %d/%d unsupported\n",
 334                                 entry->type, ffs(entry->or) - 1);
 335                         continue;
 336                 }
 337
 338                 connector = nouveau_connector_create(dev, entry->connector);
 339                 if (IS_ERR(connector))
 340                         continue;
 341
 342                 switch (entry->type) {
 343                 case DCB_OUTPUT_TMDS:
 344                 case DCB_OUTPUT_LVDS:
 345                 case DCB_OUTPUT_DP:
 346                         nv50_sor_create(connector, entry);
 347                         break;
 348                 case DCB_OUTPUT_ANALOG:
 349                         nv50_dac_create(connector, entry);
 350                         break;
 351                 default:
 352                         NV_WARN(drm, "DCB encoder %d unknown\n", entry->type);
 353                         continue;
 354                 }
 355         }
 356
 357         list_for_each_entry_safe(connector, ct,
 358                                  &dev->mode_config.connector_list, head) {
 359                 if (!connector->encoder_ids[0]) {
 360                         NV_WARN(drm, "%s has no encoders, removing\n",
 361                                 drm_get_connector_name(connector));
 362                         connector->funcs->destroy(connector);
 363                 }
 364         }
 365
 366         tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
 367
 368         ret = nv50_evo_create(dev);
 369         if (ret) {
 370                 nv50_display_destroy(dev);
 371                 return ret;
 372         }
 373
 374         return 0;
 375 }
 376
 377 void
 378 nv50_display_destroy(struct drm_device *dev)
 379 {
 380         struct nv50_display *disp = nv50_display(dev);
 381
 382         nv50_evo_destroy(dev);
 383         kfree(disp);
 384 }
 385
 386 struct nouveau_bo *
 387 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 388 {
 389         return nv50_display(dev)->crtc[crtc].sem.bo;
 390 }
 391
 392 void
 393 nv50_display_flip_stop(struct drm_crtc *crtc)
 394 {
 395         struct nv50_display *disp = nv50_display(crtc->dev);
 396         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 397         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 398         struct nouveau_channel *evo = dispc->sync;
 399         int ret;
 400
 401         ret = RING_SPACE(evo, 8);
 402         if (ret) {
 403                 WARN_ON(1);
 404                 return;
 405         }
 406
 407         BEGIN_NV04(evo, 0, 0x0084, 1);
 408         OUT_RING  (evo, 0x00000000);
 409         BEGIN_NV04(evo, 0, 0x0094, 1);
 410         OUT_RING  (evo, 0x00000000);
 411         BEGIN_NV04(evo, 0, 0x00c0, 1);
 412         OUT_RING  (evo, 0x00000000);
 413         BEGIN_NV04(evo, 0, 0x0080, 1);
 414         OUT_RING  (evo, 0x00000000);
 415         FIRE_RING (evo);
 416 }
 417
 418 int
 419 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 420                        struct nouveau_channel *chan)
 421 {
 422         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
 423         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 424         struct nv50_display *disp = nv50_display(crtc->dev);
 425         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 426         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 427         struct nouveau_channel *evo = dispc->sync;
 428         int ret;
 429
 430         ret = RING_SPACE(evo, chan ? 25 : 27);
 431         if (unlikely(ret))
 432                 return ret;
 433
 434         /* synchronise with the rendering channel, if necessary */
 435         if (likely(chan)) {
 436                 ret = RING_SPACE(chan, 10);
 437                 if (ret) {
 438                         WIND_RING(evo);
 439                         return ret;
 440                 }
 441
 442                 if (nv_device(drm->device)->chipset < 0xc0) {
 443                         BEGIN_NV04(chan, 0, 0x0060, 2);
 444                         OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 445                         OUT_RING  (chan, dispc->sem.offset);
 446                         BEGIN_NV04(chan, 0, 0x006c, 1);
 447                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 448                         BEGIN_NV04(chan, 0, 0x0064, 2);
 449                         OUT_RING  (chan, dispc->sem.offset ^ 0x10);
 450                         OUT_RING  (chan, 0x74b1e000);
 451                         BEGIN_NV04(chan, 0, 0x0060, 1);
 452                         if (nv_device(drm->device)->chipset < 0x84)
 453                                 OUT_RING  (chan, NvSema);
 454                         else
 455                                 OUT_RING  (chan, chan->vram);
 456                 } else {
 457                         u64 offset = nvc0_fence_crtc(chan, nv_crtc->index);
 458                         offset += dispc->sem.offset;
 459                         BEGIN_NVC0(chan, 0, 0x0010, 4);
 460                         OUT_RING  (chan, upper_32_bits(offset));
 461                         OUT_RING  (chan, lower_32_bits(offset));
 462                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 463                         OUT_RING  (chan, 0x1002);
 464                         BEGIN_NVC0(chan, 0, 0x0010, 4);
 465                         OUT_RING  (chan, upper_32_bits(offset));
 466                         OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 467                         OUT_RING  (chan, 0x74b1e000);
 468                         OUT_RING  (chan, 0x1001);
 469                 }
 470                 FIRE_RING (chan);
 471         } else {
 472                 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
 473                                 0xf00d0000 | dispc->sem.value);
 474         }
 475
 476         /* queue the flip on the crtc's "display sync" channel */
 477         BEGIN_NV04(evo, 0, 0x0100, 1);
 478         OUT_RING  (evo, 0xfffe0000);
 479         if (chan) {
 480                 BEGIN_NV04(evo, 0, 0x0084, 1);
 481                 OUT_RING  (evo, 0x00000100);
 482         } else {
 483                 BEGIN_NV04(evo, 0, 0x0084, 1);
 484                 OUT_RING  (evo, 0x00000010);
 485                 /* allows gamma somehow, PDISP will bitch at you if
 486                  * you don't wait for vblank before changing this..
 487                  */
 488                 BEGIN_NV04(evo, 0, 0x00e0, 1);
 489                 OUT_RING  (evo, 0x40000000);
 490         }
 491         BEGIN_NV04(evo, 0, 0x0088, 4);
 492         OUT_RING  (evo, dispc->sem.offset);
 493         OUT_RING  (evo, 0xf00d0000 | dispc->sem.value);
 494         OUT_RING  (evo, 0x74b1e000);
 495         OUT_RING  (evo, NvEvoSync);
 496         BEGIN_NV04(evo, 0, 0x00a0, 2);
 497         OUT_RING  (evo, 0x00000000);
 498         OUT_RING  (evo, 0x00000000);
 499         BEGIN_NV04(evo, 0, 0x00c0, 1);
 500         OUT_RING  (evo, nv_fb->r_dma);
 501         BEGIN_NV04(evo, 0, 0x0110, 2);
 502         OUT_RING  (evo, 0x00000000);
 503         OUT_RING  (evo, 0x00000000);
 504         BEGIN_NV04(evo, 0, 0x0800, 5);
 505         OUT_RING  (evo, nv_fb->nvbo->bo.offset >> 8);
 506         OUT_RING  (evo, 0);
 507         OUT_RING  (evo, (fb->height << 16) | fb->width);
 508         OUT_RING  (evo, nv_fb->r_pitch);
 509         OUT_RING  (evo, nv_fb->r_format);
 510         BEGIN_NV04(evo, 0, 0x0080, 1);
 511         OUT_RING  (evo, 0x00000000);
 512         FIRE_RING (evo);
 513
 514         dispc->sem.offset ^= 0x10;
 515         dispc->sem.value++;
 516         return 0;
 517 }
 518
 519 static u16
 520 nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb,
 521                            u32 mc, int pxclk)
 522 {
 523         struct nouveau_drm *drm = nouveau_drm(dev);
 524         struct nouveau_connector *nv_connector = NULL;
 525         struct drm_encoder *encoder;
 526         struct nvbios *bios = &drm->vbios;
 527         u32 script = 0, or;
 528
 529         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 530                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 531
 532                 if (nv_encoder->dcb != dcb)
 533                         continue;
 534
 535                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 536                 break;
 537         }
 538
 539         or = ffs(dcb->or) - 1;
 540         switch (dcb->type) {
 541         case DCB_OUTPUT_LVDS:
 542                 script = (mc >> 8) & 0xf;
 543                 if (bios->fp_no_ddc) {
 544                         if (bios->fp.dual_link)
 545                                 script |= 0x0100;
 546                         if (bios->fp.if_is_24bit)
 547                                 script |= 0x0200;
 548                 } else {
 549                         /* determine number of lvds links */
 550                         if (nv_connector && nv_connector->edid &&
 551                             nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
 552                                 /* http://www.spwg.org */
 553                                 if (((u8 *)nv_connector->edid)[121] == 2)
 554                                         script |= 0x0100;
 555                         } else
 556                         if (pxclk >= bios->fp.duallink_transition_clk) {
 557                                 script |= 0x0100;
 558                         }
 559
 560                         /* determine panel depth */
 561                         if (script & 0x0100) {
 562                                 if (bios->fp.strapless_is_24bit & 2)
 563                                         script |= 0x0200;
 564                         } else {
 565                                 if (bios->fp.strapless_is_24bit & 1)
 566                                         script |= 0x0200;
 567                         }
 568
 569                         if (nv_connector && nv_connector->edid &&
 570                             (nv_connector->edid->revision >= 4) &&
 571                             (nv_connector->edid->input & 0x70) >= 0x20)
 572                                 script |= 0x0200;
 573                 }
 574                 break;
 575         case DCB_OUTPUT_TMDS:
 576                 script = (mc >> 8) & 0xf;
 577                 if (pxclk >= 165000)
 578                         script |= 0x0100;
 579                 break;
 580         case DCB_OUTPUT_DP:
 581                 script = (mc >> 8) & 0xf;
 582                 break;
 583         case DCB_OUTPUT_ANALOG:
 584                 script = 0xff;
 585                 break;
 586         default:
 587                 NV_ERROR(drm, "modeset on unsupported output type!\n");
 588                 break;
 589         }
 590
 591         return script;
 592 }
 593
 594 static void
 595 nv50_display_unk10_handler(struct drm_device *dev)
 596 {
 597         struct nouveau_device *device = nouveau_dev(dev);
 598         struct nouveau_drm *drm = nouveau_drm(dev);
 599         struct nv50_display *disp = nv50_display(dev);
 600         u32 unk30 = nv_rd32(device, 0x610030), mc;
 601         int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
 602
 603         NV_DEBUG(drm, "0x610030: 0x%08x\n", unk30);
 604         disp->irq.dcb = NULL;
 605
 606         nv_wr32(device, 0x619494, nv_rd32(device, 0x619494) & ~8);
 607
 608         /* Determine which CRTC we're dealing with, only 1 ever will be
 609          * signalled at the same time with the current nouveau code.
 610          */
 611         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 612         if (crtc < 0)
 613                 goto ack;
 614
 615         /* Nothing needs to be done for the encoder */
 616         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 617         if (crtc < 0)
 618                 goto ack;
 619
 620         /* Find which encoder was connected to the CRTC */
 621         for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
 622                 mc = nv_rd32(device, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 623                 NV_DEBUG(drm, "DAC-%d mc: 0x%08x\n", i, mc);
 624                 if (!(mc & (1 << crtc)))
 625                         continue;
 626
 627                 switch ((mc & 0x00000f00) >> 8) {
 628                 case 0: type = DCB_OUTPUT_ANALOG; break;
 629                 case 1: type = DCB_OUTPUT_TV; break;
 630                 default:
 631                         NV_ERROR(drm, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 632                         goto ack;
 633                 }
 634
 635                 or = i;
 636         }
 637
 638         for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 639                 if (nv_device(drm->device)->chipset  < 0x90 ||
 640                     nv_device(drm->device)->chipset == 0x92 ||
 641                     nv_device(drm->device)->chipset == 0xa0)
 642                         mc = nv_rd32(device, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 643                 else
 644                         mc = nv_rd32(device, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 645
 646                 NV_DEBUG(drm, "SOR-%d mc: 0x%08x\n", i, mc);
 647                 if (!(mc & (1 << crtc)))
 648                         continue;
 649
 650                 switch ((mc & 0x00000f00) >> 8) {
 651                 case 0: type = DCB_OUTPUT_LVDS; break;
 652                 case 1: type = DCB_OUTPUT_TMDS; break;
 653                 case 2: type = DCB_OUTPUT_TMDS; break;
 654                 case 5: type = DCB_OUTPUT_TMDS; break;
 655                 case 8: type = DCB_OUTPUT_DP; break;
 656                 case 9: type = DCB_OUTPUT_DP; break;
 657                 default:
 658                         NV_ERROR(drm, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 659                         goto ack;
 660                 }
 661
 662                 or = i;
 663         }
 664
 665         /* There was no encoder to disable */
 666         if (type == DCB_OUTPUT_ANY)
 667                 goto ack;
 668
 669         /* Disable the encoder */
 670         for (i = 0; i < drm->vbios.dcb.entries; i++) {
 671                 struct dcb_output *dcb = &drm->vbios.dcb.entry[i];
 672
 673                 if (dcb->type == type && (dcb->or & (1 << or))) {
 674                         nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
 675                         disp->irq.dcb = dcb;
 676                         goto ack;
 677                 }
 678         }
 679
 680         NV_ERROR(drm, "no dcb for %d %d 0x%08x\n", or, type, mc);
 681 ack:
 682         nv_wr32(device, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 683         nv_wr32(device, 0x610030, 0x80000000);
 684 }
 685
 686 static void
 687 nv50_display_unk20_handler(struct drm_device *dev)
 688 {
 689         struct nouveau_device *device = nouveau_dev(dev);
 690         struct nouveau_drm *drm = nouveau_drm(dev);
 691         struct nv50_display *disp = nv50_display(dev);
 692         u32 unk30 = nv_rd32(device, 0x610030), tmp, pclk, script, mc = 0;
 693         struct dcb_output *dcb;
 694         int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
 695
 696         NV_DEBUG(drm, "0x610030: 0x%08x\n", unk30);
 697         dcb = disp->irq.dcb;
 698         if (dcb) {
 699                 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1);
 700                 disp->irq.dcb = NULL;
 701         }
 702
 703         /* CRTC clock change requested? */
 704         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 705         if (crtc >= 0) {
 706                 pclk  = nv_rd32(device, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 707                 pclk &= 0x003fffff;
 708                 if (pclk)
 709                         nv50_crtc_set_clock(dev, crtc, pclk);
 710
 711                 tmp = nv_rd32(device, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 712                 tmp &= ~0x000000f;
 713                 nv_wr32(device, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 714         }
 715
 716         /* Nothing needs to be done for the encoder */
 717         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 718         if (crtc < 0)
 719                 goto ack;
 720         pclk  = nv_rd32(device, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 721
 722         /* Find which encoder is connected to the CRTC */
 723         for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
 724                 mc = nv_rd32(device, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 725                 NV_DEBUG(drm, "DAC-%d mc: 0x%08x\n", i, mc);
 726                 if (!(mc & (1 << crtc)))
 727                         continue;
 728
 729                 switch ((mc & 0x00000f00) >> 8) {
 730                 case 0: type = DCB_OUTPUT_ANALOG; break;
 731                 case 1: type = DCB_OUTPUT_TV; break;
 732                 default:
 733                         NV_ERROR(drm, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 734                         goto ack;
 735                 }
 736
 737                 or = i;
 738         }
 739
 740         for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 741                 if (nv_device(drm->device)->chipset  < 0x90 ||
 742                     nv_device(drm->device)->chipset == 0x92 ||
 743                     nv_device(drm->device)->chipset == 0xa0)
 744                         mc = nv_rd32(device, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 745                 else
 746                         mc = nv_rd32(device, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 747
 748                 NV_DEBUG(drm, "SOR-%d mc: 0x%08x\n", i, mc);
 749                 if (!(mc & (1 << crtc)))
 750                         continue;
 751
 752                 switch ((mc & 0x00000f00) >> 8) {
 753                 case 0: type = DCB_OUTPUT_LVDS; break;
 754                 case 1: type = DCB_OUTPUT_TMDS; break;
 755                 case 2: type = DCB_OUTPUT_TMDS; break;
 756                 case 5: type = DCB_OUTPUT_TMDS; break;
 757                 case 8: type = DCB_OUTPUT_DP; break;
 758                 case 9: type = DCB_OUTPUT_DP; break;
 759                 default:
 760                         NV_ERROR(drm, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 761                         goto ack;
 762                 }
 763
 764                 or = i;
 765         }
 766
 767         if (type == DCB_OUTPUT_ANY)
 768                 goto ack;
 769
 770         /* Enable the encoder */
 771         for (i = 0; i < drm->vbios.dcb.entries; i++) {
 772                 dcb = &drm->vbios.dcb.entry[i];
 773                 if (dcb->type == type && (dcb->or & (1 << or)))
 774                         break;
 775         }
 776
 777         if (i == drm->vbios.dcb.entries) {
 778                 NV_ERROR(drm, "no dcb for %d %d 0x%08x\n", or, type, mc);
 779                 goto ack;
 780         }
 781
 782         script = nv50_display_script_select(dev, dcb, mc, pclk);
 783         nouveau_bios_run_display_table(dev, script, pclk, dcb, -1);
 784
 785         if (type == DCB_OUTPUT_DP) {
 786                 int link = !(dcb->dpconf.sor.link & 1);
 787                 if ((mc & 0x000f0000) == 0x00020000)
 788                         nv50_sor_dp_calc_tu(dev, or, link, pclk, 18);
 789                 else
 790                         nv50_sor_dp_calc_tu(dev, or, link, pclk, 24);
 791         }
 792
 793         if (dcb->type != DCB_OUTPUT_ANALOG) {
 794                 tmp = nv_rd32(device, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 795                 tmp &= ~0x00000f0f;
 796                 if (script & 0x0100)
 797                         tmp |= 0x00000101;
 798                 nv_wr32(device, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 799         } else {
 800                 nv_wr32(device, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 801         }
 802
 803         disp->irq.dcb = dcb;
 804         disp->irq.pclk = pclk;
 805         disp->irq.script = script;
 806
 807 ack:
 808         nv_wr32(device, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 809         nv_wr32(device, 0x610030, 0x80000000);
 810 }
 811
 812 /* If programming a TMDS output on a SOR that can also be configured for
 813  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 814  *
 815  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 816  * the VBIOS scripts on at least one board I have only switch it off on
 817  * link 0, causing a blank display if the output has previously been
 818  * programmed for DisplayPort.
 819  */
 820 static void
 821 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_output *dcb)
 822 {
 823         struct nouveau_device *device = nouveau_dev(dev);
 824         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 825         struct drm_encoder *encoder;
 826         u32 tmp;
 827
 828         if (dcb->type != DCB_OUTPUT_TMDS)
 829                 return;
 830
 831         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 832                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 833
 834                 if (nv_encoder->dcb->type == DCB_OUTPUT_DP &&
 835                     nv_encoder->dcb->or & (1 << or)) {
 836                         tmp  = nv_rd32(device, NV50_SOR_DP_CTRL(or, link));
 837                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 838                         nv_wr32(device, NV50_SOR_DP_CTRL(or, link), tmp);
 839                         break;
 840                 }
 841         }
 842 }
 843
 844 static void
 845 nv50_display_unk40_handler(struct drm_device *dev)
 846 {
 847         struct nouveau_device *device = nouveau_dev(dev);
 848         struct nouveau_drm *drm = nouveau_drm(dev);
 849         struct nv50_display *disp = nv50_display(dev);
 850         struct dcb_output *dcb = disp->irq.dcb;
 851         u16 script = disp->irq.script;
 852         u32 unk30 = nv_rd32(device, 0x610030), pclk = disp->irq.pclk;
 853
 854         NV_DEBUG(drm, "0x610030: 0x%08x\n", unk30);
 855         disp->irq.dcb = NULL;
 856         if (!dcb)
 857                 goto ack;
 858
 859         nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1);
 860         nv50_display_unk40_dp_set_tmds(dev, dcb);
 861
 862 ack:
 863         nv_wr32(device, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 864         nv_wr32(device, 0x610030, 0x80000000);
 865         nv_wr32(device, 0x619494, nv_rd32(device, 0x619494) | 8);
 866 }
 867
 868 static void
 869 nv50_display_bh(unsigned long data)
 870 {
 871         struct drm_device *dev = (struct drm_device *)data;
 872         struct nouveau_device *device = nouveau_dev(dev);
 873         struct nouveau_drm *drm = nouveau_drm(dev);
 874
 875         for (;;) {
 876                 uint32_t intr0 = nv_rd32(device, NV50_PDISPLAY_INTR_0);
 877                 uint32_t intr1 = nv_rd32(device, NV50_PDISPLAY_INTR_1);
 878
 879                 NV_DEBUG(drm, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 880
 881                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 882                         nv50_display_unk10_handler(dev);
 883                 else
 884                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 885                         nv50_display_unk20_handler(dev);
 886                 else
 887                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 888                         nv50_display_unk40_handler(dev);
 889                 else
 890                         break;
 891         }
 892
 893         nv_wr32(device, NV03_PMC_INTR_EN_0, 1);
 894 }
 895
 896 static void
 897 nv50_display_error_handler(struct drm_device *dev)
 898 {
 899         struct nouveau_device *device = nouveau_dev(dev);
 900         struct nouveau_drm *drm = nouveau_drm(dev);
 901         u32 channels = (nv_rd32(device, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
 902         u32 addr, data;
 903         int chid;
 904
 905         for (chid = 0; chid < 5; chid++) {
 906                 if (!(channels & (1 << chid)))
 907                         continue;
 908
 909                 nv_wr32(device, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
 910                 addr = nv_rd32(device, NV50_PDISPLAY_TRAPPED_ADDR(chid));
 911                 data = nv_rd32(device, NV50_PDISPLAY_TRAPPED_DATA(chid));
 912                 NV_ERROR(drm, "EvoCh %d Mthd 0x%04x Data 0x%08x "
 913                               "(0x%04x 0x%02x)\n", chid,
 914                          addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 915
 916                 nv_wr32(device, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
 917         }
 918 }
 919
 920 void
 921 nv50_display_intr(struct drm_device *dev)
 922 {
 923         struct nouveau_device *device = nouveau_dev(dev);
 924         struct nouveau_drm *drm = nouveau_drm(dev);
 925         struct nv50_display *disp = nv50_display(dev);
 926         uint32_t delayed = 0;
 927
 928         while (nv_rd32(device, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
 929                 uint32_t intr0 = nv_rd32(device, NV50_PDISPLAY_INTR_0);
 930                 uint32_t intr1 = nv_rd32(device, NV50_PDISPLAY_INTR_1);
 931                 uint32_t clock;
 932
 933                 NV_DEBUG(drm, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
 934
 935                 if (!intr0 && !(intr1 & ~delayed))
 936                         break;
 937
 938                 if (intr0 & 0x001f0000) {
 939                         nv50_display_error_handler(dev);
 940                         intr0 &= ~0x001f0000;
 941                 }
 942
 943                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
 944                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 945                         delayed |= NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 946                 }
 947
 948                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
 949                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
 950                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
 951                 if (clock) {
 952                         nv_wr32(device, NV03_PMC_INTR_EN_0, 0);
 953                         tasklet_schedule(&disp->tasklet);
 954                         delayed |= clock;
 955                         intr1 &= ~clock;
 956                 }
 957
 958                 if (intr0) {
 959                         NV_ERROR(drm, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
 960                         nv_wr32(device, NV50_PDISPLAY_INTR_0, intr0);
 961                 }
 962
 963                 if (intr1) {
 964                         NV_ERROR(drm,
 965                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
 966                         nv_wr32(device, NV50_PDISPLAY_INTR_1, intr1);
 967                 }
 968         }
 969 }