drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33 #include <drm/i915_powerwell.h>
  34
  35 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  36  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  37  * during in-memory transfers and, therefore, reduce the power packet.
  38  *
  39  * The benefits of FBC are mostly visible with solid backgrounds and
  40  * variation-less patterns.
  41  *
  42  * FBC-related functionality can be enabled by the means of the
  43  * i915.i915_enable_fbc parameter
  44  */
  45
  46 static bool intel_crtc_active(struct drm_crtc *crtc)
  47 {
  48         /* Be paranoid as we can arrive here with only partial
  49          * state retrieved from the hardware during setup.
  50          */
  51         return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
  52 }
  53
  54 static void i8xx_disable_fbc(struct drm_device *dev)
  55 {
  56         struct drm_i915_private *dev_priv = dev->dev_private;
  57         u32 fbc_ctl;
  58
  59         /* Disable compression */
  60         fbc_ctl = I915_READ(FBC_CONTROL);
  61         if ((fbc_ctl & FBC_CTL_EN) == 0)
  62                 return;
  63
  64         fbc_ctl &= ~FBC_CTL_EN;
  65         I915_WRITE(FBC_CONTROL, fbc_ctl);
  66
  67         /* Wait for compressing bit to clear */
  68         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  69                 DRM_DEBUG_KMS("FBC idle timed out\n");
  70                 return;
  71         }
  72
  73         DRM_DEBUG_KMS("disabled FBC\n");
  74 }
  75
  76 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  77 {
  78         struct drm_device *dev = crtc->dev;
  79         struct drm_i915_private *dev_priv = dev->dev_private;
  80         struct drm_framebuffer *fb = crtc->fb;
  81         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  82         struct drm_i915_gem_object *obj = intel_fb->obj;
  83         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  84         int cfb_pitch;
  85         int plane, i;
  86         u32 fbc_ctl, fbc_ctl2;
  87
  88         cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
  89         if (fb->pitches[0] < cfb_pitch)
  90                 cfb_pitch = fb->pitches[0];
  91
  92         /* FBC_CTL wants 64B units */
  93         cfb_pitch = (cfb_pitch / 64) - 1;
  94         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  95
  96         /* Clear old tags */
  97         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  98                 I915_WRITE(FBC_TAG + (i * 4), 0);
  99
 100         /* Set it up... */
 101         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 102         fbc_ctl2 |= plane;
 103         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 104         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 105
 106         /* enable it... */
 107         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 108         if (IS_I945GM(dev))
 109                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 110         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 111         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 112         fbc_ctl |= obj->fence_reg;
 113         I915_WRITE(FBC_CONTROL, fbc_ctl);
 114
 115         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 116                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 117 }
 118
 119 static bool i8xx_fbc_enabled(struct drm_device *dev)
 120 {
 121         struct drm_i915_private *dev_priv = dev->dev_private;
 122
 123         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 124 }
 125
 126 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 127 {
 128         struct drm_device *dev = crtc->dev;
 129         struct drm_i915_private *dev_priv = dev->dev_private;
 130         struct drm_framebuffer *fb = crtc->fb;
 131         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 132         struct drm_i915_gem_object *obj = intel_fb->obj;
 133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 134         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 135         unsigned long stall_watermark = 200;
 136         u32 dpfc_ctl;
 137
 138         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 139         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 140         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 141
 142         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 143                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 144                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 145         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 146
 147         /* enable it... */
 148         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 149
 150         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 151 }
 152
 153 static void g4x_disable_fbc(struct drm_device *dev)
 154 {
 155         struct drm_i915_private *dev_priv = dev->dev_private;
 156         u32 dpfc_ctl;
 157
 158         /* Disable compression */
 159         dpfc_ctl = I915_READ(DPFC_CONTROL);
 160         if (dpfc_ctl & DPFC_CTL_EN) {
 161                 dpfc_ctl &= ~DPFC_CTL_EN;
 162                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 163
 164                 DRM_DEBUG_KMS("disabled FBC\n");
 165         }
 166 }
 167
 168 static bool g4x_fbc_enabled(struct drm_device *dev)
 169 {
 170         struct drm_i915_private *dev_priv = dev->dev_private;
 171
 172         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 173 }
 174
 175 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 176 {
 177         struct drm_i915_private *dev_priv = dev->dev_private;
 178         u32 blt_ecoskpd;
 179
 180         /* Make sure blitter notifies FBC of writes */
 181         gen6_gt_force_wake_get(dev_priv);
 182         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 183         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 184                 GEN6_BLITTER_LOCK_SHIFT;
 185         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 186         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 187         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 188         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 189                          GEN6_BLITTER_LOCK_SHIFT);
 190         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 191         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 192         gen6_gt_force_wake_put(dev_priv);
 193 }
 194
 195 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 196 {
 197         struct drm_device *dev = crtc->dev;
 198         struct drm_i915_private *dev_priv = dev->dev_private;
 199         struct drm_framebuffer *fb = crtc->fb;
 200         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 201         struct drm_i915_gem_object *obj = intel_fb->obj;
 202         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 203         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 204         unsigned long stall_watermark = 200;
 205         u32 dpfc_ctl;
 206
 207         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 208         dpfc_ctl &= DPFC_RESERVED;
 209         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 210         /* Set persistent mode for front-buffer rendering, ala X. */
 211         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 212         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 213         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 214
 215         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 216                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 217                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 218         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 219         I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
 220         /* enable it... */
 221         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 222
 223         if (IS_GEN6(dev)) {
 224                 I915_WRITE(SNB_DPFC_CTL_SA,
 225                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 226                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 227                 sandybridge_blit_fbc_update(dev);
 228         }
 229
 230         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 231 }
 232
 233 static void ironlake_disable_fbc(struct drm_device *dev)
 234 {
 235         struct drm_i915_private *dev_priv = dev->dev_private;
 236         u32 dpfc_ctl;
 237
 238         /* Disable compression */
 239         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 240         if (dpfc_ctl & DPFC_CTL_EN) {
 241                 dpfc_ctl &= ~DPFC_CTL_EN;
 242                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 243
 244                 if (IS_IVYBRIDGE(dev))
 245                         /* WaFbcDisableDpfcClockGating:ivb */
 246                         I915_WRITE(ILK_DSPCLK_GATE_D,
 247                                    I915_READ(ILK_DSPCLK_GATE_D) &
 248                                    ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 249
 250                 if (IS_HASWELL(dev))
 251                         /* WaFbcDisableDpfcClockGating:hsw */
 252                         I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 253                                    I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
 254                                    ~HSW_DPFC_GATING_DISABLE);
 255
 256                 DRM_DEBUG_KMS("disabled FBC\n");
 257         }
 258 }
 259
 260 static bool ironlake_fbc_enabled(struct drm_device *dev)
 261 {
 262         struct drm_i915_private *dev_priv = dev->dev_private;
 263
 264         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 265 }
 266
 267 static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 268 {
 269         struct drm_device *dev = crtc->dev;
 270         struct drm_i915_private *dev_priv = dev->dev_private;
 271         struct drm_framebuffer *fb = crtc->fb;
 272         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 273         struct drm_i915_gem_object *obj = intel_fb->obj;
 274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 275
 276         I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
 277
 278         I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
 279                    IVB_DPFC_CTL_FENCE_EN |
 280                    intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
 281
 282         if (IS_IVYBRIDGE(dev)) {
 283                 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
 284                 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
 285                 /* WaFbcDisableDpfcClockGating:ivb */
 286                 I915_WRITE(ILK_DSPCLK_GATE_D,
 287                            I915_READ(ILK_DSPCLK_GATE_D) |
 288                            ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
 289         } else {
 290                 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
 291                 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
 292                            HSW_BYPASS_FBC_QUEUE);
 293                 /* WaFbcDisableDpfcClockGating:hsw */
 294                 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
 295                            I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
 296                            HSW_DPFC_GATING_DISABLE);
 297         }
 298
 299         I915_WRITE(SNB_DPFC_CTL_SA,
 300                    SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 301         I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 302
 303         sandybridge_blit_fbc_update(dev);
 304
 305         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
 306 }
 307
 308 bool intel_fbc_enabled(struct drm_device *dev)
 309 {
 310         struct drm_i915_private *dev_priv = dev->dev_private;
 311
 312         if (!dev_priv->display.fbc_enabled)
 313                 return false;
 314
 315         return dev_priv->display.fbc_enabled(dev);
 316 }
 317
 318 static void intel_fbc_work_fn(struct work_struct *__work)
 319 {
 320         struct intel_fbc_work *work =
 321                 container_of(to_delayed_work(__work),
 322                              struct intel_fbc_work, work);
 323         struct drm_device *dev = work->crtc->dev;
 324         struct drm_i915_private *dev_priv = dev->dev_private;
 325
 326         mutex_lock(&dev->struct_mutex);
 327         if (work == dev_priv->fbc.fbc_work) {
 328                 /* Double check that we haven't switched fb without cancelling
 329                  * the prior work.
 330                  */
 331                 if (work->crtc->fb == work->fb) {
 332                         dev_priv->display.enable_fbc(work->crtc,
 333                                                      work->interval);
 334
 335                         dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
 336                         dev_priv->fbc.fb_id = work->crtc->fb->base.id;
 337                         dev_priv->fbc.y = work->crtc->y;
 338                 }
 339
 340                 dev_priv->fbc.fbc_work = NULL;
 341         }
 342         mutex_unlock(&dev->struct_mutex);
 343
 344         kfree(work);
 345 }
 346
 347 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 348 {
 349         if (dev_priv->fbc.fbc_work == NULL)
 350                 return;
 351
 352         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 353
 354         /* Synchronisation is provided by struct_mutex and checking of
 355          * dev_priv->fbc.fbc_work, so we can perform the cancellation
 356          * entirely asynchronously.
 357          */
 358         if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
 359                 /* tasklet was killed before being run, clean up */
 360                 kfree(dev_priv->fbc.fbc_work);
 361
 362         /* Mark the work as no longer wanted so that if it does
 363          * wake-up (because the work was already running and waiting
 364          * for our mutex), it will discover that is no longer
 365          * necessary to run.
 366          */
 367         dev_priv->fbc.fbc_work = NULL;
 368 }
 369
 370 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 371 {
 372         struct intel_fbc_work *work;
 373         struct drm_device *dev = crtc->dev;
 374         struct drm_i915_private *dev_priv = dev->dev_private;
 375
 376         if (!dev_priv->display.enable_fbc)
 377                 return;
 378
 379         intel_cancel_fbc_work(dev_priv);
 380
 381         work = kzalloc(sizeof *work, GFP_KERNEL);
 382         if (work == NULL) {
 383                 DRM_ERROR("Failed to allocate FBC work structure\n");
 384                 dev_priv->display.enable_fbc(crtc, interval);
 385                 return;
 386         }
 387
 388         work->crtc = crtc;
 389         work->fb = crtc->fb;
 390         work->interval = interval;
 391         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 392
 393         dev_priv->fbc.fbc_work = work;
 394
 395         /* Delay the actual enabling to let pageflipping cease and the
 396          * display to settle before starting the compression. Note that
 397          * this delay also serves a second purpose: it allows for a
 398          * vblank to pass after disabling the FBC before we attempt
 399          * to modify the control registers.
 400          *
 401          * A more complicated solution would involve tracking vblanks
 402          * following the termination of the page-flipping sequence
 403          * and indeed performing the enable as a co-routine and not
 404          * waiting synchronously upon the vblank.
 405          *
 406          * WaFbcWaitForVBlankBeforeEnable:ilk,snb
 407          */
 408         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 409 }
 410
 411 void intel_disable_fbc(struct drm_device *dev)
 412 {
 413         struct drm_i915_private *dev_priv = dev->dev_private;
 414
 415         intel_cancel_fbc_work(dev_priv);
 416
 417         if (!dev_priv->display.disable_fbc)
 418                 return;
 419
 420         dev_priv->display.disable_fbc(dev);
 421         dev_priv->fbc.plane = -1;
 422 }
 423
 424 static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
 425                               enum no_fbc_reason reason)
 426 {
 427         if (dev_priv->fbc.no_fbc_reason == reason)
 428                 return false;
 429
 430         dev_priv->fbc.no_fbc_reason = reason;
 431         return true;
 432 }
 433
 434 /**
 435  * intel_update_fbc - enable/disable FBC as needed
 436  * @dev: the drm_device
 437  *
 438  * Set up the framebuffer compression hardware at mode set time.  We
 439  * enable it if possible:
 440  *   - plane A only (on pre-965)
 441  *   - no pixel mulitply/line duplication
 442  *   - no alpha buffer discard
 443  *   - no dual wide
 444  *   - framebuffer <= max_hdisplay in width, max_vdisplay in height
 445  *
 446  * We can't assume that any compression will take place (worst case),
 447  * so the compressed buffer has to be the same size as the uncompressed
 448  * one.  It also must reside (along with the line length buffer) in
 449  * stolen memory.
 450  *
 451  * We need to enable/disable FBC on a global basis.
 452  */
 453 void intel_update_fbc(struct drm_device *dev)
 454 {
 455         struct drm_i915_private *dev_priv = dev->dev_private;
 456         struct drm_crtc *crtc = NULL, *tmp_crtc;
 457         struct intel_crtc *intel_crtc;
 458         struct drm_framebuffer *fb;
 459         struct intel_framebuffer *intel_fb;
 460         struct drm_i915_gem_object *obj;
 461         unsigned int max_hdisplay, max_vdisplay;
 462
 463         if (!I915_HAS_FBC(dev)) {
 464                 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
 465                 return;
 466         }
 467
 468         if (!i915_powersave) {
 469                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 470                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 471                 return;
 472         }
 473
 474         /*
 475          * If FBC is already on, we just have to verify that we can
 476          * keep it that way...
 477          * Need to disable if:
 478          *   - more than one pipe is active
 479          *   - changing FBC params (stride, fence, mode)
 480          *   - new fb is too large to fit in compressed buffer
 481          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 482          */
 483         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 484                 if (intel_crtc_active(tmp_crtc) &&
 485                     !to_intel_crtc(tmp_crtc)->primary_disabled) {
 486                         if (crtc) {
 487                                 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
 488                                         DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 489                                 goto out_disable;
 490                         }
 491                         crtc = tmp_crtc;
 492                 }
 493         }
 494
 495         if (!crtc || crtc->fb == NULL) {
 496                 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
 497                         DRM_DEBUG_KMS("no output, disabling\n");
 498                 goto out_disable;
 499         }
 500
 501         intel_crtc = to_intel_crtc(crtc);
 502         fb = crtc->fb;
 503         intel_fb = to_intel_framebuffer(fb);
 504         obj = intel_fb->obj;
 505
 506         if (i915_enable_fbc < 0 &&
 507             INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
 508                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
 509                         DRM_DEBUG_KMS("disabled per chip default\n");
 510                 goto out_disable;
 511         }
 512         if (!i915_enable_fbc) {
 513                 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
 514                         DRM_DEBUG_KMS("fbc disabled per module param\n");
 515                 goto out_disable;
 516         }
 517         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 518             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 519                 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
 520                         DRM_DEBUG_KMS("mode incompatible with compression, "
 521                                       "disabling\n");
 522                 goto out_disable;
 523         }
 524
 525         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 526                 max_hdisplay = 4096;
 527                 max_vdisplay = 2048;
 528         } else {
 529                 max_hdisplay = 2048;
 530                 max_vdisplay = 1536;
 531         }
 532         if ((crtc->mode.hdisplay > max_hdisplay) ||
 533             (crtc->mode.vdisplay > max_vdisplay)) {
 534                 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
 535                         DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 536                 goto out_disable;
 537         }
 538         if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
 539             intel_crtc->plane != 0) {
 540                 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
 541                         DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 542                 goto out_disable;
 543         }
 544
 545         /* The use of a CPU fence is mandatory in order to detect writes
 546          * by the CPU to the scanout and trigger updates to the FBC.
 547          */
 548         if (obj->tiling_mode != I915_TILING_X ||
 549             obj->fence_reg == I915_FENCE_REG_NONE) {
 550                 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
 551                         DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 552                 goto out_disable;
 553         }
 554
 555         /* If the kernel debugger is active, always disable compression */
 556         if (in_dbg_master())
 557                 goto out_disable;
 558
 559         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 560                 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
 561                         DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 562                 goto out_disable;
 563         }
 564
 565         /* If the scanout has not changed, don't modify the FBC settings.
 566          * Note that we make the fundamental assumption that the fb->obj
 567          * cannot be unpinned (and have its GTT offset and fence revoked)
 568          * without first being decoupled from the scanout and FBC disabled.
 569          */
 570         if (dev_priv->fbc.plane == intel_crtc->plane &&
 571             dev_priv->fbc.fb_id == fb->base.id &&
 572             dev_priv->fbc.y == crtc->y)
 573                 return;
 574
 575         if (intel_fbc_enabled(dev)) {
 576                 /* We update FBC along two paths, after changing fb/crtc
 577                  * configuration (modeswitching) and after page-flipping
 578                  * finishes. For the latter, we know that not only did
 579                  * we disable the FBC at the start of the page-flip
 580                  * sequence, but also more than one vblank has passed.
 581                  *
 582                  * For the former case of modeswitching, it is possible
 583                  * to switch between two FBC valid configurations
 584                  * instantaneously so we do need to disable the FBC
 585                  * before we can modify its control registers. We also
 586                  * have to wait for the next vblank for that to take
 587                  * effect. However, since we delay enabling FBC we can
 588                  * assume that a vblank has passed since disabling and
 589                  * that we can safely alter the registers in the deferred
 590                  * callback.
 591                  *
 592                  * In the scenario that we go from a valid to invalid
 593                  * and then back to valid FBC configuration we have
 594                  * no strict enforcement that a vblank occurred since
 595                  * disabling the FBC. However, along all current pipe
 596                  * disabling paths we do need to wait for a vblank at
 597                  * some point. And we wait before enabling FBC anyway.
 598                  */
 599                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 600                 intel_disable_fbc(dev);
 601         }
 602
 603         intel_enable_fbc(crtc, 500);
 604         dev_priv->fbc.no_fbc_reason = FBC_OK;
 605         return;
 606
 607 out_disable:
 608         /* Multiple disables should be harmless */
 609         if (intel_fbc_enabled(dev)) {
 610                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 611                 intel_disable_fbc(dev);
 612         }
 613         i915_gem_stolen_cleanup_compression(dev);
 614 }
 615
 616 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 617 {
 618         drm_i915_private_t *dev_priv = dev->dev_private;
 619         u32 tmp;
 620
 621         tmp = I915_READ(CLKCFG);
 622
 623         switch (tmp & CLKCFG_FSB_MASK) {
 624         case CLKCFG_FSB_533:
 625                 dev_priv->fsb_freq = 533; /* 133*4 */
 626                 break;
 627         case CLKCFG_FSB_800:
 628                 dev_priv->fsb_freq = 800; /* 200*4 */
 629                 break;
 630         case CLKCFG_FSB_667:
 631                 dev_priv->fsb_freq =  667; /* 167*4 */
 632                 break;
 633         case CLKCFG_FSB_400:
 634                 dev_priv->fsb_freq = 400; /* 100*4 */
 635                 break;
 636         }
 637
 638         switch (tmp & CLKCFG_MEM_MASK) {
 639         case CLKCFG_MEM_533:
 640                 dev_priv->mem_freq = 533;
 641                 break;
 642         case CLKCFG_MEM_667:
 643                 dev_priv->mem_freq = 667;
 644                 break;
 645         case CLKCFG_MEM_800:
 646                 dev_priv->mem_freq = 800;
 647                 break;
 648         }
 649
 650         /* detect pineview DDR3 setting */
 651         tmp = I915_READ(CSHRDDR3CTL);
 652         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 653 }
 654
 655 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 656 {
 657         drm_i915_private_t *dev_priv = dev->dev_private;
 658         u16 ddrpll, csipll;
 659
 660         ddrpll = I915_READ16(DDRMPLL1);
 661         csipll = I915_READ16(CSIPLL0);
 662
 663         switch (ddrpll & 0xff) {
 664         case 0xc:
 665                 dev_priv->mem_freq = 800;
 666                 break;
 667         case 0x10:
 668                 dev_priv->mem_freq = 1066;
 669                 break;
 670         case 0x14:
 671                 dev_priv->mem_freq = 1333;
 672                 break;
 673         case 0x18:
 674                 dev_priv->mem_freq = 1600;
 675                 break;
 676         default:
 677                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 678                                  ddrpll & 0xff);
 679                 dev_priv->mem_freq = 0;
 680                 break;
 681         }
 682
 683         dev_priv->ips.r_t = dev_priv->mem_freq;
 684
 685         switch (csipll & 0x3ff) {
 686         case 0x00c:
 687                 dev_priv->fsb_freq = 3200;
 688                 break;
 689         case 0x00e:
 690                 dev_priv->fsb_freq = 3733;
 691                 break;
 692         case 0x010:
 693                 dev_priv->fsb_freq = 4266;
 694                 break;
 695         case 0x012:
 696                 dev_priv->fsb_freq = 4800;
 697                 break;
 698         case 0x014:
 699                 dev_priv->fsb_freq = 5333;
 700                 break;
 701         case 0x016:
 702                 dev_priv->fsb_freq = 5866;
 703                 break;
 704         case 0x018:
 705                 dev_priv->fsb_freq = 6400;
 706                 break;
 707         default:
 708                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 709                                  csipll & 0x3ff);
 710                 dev_priv->fsb_freq = 0;
 711                 break;
 712         }
 713
 714         if (dev_priv->fsb_freq == 3200) {
 715                 dev_priv->ips.c_m = 0;
 716         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 717                 dev_priv->ips.c_m = 1;
 718         } else {
 719                 dev_priv->ips.c_m = 2;
 720         }
 721 }
 722
 723 static const struct cxsr_latency cxsr_latency_table[] = {
 724         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 725         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 726         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 727         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 728         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 729
 730         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 731         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 732         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 733         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 734         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 735
 736         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 737         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 738         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 739         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 740         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 741
 742         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 743         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 744         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 745         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 746         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 747
 748         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 749         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 750         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 751         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 752         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 753
 754         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 755         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 756         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 757         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 758         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 759 };
 760
 761 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 762                                                          int is_ddr3,
 763                                                          int fsb,
 764                                                          int mem)
 765 {
 766         const struct cxsr_latency *latency;
 767         int i;
 768
 769         if (fsb == 0 || mem == 0)
 770                 return NULL;
 771
 772         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 773                 latency = &cxsr_latency_table[i];
 774                 if (is_desktop == latency->is_desktop &&
 775                     is_ddr3 == latency->is_ddr3 &&
 776                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 777                         return latency;
 778         }
 779
 780         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 781
 782         return NULL;
 783 }
 784
 785 static void pineview_disable_cxsr(struct drm_device *dev)
 786 {
 787         struct drm_i915_private *dev_priv = dev->dev_private;
 788
 789         /* deactivate cxsr */
 790         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 791 }
 792
 793 /*
 794  * Latency for FIFO fetches is dependent on several factors:
 795  *   - memory configuration (speed, channels)
 796  *   - chipset
 797  *   - current MCH state
 798  * It can be fairly high in some situations, so here we assume a fairly
 799  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 800  * set this value too high, the FIFO will fetch frequently to stay full)
 801  * and power consumption (set it too low to save power and we might see
 802  * FIFO underruns and display "flicker").
 803  *
 804  * A value of 5us seems to be a good balance; safe for very low end
 805  * platforms but not overly aggressive on lower latency configs.
 806  */
 807 static const int latency_ns = 5000;
 808
 809 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 810 {
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         uint32_t dsparb = I915_READ(DSPARB);
 813         int size;
 814
 815         size = dsparb & 0x7f;
 816         if (plane)
 817                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 818
 819         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 820                       plane ? "B" : "A", size);
 821
 822         return size;
 823 }
 824
 825 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 826 {
 827         struct drm_i915_private *dev_priv = dev->dev_private;
 828         uint32_t dsparb = I915_READ(DSPARB);
 829         int size;
 830
 831         size = dsparb & 0x1ff;
 832         if (plane)
 833                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 834         size >>= 1; /* Convert to cachelines */
 835
 836         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 837                       plane ? "B" : "A", size);
 838
 839         return size;
 840 }
 841
 842 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 843 {
 844         struct drm_i915_private *dev_priv = dev->dev_private;
 845         uint32_t dsparb = I915_READ(DSPARB);
 846         int size;
 847
 848         size = dsparb & 0x7f;
 849         size >>= 2; /* Convert to cachelines */
 850
 851         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 852                       plane ? "B" : "A",
 853                       size);
 854
 855         return size;
 856 }
 857
 858 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 859 {
 860         struct drm_i915_private *dev_priv = dev->dev_private;
 861         uint32_t dsparb = I915_READ(DSPARB);
 862         int size;
 863
 864         size = dsparb & 0x7f;
 865         size >>= 1; /* Convert to cachelines */
 866
 867         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 868                       plane ? "B" : "A", size);
 869
 870         return size;
 871 }
 872
 873 /* Pineview has different values for various configs */
 874 static const struct intel_watermark_params pineview_display_wm = {
 875         PINEVIEW_DISPLAY_FIFO,
 876         PINEVIEW_MAX_WM,
 877         PINEVIEW_DFT_WM,
 878         PINEVIEW_GUARD_WM,
 879         PINEVIEW_FIFO_LINE_SIZE
 880 };
 881 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 882         PINEVIEW_DISPLAY_FIFO,
 883         PINEVIEW_MAX_WM,
 884         PINEVIEW_DFT_HPLLOFF_WM,
 885         PINEVIEW_GUARD_WM,
 886         PINEVIEW_FIFO_LINE_SIZE
 887 };
 888 static const struct intel_watermark_params pineview_cursor_wm = {
 889         PINEVIEW_CURSOR_FIFO,
 890         PINEVIEW_CURSOR_MAX_WM,
 891         PINEVIEW_CURSOR_DFT_WM,
 892         PINEVIEW_CURSOR_GUARD_WM,
 893         PINEVIEW_FIFO_LINE_SIZE,
 894 };
 895 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 896         PINEVIEW_CURSOR_FIFO,
 897         PINEVIEW_CURSOR_MAX_WM,
 898         PINEVIEW_CURSOR_DFT_WM,
 899         PINEVIEW_CURSOR_GUARD_WM,
 900         PINEVIEW_FIFO_LINE_SIZE
 901 };
 902 static const struct intel_watermark_params g4x_wm_info = {
 903         G4X_FIFO_SIZE,
 904         G4X_MAX_WM,
 905         G4X_MAX_WM,
 906         2,
 907         G4X_FIFO_LINE_SIZE,
 908 };
 909 static const struct intel_watermark_params g4x_cursor_wm_info = {
 910         I965_CURSOR_FIFO,
 911         I965_CURSOR_MAX_WM,
 912         I965_CURSOR_DFT_WM,
 913         2,
 914         G4X_FIFO_LINE_SIZE,
 915 };
 916 static const struct intel_watermark_params valleyview_wm_info = {
 917         VALLEYVIEW_FIFO_SIZE,
 918         VALLEYVIEW_MAX_WM,
 919         VALLEYVIEW_MAX_WM,
 920         2,
 921         G4X_FIFO_LINE_SIZE,
 922 };
 923 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 924         I965_CURSOR_FIFO,
 925         VALLEYVIEW_CURSOR_MAX_WM,
 926         I965_CURSOR_DFT_WM,
 927         2,
 928         G4X_FIFO_LINE_SIZE,
 929 };
 930 static const struct intel_watermark_params i965_cursor_wm_info = {
 931         I965_CURSOR_FIFO,
 932         I965_CURSOR_MAX_WM,
 933         I965_CURSOR_DFT_WM,
 934         2,
 935         I915_FIFO_LINE_SIZE,
 936 };
 937 static const struct intel_watermark_params i945_wm_info = {
 938         I945_FIFO_SIZE,
 939         I915_MAX_WM,
 940         1,
 941         2,
 942         I915_FIFO_LINE_SIZE
 943 };
 944 static const struct intel_watermark_params i915_wm_info = {
 945         I915_FIFO_SIZE,
 946         I915_MAX_WM,
 947         1,
 948         2,
 949         I915_FIFO_LINE_SIZE
 950 };
 951 static const struct intel_watermark_params i855_wm_info = {
 952         I855GM_FIFO_SIZE,
 953         I915_MAX_WM,
 954         1,
 955         2,
 956         I830_FIFO_LINE_SIZE
 957 };
 958 static const struct intel_watermark_params i830_wm_info = {
 959         I830_FIFO_SIZE,
 960         I915_MAX_WM,
 961         1,
 962         2,
 963         I830_FIFO_LINE_SIZE
 964 };
 965
 966 static const struct intel_watermark_params ironlake_display_wm_info = {
 967         ILK_DISPLAY_FIFO,
 968         ILK_DISPLAY_MAXWM,
 969         ILK_DISPLAY_DFTWM,
 970         2,
 971         ILK_FIFO_LINE_SIZE
 972 };
 973 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 974         ILK_CURSOR_FIFO,
 975         ILK_CURSOR_MAXWM,
 976         ILK_CURSOR_DFTWM,
 977         2,
 978         ILK_FIFO_LINE_SIZE
 979 };
 980 static const struct intel_watermark_params ironlake_display_srwm_info = {
 981         ILK_DISPLAY_SR_FIFO,
 982         ILK_DISPLAY_MAX_SRWM,
 983         ILK_DISPLAY_DFT_SRWM,
 984         2,
 985         ILK_FIFO_LINE_SIZE
 986 };
 987 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 988         ILK_CURSOR_SR_FIFO,
 989         ILK_CURSOR_MAX_SRWM,
 990         ILK_CURSOR_DFT_SRWM,
 991         2,
 992         ILK_FIFO_LINE_SIZE
 993 };
 994
 995 static const struct intel_watermark_params sandybridge_display_wm_info = {
 996         SNB_DISPLAY_FIFO,
 997         SNB_DISPLAY_MAXWM,
 998         SNB_DISPLAY_DFTWM,
 999         2,
1000         SNB_FIFO_LINE_SIZE
1001 };
1002 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1003         SNB_CURSOR_FIFO,
1004         SNB_CURSOR_MAXWM,
1005         SNB_CURSOR_DFTWM,
1006         2,
1007         SNB_FIFO_LINE_SIZE
1008 };
1009 static const struct intel_watermark_params sandybridge_display_srwm_info = {
1010         SNB_DISPLAY_SR_FIFO,
1011         SNB_DISPLAY_MAX_SRWM,
1012         SNB_DISPLAY_DFT_SRWM,
1013         2,
1014         SNB_FIFO_LINE_SIZE
1015 };
1016 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1017         SNB_CURSOR_SR_FIFO,
1018         SNB_CURSOR_MAX_SRWM,
1019         SNB_CURSOR_DFT_SRWM,
1020         2,
1021         SNB_FIFO_LINE_SIZE
1022 };
1023
1024
1025 /**
1026  * intel_calculate_wm - calculate watermark level
1027  * @clock_in_khz: pixel clock
1028  * @wm: chip FIFO params
1029  * @pixel_size: display pixel size
1030  * @latency_ns: memory latency for the platform
1031  *
1032  * Calculate the watermark level (the level at which the display plane will
1033  * start fetching from memory again).  Each chip has a different display
1034  * FIFO size and allocation, so the caller needs to figure that out and pass
1035  * in the correct intel_watermark_params structure.
1036  *
1037  * As the pixel clock runs, the FIFO will be drained at a rate that depends
1038  * on the pixel size.  When it reaches the watermark level, it'll start
1039  * fetching FIFO line sized based chunks from memory until the FIFO fills
1040  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
1041  * will occur, and a display engine hang could result.
1042  */
1043 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1044                                         const struct intel_watermark_params *wm,
1045                                         int fifo_size,
1046                                         int pixel_size,
1047                                         unsigned long latency_ns)
1048 {
1049         long entries_required, wm_size;
1050
1051         /*
1052          * Note: we need to make sure we don't overflow for various clock &
1053          * latency values.
1054          * clocks go from a few thousand to several hundred thousand.
1055          * latency is usually a few thousand
1056          */
1057         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1058                 1000;
1059         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1060
1061         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1062
1063         wm_size = fifo_size - (entries_required + wm->guard_size);
1064
1065         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1066
1067         /* Don't promote wm_size to unsigned... */
1068         if (wm_size > (long)wm->max_wm)
1069                 wm_size = wm->max_wm;
1070         if (wm_size <= 0)
1071                 wm_size = wm->default_wm;
1072         return wm_size;
1073 }
1074
1075 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1076 {
1077         struct drm_crtc *crtc, *enabled = NULL;
1078
1079         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1080                 if (intel_crtc_active(crtc)) {
1081                         if (enabled)
1082                                 return NULL;
1083                         enabled = crtc;
1084                 }
1085         }
1086
1087         return enabled;
1088 }
1089
1090 static void pineview_update_wm(struct drm_device *dev)
1091 {
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093         struct drm_crtc *crtc;
1094         const struct cxsr_latency *latency;
1095         u32 reg;
1096         unsigned long wm;
1097
1098         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1099                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1100         if (!latency) {
1101                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1102                 pineview_disable_cxsr(dev);
1103                 return;
1104         }
1105
1106         crtc = single_enabled_crtc(dev);
1107         if (crtc) {
1108                 int clock = crtc->mode.clock;
1109                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1110
1111                 /* Display SR */
1112                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1113                                         pineview_display_wm.fifo_size,
1114                                         pixel_size, latency->display_sr);
1115                 reg = I915_READ(DSPFW1);
1116                 reg &= ~DSPFW_SR_MASK;
1117                 reg |= wm << DSPFW_SR_SHIFT;
1118                 I915_WRITE(DSPFW1, reg);
1119                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1120
1121                 /* cursor SR */
1122                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1123                                         pineview_display_wm.fifo_size,
1124                                         pixel_size, latency->cursor_sr);
1125                 reg = I915_READ(DSPFW3);
1126                 reg &= ~DSPFW_CURSOR_SR_MASK;
1127                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1128                 I915_WRITE(DSPFW3, reg);
1129
1130                 /* Display HPLL off SR */
1131                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1132                                         pineview_display_hplloff_wm.fifo_size,
1133                                         pixel_size, latency->display_hpll_disable);
1134                 reg = I915_READ(DSPFW3);
1135                 reg &= ~DSPFW_HPLL_SR_MASK;
1136                 reg |= wm & DSPFW_HPLL_SR_MASK;
1137                 I915_WRITE(DSPFW3, reg);
1138
1139                 /* cursor HPLL off SR */
1140                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1141                                         pineview_display_hplloff_wm.fifo_size,
1142                                         pixel_size, latency->cursor_hpll_disable);
1143                 reg = I915_READ(DSPFW3);
1144                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1145                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1146                 I915_WRITE(DSPFW3, reg);
1147                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1148
1149                 /* activate cxsr */
1150                 I915_WRITE(DSPFW3,
1151                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1152                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1153         } else {
1154                 pineview_disable_cxsr(dev);
1155                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1156         }
1157 }
1158
1159 static bool g4x_compute_wm0(struct drm_device *dev,
1160                             int plane,
1161                             const struct intel_watermark_params *display,
1162                             int display_latency_ns,
1163                             const struct intel_watermark_params *cursor,
1164                             int cursor_latency_ns,
1165                             int *plane_wm,
1166                             int *cursor_wm)
1167 {
1168         struct drm_crtc *crtc;
1169         int htotal, hdisplay, clock, pixel_size;
1170         int line_time_us, line_count;
1171         int entries, tlb_miss;
1172
1173         crtc = intel_get_crtc_for_plane(dev, plane);
1174         if (!intel_crtc_active(crtc)) {
1175                 *cursor_wm = cursor->guard_size;
1176                 *plane_wm = display->guard_size;
1177                 return false;
1178         }
1179
1180         htotal = crtc->mode.htotal;
1181         hdisplay = crtc->mode.hdisplay;
1182         clock = crtc->mode.clock;
1183         pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185         /* Use the small buffer method to calculate plane watermark */
1186         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1187         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1188         if (tlb_miss > 0)
1189                 entries += tlb_miss;
1190         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1191         *plane_wm = entries + display->guard_size;
1192         if (*plane_wm > (int)display->max_wm)
1193                 *plane_wm = display->max_wm;
1194
1195         /* Use the large buffer method to calculate cursor watermark */
1196         line_time_us = ((htotal * 1000) / clock);
1197         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1198         entries = line_count * 64 * pixel_size;
1199         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1200         if (tlb_miss > 0)
1201                 entries += tlb_miss;
1202         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1203         *cursor_wm = entries + cursor->guard_size;
1204         if (*cursor_wm > (int)cursor->max_wm)
1205                 *cursor_wm = (int)cursor->max_wm;
1206
1207         return true;
1208 }
1209
1210 /*
1211  * Check the wm result.
1212  *
1213  * If any calculated watermark values is larger than the maximum value that
1214  * can be programmed into the associated watermark register, that watermark
1215  * must be disabled.
1216  */
1217 static bool g4x_check_srwm(struct drm_device *dev,
1218                            int display_wm, int cursor_wm,
1219                            const struct intel_watermark_params *display,
1220                            const struct intel_watermark_params *cursor)
1221 {
1222         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1223                       display_wm, cursor_wm);
1224
1225         if (display_wm > display->max_wm) {
1226                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1227                               display_wm, display->max_wm);
1228                 return false;
1229         }
1230
1231         if (cursor_wm > cursor->max_wm) {
1232                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1233                               cursor_wm, cursor->max_wm);
1234                 return false;
1235         }
1236
1237         if (!(display_wm || cursor_wm)) {
1238                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1239                 return false;
1240         }
1241
1242         return true;
1243 }
1244
1245 static bool g4x_compute_srwm(struct drm_device *dev,
1246                              int plane,
1247                              int latency_ns,
1248                              const struct intel_watermark_params *display,
1249                              const struct intel_watermark_params *cursor,
1250                              int *display_wm, int *cursor_wm)
1251 {
1252         struct drm_crtc *crtc;
1253         int hdisplay, htotal, pixel_size, clock;
1254         unsigned long line_time_us;
1255         int line_count, line_size;
1256         int small, large;
1257         int entries;
1258
1259         if (!latency_ns) {
1260                 *display_wm = *cursor_wm = 0;
1261                 return false;
1262         }
1263
1264         crtc = intel_get_crtc_for_plane(dev, plane);
1265         hdisplay = crtc->mode.hdisplay;
1266         htotal = crtc->mode.htotal;
1267         clock = crtc->mode.clock;
1268         pixel_size = crtc->fb->bits_per_pixel / 8;
1269
1270         line_time_us = (htotal * 1000) / clock;
1271         line_count = (latency_ns / line_time_us + 1000) / 1000;
1272         line_size = hdisplay * pixel_size;
1273
1274         /* Use the minimum of the small and large buffer method for primary */
1275         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1276         large = line_count * line_size;
1277
1278         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1279         *display_wm = entries + display->guard_size;
1280
1281         /* calculate the self-refresh watermark for display cursor */
1282         entries = line_count * pixel_size * 64;
1283         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1284         *cursor_wm = entries + cursor->guard_size;
1285
1286         return g4x_check_srwm(dev,
1287                               *display_wm, *cursor_wm,
1288                               display, cursor);
1289 }
1290
1291 static bool vlv_compute_drain_latency(struct drm_device *dev,
1292                                      int plane,
1293                                      int *plane_prec_mult,
1294                                      int *plane_dl,
1295                                      int *cursor_prec_mult,
1296                                      int *cursor_dl)
1297 {
1298         struct drm_crtc *crtc;
1299         int clock, pixel_size;
1300         int entries;
1301
1302         crtc = intel_get_crtc_for_plane(dev, plane);
1303         if (!intel_crtc_active(crtc))
1304                 return false;
1305
1306         clock = crtc->mode.clock;       /* VESA DOT Clock */
1307         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1308
1309         entries = (clock / 1000) * pixel_size;
1310         *plane_prec_mult = (entries > 256) ?
1311                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1312         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1313                                                      pixel_size);
1314
1315         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1316         *cursor_prec_mult = (entries > 256) ?
1317                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1318         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1319
1320         return true;
1321 }
1322
1323 /*
1324  * Update drain latency registers of memory arbiter
1325  *
1326  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1327  * to be programmed. Each plane has a drain latency multiplier and a drain
1328  * latency value.
1329  */
1330
1331 static void vlv_update_drain_latency(struct drm_device *dev)
1332 {
1333         struct drm_i915_private *dev_priv = dev->dev_private;
1334         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1335         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1336         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1337                                                         either 16 or 32 */
1338
1339         /* For plane A, Cursor A */
1340         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1341                                       &cursor_prec_mult, &cursora_dl)) {
1342                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1343                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1344                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1345                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1346
1347                 I915_WRITE(VLV_DDL1, cursora_prec |
1348                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1349                                 planea_prec | planea_dl);
1350         }
1351
1352         /* For plane B, Cursor B */
1353         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1354                                       &cursor_prec_mult, &cursorb_dl)) {
1355                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1357                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1358                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1359
1360                 I915_WRITE(VLV_DDL2, cursorb_prec |
1361                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1362                                 planeb_prec | planeb_dl);
1363         }
1364 }
1365
1366 #define single_plane_enabled(mask) is_power_of_2(mask)
1367
1368 static void valleyview_update_wm(struct drm_device *dev)
1369 {
1370         static const int sr_latency_ns = 12000;
1371         struct drm_i915_private *dev_priv = dev->dev_private;
1372         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1373         int plane_sr, cursor_sr;
1374         int ignore_plane_sr, ignore_cursor_sr;
1375         unsigned int enabled = 0;
1376
1377         vlv_update_drain_latency(dev);
1378
1379         if (g4x_compute_wm0(dev, PIPE_A,
1380                             &valleyview_wm_info, latency_ns,
1381                             &valleyview_cursor_wm_info, latency_ns,
1382                             &planea_wm, &cursora_wm))
1383                 enabled |= 1 << PIPE_A;
1384
1385         if (g4x_compute_wm0(dev, PIPE_B,
1386                             &valleyview_wm_info, latency_ns,
1387                             &valleyview_cursor_wm_info, latency_ns,
1388                             &planeb_wm, &cursorb_wm))
1389                 enabled |= 1 << PIPE_B;
1390
1391         if (single_plane_enabled(enabled) &&
1392             g4x_compute_srwm(dev, ffs(enabled) - 1,
1393                              sr_latency_ns,
1394                              &valleyview_wm_info,
1395                              &valleyview_cursor_wm_info,
1396                              &plane_sr, &ignore_cursor_sr) &&
1397             g4x_compute_srwm(dev, ffs(enabled) - 1,
1398                              2*sr_latency_ns,
1399                              &valleyview_wm_info,
1400                              &valleyview_cursor_wm_info,
1401                              &ignore_plane_sr, &cursor_sr)) {
1402                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1403         } else {
1404                 I915_WRITE(FW_BLC_SELF_VLV,
1405                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1406                 plane_sr = cursor_sr = 0;
1407         }
1408
1409         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1410                       planea_wm, cursora_wm,
1411                       planeb_wm, cursorb_wm,
1412                       plane_sr, cursor_sr);
1413
1414         I915_WRITE(DSPFW1,
1415                    (plane_sr << DSPFW_SR_SHIFT) |
1416                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1417                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1418                    planea_wm);
1419         I915_WRITE(DSPFW2,
1420                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1421                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1422         I915_WRITE(DSPFW3,
1423                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1424                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1425 }
1426
1427 static void g4x_update_wm(struct drm_device *dev)
1428 {
1429         static const int sr_latency_ns = 12000;
1430         struct drm_i915_private *dev_priv = dev->dev_private;
1431         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1432         int plane_sr, cursor_sr;
1433         unsigned int enabled = 0;
1434
1435         if (g4x_compute_wm0(dev, PIPE_A,
1436                             &g4x_wm_info, latency_ns,
1437                             &g4x_cursor_wm_info, latency_ns,
1438                             &planea_wm, &cursora_wm))
1439                 enabled |= 1 << PIPE_A;
1440
1441         if (g4x_compute_wm0(dev, PIPE_B,
1442                             &g4x_wm_info, latency_ns,
1443                             &g4x_cursor_wm_info, latency_ns,
1444                             &planeb_wm, &cursorb_wm))
1445                 enabled |= 1 << PIPE_B;
1446
1447         if (single_plane_enabled(enabled) &&
1448             g4x_compute_srwm(dev, ffs(enabled) - 1,
1449                              sr_latency_ns,
1450                              &g4x_wm_info,
1451                              &g4x_cursor_wm_info,
1452                              &plane_sr, &cursor_sr)) {
1453                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1454         } else {
1455                 I915_WRITE(FW_BLC_SELF,
1456                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1457                 plane_sr = cursor_sr = 0;
1458         }
1459
1460         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1461                       planea_wm, cursora_wm,
1462                       planeb_wm, cursorb_wm,
1463                       plane_sr, cursor_sr);
1464
1465         I915_WRITE(DSPFW1,
1466                    (plane_sr << DSPFW_SR_SHIFT) |
1467                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1468                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1469                    planea_wm);
1470         I915_WRITE(DSPFW2,
1471                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1472                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1473         /* HPLL off in SR has some issues on G4x... disable it */
1474         I915_WRITE(DSPFW3,
1475                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1476                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1477 }
1478
1479 static void i965_update_wm(struct drm_device *dev)
1480 {
1481         struct drm_i915_private *dev_priv = dev->dev_private;
1482         struct drm_crtc *crtc;
1483         int srwm = 1;
1484         int cursor_sr = 16;
1485
1486         /* Calc sr entries for one plane configs */
1487         crtc = single_enabled_crtc(dev);
1488         if (crtc) {
1489                 /* self-refresh has much higher latency */
1490                 static const int sr_latency_ns = 12000;
1491                 int clock = crtc->mode.clock;
1492                 int htotal = crtc->mode.htotal;
1493                 int hdisplay = crtc->mode.hdisplay;
1494                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1495                 unsigned long line_time_us;
1496                 int entries;
1497
1498                 line_time_us = ((htotal * 1000) / clock);
1499
1500                 /* Use ns/us then divide to preserve precision */
1501                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1502                         pixel_size * hdisplay;
1503                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1504                 srwm = I965_FIFO_SIZE - entries;
1505                 if (srwm < 0)
1506                         srwm = 1;
1507                 srwm &= 0x1ff;
1508                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1509                               entries, srwm);
1510
1511                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1512                         pixel_size * 64;
1513                 entries = DIV_ROUND_UP(entries,
1514                                           i965_cursor_wm_info.cacheline_size);
1515                 cursor_sr = i965_cursor_wm_info.fifo_size -
1516                         (entries + i965_cursor_wm_info.guard_size);
1517
1518                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1519                         cursor_sr = i965_cursor_wm_info.max_wm;
1520
1521                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1522                               "cursor %d\n", srwm, cursor_sr);
1523
1524                 if (IS_CRESTLINE(dev))
1525                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1526         } else {
1527                 /* Turn off self refresh if both pipes are enabled */
1528                 if (IS_CRESTLINE(dev))
1529                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1530                                    & ~FW_BLC_SELF_EN);
1531         }
1532
1533         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1534                       srwm);
1535
1536         /* 965 has limitations... */
1537         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1538                    (8 << 16) | (8 << 8) | (8 << 0));
1539         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1540         /* update cursor SR watermark */
1541         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1542 }
1543
1544 static void i9xx_update_wm(struct drm_device *dev)
1545 {
1546         struct drm_i915_private *dev_priv = dev->dev_private;
1547         const struct intel_watermark_params *wm_info;
1548         uint32_t fwater_lo;
1549         uint32_t fwater_hi;
1550         int cwm, srwm = 1;
1551         int fifo_size;
1552         int planea_wm, planeb_wm;
1553         struct drm_crtc *crtc, *enabled = NULL;
1554
1555         if (IS_I945GM(dev))
1556                 wm_info = &i945_wm_info;
1557         else if (!IS_GEN2(dev))
1558                 wm_info = &i915_wm_info;
1559         else
1560                 wm_info = &i855_wm_info;
1561
1562         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1563         crtc = intel_get_crtc_for_plane(dev, 0);
1564         if (intel_crtc_active(crtc)) {
1565                 int cpp = crtc->fb->bits_per_pixel / 8;
1566                 if (IS_GEN2(dev))
1567                         cpp = 4;
1568
1569                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1570                                                wm_info, fifo_size, cpp,
1571                                                latency_ns);
1572                 enabled = crtc;
1573         } else
1574                 planea_wm = fifo_size - wm_info->guard_size;
1575
1576         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1577         crtc = intel_get_crtc_for_plane(dev, 1);
1578         if (intel_crtc_active(crtc)) {
1579                 int cpp = crtc->fb->bits_per_pixel / 8;
1580                 if (IS_GEN2(dev))
1581                         cpp = 4;
1582
1583                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1584                                                wm_info, fifo_size, cpp,
1585                                                latency_ns);
1586                 if (enabled == NULL)
1587                         enabled = crtc;
1588                 else
1589                         enabled = NULL;
1590         } else
1591                 planeb_wm = fifo_size - wm_info->guard_size;
1592
1593         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1594
1595         /*
1596          * Overlay gets an aggressive default since video jitter is bad.
1597          */
1598         cwm = 2;
1599
1600         /* Play safe and disable self-refresh before adjusting watermarks. */
1601         if (IS_I945G(dev) || IS_I945GM(dev))
1602                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1603         else if (IS_I915GM(dev))
1604                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1605
1606         /* Calc sr entries for one plane configs */
1607         if (HAS_FW_BLC(dev) && enabled) {
1608                 /* self-refresh has much higher latency */
1609                 static const int sr_latency_ns = 6000;
1610                 int clock = enabled->mode.clock;
1611                 int htotal = enabled->mode.htotal;
1612                 int hdisplay = enabled->mode.hdisplay;
1613                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1614                 unsigned long line_time_us;
1615                 int entries;
1616
1617                 line_time_us = (htotal * 1000) / clock;
1618
1619                 /* Use ns/us then divide to preserve precision */
1620                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1621                         pixel_size * hdisplay;
1622                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624                 srwm = wm_info->fifo_size - entries;
1625                 if (srwm < 0)
1626                         srwm = 1;
1627
1628                 if (IS_I945G(dev) || IS_I945GM(dev))
1629                         I915_WRITE(FW_BLC_SELF,
1630                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1631                 else if (IS_I915GM(dev))
1632                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633         }
1634
1635         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636                       planea_wm, planeb_wm, cwm, srwm);
1637
1638         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639         fwater_hi = (cwm & 0x1f);
1640
1641         /* Set request length to 8 cachelines per fetch */
1642         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643         fwater_hi = fwater_hi | (1 << 8);
1644
1645         I915_WRITE(FW_BLC, fwater_lo);
1646         I915_WRITE(FW_BLC2, fwater_hi);
1647
1648         if (HAS_FW_BLC(dev)) {
1649                 if (enabled) {
1650                         if (IS_I945G(dev) || IS_I945GM(dev))
1651                                 I915_WRITE(FW_BLC_SELF,
1652                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1653                         else if (IS_I915GM(dev))
1654                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1655                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1656                 } else
1657                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1658         }
1659 }
1660
1661 static void i830_update_wm(struct drm_device *dev)
1662 {
1663         struct drm_i915_private *dev_priv = dev->dev_private;
1664         struct drm_crtc *crtc;
1665         uint32_t fwater_lo;
1666         int planea_wm;
1667
1668         crtc = single_enabled_crtc(dev);
1669         if (crtc == NULL)
1670                 return;
1671
1672         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1673                                        dev_priv->display.get_fifo_size(dev, 0),
1674                                        4, latency_ns);
1675         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1676         fwater_lo |= (3<<8) | planea_wm;
1677
1678         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1679
1680         I915_WRITE(FW_BLC, fwater_lo);
1681 }
1682
1683 /*
1684  * Check the wm result.
1685  *
1686  * If any calculated watermark values is larger than the maximum value that
1687  * can be programmed into the associated watermark register, that watermark
1688  * must be disabled.
1689  */
1690 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1691                                 int fbc_wm, int display_wm, int cursor_wm,
1692                                 const struct intel_watermark_params *display,
1693                                 const struct intel_watermark_params *cursor)
1694 {
1695         struct drm_i915_private *dev_priv = dev->dev_private;
1696
1697         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1698                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1699
1700         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1701                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1702                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1703
1704                 /* fbc has it's own way to disable FBC WM */
1705                 I915_WRITE(DISP_ARB_CTL,
1706                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1707                 return false;
1708         } else if (INTEL_INFO(dev)->gen >= 6) {
1709                 /* enable FBC WM (except on ILK, where it must remain off) */
1710                 I915_WRITE(DISP_ARB_CTL,
1711                            I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
1712         }
1713
1714         if (display_wm > display->max_wm) {
1715                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1716                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1717                 return false;
1718         }
1719
1720         if (cursor_wm > cursor->max_wm) {
1721                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1722                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1723                 return false;
1724         }
1725
1726         if (!(fbc_wm || display_wm || cursor_wm)) {
1727                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1728                 return false;
1729         }
1730
1731         return true;
1732 }
1733
1734 /*
1735  * Compute watermark values of WM[1-3],
1736  */
1737 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1738                                   int latency_ns,
1739                                   const struct intel_watermark_params *display,
1740                                   const struct intel_watermark_params *cursor,
1741                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1742 {
1743         struct drm_crtc *crtc;
1744         unsigned long line_time_us;
1745         int hdisplay, htotal, pixel_size, clock;
1746         int line_count, line_size;
1747         int small, large;
1748         int entries;
1749
1750         if (!latency_ns) {
1751                 *fbc_wm = *display_wm = *cursor_wm = 0;
1752                 return false;
1753         }
1754
1755         crtc = intel_get_crtc_for_plane(dev, plane);
1756         hdisplay = crtc->mode.hdisplay;
1757         htotal = crtc->mode.htotal;
1758         clock = crtc->mode.clock;
1759         pixel_size = crtc->fb->bits_per_pixel / 8;
1760
1761         line_time_us = (htotal * 1000) / clock;
1762         line_count = (latency_ns / line_time_us + 1000) / 1000;
1763         line_size = hdisplay * pixel_size;
1764
1765         /* Use the minimum of the small and large buffer method for primary */
1766         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1767         large = line_count * line_size;
1768
1769         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1770         *display_wm = entries + display->guard_size;
1771
1772         /*
1773          * Spec says:
1774          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1775          */
1776         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1777
1778         /* calculate the self-refresh watermark for display cursor */
1779         entries = line_count * pixel_size * 64;
1780         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1781         *cursor_wm = entries + cursor->guard_size;
1782
1783         return ironlake_check_srwm(dev, level,
1784                                    *fbc_wm, *display_wm, *cursor_wm,
1785                                    display, cursor);
1786 }
1787
1788 static void ironlake_update_wm(struct drm_device *dev)
1789 {
1790         struct drm_i915_private *dev_priv = dev->dev_private;
1791         int fbc_wm, plane_wm, cursor_wm;
1792         unsigned int enabled;
1793
1794         enabled = 0;
1795         if (g4x_compute_wm0(dev, PIPE_A,
1796                             &ironlake_display_wm_info,
1797                             dev_priv->wm.pri_latency[0] * 100,
1798                             &ironlake_cursor_wm_info,
1799                             dev_priv->wm.cur_latency[0] * 100,
1800                             &plane_wm, &cursor_wm)) {
1801                 I915_WRITE(WM0_PIPEA_ILK,
1802                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1803                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1804                               " plane %d, " "cursor: %d\n",
1805                               plane_wm, cursor_wm);
1806                 enabled |= 1 << PIPE_A;
1807         }
1808
1809         if (g4x_compute_wm0(dev, PIPE_B,
1810                             &ironlake_display_wm_info,
1811                             dev_priv->wm.pri_latency[0] * 100,
1812                             &ironlake_cursor_wm_info,
1813                             dev_priv->wm.cur_latency[0] * 100,
1814                             &plane_wm, &cursor_wm)) {
1815                 I915_WRITE(WM0_PIPEB_ILK,
1816                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1817                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1818                               " plane %d, cursor: %d\n",
1819                               plane_wm, cursor_wm);
1820                 enabled |= 1 << PIPE_B;
1821         }
1822
1823         /*
1824          * Calculate and update the self-refresh watermark only when one
1825          * display plane is used.
1826          */
1827         I915_WRITE(WM3_LP_ILK, 0);
1828         I915_WRITE(WM2_LP_ILK, 0);
1829         I915_WRITE(WM1_LP_ILK, 0);
1830
1831         if (!single_plane_enabled(enabled))
1832                 return;
1833         enabled = ffs(enabled) - 1;
1834
1835         /* WM1 */
1836         if (!ironlake_compute_srwm(dev, 1, enabled,
1837                                    dev_priv->wm.pri_latency[1] * 500,
1838                                    &ironlake_display_srwm_info,
1839                                    &ironlake_cursor_srwm_info,
1840                                    &fbc_wm, &plane_wm, &cursor_wm))
1841                 return;
1842
1843         I915_WRITE(WM1_LP_ILK,
1844                    WM1_LP_SR_EN |
1845                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1846                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1847                    (plane_wm << WM1_LP_SR_SHIFT) |
1848                    cursor_wm);
1849
1850         /* WM2 */
1851         if (!ironlake_compute_srwm(dev, 2, enabled,
1852                                    dev_priv->wm.pri_latency[2] * 500,
1853                                    &ironlake_display_srwm_info,
1854                                    &ironlake_cursor_srwm_info,
1855                                    &fbc_wm, &plane_wm, &cursor_wm))
1856                 return;
1857
1858         I915_WRITE(WM2_LP_ILK,
1859                    WM2_LP_EN |
1860                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1861                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1862                    (plane_wm << WM1_LP_SR_SHIFT) |
1863                    cursor_wm);
1864
1865         /*
1866          * WM3 is unsupported on ILK, probably because we don't have latency
1867          * data for that power state
1868          */
1869 }
1870
1871 static void sandybridge_update_wm(struct drm_device *dev)
1872 {
1873         struct drm_i915_private *dev_priv = dev->dev_private;
1874         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
1875         u32 val;
1876         int fbc_wm, plane_wm, cursor_wm;
1877         unsigned int enabled;
1878
1879         enabled = 0;
1880         if (g4x_compute_wm0(dev, PIPE_A,
1881                             &sandybridge_display_wm_info, latency,
1882                             &sandybridge_cursor_wm_info, latency,
1883                             &plane_wm, &cursor_wm)) {
1884                 val = I915_READ(WM0_PIPEA_ILK);
1885                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1886                 I915_WRITE(WM0_PIPEA_ILK, val |
1887                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1888                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1889                               " plane %d, " "cursor: %d\n",
1890                               plane_wm, cursor_wm);
1891                 enabled |= 1 << PIPE_A;
1892         }
1893
1894         if (g4x_compute_wm0(dev, PIPE_B,
1895                             &sandybridge_display_wm_info, latency,
1896                             &sandybridge_cursor_wm_info, latency,
1897                             &plane_wm, &cursor_wm)) {
1898                 val = I915_READ(WM0_PIPEB_ILK);
1899                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1900                 I915_WRITE(WM0_PIPEB_ILK, val |
1901                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1902                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1903                               " plane %d, cursor: %d\n",
1904                               plane_wm, cursor_wm);
1905                 enabled |= 1 << PIPE_B;
1906         }
1907
1908         /*
1909          * Calculate and update the self-refresh watermark only when one
1910          * display plane is used.
1911          *
1912          * SNB support 3 levels of watermark.
1913          *
1914          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1915          * and disabled in the descending order
1916          *
1917          */
1918         I915_WRITE(WM3_LP_ILK, 0);
1919         I915_WRITE(WM2_LP_ILK, 0);
1920         I915_WRITE(WM1_LP_ILK, 0);
1921
1922         if (!single_plane_enabled(enabled) ||
1923             dev_priv->sprite_scaling_enabled)
1924                 return;
1925         enabled = ffs(enabled) - 1;
1926
1927         /* WM1 */
1928         if (!ironlake_compute_srwm(dev, 1, enabled,
1929                                    dev_priv->wm.pri_latency[1] * 500,
1930                                    &sandybridge_display_srwm_info,
1931                                    &sandybridge_cursor_srwm_info,
1932                                    &fbc_wm, &plane_wm, &cursor_wm))
1933                 return;
1934
1935         I915_WRITE(WM1_LP_ILK,
1936                    WM1_LP_SR_EN |
1937                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
1938                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1939                    (plane_wm << WM1_LP_SR_SHIFT) |
1940                    cursor_wm);
1941
1942         /* WM2 */
1943         if (!ironlake_compute_srwm(dev, 2, enabled,
1944                                    dev_priv->wm.pri_latency[2] * 500,
1945                                    &sandybridge_display_srwm_info,
1946                                    &sandybridge_cursor_srwm_info,
1947                                    &fbc_wm, &plane_wm, &cursor_wm))
1948                 return;
1949
1950         I915_WRITE(WM2_LP_ILK,
1951                    WM2_LP_EN |
1952                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
1953                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1954                    (plane_wm << WM1_LP_SR_SHIFT) |
1955                    cursor_wm);
1956
1957         /* WM3 */
1958         if (!ironlake_compute_srwm(dev, 3, enabled,
1959                                    dev_priv->wm.pri_latency[3] * 500,
1960                                    &sandybridge_display_srwm_info,
1961                                    &sandybridge_cursor_srwm_info,
1962                                    &fbc_wm, &plane_wm, &cursor_wm))
1963                 return;
1964
1965         I915_WRITE(WM3_LP_ILK,
1966                    WM3_LP_EN |
1967                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
1968                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1969                    (plane_wm << WM1_LP_SR_SHIFT) |
1970                    cursor_wm);
1971 }
1972
1973 static void ivybridge_update_wm(struct drm_device *dev)
1974 {
1975         struct drm_i915_private *dev_priv = dev->dev_private;
1976         int latency = dev_priv->wm.pri_latency[0] * 100;        /* In unit 0.1us */
1977         u32 val;
1978         int fbc_wm, plane_wm, cursor_wm;
1979         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1980         unsigned int enabled;
1981
1982         enabled = 0;
1983         if (g4x_compute_wm0(dev, PIPE_A,
1984                             &sandybridge_display_wm_info, latency,
1985                             &sandybridge_cursor_wm_info, latency,
1986                             &plane_wm, &cursor_wm)) {
1987                 val = I915_READ(WM0_PIPEA_ILK);
1988                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1989                 I915_WRITE(WM0_PIPEA_ILK, val |
1990                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1991                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1992                               " plane %d, " "cursor: %d\n",
1993                               plane_wm, cursor_wm);
1994                 enabled |= 1 << PIPE_A;
1995         }
1996
1997         if (g4x_compute_wm0(dev, PIPE_B,
1998                             &sandybridge_display_wm_info, latency,
1999                             &sandybridge_cursor_wm_info, latency,
2000                             &plane_wm, &cursor_wm)) {
2001                 val = I915_READ(WM0_PIPEB_ILK);
2002                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2003                 I915_WRITE(WM0_PIPEB_ILK, val |
2004                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2005                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2006                               " plane %d, cursor: %d\n",
2007                               plane_wm, cursor_wm);
2008                 enabled |= 1 << PIPE_B;
2009         }
2010
2011         if (g4x_compute_wm0(dev, PIPE_C,
2012                             &sandybridge_display_wm_info, latency,
2013                             &sandybridge_cursor_wm_info, latency,
2014                             &plane_wm, &cursor_wm)) {
2015                 val = I915_READ(WM0_PIPEC_IVB);
2016                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2017                 I915_WRITE(WM0_PIPEC_IVB, val |
2018                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2019                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2020                               " plane %d, cursor: %d\n",
2021                               plane_wm, cursor_wm);
2022                 enabled |= 1 << PIPE_C;
2023         }
2024
2025         /*
2026          * Calculate and update the self-refresh watermark only when one
2027          * display plane is used.
2028          *
2029          * SNB support 3 levels of watermark.
2030          *
2031          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2032          * and disabled in the descending order
2033          *
2034          */
2035         I915_WRITE(WM3_LP_ILK, 0);
2036         I915_WRITE(WM2_LP_ILK, 0);
2037         I915_WRITE(WM1_LP_ILK, 0);
2038
2039         if (!single_plane_enabled(enabled) ||
2040             dev_priv->sprite_scaling_enabled)
2041                 return;
2042         enabled = ffs(enabled) - 1;
2043
2044         /* WM1 */
2045         if (!ironlake_compute_srwm(dev, 1, enabled,
2046                                    dev_priv->wm.pri_latency[1] * 500,
2047                                    &sandybridge_display_srwm_info,
2048                                    &sandybridge_cursor_srwm_info,
2049                                    &fbc_wm, &plane_wm, &cursor_wm))
2050                 return;
2051
2052         I915_WRITE(WM1_LP_ILK,
2053                    WM1_LP_SR_EN |
2054                    (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
2055                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2056                    (plane_wm << WM1_LP_SR_SHIFT) |
2057                    cursor_wm);
2058
2059         /* WM2 */
2060         if (!ironlake_compute_srwm(dev, 2, enabled,
2061                                    dev_priv->wm.pri_latency[2] * 500,
2062                                    &sandybridge_display_srwm_info,
2063                                    &sandybridge_cursor_srwm_info,
2064                                    &fbc_wm, &plane_wm, &cursor_wm))
2065                 return;
2066
2067         I915_WRITE(WM2_LP_ILK,
2068                    WM2_LP_EN |
2069                    (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
2070                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2071                    (plane_wm << WM1_LP_SR_SHIFT) |
2072                    cursor_wm);
2073
2074         /* WM3, note we have to correct the cursor latency */
2075         if (!ironlake_compute_srwm(dev, 3, enabled,
2076                                    dev_priv->wm.pri_latency[3] * 500,
2077                                    &sandybridge_display_srwm_info,
2078                                    &sandybridge_cursor_srwm_info,
2079                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2080             !ironlake_compute_srwm(dev, 3, enabled,
2081                                    dev_priv->wm.cur_latency[3] * 500,
2082                                    &sandybridge_display_srwm_info,
2083                                    &sandybridge_cursor_srwm_info,
2084                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2085                 return;
2086
2087         I915_WRITE(WM3_LP_ILK,
2088                    WM3_LP_EN |
2089                    (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
2090                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2091                    (plane_wm << WM1_LP_SR_SHIFT) |
2092                    cursor_wm);
2093 }
2094
2095 static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2096                                     struct drm_crtc *crtc)
2097 {
2098         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2099         uint32_t pixel_rate, pfit_size;
2100
2101         pixel_rate = intel_crtc->config.adjusted_mode.clock;
2102
2103         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2104          * adjust the pixel_rate here. */
2105
2106         pfit_size = intel_crtc->config.pch_pfit.size;
2107         if (pfit_size) {
2108                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2109
2110                 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2111                 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2112                 pfit_w = (pfit_size >> 16) & 0xFFFF;
2113                 pfit_h = pfit_size & 0xFFFF;
2114                 if (pipe_w < pfit_w)
2115                         pipe_w = pfit_w;
2116                 if (pipe_h < pfit_h)
2117                         pipe_h = pfit_h;
2118
2119                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2120                                      pfit_w * pfit_h);
2121         }
2122
2123         return pixel_rate;
2124 }
2125
2126 /* latency must be in 0.1us units. */
2127 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2128                                uint32_t latency)
2129 {
2130         uint64_t ret;
2131
2132         if (WARN(latency == 0, "Latency value missing\n"))
2133                 return UINT_MAX;
2134
2135         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2136         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2137
2138         return ret;
2139 }
2140
2141 /* latency must be in 0.1us units. */
2142 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2143                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2144                                uint32_t latency)
2145 {
2146         uint32_t ret;
2147
2148         if (WARN(latency == 0, "Latency value missing\n"))
2149                 return UINT_MAX;
2150
2151         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2152         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2153         ret = DIV_ROUND_UP(ret, 64) + 2;
2154         return ret;
2155 }
2156
2157 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2158                            uint8_t bytes_per_pixel)
2159 {
2160         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2161 }
2162
2163 struct hsw_pipe_wm_parameters {
2164         bool active;
2165         uint32_t pipe_htotal;
2166         uint32_t pixel_rate;
2167         struct intel_plane_wm_parameters pri;
2168         struct intel_plane_wm_parameters spr;
2169         struct intel_plane_wm_parameters cur;
2170 };
2171
2172 struct hsw_wm_maximums {
2173         uint16_t pri;
2174         uint16_t spr;
2175         uint16_t cur;
2176         uint16_t fbc;
2177 };
2178
2179 struct hsw_wm_values {
2180         uint32_t wm_pipe[3];
2181         uint32_t wm_lp[3];
2182         uint32_t wm_lp_spr[3];
2183         uint32_t wm_linetime[3];
2184         bool enable_fbc_wm;
2185 };
2186
2187 /* used in computing the new watermarks state */
2188 struct intel_wm_config {
2189         unsigned int num_pipes_active;
2190         bool sprites_enabled;
2191         bool sprites_scaled;
2192         bool fbc_wm_enabled;
2193 };
2194
2195 /*
2196  * For both WM_PIPE and WM_LP.
2197  * mem_value must be in 0.1us units.
2198  */
2199 static uint32_t ilk_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
2200                                    uint32_t mem_value,
2201                                    bool is_lp)
2202 {
2203         uint32_t method1, method2;
2204
2205         if (!params->active || !params->pri.enabled)
2206                 return 0;
2207
2208         method1 = ilk_wm_method1(params->pixel_rate,
2209                                  params->pri.bytes_per_pixel,
2210                                  mem_value);
2211
2212         if (!is_lp)
2213                 return method1;
2214
2215         method2 = ilk_wm_method2(params->pixel_rate,
2216                                  params->pipe_htotal,
2217                                  params->pri.horiz_pixels,
2218                                  params->pri.bytes_per_pixel,
2219                                  mem_value);
2220
2221         return min(method1, method2);
2222 }
2223
2224 /*
2225  * For both WM_PIPE and WM_LP.
2226  * mem_value must be in 0.1us units.
2227  */
2228 static uint32_t ilk_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
2229                                    uint32_t mem_value)
2230 {
2231         uint32_t method1, method2;
2232
2233         if (!params->active || !params->spr.enabled)
2234                 return 0;
2235
2236         method1 = ilk_wm_method1(params->pixel_rate,
2237                                  params->spr.bytes_per_pixel,
2238                                  mem_value);
2239         method2 = ilk_wm_method2(params->pixel_rate,
2240                                  params->pipe_htotal,
2241                                  params->spr.horiz_pixels,
2242                                  params->spr.bytes_per_pixel,
2243                                  mem_value);
2244         return min(method1, method2);
2245 }
2246
2247 /*
2248  * For both WM_PIPE and WM_LP.
2249  * mem_value must be in 0.1us units.
2250  */
2251 static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
2252                                    uint32_t mem_value)
2253 {
2254         if (!params->active || !params->cur.enabled)
2255                 return 0;
2256
2257         return ilk_wm_method2(params->pixel_rate,
2258                               params->pipe_htotal,
2259                               params->cur.horiz_pixels,
2260                               params->cur.bytes_per_pixel,
2261                               mem_value);
2262 }
2263
2264 /* Only for WM_LP. */
2265 static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
2266                                    uint32_t pri_val)
2267 {
2268         if (!params->active || !params->pri.enabled)
2269                 return 0;
2270
2271         return ilk_wm_fbc(pri_val,
2272                           params->pri.horiz_pixels,
2273                           params->pri.bytes_per_pixel);
2274 }
2275
2276 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2277 {
2278         if (INTEL_INFO(dev)->gen >= 7)
2279                 return 768;
2280         else
2281                 return 512;
2282 }
2283
2284 /* Calculate the maximum primary/sprite plane watermark */
2285 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2286                                      int level,
2287                                      const struct intel_wm_config *config,
2288                                      enum intel_ddb_partitioning ddb_partitioning,
2289                                      bool is_sprite)
2290 {
2291         unsigned int fifo_size = ilk_display_fifo_size(dev);
2292         unsigned int max;
2293
2294         /* if sprites aren't enabled, sprites get nothing */
2295         if (is_sprite && !config->sprites_enabled)
2296                 return 0;
2297
2298         /* HSW allows LP1+ watermarks even with multiple pipes */
2299         if (level == 0 || config->num_pipes_active > 1) {
2300                 fifo_size /= INTEL_INFO(dev)->num_pipes;
2301
2302                 /*
2303                  * For some reason the non self refresh
2304                  * FIFO size is only half of the self
2305                  * refresh FIFO size on ILK/SNB.
2306                  */
2307                 if (INTEL_INFO(dev)->gen <= 6)
2308                         fifo_size /= 2;
2309         }
2310
2311         if (config->sprites_enabled) {
2312                 /* level 0 is always calculated with 1:1 split */
2313                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2314                         if (is_sprite)
2315                                 fifo_size *= 5;
2316                         fifo_size /= 6;
2317                 } else {
2318                         fifo_size /= 2;
2319                 }
2320         }
2321
2322         /* clamp to max that the registers can hold */
2323         if (INTEL_INFO(dev)->gen >= 7)
2324                 /* IVB/HSW primary/sprite plane watermarks */
2325                 max = level == 0 ? 127 : 1023;
2326         else if (!is_sprite)
2327                 /* ILK/SNB primary plane watermarks */
2328                 max = level == 0 ? 127 : 511;
2329         else
2330                 /* ILK/SNB sprite plane watermarks */
2331                 max = level == 0 ? 63 : 255;
2332
2333         return min(fifo_size, max);
2334 }
2335
2336 /* Calculate the maximum cursor plane watermark */
2337 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
2338                                       int level,
2339                                       const struct intel_wm_config *config)
2340 {
2341         /* HSW LP1+ watermarks w/ multiple pipes */
2342         if (level > 0 && config->num_pipes_active > 1)
2343                 return 64;
2344
2345         /* otherwise just report max that registers can hold */
2346         if (INTEL_INFO(dev)->gen >= 7)
2347                 return level == 0 ? 63 : 255;
2348         else
2349                 return level == 0 ? 31 : 63;
2350 }
2351
2352 /* Calculate the maximum FBC watermark */
2353 static unsigned int ilk_fbc_wm_max(void)
2354 {
2355         /* max that registers can hold */
2356         return 15;
2357 }
2358
2359 static void ilk_wm_max(struct drm_device *dev,
2360                        int level,
2361                        const struct intel_wm_config *config,
2362                        enum intel_ddb_partitioning ddb_partitioning,
2363                        struct hsw_wm_maximums *max)
2364 {
2365         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2366         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2367         max->cur = ilk_cursor_wm_max(dev, level, config);
2368         max->fbc = ilk_fbc_wm_max();
2369 }
2370
2371 static bool ilk_check_wm(int level,
2372                          const struct hsw_wm_maximums *max,
2373                          struct intel_wm_level *result)
2374 {
2375         bool ret;
2376
2377         /* already determined to be invalid? */
2378         if (!result->enable)
2379                 return false;
2380
2381         result->enable = result->pri_val <= max->pri &&
2382                          result->spr_val <= max->spr &&
2383                          result->cur_val <= max->cur;
2384
2385         ret = result->enable;
2386
2387         /*
2388          * HACK until we can pre-compute everything,
2389          * and thus fail gracefully if LP0 watermarks
2390          * are exceeded...
2391          */
2392         if (level == 0 && !result->enable) {
2393                 if (result->pri_val > max->pri)
2394                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2395                                       level, result->pri_val, max->pri);
2396                 if (result->spr_val > max->spr)
2397                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2398                                       level, result->spr_val, max->spr);
2399                 if (result->cur_val > max->cur)
2400                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2401                                       level, result->cur_val, max->cur);
2402
2403                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2404                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2405                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2406                 result->enable = true;
2407         }
2408
2409         DRM_DEBUG_KMS("WM%d: %sabled\n", level, result->enable ? "en" : "dis");
2410
2411         return ret;
2412 }
2413
2414 static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2415                                  int level,
2416                                  struct hsw_pipe_wm_parameters *p,
2417                                  struct intel_wm_level *result)
2418 {
2419         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2420         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2421         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2422
2423         /* WM1+ latency values stored in 0.5us units */
2424         if (level > 0) {
2425                 pri_latency *= 5;
2426                 spr_latency *= 5;
2427                 cur_latency *= 5;
2428         }
2429
2430         result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2431         result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2432         result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2433         result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2434         result->enable = true;
2435 }
2436
2437 static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
2438                               int level, struct hsw_wm_maximums *max,
2439                               struct hsw_pipe_wm_parameters *params,
2440                               struct intel_wm_level *result)
2441 {
2442         enum pipe pipe;
2443         struct intel_wm_level res[3];
2444
2445         for (pipe = PIPE_A; pipe <= PIPE_C; pipe++)
2446                 ilk_compute_wm_level(dev_priv, level, &params[pipe], &res[pipe]);
2447
2448         result->pri_val = max3(res[0].pri_val, res[1].pri_val, res[2].pri_val);
2449         result->spr_val = max3(res[0].spr_val, res[1].spr_val, res[2].spr_val);
2450         result->cur_val = max3(res[0].cur_val, res[1].cur_val, res[2].cur_val);
2451         result->fbc_val = max3(res[0].fbc_val, res[1].fbc_val, res[2].fbc_val);
2452         result->enable = true;
2453
2454         return ilk_check_wm(level, max, result);
2455 }
2456
2457 static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
2458                                     enum pipe pipe,
2459                                     struct hsw_pipe_wm_parameters *params)
2460 {
2461         uint32_t pri_val, cur_val, spr_val;
2462         /* WM0 latency values stored in 0.1us units */
2463         uint16_t pri_latency = dev_priv->wm.pri_latency[0];
2464         uint16_t spr_latency = dev_priv->wm.spr_latency[0];
2465         uint16_t cur_latency = dev_priv->wm.cur_latency[0];
2466
2467         pri_val = ilk_compute_pri_wm(params, pri_latency, false);
2468         spr_val = ilk_compute_spr_wm(params, spr_latency);
2469         cur_val = ilk_compute_cur_wm(params, cur_latency);
2470
2471         WARN(pri_val > 127,
2472              "Primary WM error, mode not supported for pipe %c\n",
2473              pipe_name(pipe));
2474         WARN(spr_val > 127,
2475              "Sprite WM error, mode not supported for pipe %c\n",
2476              pipe_name(pipe));
2477         WARN(cur_val > 63,
2478              "Cursor WM error, mode not supported for pipe %c\n",
2479              pipe_name(pipe));
2480
2481         return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2482                (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2483                cur_val;
2484 }
2485
2486 static uint32_t
2487 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
2488 {
2489         struct drm_i915_private *dev_priv = dev->dev_private;
2490         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2491         struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
2492         u32 linetime, ips_linetime;
2493
2494         if (!intel_crtc_active(crtc))
2495                 return 0;
2496
2497         /* The WM are computed with base on how long it takes to fill a single
2498          * row at the given clock rate, multiplied by 8.
2499          * */
2500         linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2501         ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2502                                          intel_ddi_get_cdclk_freq(dev_priv));
2503
2504         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2505                PIPE_WM_LINETIME_TIME(linetime);
2506 }
2507
2508 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2509 {
2510         struct drm_i915_private *dev_priv = dev->dev_private;
2511
2512         if (IS_HASWELL(dev)) {
2513                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2514
2515                 wm[0] = (sskpd >> 56) & 0xFF;
2516                 if (wm[0] == 0)
2517                         wm[0] = sskpd & 0xF;
2518                 wm[1] = (sskpd >> 4) & 0xFF;
2519                 wm[2] = (sskpd >> 12) & 0xFF;
2520                 wm[3] = (sskpd >> 20) & 0x1FF;
2521                 wm[4] = (sskpd >> 32) & 0x1FF;
2522         } else if (INTEL_INFO(dev)->gen >= 6) {
2523                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2524
2525                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2526                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2527                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2528                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2529         } else if (INTEL_INFO(dev)->gen >= 5) {
2530                 uint32_t mltr = I915_READ(MLTR_ILK);
2531
2532                 /* ILK primary LP0 latency is 700 ns */
2533                 wm[0] = 7;
2534                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2535                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2536         }
2537 }
2538
2539 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2540 {
2541         /* ILK sprite LP0 latency is 1300 ns */
2542         if (INTEL_INFO(dev)->gen == 5)
2543                 wm[0] = 13;
2544 }
2545
2546 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2547 {
2548         /* ILK cursor LP0 latency is 1300 ns */
2549         if (INTEL_INFO(dev)->gen == 5)
2550                 wm[0] = 13;
2551
2552         /* WaDoubleCursorLP3Latency:ivb */
2553         if (IS_IVYBRIDGE(dev))
2554                 wm[3] *= 2;
2555 }
2556
2557 static void intel_print_wm_latency(struct drm_device *dev,
2558                                    const char *name,
2559                                    const uint16_t wm[5])
2560 {
2561         int level, max_level;
2562
2563         /* how many WM levels are we expecting */
2564         if (IS_HASWELL(dev))
2565                 max_level = 4;
2566         else if (INTEL_INFO(dev)->gen >= 6)
2567                 max_level = 3;
2568         else
2569                 max_level = 2;
2570
2571         for (level = 0; level <= max_level; level++) {
2572                 unsigned int latency = wm[level];
2573
2574                 if (latency == 0) {
2575                         DRM_ERROR("%s WM%d latency not provided\n",
2576                                   name, level);
2577                         continue;
2578                 }
2579
2580                 /* WM1+ latency values in 0.5us units */
2581                 if (level > 0)
2582                         latency *= 5;
2583
2584                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2585                               name, level, wm[level],
2586                               latency / 10, latency % 10);
2587         }
2588 }
2589
2590 static void intel_setup_wm_latency(struct drm_device *dev)
2591 {
2592         struct drm_i915_private *dev_priv = dev->dev_private;
2593
2594         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2595
2596         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2597                sizeof(dev_priv->wm.pri_latency));
2598         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2599                sizeof(dev_priv->wm.pri_latency));
2600
2601         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2602         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2603
2604         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2605         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2606         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2607 }
2608
2609 static void hsw_compute_wm_parameters(struct drm_device *dev,
2610                                       struct hsw_pipe_wm_parameters *params,
2611                                       struct hsw_wm_maximums *lp_max_1_2,
2612                                       struct hsw_wm_maximums *lp_max_5_6)
2613 {
2614         struct drm_crtc *crtc;
2615         struct drm_plane *plane;
2616         enum pipe pipe;
2617         struct intel_wm_config config = {};
2618
2619         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2620                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2621                 struct hsw_pipe_wm_parameters *p;
2622
2623                 pipe = intel_crtc->pipe;
2624                 p = &params[pipe];
2625
2626                 p->active = intel_crtc_active(crtc);
2627                 if (!p->active)
2628                         continue;
2629
2630                 config.num_pipes_active++;
2631
2632                 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2633                 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
2634                 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2635                 p->cur.bytes_per_pixel = 4;
2636                 p->pri.horiz_pixels =
2637                         intel_crtc->config.requested_mode.hdisplay;
2638                 p->cur.horiz_pixels = 64;
2639                 /* TODO: for now, assume primary and cursor planes are always enabled. */
2640                 p->pri.enabled = true;
2641                 p->cur.enabled = true;
2642         }
2643
2644         list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2645                 struct intel_plane *intel_plane = to_intel_plane(plane);
2646                 struct hsw_pipe_wm_parameters *p;
2647
2648                 pipe = intel_plane->pipe;
2649                 p = &params[pipe];
2650
2651                 p->spr = intel_plane->wm;
2652
2653                 config.sprites_enabled |= p->spr.enabled;
2654                 config.sprites_scaled |= p->spr.scaled;
2655         }
2656
2657         ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, lp_max_1_2);
2658
2659         /* 5/6 split only in single pipe config on IVB+ */
2660         if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active <= 1)
2661                 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, lp_max_5_6);
2662         else
2663                 *lp_max_5_6 = *lp_max_1_2;
2664 }
2665
2666 static void hsw_compute_wm_results(struct drm_device *dev,
2667                                    struct hsw_pipe_wm_parameters *params,
2668                                    struct hsw_wm_maximums *lp_maximums,
2669                                    struct hsw_wm_values *results)
2670 {
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         struct drm_crtc *crtc;
2673         struct intel_wm_level lp_results[4] = {};
2674         enum pipe pipe;
2675         int level, max_level, wm_lp;
2676
2677         for (level = 1; level <= 4; level++)
2678                 if (!hsw_compute_lp_wm(dev_priv, level,
2679                                        lp_maximums, params,
2680                                        &lp_results[level - 1]))
2681                         break;
2682         max_level = level - 1;
2683
2684         memset(results, 0, sizeof(*results));
2685
2686         /* The spec says it is preferred to disable FBC WMs instead of disabling
2687          * a WM level. */
2688         results->enable_fbc_wm = true;
2689         for (level = 1; level <= max_level; level++) {
2690                 if (lp_results[level - 1].fbc_val > lp_maximums->fbc) {
2691                         results->enable_fbc_wm = false;
2692                         lp_results[level - 1].fbc_val = 0;
2693                 }
2694         }
2695
2696         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2697                 const struct intel_wm_level *r;
2698
2699                 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2700                 if (level > max_level)
2701                         break;
2702
2703                 r = &lp_results[level - 1];
2704                 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2705                                                           r->fbc_val,
2706                                                           r->pri_val,
2707                                                           r->cur_val);
2708                 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2709         }
2710
2711         for_each_pipe(pipe)
2712                 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, pipe,
2713                                                              &params[pipe]);
2714
2715         for_each_pipe(pipe) {
2716                 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2717                 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2718         }
2719 }
2720
2721 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2722  * case both are at the same level. Prefer r1 in case they're the same. */
2723 static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2724                                                   struct hsw_wm_values *r2)
2725 {
2726         int i, val_r1 = 0, val_r2 = 0;
2727
2728         for (i = 0; i < 3; i++) {
2729                 if (r1->wm_lp[i] & WM3_LP_EN)
2730                         val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2731                 if (r2->wm_lp[i] & WM3_LP_EN)
2732                         val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2733         }
2734
2735         if (val_r1 == val_r2) {
2736                 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2737                         return r2;
2738                 else
2739                         return r1;
2740         } else if (val_r1 > val_r2) {
2741                 return r1;
2742         } else {
2743                 return r2;
2744         }
2745 }
2746
2747 /*
2748  * The spec says we shouldn't write when we don't need, because every write
2749  * causes WMs to be re-evaluated, expending some power.
2750  */
2751 static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2752                                 struct hsw_wm_values *results,
2753                                 enum intel_ddb_partitioning partitioning)
2754 {
2755         struct hsw_wm_values previous;
2756         uint32_t val;
2757         enum intel_ddb_partitioning prev_partitioning;
2758         bool prev_enable_fbc_wm;
2759
2760         previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2761         previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2762         previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2763         previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2764         previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2765         previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2766         previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2767         previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2768         previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2769         previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2770         previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2771         previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2772
2773         prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2774                                 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
2775
2776         prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2777
2778         if (memcmp(results->wm_pipe, previous.wm_pipe,
2779                    sizeof(results->wm_pipe)) == 0 &&
2780             memcmp(results->wm_lp, previous.wm_lp,
2781                    sizeof(results->wm_lp)) == 0 &&
2782             memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2783                    sizeof(results->wm_lp_spr)) == 0 &&
2784             memcmp(results->wm_linetime, previous.wm_linetime,
2785                    sizeof(results->wm_linetime)) == 0 &&
2786             partitioning == prev_partitioning &&
2787             results->enable_fbc_wm == prev_enable_fbc_wm)
2788                 return;
2789
2790         if (previous.wm_lp[2] != 0)
2791                 I915_WRITE(WM3_LP_ILK, 0);
2792         if (previous.wm_lp[1] != 0)
2793                 I915_WRITE(WM2_LP_ILK, 0);
2794         if (previous.wm_lp[0] != 0)
2795                 I915_WRITE(WM1_LP_ILK, 0);
2796
2797         if (previous.wm_pipe[0] != results->wm_pipe[0])
2798                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2799         if (previous.wm_pipe[1] != results->wm_pipe[1])
2800                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2801         if (previous.wm_pipe[2] != results->wm_pipe[2])
2802                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2803
2804         if (previous.wm_linetime[0] != results->wm_linetime[0])
2805                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2806         if (previous.wm_linetime[1] != results->wm_linetime[1])
2807                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2808         if (previous.wm_linetime[2] != results->wm_linetime[2])
2809                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2810
2811         if (prev_partitioning != partitioning) {
2812                 val = I915_READ(WM_MISC);
2813                 if (partitioning == INTEL_DDB_PART_1_2)
2814                         val &= ~WM_MISC_DATA_PARTITION_5_6;
2815                 else
2816                         val |= WM_MISC_DATA_PARTITION_5_6;
2817                 I915_WRITE(WM_MISC, val);
2818         }
2819
2820         if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2821                 val = I915_READ(DISP_ARB_CTL);
2822                 if (results->enable_fbc_wm)
2823                         val &= ~DISP_FBC_WM_DIS;
2824                 else
2825                         val |= DISP_FBC_WM_DIS;
2826                 I915_WRITE(DISP_ARB_CTL, val);
2827         }
2828
2829         if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2830                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2831         if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2832                 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2833         if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2834                 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2835
2836         if (results->wm_lp[0] != 0)
2837                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2838         if (results->wm_lp[1] != 0)
2839                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2840         if (results->wm_lp[2] != 0)
2841                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2842 }
2843
2844 static void haswell_update_wm(struct drm_device *dev)
2845 {
2846         struct drm_i915_private *dev_priv = dev->dev_private;
2847         struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
2848         struct hsw_pipe_wm_parameters params[3];
2849         struct hsw_wm_values results_1_2, results_5_6, *best_results;
2850         enum intel_ddb_partitioning partitioning;
2851
2852         hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
2853
2854         hsw_compute_wm_results(dev, params,
2855                                &lp_max_1_2, &results_1_2);
2856         if (lp_max_1_2.pri != lp_max_5_6.pri) {
2857                 hsw_compute_wm_results(dev, params,
2858                                        &lp_max_5_6, &results_5_6);
2859                 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2860         } else {
2861                 best_results = &results_1_2;
2862         }
2863
2864         partitioning = (best_results == &results_1_2) ?
2865                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
2866
2867         hsw_write_wm_values(dev_priv, best_results, partitioning);
2868 }
2869
2870 static void haswell_update_sprite_wm(struct drm_plane *plane,
2871                                      struct drm_crtc *crtc,
2872                                      uint32_t sprite_width, int pixel_size,
2873                                      bool enabled, bool scaled)
2874 {
2875         struct intel_plane *intel_plane = to_intel_plane(plane);
2876
2877         intel_plane->wm.enabled = enabled;
2878         intel_plane->wm.scaled = scaled;
2879         intel_plane->wm.horiz_pixels = sprite_width;
2880         intel_plane->wm.bytes_per_pixel = pixel_size;
2881
2882         haswell_update_wm(plane->dev);
2883 }
2884
2885 static bool
2886 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2887                               uint32_t sprite_width, int pixel_size,
2888                               const struct intel_watermark_params *display,
2889                               int display_latency_ns, int *sprite_wm)
2890 {
2891         struct drm_crtc *crtc;
2892         int clock;
2893         int entries, tlb_miss;
2894
2895         crtc = intel_get_crtc_for_plane(dev, plane);
2896         if (!intel_crtc_active(crtc)) {
2897                 *sprite_wm = display->guard_size;
2898                 return false;
2899         }
2900
2901         clock = crtc->mode.clock;
2902
2903         /* Use the small buffer method to calculate the sprite watermark */
2904         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2905         tlb_miss = display->fifo_size*display->cacheline_size -
2906                 sprite_width * 8;
2907         if (tlb_miss > 0)
2908                 entries += tlb_miss;
2909         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2910         *sprite_wm = entries + display->guard_size;
2911         if (*sprite_wm > (int)display->max_wm)
2912                 *sprite_wm = display->max_wm;
2913
2914         return true;
2915 }
2916
2917 static bool
2918 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2919                                 uint32_t sprite_width, int pixel_size,
2920                                 const struct intel_watermark_params *display,
2921                                 int latency_ns, int *sprite_wm)
2922 {
2923         struct drm_crtc *crtc;
2924         unsigned long line_time_us;
2925         int clock;
2926         int line_count, line_size;
2927         int small, large;
2928         int entries;
2929
2930         if (!latency_ns) {
2931                 *sprite_wm = 0;
2932                 return false;
2933         }
2934
2935         crtc = intel_get_crtc_for_plane(dev, plane);
2936         clock = crtc->mode.clock;
2937         if (!clock) {
2938                 *sprite_wm = 0;
2939                 return false;
2940         }
2941
2942         line_time_us = (sprite_width * 1000) / clock;
2943         if (!line_time_us) {
2944                 *sprite_wm = 0;
2945                 return false;
2946         }
2947
2948         line_count = (latency_ns / line_time_us + 1000) / 1000;
2949         line_size = sprite_width * pixel_size;
2950
2951         /* Use the minimum of the small and large buffer method for primary */
2952         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2953         large = line_count * line_size;
2954
2955         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2956         *sprite_wm = entries + display->guard_size;
2957
2958         return *sprite_wm > 0x3ff ? false : true;
2959 }
2960
2961 static void sandybridge_update_sprite_wm(struct drm_plane *plane,
2962                                          struct drm_crtc *crtc,
2963                                          uint32_t sprite_width, int pixel_size,
2964                                          bool enabled, bool scaled)
2965 {
2966         struct drm_device *dev = plane->dev;
2967         struct drm_i915_private *dev_priv = dev->dev_private;
2968         int pipe = to_intel_plane(plane)->pipe;
2969         int latency = dev_priv->wm.spr_latency[0] * 100;        /* In unit 0.1us */
2970         u32 val;
2971         int sprite_wm, reg;
2972         int ret;
2973
2974         if (!enabled)
2975                 return;
2976
2977         switch (pipe) {
2978         case 0:
2979                 reg = WM0_PIPEA_ILK;
2980                 break;
2981         case 1:
2982                 reg = WM0_PIPEB_ILK;
2983                 break;
2984         case 2:
2985                 reg = WM0_PIPEC_IVB;
2986                 break;
2987         default:
2988                 return; /* bad pipe */
2989         }
2990
2991         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2992                                             &sandybridge_display_wm_info,
2993                                             latency, &sprite_wm);
2994         if (!ret) {
2995                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2996                               pipe_name(pipe));
2997                 return;
2998         }
2999
3000         val = I915_READ(reg);
3001         val &= ~WM0_PIPE_SPRITE_MASK;
3002         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
3003         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
3004
3005
3006         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3007                                               pixel_size,
3008                                               &sandybridge_display_srwm_info,
3009                                               dev_priv->wm.spr_latency[1] * 500,
3010                                               &sprite_wm);
3011         if (!ret) {
3012                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3013                               pipe_name(pipe));
3014                 return;
3015         }
3016         I915_WRITE(WM1S_LP_ILK, sprite_wm);
3017
3018         /* Only IVB has two more LP watermarks for sprite */
3019         if (!IS_IVYBRIDGE(dev))
3020                 return;
3021
3022         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3023                                               pixel_size,
3024                                               &sandybridge_display_srwm_info,
3025                                               dev_priv->wm.spr_latency[2] * 500,
3026                                               &sprite_wm);
3027         if (!ret) {
3028                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3029                               pipe_name(pipe));
3030                 return;
3031         }
3032         I915_WRITE(WM2S_LP_IVB, sprite_wm);
3033
3034         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3035                                               pixel_size,
3036                                               &sandybridge_display_srwm_info,
3037                                               dev_priv->wm.spr_latency[3] * 500,
3038                                               &sprite_wm);
3039         if (!ret) {
3040                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3041                               pipe_name(pipe));
3042                 return;
3043         }
3044         I915_WRITE(WM3S_LP_IVB, sprite_wm);
3045 }
3046
3047 /**
3048  * intel_update_watermarks - update FIFO watermark values based on current modes
3049  *
3050  * Calculate watermark values for the various WM regs based on current mode
3051  * and plane configuration.
3052  *
3053  * There are several cases to deal with here:
3054  *   - normal (i.e. non-self-refresh)
3055  *   - self-refresh (SR) mode
3056  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3057  *   - lines are small relative to FIFO size (buffer can hold more than 2
3058  *     lines), so need to account for TLB latency
3059  *
3060  *   The normal calculation is:
3061  *     watermark = dotclock * bytes per pixel * latency
3062  *   where latency is platform & configuration dependent (we assume pessimal
3063  *   values here).
3064  *
3065  *   The SR calculation is:
3066  *     watermark = (trunc(latency/line time)+1) * surface width *
3067  *       bytes per pixel
3068  *   where
3069  *     line time = htotal / dotclock
3070  *     surface width = hdisplay for normal plane and 64 for cursor
3071  *   and latency is assumed to be high, as above.
3072  *
3073  * The final value programmed to the register should always be rounded up,
3074  * and include an extra 2 entries to account for clock crossings.
3075  *
3076  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3077  * to set the non-SR watermarks to 8.
3078  */
3079 void intel_update_watermarks(struct drm_device *dev)
3080 {
3081         struct drm_i915_private *dev_priv = dev->dev_private;
3082
3083         if (dev_priv->display.update_wm)
3084                 dev_priv->display.update_wm(dev);
3085 }
3086
3087 void intel_update_sprite_watermarks(struct drm_plane *plane,
3088                                     struct drm_crtc *crtc,
3089                                     uint32_t sprite_width, int pixel_size,
3090                                     bool enabled, bool scaled)
3091 {
3092         struct drm_i915_private *dev_priv = plane->dev->dev_private;
3093
3094         if (dev_priv->display.update_sprite_wm)
3095                 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
3096                                                    pixel_size, enabled, scaled);
3097 }
3098
3099 static struct drm_i915_gem_object *
3100 intel_alloc_context_page(struct drm_device *dev)
3101 {
3102         struct drm_i915_gem_object *ctx;
3103         int ret;
3104
3105         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3106
3107         ctx = i915_gem_alloc_object(dev, 4096);
3108         if (!ctx) {
3109                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3110                 return NULL;
3111         }
3112
3113         ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
3114         if (ret) {
3115                 DRM_ERROR("failed to pin power context: %d\n", ret);
3116                 goto err_unref;
3117         }
3118
3119         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3120         if (ret) {
3121                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3122                 goto err_unpin;
3123         }
3124
3125         return ctx;
3126
3127 err_unpin:
3128         i915_gem_object_unpin(ctx);
3129 err_unref:
3130         drm_gem_object_unreference(&ctx->base);
3131         return NULL;
3132 }
3133
3134 /**
3135  * Lock protecting IPS related data structures
3136  */
3137 DEFINE_SPINLOCK(mchdev_lock);
3138
3139 /* Global for IPS driver to get at the current i915 device. Protected by
3140  * mchdev_lock. */
3141 static struct drm_i915_private *i915_mch_dev;
3142
3143 bool ironlake_set_drps(struct drm_device *dev, u8 val)
3144 {
3145         struct drm_i915_private *dev_priv = dev->dev_private;
3146         u16 rgvswctl;
3147
3148         assert_spin_locked(&mchdev_lock);
3149
3150         rgvswctl = I915_READ16(MEMSWCTL);
3151         if (rgvswctl & MEMCTL_CMD_STS) {
3152                 DRM_DEBUG("gpu busy, RCS change rejected\n");
3153                 return false; /* still busy with another command */
3154         }
3155
3156         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3157                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3158         I915_WRITE16(MEMSWCTL, rgvswctl);
3159         POSTING_READ16(MEMSWCTL);
3160
3161         rgvswctl |= MEMCTL_CMD_STS;
3162         I915_WRITE16(MEMSWCTL, rgvswctl);
3163
3164         return true;
3165 }
3166
3167 static void ironlake_enable_drps(struct drm_device *dev)
3168 {
3169         struct drm_i915_private *dev_priv = dev->dev_private;
3170         u32 rgvmodectl = I915_READ(MEMMODECTL);
3171         u8 fmax, fmin, fstart, vstart;
3172
3173         spin_lock_irq(&mchdev_lock);
3174
3175         /* Enable temp reporting */
3176         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3177         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3178
3179         /* 100ms RC evaluation intervals */
3180         I915_WRITE(RCUPEI, 100000);
3181         I915_WRITE(RCDNEI, 100000);
3182
3183         /* Set max/min thresholds to 90ms and 80ms respectively */
3184         I915_WRITE(RCBMAXAVG, 90000);
3185         I915_WRITE(RCBMINAVG, 80000);
3186
3187         I915_WRITE(MEMIHYST, 1);
3188
3189         /* Set up min, max, and cur for interrupt handling */
3190         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3191         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3192         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3193                 MEMMODE_FSTART_SHIFT;
3194
3195         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3196                 PXVFREQ_PX_SHIFT;
3197
3198         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3199         dev_priv->ips.fstart = fstart;
3200
3201         dev_priv->ips.max_delay = fstart;
3202         dev_priv->ips.min_delay = fmin;
3203         dev_priv->ips.cur_delay = fstart;
3204
3205         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3206                          fmax, fmin, fstart);
3207
3208         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3209
3210         /*
3211          * Interrupts will be enabled in ironlake_irq_postinstall
3212          */
3213
3214         I915_WRITE(VIDSTART, vstart);
3215         POSTING_READ(VIDSTART);
3216
3217         rgvmodectl |= MEMMODE_SWMODE_EN;
3218         I915_WRITE(MEMMODECTL, rgvmodectl);
3219
3220         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
3221                 DRM_ERROR("stuck trying to change perf mode\n");
3222         mdelay(1);
3223
3224         ironlake_set_drps(dev, fstart);
3225
3226         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
3227                 I915_READ(0x112e0);
3228         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3229         dev_priv->ips.last_count2 = I915_READ(0x112f4);
3230         getrawmonotonic(&dev_priv->ips.last_time2);
3231
3232         spin_unlock_irq(&mchdev_lock);
3233 }
3234
3235 static void ironlake_disable_drps(struct drm_device *dev)
3236 {
3237         struct drm_i915_private *dev_priv = dev->dev_private;
3238         u16 rgvswctl;
3239
3240         spin_lock_irq(&mchdev_lock);
3241
3242         rgvswctl = I915_READ16(MEMSWCTL);
3243
3244         /* Ack interrupts, disable EFC interrupt */
3245         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3246         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3247         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3248         I915_WRITE(DEIIR, DE_PCU_EVENT);
3249         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3250
3251         /* Go back to the starting frequency */
3252         ironlake_set_drps(dev, dev_priv->ips.fstart);
3253         mdelay(1);
3254         rgvswctl |= MEMCTL_CMD_STS;
3255         I915_WRITE(MEMSWCTL, rgvswctl);
3256         mdelay(1);
3257
3258         spin_unlock_irq(&mchdev_lock);
3259 }
3260
3261 /* There's a funny hw issue where the hw returns all 0 when reading from
3262  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3263  * ourselves, instead of doing a rmw cycle (which might result in us clearing
3264  * all limits and the gpu stuck at whatever frequency it is at atm).
3265  */
3266 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
3267 {
3268         u32 limits;
3269
3270         limits = 0;
3271
3272         if (*val >= dev_priv->rps.max_delay)
3273                 *val = dev_priv->rps.max_delay;
3274         limits |= dev_priv->rps.max_delay << 24;
3275
3276         /* Only set the down limit when we've reached the lowest level to avoid
3277          * getting more interrupts, otherwise leave this clear. This prevents a
3278          * race in the hw when coming out of rc6: There's a tiny window where
3279          * the hw runs at the minimal clock before selecting the desired
3280          * frequency, if the down threshold expires in that window we will not
3281          * receive a down interrupt. */
3282         if (*val <= dev_priv->rps.min_delay) {
3283                 *val = dev_priv->rps.min_delay;
3284                 limits |= dev_priv->rps.min_delay << 16;
3285         }
3286
3287         return limits;
3288 }
3289
3290 void gen6_set_rps(struct drm_device *dev, u8 val)
3291 {
3292         struct drm_i915_private *dev_priv = dev->dev_private;
3293         u32 limits = gen6_rps_limits(dev_priv, &val);
3294
3295         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3296         WARN_ON(val > dev_priv->rps.max_delay);
3297         WARN_ON(val < dev_priv->rps.min_delay);
3298
3299         if (val == dev_priv->rps.cur_delay)
3300                 return;
3301
3302         if (IS_HASWELL(dev))
3303                 I915_WRITE(GEN6_RPNSWREQ,
3304                            HSW_FREQUENCY(val));
3305         else
3306                 I915_WRITE(GEN6_RPNSWREQ,
3307                            GEN6_FREQUENCY(val) |
3308                            GEN6_OFFSET(0) |
3309                            GEN6_AGGRESSIVE_TURBO);
3310
3311         /* Make sure we continue to get interrupts
3312          * until we hit the minimum or maximum frequencies.
3313          */
3314         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3315
3316         POSTING_READ(GEN6_RPNSWREQ);
3317
3318         dev_priv->rps.cur_delay = val;
3319
3320         trace_intel_gpu_freq_change(val * 50);
3321 }
3322
3323 /*
3324  * Wait until the previous freq change has completed,
3325  * or the timeout elapsed, and then update our notion
3326  * of the current GPU frequency.
3327  */
3328 static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3329 {
3330         u32 pval;
3331
3332         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3333
3334         if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3335                 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3336
3337         pval >>= 8;
3338
3339         if (pval != dev_priv->rps.cur_delay)
3340                 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3341                                  vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3342                                  dev_priv->rps.cur_delay,
3343                                  vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3344
3345         dev_priv->rps.cur_delay = pval;
3346 }
3347
3348 void valleyview_set_rps(struct drm_device *dev, u8 val)
3349 {
3350         struct drm_i915_private *dev_priv = dev->dev_private;
3351
3352         gen6_rps_limits(dev_priv, &val);
3353
3354         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3355         WARN_ON(val > dev_priv->rps.max_delay);
3356         WARN_ON(val < dev_priv->rps.min_delay);
3357
3358         vlv_update_rps_cur_delay(dev_priv);
3359
3360         DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3361                          vlv_gpu_freq(dev_priv->mem_freq,
3362                                       dev_priv->rps.cur_delay),
3363                          dev_priv->rps.cur_delay,
3364                          vlv_gpu_freq(dev_priv->mem_freq, val), val);
3365
3366         if (val == dev_priv->rps.cur_delay)
3367                 return;
3368
3369         vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
3370
3371         dev_priv->rps.cur_delay = val;
3372
3373         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3374 }
3375
3376 static void gen6_disable_rps_interrupts(struct drm_device *dev)
3377 {
3378         struct drm_i915_private *dev_priv = dev->dev_private;
3379
3380         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
3381         I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
3382         /* Complete PM interrupt masking here doesn't race with the rps work
3383          * item again unmasking PM interrupts because that is using a different
3384          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3385          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3386
3387         spin_lock_irq(&dev_priv->irq_lock);
3388         dev_priv->rps.pm_iir = 0;
3389         spin_unlock_irq(&dev_priv->irq_lock);
3390
3391         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3392 }
3393
3394 static void gen6_disable_rps(struct drm_device *dev)
3395 {
3396         struct drm_i915_private *dev_priv = dev->dev_private;
3397
3398         I915_WRITE(GEN6_RC_CONTROL, 0);
3399         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
3400
3401         gen6_disable_rps_interrupts(dev);
3402 }
3403
3404 static void valleyview_disable_rps(struct drm_device *dev)
3405 {
3406         struct drm_i915_private *dev_priv = dev->dev_private;
3407
3408         I915_WRITE(GEN6_RC_CONTROL, 0);
3409
3410         gen6_disable_rps_interrupts(dev);
3411
3412         if (dev_priv->vlv_pctx) {
3413                 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3414                 dev_priv->vlv_pctx = NULL;
3415         }
3416 }
3417
3418 int intel_enable_rc6(const struct drm_device *dev)
3419 {
3420         /* No RC6 before Ironlake */
3421         if (INTEL_INFO(dev)->gen < 5)
3422                 return 0;
3423
3424         /* Respect the kernel parameter if it is set */
3425         if (i915_enable_rc6 >= 0)
3426                 return i915_enable_rc6;
3427
3428         /* Disable RC6 on Ironlake */
3429         if (INTEL_INFO(dev)->gen == 5)
3430                 return 0;
3431
3432         if (IS_HASWELL(dev)) {
3433                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3434                 return INTEL_RC6_ENABLE;
3435         }
3436
3437         /* snb/ivb have more than one rc6 state. */
3438         if (INTEL_INFO(dev)->gen == 6) {
3439                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3440                 return INTEL_RC6_ENABLE;
3441         }
3442
3443         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3444         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3445 }
3446
3447 static void gen6_enable_rps_interrupts(struct drm_device *dev)
3448 {
3449         struct drm_i915_private *dev_priv = dev->dev_private;
3450
3451         spin_lock_irq(&dev_priv->irq_lock);
3452         WARN_ON(dev_priv->rps.pm_iir);
3453         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
3454         I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3455         spin_unlock_irq(&dev_priv->irq_lock);
3456         /* only unmask PM interrupts we need. Mask all others. */
3457         I915_WRITE(GEN6_PMINTRMSK, ~GEN6_PM_RPS_EVENTS);
3458 }
3459
3460 static void gen6_enable_rps(struct drm_device *dev)
3461 {
3462         struct drm_i915_private *dev_priv = dev->dev_private;
3463         struct intel_ring_buffer *ring;
3464         u32 rp_state_cap;
3465         u32 gt_perf_status;
3466         u32 rc6vids, pcu_mbox, rc6_mask = 0;
3467         u32 gtfifodbg;
3468         int rc6_mode;
3469         int i, ret;
3470
3471         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3472
3473         /* Here begins a magic sequence of register writes to enable
3474          * auto-downclocking.
3475          *
3476          * Perhaps there might be some value in exposing these to
3477          * userspace...
3478          */
3479         I915_WRITE(GEN6_RC_STATE, 0);
3480
3481         /* Clear the DBG now so we don't confuse earlier errors */
3482         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3483                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3484                 I915_WRITE(GTFIFODBG, gtfifodbg);
3485         }
3486
3487         gen6_gt_force_wake_get(dev_priv);
3488
3489         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3490         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3491
3492         /* In units of 50MHz */
3493         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
3494         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3495         dev_priv->rps.cur_delay = 0;
3496
3497         /* disable the counters and set deterministic thresholds */
3498         I915_WRITE(GEN6_RC_CONTROL, 0);
3499
3500         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3501         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3502         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3503         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3504         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3505
3506         for_each_ring(ring, dev_priv, i)
3507                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3508
3509         I915_WRITE(GEN6_RC_SLEEP, 0);
3510         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3511         if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3512                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3513         else
3514                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
3515         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
3516         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3517
3518         /* Check if we are enabling RC6 */
3519         rc6_mode = intel_enable_rc6(dev_priv->dev);
3520         if (rc6_mode & INTEL_RC6_ENABLE)
3521                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3522
3523         /* We don't use those on Haswell */
3524         if (!IS_HASWELL(dev)) {
3525                 if (rc6_mode & INTEL_RC6p_ENABLE)
3526                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
3527
3528                 if (rc6_mode & INTEL_RC6pp_ENABLE)
3529                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3530         }
3531
3532         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3533                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3534                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3535                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3536
3537         I915_WRITE(GEN6_RC_CONTROL,
3538                    rc6_mask |
3539                    GEN6_RC_CTL_EI_MODE(1) |
3540                    GEN6_RC_CTL_HW_ENABLE);
3541
3542         if (IS_HASWELL(dev)) {
3543                 I915_WRITE(GEN6_RPNSWREQ,
3544                            HSW_FREQUENCY(10));
3545                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3546                            HSW_FREQUENCY(12));
3547         } else {
3548                 I915_WRITE(GEN6_RPNSWREQ,
3549                            GEN6_FREQUENCY(10) |
3550                            GEN6_OFFSET(0) |
3551                            GEN6_AGGRESSIVE_TURBO);
3552                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3553                            GEN6_FREQUENCY(12));
3554         }
3555
3556         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3557         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3558                    dev_priv->rps.max_delay << 24 |
3559                    dev_priv->rps.min_delay << 16);
3560
3561         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3562         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3563         I915_WRITE(GEN6_RP_UP_EI, 66000);
3564         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3565
3566         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3567         I915_WRITE(GEN6_RP_CONTROL,
3568                    GEN6_RP_MEDIA_TURBO |
3569                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3570                    GEN6_RP_MEDIA_IS_GFX |
3571                    GEN6_RP_ENABLE |
3572                    GEN6_RP_UP_BUSY_AVG |
3573                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
3574
3575         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
3576         if (!ret) {
3577                 pcu_mbox = 0;
3578                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
3579                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
3580                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3581                                          (dev_priv->rps.max_delay & 0xff) * 50,
3582                                          (pcu_mbox & 0xff) * 50);
3583                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
3584                 }
3585         } else {
3586                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3587         }
3588
3589         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
3590
3591         gen6_enable_rps_interrupts(dev);
3592
3593         rc6vids = 0;
3594         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3595         if (IS_GEN6(dev) && ret) {
3596                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3597         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3598                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3599                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3600                 rc6vids &= 0xffff00;
3601                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3602                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3603                 if (ret)
3604                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3605         }
3606
3607         gen6_gt_force_wake_put(dev_priv);
3608 }
3609
3610 static void gen6_update_ring_freq(struct drm_device *dev)
3611 {
3612         struct drm_i915_private *dev_priv = dev->dev_private;
3613         int min_freq = 15;
3614         unsigned int gpu_freq;
3615         unsigned int max_ia_freq, min_ring_freq;
3616         int scaling_factor = 180;
3617
3618         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3619
3620         max_ia_freq = cpufreq_quick_get_max(0);
3621         /*
3622          * Default to measured freq if none found, PCU will ensure we don't go
3623          * over
3624          */
3625         if (!max_ia_freq)
3626                 max_ia_freq = tsc_khz;
3627
3628         /* Convert from kHz to MHz */
3629         max_ia_freq /= 1000;
3630
3631         min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3632         /* convert DDR frequency from units of 133.3MHz to bandwidth */
3633         min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3634
3635         /*
3636          * For each potential GPU frequency, load a ring frequency we'd like
3637          * to use for memory access.  We do this by specifying the IA frequency
3638          * the PCU should use as a reference to determine the ring frequency.
3639          */
3640         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
3641              gpu_freq--) {
3642                 int diff = dev_priv->rps.max_delay - gpu_freq;
3643                 unsigned int ia_freq = 0, ring_freq = 0;
3644
3645                 if (IS_HASWELL(dev)) {
3646                         ring_freq = (gpu_freq * 5 + 3) / 4;
3647                         ring_freq = max(min_ring_freq, ring_freq);
3648                         /* leave ia_freq as the default, chosen by cpufreq */
3649                 } else {
3650                         /* On older processors, there is no separate ring
3651                          * clock domain, so in order to boost the bandwidth
3652                          * of the ring, we need to upclock the CPU (ia_freq).
3653                          *
3654                          * For GPU frequencies less than 750MHz,
3655                          * just use the lowest ring freq.
3656                          */
3657                         if (gpu_freq < min_freq)
3658                                 ia_freq = 800;
3659                         else
3660                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3661                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3662                 }
3663
3664                 sandybridge_pcode_write(dev_priv,
3665                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3666                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3667                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3668                                         gpu_freq);
3669         }
3670 }
3671
3672 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3673 {
3674         u32 val, rp0;
3675
3676         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
3677
3678         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3679         /* Clamp to max */
3680         rp0 = min_t(u32, rp0, 0xea);
3681
3682         return rp0;
3683 }
3684
3685 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3686 {
3687         u32 val, rpe;
3688
3689         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
3690         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
3691         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
3692         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3693
3694         return rpe;
3695 }
3696
3697 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3698 {
3699         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
3700 }
3701
3702 static void vlv_rps_timer_work(struct work_struct *work)
3703 {
3704         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3705                                                     rps.vlv_work.work);
3706
3707         /*
3708          * Timer fired, we must be idle.  Drop to min voltage state.
3709          * Note: we use RPe here since it should match the
3710          * Vmin we were shooting for.  That should give us better
3711          * perf when we come back out of RC6 than if we used the
3712          * min freq available.
3713          */
3714         mutex_lock(&dev_priv->rps.hw_lock);
3715         if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3716                 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3717         mutex_unlock(&dev_priv->rps.hw_lock);
3718 }
3719
3720 static void valleyview_setup_pctx(struct drm_device *dev)
3721 {
3722         struct drm_i915_private *dev_priv = dev->dev_private;
3723         struct drm_i915_gem_object *pctx;
3724         unsigned long pctx_paddr;
3725         u32 pcbr;
3726         int pctx_size = 24*1024;
3727
3728         pcbr = I915_READ(VLV_PCBR);
3729         if (pcbr) {
3730                 /* BIOS set it up already, grab the pre-alloc'd space */
3731                 int pcbr_offset;
3732
3733                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3734                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3735                                                                       pcbr_offset,
3736                                                                       I915_GTT_OFFSET_NONE,
3737                                                                       pctx_size);
3738                 goto out;
3739         }
3740
3741         /*
3742          * From the Gunit register HAS:
3743          * The Gfx driver is expected to program this register and ensure
3744          * proper allocation within Gfx stolen memory.  For example, this
3745          * register should be programmed such than the PCBR range does not
3746          * overlap with other ranges, such as the frame buffer, protected
3747          * memory, or any other relevant ranges.
3748          */
3749         pctx = i915_gem_object_create_stolen(dev, pctx_size);
3750         if (!pctx) {
3751                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3752                 return;
3753         }
3754
3755         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3756         I915_WRITE(VLV_PCBR, pctx_paddr);
3757
3758 out:
3759         dev_priv->vlv_pctx = pctx;
3760 }
3761
3762 static void valleyview_enable_rps(struct drm_device *dev)
3763 {
3764         struct drm_i915_private *dev_priv = dev->dev_private;
3765         struct intel_ring_buffer *ring;
3766         u32 gtfifodbg, val;
3767         int i;
3768
3769         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3770
3771         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3772                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3773                 I915_WRITE(GTFIFODBG, gtfifodbg);
3774         }
3775
3776         valleyview_setup_pctx(dev);
3777
3778         gen6_gt_force_wake_get(dev_priv);
3779
3780         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3781         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3782         I915_WRITE(GEN6_RP_UP_EI, 66000);
3783         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3784
3785         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3786
3787         I915_WRITE(GEN6_RP_CONTROL,
3788                    GEN6_RP_MEDIA_TURBO |
3789                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
3790                    GEN6_RP_MEDIA_IS_GFX |
3791                    GEN6_RP_ENABLE |
3792                    GEN6_RP_UP_BUSY_AVG |
3793                    GEN6_RP_DOWN_IDLE_CONT);
3794
3795         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3796         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3797         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3798
3799         for_each_ring(ring, dev_priv, i)
3800                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3801
3802         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3803
3804         /* allows RC6 residency counter to work */
3805         I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3806         I915_WRITE(GEN6_RC_CONTROL,
3807                    GEN7_RC_CTL_TO_MODE);
3808
3809         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
3810         switch ((val >> 6) & 3) {
3811         case 0:
3812         case 1:
3813                 dev_priv->mem_freq = 800;
3814                 break;
3815         case 2:
3816                 dev_priv->mem_freq = 1066;
3817                 break;
3818         case 3:
3819                 dev_priv->mem_freq = 1333;
3820                 break;
3821         }
3822         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3823
3824         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3825         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3826
3827         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
3828         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3829                          vlv_gpu_freq(dev_priv->mem_freq,
3830                                       dev_priv->rps.cur_delay),
3831                          dev_priv->rps.cur_delay);
3832
3833         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3834         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
3835         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3836                          vlv_gpu_freq(dev_priv->mem_freq,
3837                                       dev_priv->rps.max_delay),
3838                          dev_priv->rps.max_delay);
3839
3840         dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3841         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3842                          vlv_gpu_freq(dev_priv->mem_freq,
3843                                       dev_priv->rps.rpe_delay),
3844                          dev_priv->rps.rpe_delay);
3845
3846         dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3847         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3848                          vlv_gpu_freq(dev_priv->mem_freq,
3849                                       dev_priv->rps.min_delay),
3850                          dev_priv->rps.min_delay);
3851
3852         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3853                          vlv_gpu_freq(dev_priv->mem_freq,
3854                                       dev_priv->rps.rpe_delay),
3855                          dev_priv->rps.rpe_delay);
3856
3857         INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3858
3859         valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
3860
3861         gen6_enable_rps_interrupts(dev);
3862
3863         gen6_gt_force_wake_put(dev_priv);
3864 }
3865
3866 void ironlake_teardown_rc6(struct drm_device *dev)
3867 {
3868         struct drm_i915_private *dev_priv = dev->dev_private;
3869
3870         if (dev_priv->ips.renderctx) {
3871                 i915_gem_object_unpin(dev_priv->ips.renderctx);
3872                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3873                 dev_priv->ips.renderctx = NULL;
3874         }
3875
3876         if (dev_priv->ips.pwrctx) {
3877                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3878                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3879                 dev_priv->ips.pwrctx = NULL;
3880         }
3881 }
3882
3883 static void ironlake_disable_rc6(struct drm_device *dev)
3884 {
3885         struct drm_i915_private *dev_priv = dev->dev_private;
3886
3887         if (I915_READ(PWRCTXA)) {
3888                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3889                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3890                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3891                          50);
3892
3893                 I915_WRITE(PWRCTXA, 0);
3894                 POSTING_READ(PWRCTXA);
3895
3896                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3897                 POSTING_READ(RSTDBYCTL);
3898         }
3899 }
3900
3901 static int ironlake_setup_rc6(struct drm_device *dev)
3902 {
3903         struct drm_i915_private *dev_priv = dev->dev_private;
3904
3905         if (dev_priv->ips.renderctx == NULL)
3906                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3907         if (!dev_priv->ips.renderctx)
3908                 return -ENOMEM;
3909
3910         if (dev_priv->ips.pwrctx == NULL)
3911                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3912         if (!dev_priv->ips.pwrctx) {
3913                 ironlake_teardown_rc6(dev);
3914                 return -ENOMEM;
3915         }
3916
3917         return 0;
3918 }
3919
3920 static void ironlake_enable_rc6(struct drm_device *dev)
3921 {
3922         struct drm_i915_private *dev_priv = dev->dev_private;
3923         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3924         bool was_interruptible;
3925         int ret;
3926
3927         /* rc6 disabled by default due to repeated reports of hanging during
3928          * boot and resume.
3929          */
3930         if (!intel_enable_rc6(dev))
3931                 return;
3932
3933         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3934
3935         ret = ironlake_setup_rc6(dev);
3936         if (ret)
3937                 return;
3938
3939         was_interruptible = dev_priv->mm.interruptible;
3940         dev_priv->mm.interruptible = false;
3941
3942         /*
3943          * GPU can automatically power down the render unit if given a page
3944          * to save state.
3945          */
3946         ret = intel_ring_begin(ring, 6);
3947         if (ret) {
3948                 ironlake_teardown_rc6(dev);
3949                 dev_priv->mm.interruptible = was_interruptible;
3950                 return;
3951         }
3952
3953         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3954         intel_ring_emit(ring, MI_SET_CONTEXT);
3955         intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
3956                         MI_MM_SPACE_GTT |
3957                         MI_SAVE_EXT_STATE_EN |
3958                         MI_RESTORE_EXT_STATE_EN |
3959                         MI_RESTORE_INHIBIT);
3960         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3961         intel_ring_emit(ring, MI_NOOP);
3962         intel_ring_emit(ring, MI_FLUSH);
3963         intel_ring_advance(ring);
3964
3965         /*
3966          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3967          * does an implicit flush, combined with MI_FLUSH above, it should be
3968          * safe to assume that renderctx is valid
3969          */
3970         ret = intel_ring_idle(ring);
3971         dev_priv->mm.interruptible = was_interruptible;
3972         if (ret) {
3973                 DRM_ERROR("failed to enable ironlake power savings\n");
3974                 ironlake_teardown_rc6(dev);
3975                 return;
3976         }
3977
3978         I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
3979         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3980 }
3981
3982 static unsigned long intel_pxfreq(u32 vidfreq)
3983 {
3984         unsigned long freq;
3985         int div = (vidfreq & 0x3f0000) >> 16;
3986         int post = (vidfreq & 0x3000) >> 12;
3987         int pre = (vidfreq & 0x7);
3988
3989         if (!pre)
3990                 return 0;
3991
3992         freq = ((div * 133333) / ((1<<post) * pre));
3993
3994         return freq;
3995 }
3996
3997 static const struct cparams {
3998         u16 i;
3999         u16 t;
4000         u16 m;
4001         u16 c;
4002 } cparams[] = {
4003         { 1, 1333, 301, 28664 },
4004         { 1, 1066, 294, 24460 },
4005         { 1, 800, 294, 25192 },
4006         { 0, 1333, 276, 27605 },
4007         { 0, 1066, 276, 27605 },
4008         { 0, 800, 231, 23784 },
4009 };
4010
4011 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
4012 {
4013         u64 total_count, diff, ret;
4014         u32 count1, count2, count3, m = 0, c = 0;
4015         unsigned long now = jiffies_to_msecs(jiffies), diff1;
4016         int i;
4017
4018         assert_spin_locked(&mchdev_lock);
4019
4020         diff1 = now - dev_priv->ips.last_time1;
4021
4022         /* Prevent division-by-zero if we are asking too fast.
4023          * Also, we don't get interesting results if we are polling
4024          * faster than once in 10ms, so just return the saved value
4025          * in such cases.
4026          */
4027         if (diff1 <= 10)
4028                 return dev_priv->ips.chipset_power;
4029
4030         count1 = I915_READ(DMIEC);
4031         count2 = I915_READ(DDREC);
4032         count3 = I915_READ(CSIEC);
4033
4034         total_count = count1 + count2 + count3;
4035
4036         /* FIXME: handle per-counter overflow */
4037         if (total_count < dev_priv->ips.last_count1) {
4038                 diff = ~0UL - dev_priv->ips.last_count1;
4039                 diff += total_count;
4040         } else {
4041                 diff = total_count - dev_priv->ips.last_count1;
4042         }
4043
4044         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
4045                 if (cparams[i].i == dev_priv->ips.c_m &&
4046                     cparams[i].t == dev_priv->ips.r_t) {
4047                         m = cparams[i].m;
4048                         c = cparams[i].c;
4049                         break;
4050                 }
4051         }
4052
4053         diff = div_u64(diff, diff1);
4054         ret = ((m * diff) + c);
4055         ret = div_u64(ret, 10);
4056
4057         dev_priv->ips.last_count1 = total_count;
4058         dev_priv->ips.last_time1 = now;
4059
4060         dev_priv->ips.chipset_power = ret;
4061
4062         return ret;
4063 }
4064
4065 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4066 {
4067         unsigned long val;
4068
4069         if (dev_priv->info->gen != 5)
4070                 return 0;
4071
4072         spin_lock_irq(&mchdev_lock);
4073
4074         val = __i915_chipset_val(dev_priv);
4075
4076         spin_unlock_irq(&mchdev_lock);
4077
4078         return val;
4079 }
4080
4081 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4082 {
4083         unsigned long m, x, b;
4084         u32 tsfs;
4085
4086         tsfs = I915_READ(TSFS);
4087
4088         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4089         x = I915_READ8(TR1);
4090
4091         b = tsfs & TSFS_INTR_MASK;
4092
4093         return ((m * x) / 127) - b;
4094 }
4095
4096 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4097 {
4098         static const struct v_table {
4099                 u16 vd; /* in .1 mil */
4100                 u16 vm; /* in .1 mil */
4101         } v_table[] = {
4102                 { 0, 0, },
4103                 { 375, 0, },
4104                 { 500, 0, },
4105                 { 625, 0, },
4106                 { 750, 0, },
4107                 { 875, 0, },
4108                 { 1000, 0, },
4109                 { 1125, 0, },
4110                 { 4125, 3000, },
4111                 { 4125, 3000, },
4112                 { 4125, 3000, },
4113                 { 4125, 3000, },
4114                 { 4125, 3000, },
4115                 { 4125, 3000, },
4116                 { 4125, 3000, },
4117                 { 4125, 3000, },
4118                 { 4125, 3000, },
4119                 { 4125, 3000, },
4120                 { 4125, 3000, },
4121                 { 4125, 3000, },
4122                 { 4125, 3000, },
4123                 { 4125, 3000, },
4124                 { 4125, 3000, },
4125                 { 4125, 3000, },
4126                 { 4125, 3000, },
4127                 { 4125, 3000, },
4128                 { 4125, 3000, },
4129                 { 4125, 3000, },
4130                 { 4125, 3000, },
4131                 { 4125, 3000, },
4132                 { 4125, 3000, },
4133                 { 4125, 3000, },
4134                 { 4250, 3125, },
4135                 { 4375, 3250, },
4136                 { 4500, 3375, },
4137                 { 4625, 3500, },
4138                 { 4750, 3625, },
4139                 { 4875, 3750, },
4140                 { 5000, 3875, },
4141                 { 5125, 4000, },
4142                 { 5250, 4125, },
4143                 { 5375, 4250, },
4144                 { 5500, 4375, },
4145                 { 5625, 4500, },
4146                 { 5750, 4625, },
4147                 { 5875, 4750, },
4148                 { 6000, 4875, },
4149                 { 6125, 5000, },
4150                 { 6250, 5125, },
4151                 { 6375, 5250, },
4152                 { 6500, 5375, },
4153                 { 6625, 5500, },
4154                 { 6750, 5625, },
4155                 { 6875, 5750, },
4156                 { 7000, 5875, },
4157                 { 7125, 6000, },
4158                 { 7250, 6125, },
4159                 { 7375, 6250, },
4160                 { 7500, 6375, },
4161                 { 7625, 6500, },
4162                 { 7750, 6625, },
4163                 { 7875, 6750, },
4164                 { 8000, 6875, },
4165                 { 8125, 7000, },
4166                 { 8250, 7125, },
4167                 { 8375, 7250, },
4168                 { 8500, 7375, },
4169                 { 8625, 7500, },
4170                 { 8750, 7625, },
4171                 { 8875, 7750, },
4172                 { 9000, 7875, },
4173                 { 9125, 8000, },
4174                 { 9250, 8125, },
4175                 { 9375, 8250, },
4176                 { 9500, 8375, },
4177                 { 9625, 8500, },
4178                 { 9750, 8625, },
4179                 { 9875, 8750, },
4180                 { 10000, 8875, },
4181                 { 10125, 9000, },
4182                 { 10250, 9125, },
4183                 { 10375, 9250, },
4184                 { 10500, 9375, },
4185                 { 10625, 9500, },
4186                 { 10750, 9625, },
4187                 { 10875, 9750, },
4188                 { 11000, 9875, },
4189                 { 11125, 10000, },
4190                 { 11250, 10125, },
4191                 { 11375, 10250, },
4192                 { 11500, 10375, },
4193                 { 11625, 10500, },
4194                 { 11750, 10625, },
4195                 { 11875, 10750, },
4196                 { 12000, 10875, },
4197                 { 12125, 11000, },
4198                 { 12250, 11125, },
4199                 { 12375, 11250, },
4200                 { 12500, 11375, },
4201                 { 12625, 11500, },
4202                 { 12750, 11625, },
4203                 { 12875, 11750, },
4204                 { 13000, 11875, },
4205                 { 13125, 12000, },
4206                 { 13250, 12125, },
4207                 { 13375, 12250, },
4208                 { 13500, 12375, },
4209                 { 13625, 12500, },
4210                 { 13750, 12625, },
4211                 { 13875, 12750, },
4212                 { 14000, 12875, },
4213                 { 14125, 13000, },
4214                 { 14250, 13125, },
4215                 { 14375, 13250, },
4216                 { 14500, 13375, },
4217                 { 14625, 13500, },
4218                 { 14750, 13625, },
4219                 { 14875, 13750, },
4220                 { 15000, 13875, },
4221                 { 15125, 14000, },
4222                 { 15250, 14125, },
4223                 { 15375, 14250, },
4224                 { 15500, 14375, },
4225                 { 15625, 14500, },
4226                 { 15750, 14625, },
4227                 { 15875, 14750, },
4228                 { 16000, 14875, },
4229                 { 16125, 15000, },
4230         };
4231         if (dev_priv->info->is_mobile)
4232                 return v_table[pxvid].vm;
4233         else
4234                 return v_table[pxvid].vd;
4235 }
4236
4237 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
4238 {
4239         struct timespec now, diff1;
4240         u64 diff;
4241         unsigned long diffms;
4242         u32 count;
4243
4244         assert_spin_locked(&mchdev_lock);
4245
4246         getrawmonotonic(&now);
4247         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
4248
4249         /* Don't divide by 0 */
4250         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4251         if (!diffms)
4252                 return;
4253
4254         count = I915_READ(GFXEC);
4255
4256         if (count < dev_priv->ips.last_count2) {
4257                 diff = ~0UL - dev_priv->ips.last_count2;
4258                 diff += count;
4259         } else {
4260                 diff = count - dev_priv->ips.last_count2;
4261         }
4262
4263         dev_priv->ips.last_count2 = count;
4264         dev_priv->ips.last_time2 = now;
4265
4266         /* More magic constants... */
4267         diff = diff * 1181;
4268         diff = div_u64(diff, diffms * 10);
4269         dev_priv->ips.gfx_power = diff;
4270 }
4271
4272 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4273 {
4274         if (dev_priv->info->gen != 5)
4275                 return;
4276
4277         spin_lock_irq(&mchdev_lock);
4278
4279         __i915_update_gfx_val(dev_priv);
4280
4281         spin_unlock_irq(&mchdev_lock);
4282 }
4283
4284 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
4285 {
4286         unsigned long t, corr, state1, corr2, state2;
4287         u32 pxvid, ext_v;
4288
4289         assert_spin_locked(&mchdev_lock);
4290
4291         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
4292         pxvid = (pxvid >> 24) & 0x7f;
4293         ext_v = pvid_to_extvid(dev_priv, pxvid);
4294
4295         state1 = ext_v;
4296
4297         t = i915_mch_val(dev_priv);
4298
4299         /* Revel in the empirically derived constants */
4300
4301         /* Correction factor in 1/100000 units */
4302         if (t > 80)
4303                 corr = ((t * 2349) + 135940);
4304         else if (t >= 50)
4305                 corr = ((t * 964) + 29317);
4306         else /* < 50 */
4307                 corr = ((t * 301) + 1004);
4308
4309         corr = corr * ((150142 * state1) / 10000 - 78642);
4310         corr /= 100000;
4311         corr2 = (corr * dev_priv->ips.corr);
4312
4313         state2 = (corr2 * state1) / 10000;
4314         state2 /= 100; /* convert to mW */
4315
4316         __i915_update_gfx_val(dev_priv);
4317
4318         return dev_priv->ips.gfx_power + state2;
4319 }
4320
4321 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4322 {
4323         unsigned long val;
4324
4325         if (dev_priv->info->gen != 5)
4326                 return 0;
4327
4328         spin_lock_irq(&mchdev_lock);
4329
4330         val = __i915_gfx_val(dev_priv);
4331
4332         spin_unlock_irq(&mchdev_lock);
4333
4334         return val;
4335 }
4336
4337 /**
4338  * i915_read_mch_val - return value for IPS use
4339  *
4340  * Calculate and return a value for the IPS driver to use when deciding whether
4341  * we have thermal and power headroom to increase CPU or GPU power budget.
4342  */
4343 unsigned long i915_read_mch_val(void)
4344 {
4345         struct drm_i915_private *dev_priv;
4346         unsigned long chipset_val, graphics_val, ret = 0;
4347
4348         spin_lock_irq(&mchdev_lock);
4349         if (!i915_mch_dev)
4350                 goto out_unlock;
4351         dev_priv = i915_mch_dev;
4352
4353         chipset_val = __i915_chipset_val(dev_priv);
4354         graphics_val = __i915_gfx_val(dev_priv);
4355
4356         ret = chipset_val + graphics_val;
4357
4358 out_unlock:
4359         spin_unlock_irq(&mchdev_lock);
4360
4361         return ret;
4362 }
4363 EXPORT_SYMBOL_GPL(i915_read_mch_val);
4364
4365 /**
4366  * i915_gpu_raise - raise GPU frequency limit
4367  *
4368  * Raise the limit; IPS indicates we have thermal headroom.
4369  */
4370 bool i915_gpu_raise(void)
4371 {
4372         struct drm_i915_private *dev_priv;
4373         bool ret = true;
4374
4375         spin_lock_irq(&mchdev_lock);
4376         if (!i915_mch_dev) {
4377                 ret = false;
4378                 goto out_unlock;
4379         }
4380         dev_priv = i915_mch_dev;
4381
4382         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4383                 dev_priv->ips.max_delay--;
4384
4385 out_unlock:
4386         spin_unlock_irq(&mchdev_lock);
4387
4388         return ret;
4389 }
4390 EXPORT_SYMBOL_GPL(i915_gpu_raise);
4391
4392 /**
4393  * i915_gpu_lower - lower GPU frequency limit
4394  *
4395  * IPS indicates we're close to a thermal limit, so throttle back the GPU
4396  * frequency maximum.
4397  */
4398 bool i915_gpu_lower(void)
4399 {
4400         struct drm_i915_private *dev_priv;
4401         bool ret = true;
4402
4403         spin_lock_irq(&mchdev_lock);
4404         if (!i915_mch_dev) {
4405                 ret = false;
4406                 goto out_unlock;
4407         }
4408         dev_priv = i915_mch_dev;
4409
4410         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4411                 dev_priv->ips.max_delay++;
4412
4413 out_unlock:
4414         spin_unlock_irq(&mchdev_lock);
4415
4416         return ret;
4417 }
4418 EXPORT_SYMBOL_GPL(i915_gpu_lower);
4419
4420 /**
4421  * i915_gpu_busy - indicate GPU business to IPS
4422  *
4423  * Tell the IPS driver whether or not the GPU is busy.
4424  */
4425 bool i915_gpu_busy(void)
4426 {
4427         struct drm_i915_private *dev_priv;
4428         struct intel_ring_buffer *ring;
4429         bool ret = false;
4430         int i;
4431
4432         spin_lock_irq(&mchdev_lock);
4433         if (!i915_mch_dev)
4434                 goto out_unlock;
4435         dev_priv = i915_mch_dev;
4436
4437         for_each_ring(ring, dev_priv, i)
4438                 ret |= !list_empty(&ring->request_list);
4439
4440 out_unlock:
4441         spin_unlock_irq(&mchdev_lock);
4442
4443         return ret;
4444 }
4445 EXPORT_SYMBOL_GPL(i915_gpu_busy);
4446
4447 /**
4448  * i915_gpu_turbo_disable - disable graphics turbo
4449  *
4450  * Disable graphics turbo by resetting the max frequency and setting the
4451  * current frequency to the default.
4452  */
4453 bool i915_gpu_turbo_disable(void)
4454 {
4455         struct drm_i915_private *dev_priv;
4456         bool ret = true;
4457
4458         spin_lock_irq(&mchdev_lock);
4459         if (!i915_mch_dev) {
4460                 ret = false;
4461                 goto out_unlock;
4462         }
4463         dev_priv = i915_mch_dev;
4464
4465         dev_priv->ips.max_delay = dev_priv->ips.fstart;
4466
4467         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
4468                 ret = false;
4469
4470 out_unlock:
4471         spin_unlock_irq(&mchdev_lock);
4472
4473         return ret;
4474 }
4475 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4476
4477 /**
4478  * Tells the intel_ips driver that the i915 driver is now loaded, if
4479  * IPS got loaded first.
4480  *
4481  * This awkward dance is so that neither module has to depend on the
4482  * other in order for IPS to do the appropriate communication of
4483  * GPU turbo limits to i915.
4484  */
4485 static void
4486 ips_ping_for_i915_load(void)
4487 {
4488         void (*link)(void);
4489
4490         link = symbol_get(ips_link_to_i915_driver);
4491         if (link) {
4492                 link();
4493                 symbol_put(ips_link_to_i915_driver);
4494         }
4495 }
4496
4497 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4498 {
4499         /* We only register the i915 ips part with intel-ips once everything is
4500          * set up, to avoid intel-ips sneaking in and reading bogus values. */
4501         spin_lock_irq(&mchdev_lock);
4502         i915_mch_dev = dev_priv;
4503         spin_unlock_irq(&mchdev_lock);
4504
4505         ips_ping_for_i915_load();
4506 }
4507
4508 void intel_gpu_ips_teardown(void)
4509 {
4510         spin_lock_irq(&mchdev_lock);
4511         i915_mch_dev = NULL;
4512         spin_unlock_irq(&mchdev_lock);
4513 }
4514 static void intel_init_emon(struct drm_device *dev)
4515 {
4516         struct drm_i915_private *dev_priv = dev->dev_private;
4517         u32 lcfuse;
4518         u8 pxw[16];
4519         int i;
4520
4521         /* Disable to program */
4522         I915_WRITE(ECR, 0);
4523         POSTING_READ(ECR);
4524
4525         /* Program energy weights for various events */
4526         I915_WRITE(SDEW, 0x15040d00);
4527         I915_WRITE(CSIEW0, 0x007f0000);
4528         I915_WRITE(CSIEW1, 0x1e220004);
4529         I915_WRITE(CSIEW2, 0x04000004);
4530
4531         for (i = 0; i < 5; i++)
4532                 I915_WRITE(PEW + (i * 4), 0);
4533         for (i = 0; i < 3; i++)
4534                 I915_WRITE(DEW + (i * 4), 0);
4535
4536         /* Program P-state weights to account for frequency power adjustment */
4537         for (i = 0; i < 16; i++) {
4538                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4539                 unsigned long freq = intel_pxfreq(pxvidfreq);
4540                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4541                         PXVFREQ_PX_SHIFT;
4542                 unsigned long val;
4543
4544                 val = vid * vid;
4545                 val *= (freq / 1000);
4546                 val *= 255;
4547                 val /= (127*127*900);
4548                 if (val > 0xff)
4549                         DRM_ERROR("bad pxval: %ld\n", val);
4550                 pxw[i] = val;
4551         }
4552         /* Render standby states get 0 weight */
4553         pxw[14] = 0;
4554         pxw[15] = 0;
4555
4556         for (i = 0; i < 4; i++) {
4557                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4558                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4559                 I915_WRITE(PXW + (i * 4), val);
4560         }
4561
4562         /* Adjust magic regs to magic values (more experimental results) */
4563         I915_WRITE(OGW0, 0);
4564         I915_WRITE(OGW1, 0);
4565         I915_WRITE(EG0, 0x00007f00);
4566         I915_WRITE(EG1, 0x0000000e);
4567         I915_WRITE(EG2, 0x000e0000);
4568         I915_WRITE(EG3, 0x68000300);
4569         I915_WRITE(EG4, 0x42000000);
4570         I915_WRITE(EG5, 0x00140031);
4571         I915_WRITE(EG6, 0);
4572         I915_WRITE(EG7, 0);
4573
4574         for (i = 0; i < 8; i++)
4575                 I915_WRITE(PXWL + (i * 4), 0);
4576
4577         /* Enable PMON + select events */
4578         I915_WRITE(ECR, 0x80000019);
4579
4580         lcfuse = I915_READ(LCFUSE02);
4581
4582         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
4583 }
4584
4585 void intel_disable_gt_powersave(struct drm_device *dev)
4586 {
4587         struct drm_i915_private *dev_priv = dev->dev_private;
4588
4589         /* Interrupts should be disabled already to avoid re-arming. */
4590         WARN_ON(dev->irq_enabled);
4591
4592         if (IS_IRONLAKE_M(dev)) {
4593                 ironlake_disable_drps(dev);
4594                 ironlake_disable_rc6(dev);
4595         } else if (INTEL_INFO(dev)->gen >= 6) {
4596                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4597                 cancel_work_sync(&dev_priv->rps.work);
4598                 if (IS_VALLEYVIEW(dev))
4599                         cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4600                 mutex_lock(&dev_priv->rps.hw_lock);
4601                 if (IS_VALLEYVIEW(dev))
4602                         valleyview_disable_rps(dev);
4603                 else
4604                         gen6_disable_rps(dev);
4605                 mutex_unlock(&dev_priv->rps.hw_lock);
4606         }
4607 }
4608
4609 static void intel_gen6_powersave_work(struct work_struct *work)
4610 {
4611         struct drm_i915_private *dev_priv =
4612                 container_of(work, struct drm_i915_private,
4613                              rps.delayed_resume_work.work);
4614         struct drm_device *dev = dev_priv->dev;
4615
4616         mutex_lock(&dev_priv->rps.hw_lock);
4617
4618         if (IS_VALLEYVIEW(dev)) {
4619                 valleyview_enable_rps(dev);
4620         } else {
4621                 gen6_enable_rps(dev);
4622                 gen6_update_ring_freq(dev);
4623         }
4624         mutex_unlock(&dev_priv->rps.hw_lock);
4625 }
4626
4627 void intel_enable_gt_powersave(struct drm_device *dev)
4628 {
4629         struct drm_i915_private *dev_priv = dev->dev_private;
4630
4631         if (IS_IRONLAKE_M(dev)) {
4632                 ironlake_enable_drps(dev);
4633                 ironlake_enable_rc6(dev);
4634                 intel_init_emon(dev);
4635         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
4636                 /*
4637                  * PCU communication is slow and this doesn't need to be
4638                  * done at any specific time, so do this out of our fast path
4639                  * to make resume and init faster.
4640                  */
4641                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4642                                       round_jiffies_up_relative(HZ));
4643         }
4644 }
4645
4646 static void ibx_init_clock_gating(struct drm_device *dev)
4647 {
4648         struct drm_i915_private *dev_priv = dev->dev_private;
4649
4650         /*
4651          * On Ibex Peak and Cougar Point, we need to disable clock
4652          * gating for the panel power sequencer or it will fail to
4653          * start up when no ports are active.
4654          */
4655         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4656 }
4657
4658 static void g4x_disable_trickle_feed(struct drm_device *dev)
4659 {
4660         struct drm_i915_private *dev_priv = dev->dev_private;
4661         int pipe;
4662
4663         for_each_pipe(pipe) {
4664                 I915_WRITE(DSPCNTR(pipe),
4665                            I915_READ(DSPCNTR(pipe)) |
4666                            DISPPLANE_TRICKLE_FEED_DISABLE);
4667                 intel_flush_display_plane(dev_priv, pipe);
4668         }
4669 }
4670
4671 static void ironlake_init_clock_gating(struct drm_device *dev)
4672 {
4673         struct drm_i915_private *dev_priv = dev->dev_private;
4674         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4675
4676         /*
4677          * Required for FBC
4678          * WaFbcDisableDpfcClockGating:ilk
4679          */
4680         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4681                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4682                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
4683
4684         I915_WRITE(PCH_3DCGDIS0,
4685                    MARIUNIT_CLOCK_GATE_DISABLE |
4686                    SVSMUNIT_CLOCK_GATE_DISABLE);
4687         I915_WRITE(PCH_3DCGDIS1,
4688                    VFMUNIT_CLOCK_GATE_DISABLE);
4689
4690         /*
4691          * According to the spec the following bits should be set in
4692          * order to enable memory self-refresh
4693          * The bit 22/21 of 0x42004
4694          * The bit 5 of 0x42020
4695          * The bit 15 of 0x45000
4696          */
4697         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4698                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
4699                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4700         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
4701         I915_WRITE(DISP_ARB_CTL,
4702                    (I915_READ(DISP_ARB_CTL) |
4703                     DISP_FBC_WM_DIS));
4704         I915_WRITE(WM3_LP_ILK, 0);
4705         I915_WRITE(WM2_LP_ILK, 0);
4706         I915_WRITE(WM1_LP_ILK, 0);
4707
4708         /*
4709          * Based on the document from hardware guys the following bits
4710          * should be set unconditionally in order to enable FBC.
4711          * The bit 22 of 0x42000
4712          * The bit 22 of 0x42004
4713          * The bit 7,8,9 of 0x42020.
4714          */
4715         if (IS_IRONLAKE_M(dev)) {
4716                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
4717                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4718                            I915_READ(ILK_DISPLAY_CHICKEN1) |
4719                            ILK_FBCQ_DIS);
4720                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4721                            I915_READ(ILK_DISPLAY_CHICKEN2) |
4722                            ILK_DPARB_GATE);
4723         }
4724
4725         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4726
4727         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4728                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4729                    ILK_ELPIN_409_SELECT);
4730         I915_WRITE(_3D_CHICKEN2,
4731                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4732                    _3D_CHICKEN2_WM_READ_PIPELINED);
4733
4734         /* WaDisableRenderCachePipelinedFlush:ilk */
4735         I915_WRITE(CACHE_MODE_0,
4736                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4737
4738         g4x_disable_trickle_feed(dev);
4739
4740         ibx_init_clock_gating(dev);
4741 }
4742
4743 static void cpt_init_clock_gating(struct drm_device *dev)
4744 {
4745         struct drm_i915_private *dev_priv = dev->dev_private;
4746         int pipe;
4747         uint32_t val;
4748
4749         /*
4750          * On Ibex Peak and Cougar Point, we need to disable clock
4751          * gating for the panel power sequencer or it will fail to
4752          * start up when no ports are active.
4753          */
4754         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4755         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4756                    DPLS_EDP_PPS_FIX_DIS);
4757         /* The below fixes the weird display corruption, a few pixels shifted
4758          * downward, on (only) LVDS of some HP laptops with IVY.
4759          */
4760         for_each_pipe(pipe) {
4761                 val = I915_READ(TRANS_CHICKEN2(pipe));
4762                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4763                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4764                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
4765                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
4766                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4767                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4768                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
4769                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4770         }
4771         /* WADP0ClockGatingDisable */
4772         for_each_pipe(pipe) {
4773                 I915_WRITE(TRANS_CHICKEN1(pipe),
4774                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4775         }
4776 }
4777
4778 static void gen6_check_mch_setup(struct drm_device *dev)
4779 {
4780         struct drm_i915_private *dev_priv = dev->dev_private;
4781         uint32_t tmp;
4782
4783         tmp = I915_READ(MCH_SSKPD);
4784         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4785                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4786                 DRM_INFO("This can cause pipe underruns and display issues.\n");
4787                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4788         }
4789 }
4790
4791 static void gen6_init_clock_gating(struct drm_device *dev)
4792 {
4793         struct drm_i915_private *dev_priv = dev->dev_private;
4794         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
4795
4796         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4797
4798         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4799                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4800                    ILK_ELPIN_409_SELECT);
4801
4802         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4803         I915_WRITE(_3D_CHICKEN,
4804                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4805
4806         /* WaSetupGtModeTdRowDispatch:snb */
4807         if (IS_SNB_GT1(dev))
4808                 I915_WRITE(GEN6_GT_MODE,
4809                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4810
4811         I915_WRITE(WM3_LP_ILK, 0);
4812         I915_WRITE(WM2_LP_ILK, 0);
4813         I915_WRITE(WM1_LP_ILK, 0);
4814
4815         I915_WRITE(CACHE_MODE_0,
4816                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
4817
4818         I915_WRITE(GEN6_UCGCTL1,
4819                    I915_READ(GEN6_UCGCTL1) |
4820                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4821                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4822
4823         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4824          * gating disable must be set.  Failure to set it results in
4825          * flickering pixels due to Z write ordering failures after
4826          * some amount of runtime in the Mesa "fire" demo, and Unigine
4827          * Sanctuary and Tropics, and apparently anything else with
4828          * alpha test or pixel discard.
4829          *
4830          * According to the spec, bit 11 (RCCUNIT) must also be set,
4831          * but we didn't debug actual testcases to find it out.
4832          *
4833          * Also apply WaDisableVDSUnitClockGating:snb and
4834          * WaDisableRCPBUnitClockGating:snb.
4835          */
4836         I915_WRITE(GEN6_UCGCTL2,
4837                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4838                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4839                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4840
4841         /* Bspec says we need to always set all mask bits. */
4842         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4843                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
4844
4845         /*
4846          * According to the spec the following bits should be
4847          * set in order to enable memory self-refresh and fbc:
4848          * The bit21 and bit22 of 0x42000
4849          * The bit21 and bit22 of 0x42004
4850          * The bit5 and bit7 of 0x42020
4851          * The bit14 of 0x70180
4852          * The bit14 of 0x71180
4853          *
4854          * WaFbcAsynchFlipDisableFbcQueue:snb
4855          */
4856         I915_WRITE(ILK_DISPLAY_CHICKEN1,
4857                    I915_READ(ILK_DISPLAY_CHICKEN1) |
4858                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4859         I915_WRITE(ILK_DISPLAY_CHICKEN2,
4860                    I915_READ(ILK_DISPLAY_CHICKEN2) |
4861                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
4862         I915_WRITE(ILK_DSPCLK_GATE_D,
4863                    I915_READ(ILK_DSPCLK_GATE_D) |
4864                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
4865                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
4866
4867         /* WaMbcDriverBootEnable:snb */
4868         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4869                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4870
4871         g4x_disable_trickle_feed(dev);
4872
4873         /* The default value should be 0x200 according to docs, but the two
4874          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4875         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4876         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
4877
4878         cpt_init_clock_gating(dev);
4879
4880         gen6_check_mch_setup(dev);
4881 }
4882
4883 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4884 {
4885         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4886
4887         reg &= ~GEN7_FF_SCHED_MASK;
4888         reg |= GEN7_FF_TS_SCHED_HW;
4889         reg |= GEN7_FF_VS_SCHED_HW;
4890         reg |= GEN7_FF_DS_SCHED_HW;
4891
4892         if (IS_HASWELL(dev_priv->dev))
4893                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4894
4895         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4896 }
4897
4898 static void lpt_init_clock_gating(struct drm_device *dev)
4899 {
4900         struct drm_i915_private *dev_priv = dev->dev_private;
4901
4902         /*
4903          * TODO: this bit should only be enabled when really needed, then
4904          * disabled when not needed anymore in order to save power.
4905          */
4906         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4907                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4908                            I915_READ(SOUTH_DSPCLK_GATE_D) |
4909                            PCH_LP_PARTITION_LEVEL_DISABLE);
4910
4911         /* WADPOClockGatingDisable:hsw */
4912         I915_WRITE(_TRANSA_CHICKEN1,
4913                    I915_READ(_TRANSA_CHICKEN1) |
4914                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4915 }
4916
4917 static void lpt_suspend_hw(struct drm_device *dev)
4918 {
4919         struct drm_i915_private *dev_priv = dev->dev_private;
4920
4921         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4922                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4923
4924                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4925                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4926         }
4927 }
4928
4929 static void haswell_init_clock_gating(struct drm_device *dev)
4930 {
4931         struct drm_i915_private *dev_priv = dev->dev_private;
4932
4933         I915_WRITE(WM3_LP_ILK, 0);
4934         I915_WRITE(WM2_LP_ILK, 0);
4935         I915_WRITE(WM1_LP_ILK, 0);
4936
4937         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4938          * This implements the WaDisableRCZUnitClockGating:hsw workaround.
4939          */
4940         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4941
4942         /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
4943         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4944                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4945
4946         /* WaApplyL3ControlAndL3ChickenMode:hsw */
4947         I915_WRITE(GEN7_L3CNTLREG1,
4948                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4949         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4950                         GEN7_WA_L3_CHICKEN_MODE);
4951
4952         /* This is required by WaCatErrorRejectionIssue:hsw */
4953         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4954                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4955                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4956
4957         g4x_disable_trickle_feed(dev);
4958
4959         /* WaVSRefCountFullforceMissDisable:hsw */
4960         gen7_setup_fixed_func_scheduler(dev_priv);
4961
4962         /* WaDisable4x2SubspanOptimization:hsw */
4963         I915_WRITE(CACHE_MODE_1,
4964                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4965
4966         /* WaMbcDriverBootEnable:hsw */
4967         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4968                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4969
4970         /* WaSwitchSolVfFArbitrationPriority:hsw */
4971         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4972
4973         /* WaRsPkgCStateDisplayPMReq:hsw */
4974         I915_WRITE(CHICKEN_PAR1_1,
4975                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
4976
4977         lpt_init_clock_gating(dev);
4978 }
4979
4980 static void ivybridge_init_clock_gating(struct drm_device *dev)
4981 {
4982         struct drm_i915_private *dev_priv = dev->dev_private;
4983         uint32_t snpcr;
4984
4985         I915_WRITE(WM3_LP_ILK, 0);
4986         I915_WRITE(WM2_LP_ILK, 0);
4987         I915_WRITE(WM1_LP_ILK, 0);
4988
4989         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4990
4991         /* WaDisableEarlyCull:ivb */
4992         I915_WRITE(_3D_CHICKEN3,
4993                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4994
4995         /* WaDisableBackToBackFlipFix:ivb */
4996         I915_WRITE(IVB_CHICKEN3,
4997                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4998                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4999
5000         /* WaDisablePSDDualDispatchEnable:ivb */
5001         if (IS_IVB_GT1(dev))
5002                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5003                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5004         else
5005                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5006                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5007
5008         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5009         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5010                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5011
5012         /* WaApplyL3ControlAndL3ChickenMode:ivb */
5013         I915_WRITE(GEN7_L3CNTLREG1,
5014                         GEN7_WA_FOR_GEN7_L3_CONTROL);
5015         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5016                    GEN7_WA_L3_CHICKEN_MODE);
5017         if (IS_IVB_GT1(dev))
5018                 I915_WRITE(GEN7_ROW_CHICKEN2,
5019                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5020         else
5021                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5022                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5023
5024
5025         /* WaForceL3Serialization:ivb */
5026         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5027                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5028
5029         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5030          * gating disable must be set.  Failure to set it results in
5031          * flickering pixels due to Z write ordering failures after
5032          * some amount of runtime in the Mesa "fire" demo, and Unigine
5033          * Sanctuary and Tropics, and apparently anything else with
5034          * alpha test or pixel discard.
5035          *
5036          * According to the spec, bit 11 (RCCUNIT) must also be set,
5037          * but we didn't debug actual testcases to find it out.
5038          *
5039          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5040          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5041          */
5042         I915_WRITE(GEN6_UCGCTL2,
5043                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5044                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5045
5046         /* This is required by WaCatErrorRejectionIssue:ivb */
5047         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5048                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5049                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5050
5051         g4x_disable_trickle_feed(dev);
5052
5053         /* WaMbcDriverBootEnable:ivb */
5054         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
5055                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
5056
5057         /* WaVSRefCountFullforceMissDisable:ivb */
5058         gen7_setup_fixed_func_scheduler(dev_priv);
5059
5060         /* WaDisable4x2SubspanOptimization:ivb */
5061         I915_WRITE(CACHE_MODE_1,
5062                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5063
5064         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5065         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5066         snpcr |= GEN6_MBC_SNPCR_MED;
5067         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5068
5069         if (!HAS_PCH_NOP(dev))
5070                 cpt_init_clock_gating(dev);
5071
5072         gen6_check_mch_setup(dev);
5073 }
5074
5075 static void valleyview_init_clock_gating(struct drm_device *dev)
5076 {
5077         struct drm_i915_private *dev_priv = dev->dev_private;
5078
5079         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5080
5081         /* WaDisableEarlyCull:vlv */
5082         I915_WRITE(_3D_CHICKEN3,
5083                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5084
5085         /* WaDisableBackToBackFlipFix:vlv */
5086         I915_WRITE(IVB_CHICKEN3,
5087                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5088                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
5089
5090         /* WaDisablePSDDualDispatchEnable:vlv */
5091         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5092                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5093                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5094
5095         /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
5096         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5097                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5098
5099         /* WaApplyL3ControlAndL3ChickenMode:vlv */
5100         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
5101         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5102
5103         /* WaForceL3Serialization:vlv */
5104         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5105                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5106
5107         /* WaDisableDopClockGating:vlv */
5108         I915_WRITE(GEN7_ROW_CHICKEN2,
5109                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5110
5111         /* This is required by WaCatErrorRejectionIssue:vlv */
5112         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5113                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5114                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5115
5116         /* WaMbcDriverBootEnable:vlv */
5117         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
5118                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
5119
5120
5121         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5122          * gating disable must be set.  Failure to set it results in
5123          * flickering pixels due to Z write ordering failures after
5124          * some amount of runtime in the Mesa "fire" demo, and Unigine
5125          * Sanctuary and Tropics, and apparently anything else with
5126          * alpha test or pixel discard.
5127          *
5128          * According to the spec, bit 11 (RCCUNIT) must also be set,
5129          * but we didn't debug actual testcases to find it out.
5130          *
5131          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5132          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5133          *
5134          * Also apply WaDisableVDSUnitClockGating:vlv and
5135          * WaDisableRCPBUnitClockGating:vlv.
5136          */
5137         I915_WRITE(GEN6_UCGCTL2,
5138                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
5139                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
5140                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5141                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5142                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5143
5144         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5145
5146         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
5147
5148         I915_WRITE(CACHE_MODE_1,
5149                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
5150
5151         /*
5152          * WaDisableVLVClockGating_VBIIssue:vlv
5153          * Disable clock gating on th GCFG unit to prevent a delay
5154          * in the reporting of vblank events.
5155          */
5156         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5157
5158         /* Conservative clock gating settings for now */
5159         I915_WRITE(0x9400, 0xffffffff);
5160         I915_WRITE(0x9404, 0xffffffff);
5161         I915_WRITE(0x9408, 0xffffffff);
5162         I915_WRITE(0x940c, 0xffffffff);
5163         I915_WRITE(0x9410, 0xffffffff);
5164         I915_WRITE(0x9414, 0xffffffff);
5165         I915_WRITE(0x9418, 0xffffffff);
5166 }
5167
5168 static void g4x_init_clock_gating(struct drm_device *dev)
5169 {
5170         struct drm_i915_private *dev_priv = dev->dev_private;
5171         uint32_t dspclk_gate;
5172
5173         I915_WRITE(RENCLK_GATE_D1, 0);
5174         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5175                    GS_UNIT_CLOCK_GATE_DISABLE |
5176                    CL_UNIT_CLOCK_GATE_DISABLE);
5177         I915_WRITE(RAMCLK_GATE_D, 0);
5178         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5179                 OVRUNIT_CLOCK_GATE_DISABLE |
5180                 OVCUNIT_CLOCK_GATE_DISABLE;
5181         if (IS_GM45(dev))
5182                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5183         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5184
5185         /* WaDisableRenderCachePipelinedFlush */
5186         I915_WRITE(CACHE_MODE_0,
5187                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5188
5189         g4x_disable_trickle_feed(dev);
5190 }
5191
5192 static void crestline_init_clock_gating(struct drm_device *dev)
5193 {
5194         struct drm_i915_private *dev_priv = dev->dev_private;
5195
5196         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5197         I915_WRITE(RENCLK_GATE_D2, 0);
5198         I915_WRITE(DSPCLK_GATE_D, 0);
5199         I915_WRITE(RAMCLK_GATE_D, 0);
5200         I915_WRITE16(DEUC, 0);
5201         I915_WRITE(MI_ARB_STATE,
5202                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5203 }
5204
5205 static void broadwater_init_clock_gating(struct drm_device *dev)
5206 {
5207         struct drm_i915_private *dev_priv = dev->dev_private;
5208
5209         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5210                    I965_RCC_CLOCK_GATE_DISABLE |
5211                    I965_RCPB_CLOCK_GATE_DISABLE |
5212                    I965_ISC_CLOCK_GATE_DISABLE |
5213                    I965_FBC_CLOCK_GATE_DISABLE);
5214         I915_WRITE(RENCLK_GATE_D2, 0);
5215         I915_WRITE(MI_ARB_STATE,
5216                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
5217 }
5218
5219 static void gen3_init_clock_gating(struct drm_device *dev)
5220 {
5221         struct drm_i915_private *dev_priv = dev->dev_private;
5222         u32 dstate = I915_READ(D_STATE);
5223
5224         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5225                 DSTATE_DOT_CLOCK_GATING;
5226         I915_WRITE(D_STATE, dstate);
5227
5228         if (IS_PINEVIEW(dev))
5229                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
5230
5231         /* IIR "flip pending" means done if this bit is set */
5232         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
5233 }
5234
5235 static void i85x_init_clock_gating(struct drm_device *dev)
5236 {
5237         struct drm_i915_private *dev_priv = dev->dev_private;
5238
5239         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5240 }
5241
5242 static void i830_init_clock_gating(struct drm_device *dev)
5243 {
5244         struct drm_i915_private *dev_priv = dev->dev_private;
5245
5246         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5247 }
5248
5249 void intel_init_clock_gating(struct drm_device *dev)
5250 {
5251         struct drm_i915_private *dev_priv = dev->dev_private;
5252
5253         dev_priv->display.init_clock_gating(dev);
5254 }
5255
5256 void intel_suspend_hw(struct drm_device *dev)
5257 {
5258         if (HAS_PCH_LPT(dev))
5259                 lpt_suspend_hw(dev);
5260 }
5261
5262 /**
5263  * We should only use the power well if we explicitly asked the hardware to
5264  * enable it, so check if it's enabled and also check if we've requested it to
5265  * be enabled.
5266  */
5267 bool intel_display_power_enabled(struct drm_device *dev,
5268                                  enum intel_display_power_domain domain)
5269 {
5270         struct drm_i915_private *dev_priv = dev->dev_private;
5271
5272         if (!HAS_POWER_WELL(dev))
5273                 return true;
5274
5275         switch (domain) {
5276         case POWER_DOMAIN_PIPE_A:
5277         case POWER_DOMAIN_TRANSCODER_EDP:
5278                 return true;
5279         case POWER_DOMAIN_PIPE_B:
5280         case POWER_DOMAIN_PIPE_C:
5281         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5282         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5283         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5284         case POWER_DOMAIN_TRANSCODER_A:
5285         case POWER_DOMAIN_TRANSCODER_B:
5286         case POWER_DOMAIN_TRANSCODER_C:
5287                 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5288                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5289         default:
5290                 BUG();
5291         }
5292 }
5293
5294 static void __intel_set_power_well(struct drm_device *dev, bool enable)
5295 {
5296         struct drm_i915_private *dev_priv = dev->dev_private;
5297         bool is_enabled, enable_requested;
5298         uint32_t tmp;
5299
5300         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5301         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5302         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
5303
5304         if (enable) {
5305                 if (!enable_requested)
5306                         I915_WRITE(HSW_PWR_WELL_DRIVER,
5307                                    HSW_PWR_WELL_ENABLE_REQUEST);
5308
5309                 if (!is_enabled) {
5310                         DRM_DEBUG_KMS("Enabling power well\n");
5311                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5312                                       HSW_PWR_WELL_STATE_ENABLED), 20))
5313                                 DRM_ERROR("Timeout enabling power well\n");
5314                 }
5315         } else {
5316                 if (enable_requested) {
5317                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5318                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
5319                 }
5320         }
5321 }
5322
5323 static struct i915_power_well *hsw_pwr;
5324
5325 /* Display audio driver power well request */
5326 void i915_request_power_well(void)
5327 {
5328         if (WARN_ON(!hsw_pwr))
5329                 return;
5330
5331         spin_lock_irq(&hsw_pwr->lock);
5332         if (!hsw_pwr->count++ &&
5333                         !hsw_pwr->i915_request)
5334                 __intel_set_power_well(hsw_pwr->device, true);
5335         spin_unlock_irq(&hsw_pwr->lock);
5336 }
5337 EXPORT_SYMBOL_GPL(i915_request_power_well);
5338
5339 /* Display audio driver power well release */
5340 void i915_release_power_well(void)
5341 {
5342         if (WARN_ON(!hsw_pwr))
5343                 return;
5344
5345         spin_lock_irq(&hsw_pwr->lock);
5346         WARN_ON(!hsw_pwr->count);
5347         if (!--hsw_pwr->count &&
5348                        !hsw_pwr->i915_request)
5349                 __intel_set_power_well(hsw_pwr->device, false);
5350         spin_unlock_irq(&hsw_pwr->lock);
5351 }
5352 EXPORT_SYMBOL_GPL(i915_release_power_well);
5353
5354 int i915_init_power_well(struct drm_device *dev)
5355 {
5356         struct drm_i915_private *dev_priv = dev->dev_private;
5357
5358         hsw_pwr = &dev_priv->power_well;
5359
5360         hsw_pwr->device = dev;
5361         spin_lock_init(&hsw_pwr->lock);
5362         hsw_pwr->count = 0;
5363
5364         return 0;
5365 }
5366
5367 void i915_remove_power_well(struct drm_device *dev)
5368 {
5369         hsw_pwr = NULL;
5370 }
5371
5372 void intel_set_power_well(struct drm_device *dev, bool enable)
5373 {
5374         struct drm_i915_private *dev_priv = dev->dev_private;
5375         struct i915_power_well *power_well = &dev_priv->power_well;
5376
5377         if (!HAS_POWER_WELL(dev))
5378                 return;
5379
5380         if (!i915_disable_power_well && !enable)
5381                 return;
5382
5383         spin_lock_irq(&power_well->lock);
5384         power_well->i915_request = enable;
5385
5386         /* only reject "disable" power well request */
5387         if (power_well->count && !enable) {
5388                 spin_unlock_irq(&power_well->lock);
5389                 return;
5390         }
5391
5392         __intel_set_power_well(dev, enable);
5393         spin_unlock_irq(&power_well->lock);
5394 }
5395
5396 /*
5397  * Starting with Haswell, we have a "Power Down Well" that can be turned off
5398  * when not needed anymore. We have 4 registers that can request the power well
5399  * to be enabled, and it will only be disabled if none of the registers is
5400  * requesting it to be enabled.
5401  */
5402 void intel_init_power_well(struct drm_device *dev)
5403 {
5404         struct drm_i915_private *dev_priv = dev->dev_private;
5405
5406         if (!HAS_POWER_WELL(dev))
5407                 return;
5408
5409         /* For now, we need the power well to be always enabled. */
5410         intel_set_power_well(dev, true);
5411
5412         /* We're taking over the BIOS, so clear any requests made by it since
5413          * the driver is in charge now. */
5414         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
5415                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
5416 }
5417
5418 /* Set up chip specific power management-related functions */
5419 void intel_init_pm(struct drm_device *dev)
5420 {
5421         struct drm_i915_private *dev_priv = dev->dev_private;
5422
5423         if (I915_HAS_FBC(dev)) {
5424                 if (HAS_PCH_SPLIT(dev)) {
5425                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5426                         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
5427                                 dev_priv->display.enable_fbc =
5428                                         gen7_enable_fbc;
5429                         else
5430                                 dev_priv->display.enable_fbc =
5431                                         ironlake_enable_fbc;
5432                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5433                 } else if (IS_GM45(dev)) {
5434                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5435                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5436                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5437                 } else if (IS_CRESTLINE(dev)) {
5438                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5439                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5440                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5441                 }
5442                 /* 855GM needs testing */
5443         }
5444
5445         /* For cxsr */
5446         if (IS_PINEVIEW(dev))
5447                 i915_pineview_get_mem_freq(dev);
5448         else if (IS_GEN5(dev))
5449                 i915_ironlake_get_mem_freq(dev);
5450
5451         /* For FIFO watermark updates */
5452         if (HAS_PCH_SPLIT(dev)) {
5453                 intel_setup_wm_latency(dev);
5454
5455                 if (IS_GEN5(dev)) {
5456                         if (dev_priv->wm.pri_latency[1] &&
5457                             dev_priv->wm.spr_latency[1] &&
5458                             dev_priv->wm.cur_latency[1])
5459                                 dev_priv->display.update_wm = ironlake_update_wm;
5460                         else {
5461                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5462                                               "Disable CxSR\n");
5463                                 dev_priv->display.update_wm = NULL;
5464                         }
5465                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5466                 } else if (IS_GEN6(dev)) {
5467                         if (dev_priv->wm.pri_latency[0] &&
5468                             dev_priv->wm.spr_latency[0] &&
5469                             dev_priv->wm.cur_latency[0]) {
5470                                 dev_priv->display.update_wm = sandybridge_update_wm;
5471                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5472                         } else {
5473                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5474                                               "Disable CxSR\n");
5475                                 dev_priv->display.update_wm = NULL;
5476                         }
5477                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5478                 } else if (IS_IVYBRIDGE(dev)) {
5479                         if (dev_priv->wm.pri_latency[0] &&
5480                             dev_priv->wm.spr_latency[0] &&
5481                             dev_priv->wm.cur_latency[0]) {
5482                                 dev_priv->display.update_wm = ivybridge_update_wm;
5483                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5484                         } else {
5485                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5486                                               "Disable CxSR\n");
5487                                 dev_priv->display.update_wm = NULL;
5488                         }
5489                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
5490                 } else if (IS_HASWELL(dev)) {
5491                         if (dev_priv->wm.pri_latency[0] &&
5492                             dev_priv->wm.spr_latency[0] &&
5493                             dev_priv->wm.cur_latency[0]) {
5494                                 dev_priv->display.update_wm = haswell_update_wm;
5495                                 dev_priv->display.update_sprite_wm =
5496                                         haswell_update_sprite_wm;
5497                         } else {
5498                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
5499                                               "Disable CxSR\n");
5500                                 dev_priv->display.update_wm = NULL;
5501                         }
5502                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
5503                 } else
5504                         dev_priv->display.update_wm = NULL;
5505         } else if (IS_VALLEYVIEW(dev)) {
5506                 dev_priv->display.update_wm = valleyview_update_wm;
5507                 dev_priv->display.init_clock_gating =
5508                         valleyview_init_clock_gating;
5509         } else if (IS_PINEVIEW(dev)) {
5510                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5511                                             dev_priv->is_ddr3,
5512                                             dev_priv->fsb_freq,
5513                                             dev_priv->mem_freq)) {
5514                         DRM_INFO("failed to find known CxSR latency "
5515                                  "(found ddr%s fsb freq %d, mem freq %d), "
5516                                  "disabling CxSR\n",
5517                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
5518                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5519                         /* Disable CxSR and never update its watermark again */
5520                         pineview_disable_cxsr(dev);
5521                         dev_priv->display.update_wm = NULL;
5522                 } else
5523                         dev_priv->display.update_wm = pineview_update_wm;
5524                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5525         } else if (IS_G4X(dev)) {
5526                 dev_priv->display.update_wm = g4x_update_wm;
5527                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5528         } else if (IS_GEN4(dev)) {
5529                 dev_priv->display.update_wm = i965_update_wm;
5530                 if (IS_CRESTLINE(dev))
5531                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5532                 else if (IS_BROADWATER(dev))
5533                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5534         } else if (IS_GEN3(dev)) {
5535                 dev_priv->display.update_wm = i9xx_update_wm;
5536                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5537                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5538         } else if (IS_I865G(dev)) {
5539                 dev_priv->display.update_wm = i830_update_wm;
5540                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5541                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5542         } else if (IS_I85X(dev)) {
5543                 dev_priv->display.update_wm = i9xx_update_wm;
5544                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5545                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5546         } else {
5547                 dev_priv->display.update_wm = i830_update_wm;
5548                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5549                 if (IS_845G(dev))
5550                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5551                 else
5552                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5553         }
5554 }
5555
5556 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5557 {
5558         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5559
5560         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5561                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5562                 return -EAGAIN;
5563         }
5564
5565         I915_WRITE(GEN6_PCODE_DATA, *val);
5566         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5567
5568         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5569                      500)) {
5570                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5571                 return -ETIMEDOUT;
5572         }
5573
5574         *val = I915_READ(GEN6_PCODE_DATA);
5575         I915_WRITE(GEN6_PCODE_DATA, 0);
5576
5577         return 0;
5578 }
5579
5580 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5581 {
5582         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5583
5584         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5585                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5586                 return -EAGAIN;
5587         }
5588
5589         I915_WRITE(GEN6_PCODE_DATA, val);
5590         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5591
5592         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5593                      500)) {
5594                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5595                 return -ETIMEDOUT;
5596         }
5597
5598         I915_WRITE(GEN6_PCODE_DATA, 0);
5599
5600         return 0;
5601 }
5602
5603 int vlv_gpu_freq(int ddr_freq, int val)
5604 {
5605         int mult, base;
5606
5607         switch (ddr_freq) {
5608         case 800:
5609                 mult = 20;
5610                 base = 120;
5611                 break;
5612         case 1066:
5613                 mult = 22;
5614                 base = 133;
5615                 break;
5616         case 1333:
5617                 mult = 21;
5618                 base = 125;
5619                 break;
5620         default:
5621                 return -1;
5622         }
5623
5624         return ((val - 0xbd) * mult) + base;
5625 }
5626
5627 int vlv_freq_opcode(int ddr_freq, int val)
5628 {
5629         int mult, base;
5630
5631         switch (ddr_freq) {
5632         case 800:
5633                 mult = 20;
5634                 base = 120;
5635                 break;
5636         case 1066:
5637                 mult = 22;
5638                 base = 133;
5639                 break;
5640         case 1333:
5641                 mult = 21;
5642                 base = 125;
5643                 break;
5644         default:
5645                 return -1;
5646         }
5647
5648         val /= mult;
5649         val -= base / mult;
5650         val += 0xbd;
5651
5652         if (val > 0xea)
5653                 val = 0xea;
5654
5655         return val;
5656 }
5657
5658 void intel_pm_init(struct drm_device *dev)
5659 {
5660         struct drm_i915_private *dev_priv = dev->dev_private;
5661
5662         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5663                           intel_gen6_powersave_work);
5664 }
5665