drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
  46 #define IS_PCH_eDP(i) ((i)->is_pch_edp)
  47
  48 struct intel_dp {
  49         struct intel_encoder base;
  50         uint32_t output_reg;
  51         uint32_t DP;
  52         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  53         bool has_audio;
  54         int dpms_mode;
  55         uint8_t link_bw;
  56         uint8_t lane_count;
  57         uint8_t dpcd[4];
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61         uint8_t train_set[4];
  62         uint8_t link_status[DP_LINK_STATUS_SIZE];
  63 };
  64
  65 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  66 {
  67         return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base);
  68 }
  69
  70 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
  71 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
  72 static void intel_dp_link_down(struct intel_dp *intel_dp);
  73
  74 void
  75 intel_edp_link_config (struct intel_encoder *intel_encoder,
  76                        int *lane_num, int *link_bw)
  77 {
  78         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
  79
  80         *lane_num = intel_dp->lane_count;
  81         if (intel_dp->link_bw == DP_LINK_BW_1_62)
  82                 *link_bw = 162000;
  83         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
  84                 *link_bw = 270000;
  85 }
  86
  87 static int
  88 intel_dp_max_lane_count(struct intel_dp *intel_dp)
  89 {
  90         int max_lane_count = 4;
  91
  92         if (intel_dp->dpcd[0] >= 0x11) {
  93                 max_lane_count = intel_dp->dpcd[2] & 0x1f;
  94                 switch (max_lane_count) {
  95                 case 1: case 2: case 4:
  96                         break;
  97                 default:
  98                         max_lane_count = 4;
  99                 }
 100         }
 101         return max_lane_count;
 102 }
 103
 104 static int
 105 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 106 {
 107         int max_link_bw = intel_dp->dpcd[1];
 108
 109         switch (max_link_bw) {
 110         case DP_LINK_BW_1_62:
 111         case DP_LINK_BW_2_7:
 112                 break;
 113         default:
 114                 max_link_bw = DP_LINK_BW_1_62;
 115                 break;
 116         }
 117         return max_link_bw;
 118 }
 119
 120 static int
 121 intel_dp_link_clock(uint8_t link_bw)
 122 {
 123         if (link_bw == DP_LINK_BW_2_7)
 124                 return 270000;
 125         else
 126                 return 162000;
 127 }
 128
 129 /* I think this is a fiction */
 130 static int
 131 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 132 {
 133         struct drm_i915_private *dev_priv = dev->dev_private;
 134
 135         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 136                 return (pixel_clock * dev_priv->edp_bpp) / 8;
 137         else
 138                 return pixel_clock * 3;
 139 }
 140
 141 static int
 142 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 143 {
 144         return (max_link_clock * max_lanes * 8) / 10;
 145 }
 146
 147 static int
 148 intel_dp_mode_valid(struct drm_connector *connector,
 149                     struct drm_display_mode *mode)
 150 {
 151         struct drm_encoder *encoder = intel_attached_encoder(connector);
 152         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 153         struct drm_device *dev = connector->dev;
 154         struct drm_i915_private *dev_priv = dev->dev_private;
 155         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 156         int max_lanes = intel_dp_max_lane_count(intel_dp);
 157
 158         if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
 159             dev_priv->panel_fixed_mode) {
 160                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 161                         return MODE_PANEL;
 162
 163                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 164                         return MODE_PANEL;
 165         }
 166
 167         /* only refuse the mode on non eDP since we have seen some wierd eDP panels
 168            which are outside spec tolerances but somehow work by magic */
 169         if (!IS_eDP(intel_dp) &&
 170             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 171              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 172                 return MODE_CLOCK_HIGH;
 173
 174         if (mode->clock < 10000)
 175                 return MODE_CLOCK_LOW;
 176
 177         return MODE_OK;
 178 }
 179
 180 static uint32_t
 181 pack_aux(uint8_t *src, int src_bytes)
 182 {
 183         int     i;
 184         uint32_t v = 0;
 185
 186         if (src_bytes > 4)
 187                 src_bytes = 4;
 188         for (i = 0; i < src_bytes; i++)
 189                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 190         return v;
 191 }
 192
 193 static void
 194 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 195 {
 196         int i;
 197         if (dst_bytes > 4)
 198                 dst_bytes = 4;
 199         for (i = 0; i < dst_bytes; i++)
 200                 dst[i] = src >> ((3-i) * 8);
 201 }
 202
 203 /* hrawclock is 1/4 the FSB frequency */
 204 static int
 205 intel_hrawclk(struct drm_device *dev)
 206 {
 207         struct drm_i915_private *dev_priv = dev->dev_private;
 208         uint32_t clkcfg;
 209
 210         clkcfg = I915_READ(CLKCFG);
 211         switch (clkcfg & CLKCFG_FSB_MASK) {
 212         case CLKCFG_FSB_400:
 213                 return 100;
 214         case CLKCFG_FSB_533:
 215                 return 133;
 216         case CLKCFG_FSB_667:
 217                 return 166;
 218         case CLKCFG_FSB_800:
 219                 return 200;
 220         case CLKCFG_FSB_1067:
 221                 return 266;
 222         case CLKCFG_FSB_1333:
 223                 return 333;
 224         /* these two are just a guess; one of them might be right */
 225         case CLKCFG_FSB_1600:
 226         case CLKCFG_FSB_1600_ALT:
 227                 return 400;
 228         default:
 229                 return 133;
 230         }
 231 }
 232
 233 static int
 234 intel_dp_aux_ch(struct intel_dp *intel_dp,
 235                 uint8_t *send, int send_bytes,
 236                 uint8_t *recv, int recv_size)
 237 {
 238         uint32_t output_reg = intel_dp->output_reg;
 239         struct drm_device *dev = intel_dp->base.enc.dev;
 240         struct drm_i915_private *dev_priv = dev->dev_private;
 241         uint32_t ch_ctl = output_reg + 0x10;
 242         uint32_t ch_data = ch_ctl + 4;
 243         int i;
 244         int recv_bytes;
 245         uint32_t status;
 246         uint32_t aux_clock_divider;
 247         int try, precharge;
 248
 249         /* The clock divider is based off the hrawclk,
 250          * and would like to run at 2MHz. So, take the
 251          * hrawclk value and divide by 2 and use that
 252          *
 253          * Note that PCH attached eDP panels should use a 125MHz input
 254          * clock divider.
 255          */
 256         if (IS_eDP(intel_dp) && !IS_PCH_eDP(intel_dp)) {
 257                 if (IS_GEN6(dev))
 258                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 259                 else
 260                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 261         } else if (HAS_PCH_SPLIT(dev))
 262                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 263         else
 264                 aux_clock_divider = intel_hrawclk(dev) / 2;
 265
 266         if (IS_GEN6(dev))
 267                 precharge = 3;
 268         else
 269                 precharge = 5;
 270
 271         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
 272                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
 273                           I915_READ(ch_ctl));
 274                 return -EBUSY;
 275         }
 276
 277         /* Must try at least 3 times according to DP spec */
 278         for (try = 0; try < 5; try++) {
 279                 /* Load the send data into the aux channel data registers */
 280                 for (i = 0; i < send_bytes; i += 4)
 281                         I915_WRITE(ch_data + i,
 282                                    pack_aux(send + i, send_bytes - i));
 283
 284                 /* Send the command and wait for it to complete */
 285                 I915_WRITE(ch_ctl,
 286                            DP_AUX_CH_CTL_SEND_BUSY |
 287                            DP_AUX_CH_CTL_TIME_OUT_400us |
 288                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 289                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 290                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 291                            DP_AUX_CH_CTL_DONE |
 292                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 293                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 294                 for (;;) {
 295                         status = I915_READ(ch_ctl);
 296                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 297                                 break;
 298                         udelay(100);
 299                 }
 300
 301                 /* Clear done status and any errors */
 302                 I915_WRITE(ch_ctl,
 303                            status |
 304                            DP_AUX_CH_CTL_DONE |
 305                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 306                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 307                 if (status & DP_AUX_CH_CTL_DONE)
 308                         break;
 309         }
 310
 311         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 312                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 313                 return -EBUSY;
 314         }
 315
 316         /* Check for timeout or receive error.
 317          * Timeouts occur when the sink is not connected
 318          */
 319         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 320                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 321                 return -EIO;
 322         }
 323
 324         /* Timeouts occur when the device isn't connected, so they're
 325          * "normal" -- don't fill the kernel log with these */
 326         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 327                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 328                 return -ETIMEDOUT;
 329         }
 330
 331         /* Unload any bytes sent back from the other side */
 332         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 333                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 334         if (recv_bytes > recv_size)
 335                 recv_bytes = recv_size;
 336
 337         for (i = 0; i < recv_bytes; i += 4)
 338                 unpack_aux(I915_READ(ch_data + i),
 339                            recv + i, recv_bytes - i);
 340
 341         return recv_bytes;
 342 }
 343
 344 /* Write data to the aux channel in native mode */
 345 static int
 346 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 347                           uint16_t address, uint8_t *send, int send_bytes)
 348 {
 349         int ret;
 350         uint8_t msg[20];
 351         int msg_bytes;
 352         uint8_t ack;
 353
 354         if (send_bytes > 16)
 355                 return -1;
 356         msg[0] = AUX_NATIVE_WRITE << 4;
 357         msg[1] = address >> 8;
 358         msg[2] = address & 0xff;
 359         msg[3] = send_bytes - 1;
 360         memcpy(&msg[4], send, send_bytes);
 361         msg_bytes = send_bytes + 4;
 362         for (;;) {
 363                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 364                 if (ret < 0)
 365                         return ret;
 366                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 367                         break;
 368                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 369                         udelay(100);
 370                 else
 371                         return -EIO;
 372         }
 373         return send_bytes;
 374 }
 375
 376 /* Write a single byte to the aux channel in native mode */
 377 static int
 378 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 379                             uint16_t address, uint8_t byte)
 380 {
 381         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 382 }
 383
 384 /* read bytes from a native aux channel */
 385 static int
 386 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 387                          uint16_t address, uint8_t *recv, int recv_bytes)
 388 {
 389         uint8_t msg[4];
 390         int msg_bytes;
 391         uint8_t reply[20];
 392         int reply_bytes;
 393         uint8_t ack;
 394         int ret;
 395
 396         msg[0] = AUX_NATIVE_READ << 4;
 397         msg[1] = address >> 8;
 398         msg[2] = address & 0xff;
 399         msg[3] = recv_bytes - 1;
 400
 401         msg_bytes = 4;
 402         reply_bytes = recv_bytes + 1;
 403
 404         for (;;) {
 405                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 406                                       reply, reply_bytes);
 407                 if (ret == 0)
 408                         return -EPROTO;
 409                 if (ret < 0)
 410                         return ret;
 411                 ack = reply[0];
 412                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 413                         memcpy(recv, reply + 1, ret - 1);
 414                         return ret - 1;
 415                 }
 416                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 417                         udelay(100);
 418                 else
 419                         return -EIO;
 420         }
 421 }
 422
 423 static int
 424 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 425                     uint8_t write_byte, uint8_t *read_byte)
 426 {
 427         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 428         struct intel_dp *intel_dp = container_of(adapter,
 429                                                 struct intel_dp,
 430                                                 adapter);
 431         uint16_t address = algo_data->address;
 432         uint8_t msg[5];
 433         uint8_t reply[2];
 434         int msg_bytes;
 435         int reply_bytes;
 436         int ret;
 437
 438         /* Set up the command byte */
 439         if (mode & MODE_I2C_READ)
 440                 msg[0] = AUX_I2C_READ << 4;
 441         else
 442                 msg[0] = AUX_I2C_WRITE << 4;
 443
 444         if (!(mode & MODE_I2C_STOP))
 445                 msg[0] |= AUX_I2C_MOT << 4;
 446
 447         msg[1] = address >> 8;
 448         msg[2] = address;
 449
 450         switch (mode) {
 451         case MODE_I2C_WRITE:
 452                 msg[3] = 0;
 453                 msg[4] = write_byte;
 454                 msg_bytes = 5;
 455                 reply_bytes = 1;
 456                 break;
 457         case MODE_I2C_READ:
 458                 msg[3] = 0;
 459                 msg_bytes = 4;
 460                 reply_bytes = 2;
 461                 break;
 462         default:
 463                 msg_bytes = 3;
 464                 reply_bytes = 1;
 465                 break;
 466         }
 467
 468         for (;;) {
 469           ret = intel_dp_aux_ch(intel_dp,
 470                                 msg, msg_bytes,
 471                                 reply, reply_bytes);
 472                 if (ret < 0) {
 473                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 474                         return ret;
 475                 }
 476                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 477                 case AUX_I2C_REPLY_ACK:
 478                         if (mode == MODE_I2C_READ) {
 479                                 *read_byte = reply[1];
 480                         }
 481                         return reply_bytes - 1;
 482                 case AUX_I2C_REPLY_NACK:
 483                         DRM_DEBUG_KMS("aux_ch nack\n");
 484                         return -EREMOTEIO;
 485                 case AUX_I2C_REPLY_DEFER:
 486                         DRM_DEBUG_KMS("aux_ch defer\n");
 487                         udelay(100);
 488                         break;
 489                 default:
 490                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 491                         return -EREMOTEIO;
 492                 }
 493         }
 494 }
 495
 496 static int
 497 intel_dp_i2c_init(struct intel_dp *intel_dp,
 498                   struct intel_connector *intel_connector, const char *name)
 499 {
 500         DRM_DEBUG_KMS("i2c_init %s\n", name);
 501         intel_dp->algo.running = false;
 502         intel_dp->algo.address = 0;
 503         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 504
 505         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 506         intel_dp->adapter.owner = THIS_MODULE;
 507         intel_dp->adapter.class = I2C_CLASS_DDC;
 508         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 509         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 510         intel_dp->adapter.algo_data = &intel_dp->algo;
 511         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 512
 513         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 514 }
 515
 516 static bool
 517 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 518                     struct drm_display_mode *adjusted_mode)
 519 {
 520         struct drm_device *dev = encoder->dev;
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 523         int lane_count, clock;
 524         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 525         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 526         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 527
 528         if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
 529             dev_priv->panel_fixed_mode) {
 530                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 531                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 532                                         mode, adjusted_mode);
 533                 /*
 534                  * the mode->clock is used to calculate the Data&Link M/N
 535                  * of the pipe. For the eDP the fixed clock should be used.
 536                  */
 537                 mode->clock = dev_priv->panel_fixed_mode->clock;
 538         }
 539
 540         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 541                 for (clock = 0; clock <= max_clock; clock++) {
 542                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 543
 544                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 545                                         <= link_avail) {
 546                                 intel_dp->link_bw = bws[clock];
 547                                 intel_dp->lane_count = lane_count;
 548                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 549                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 550                                                 "count %d clock %d\n",
 551                                        intel_dp->link_bw, intel_dp->lane_count,
 552                                        adjusted_mode->clock);
 553                                 return true;
 554                         }
 555                 }
 556         }
 557
 558         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
 559                 /* okay we failed just pick the highest */
 560                 intel_dp->lane_count = max_lane_count;
 561                 intel_dp->link_bw = bws[max_clock];
 562                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 563                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 564                               "count %d clock %d\n",
 565                               intel_dp->link_bw, intel_dp->lane_count,
 566                               adjusted_mode->clock);
 567
 568                 return true;
 569         }
 570
 571         return false;
 572 }
 573
 574 struct intel_dp_m_n {
 575         uint32_t        tu;
 576         uint32_t        gmch_m;
 577         uint32_t        gmch_n;
 578         uint32_t        link_m;
 579         uint32_t        link_n;
 580 };
 581
 582 static void
 583 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 584 {
 585         while (*num > 0xffffff || *den > 0xffffff) {
 586                 *num >>= 1;
 587                 *den >>= 1;
 588         }
 589 }
 590
 591 static void
 592 intel_dp_compute_m_n(int bpp,
 593                      int nlanes,
 594                      int pixel_clock,
 595                      int link_clock,
 596                      struct intel_dp_m_n *m_n)
 597 {
 598         m_n->tu = 64;
 599         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 600         m_n->gmch_n = link_clock * nlanes;
 601         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 602         m_n->link_m = pixel_clock;
 603         m_n->link_n = link_clock;
 604         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 605 }
 606
 607 bool intel_pch_has_edp(struct drm_crtc *crtc)
 608 {
 609         struct drm_device *dev = crtc->dev;
 610         struct drm_mode_config *mode_config = &dev->mode_config;
 611         struct drm_encoder *encoder;
 612
 613         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 614                 struct intel_dp *intel_dp;
 615
 616                 if (encoder->crtc != crtc)
 617                         continue;
 618
 619                 intel_dp = enc_to_intel_dp(encoder);
 620                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
 621                         return intel_dp->is_pch_edp;
 622         }
 623         return false;
 624 }
 625
 626 void
 627 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 628                  struct drm_display_mode *adjusted_mode)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         struct drm_mode_config *mode_config = &dev->mode_config;
 632         struct drm_encoder *encoder;
 633         struct drm_i915_private *dev_priv = dev->dev_private;
 634         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 635         int lane_count = 4, bpp = 24;
 636         struct intel_dp_m_n m_n;
 637
 638         /*
 639          * Find the lane count in the intel_encoder private
 640          */
 641         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 642                 struct intel_dp *intel_dp;
 643
 644                 if (encoder->crtc != crtc)
 645                         continue;
 646
 647                 intel_dp = enc_to_intel_dp(encoder);
 648                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 649                         lane_count = intel_dp->lane_count;
 650                         if (IS_PCH_eDP(intel_dp))
 651                                 bpp = dev_priv->edp_bpp;
 652                         break;
 653                 }
 654         }
 655
 656         /*
 657          * Compute the GMCH and Link ratios. The '3' here is
 658          * the number of bytes_per_pixel post-LUT, which we always
 659          * set up for 8-bits of R/G/B, or 3 bytes total.
 660          */
 661         intel_dp_compute_m_n(bpp, lane_count,
 662                              mode->clock, adjusted_mode->clock, &m_n);
 663
 664         if (HAS_PCH_SPLIT(dev)) {
 665                 if (intel_crtc->pipe == 0) {
 666                         I915_WRITE(TRANSA_DATA_M1,
 667                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 668                                    m_n.gmch_m);
 669                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 670                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 671                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 672                 } else {
 673                         I915_WRITE(TRANSB_DATA_M1,
 674                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 675                                    m_n.gmch_m);
 676                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 677                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 678                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 679                 }
 680         } else {
 681                 if (intel_crtc->pipe == 0) {
 682                         I915_WRITE(PIPEA_GMCH_DATA_M,
 683                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 684                                    m_n.gmch_m);
 685                         I915_WRITE(PIPEA_GMCH_DATA_N,
 686                                    m_n.gmch_n);
 687                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 688                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 689                 } else {
 690                         I915_WRITE(PIPEB_GMCH_DATA_M,
 691                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 692                                    m_n.gmch_m);
 693                         I915_WRITE(PIPEB_GMCH_DATA_N,
 694                                         m_n.gmch_n);
 695                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 696                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 697                 }
 698         }
 699 }
 700
 701 static void
 702 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 703                   struct drm_display_mode *adjusted_mode)
 704 {
 705         struct drm_device *dev = encoder->dev;
 706         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 707         struct drm_crtc *crtc = intel_dp->base.enc.crtc;
 708         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 709
 710         intel_dp->DP = (DP_VOLTAGE_0_4 |
 711                        DP_PRE_EMPHASIS_0);
 712
 713         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 714                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 715         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 716                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 717
 718         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
 719                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 720         else
 721                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 722
 723         switch (intel_dp->lane_count) {
 724         case 1:
 725                 intel_dp->DP |= DP_PORT_WIDTH_1;
 726                 break;
 727         case 2:
 728                 intel_dp->DP |= DP_PORT_WIDTH_2;
 729                 break;
 730         case 4:
 731                 intel_dp->DP |= DP_PORT_WIDTH_4;
 732                 break;
 733         }
 734         if (intel_dp->has_audio)
 735                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 736
 737         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 738         intel_dp->link_configuration[0] = intel_dp->link_bw;
 739         intel_dp->link_configuration[1] = intel_dp->lane_count;
 740
 741         /*
 742          * Check for DPCD version > 1.1 and enhanced framing support
 743          */
 744         if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
 745                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 746                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 747         }
 748
 749         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 750         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 751                 intel_dp->DP |= DP_PIPEB_SELECT;
 752
 753         if (IS_eDP(intel_dp)) {
 754                 /* don't miss out required setting for eDP */
 755                 intel_dp->DP |= DP_PLL_ENABLE;
 756                 if (adjusted_mode->clock < 200000)
 757                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 758                 else
 759                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 760         }
 761 }
 762
 763 /* Returns true if the panel was already on when called */
 764 static bool ironlake_edp_panel_on (struct drm_device *dev)
 765 {
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         u32 pp;
 768
 769         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 770                 return true;
 771
 772         pp = I915_READ(PCH_PP_CONTROL);
 773
 774         /* ILK workaround: disable reset around power sequence */
 775         pp &= ~PANEL_POWER_RESET;
 776         I915_WRITE(PCH_PP_CONTROL, pp);
 777         POSTING_READ(PCH_PP_CONTROL);
 778
 779         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 780         I915_WRITE(PCH_PP_CONTROL, pp);
 781
 782         if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000))
 783                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 784                           I915_READ(PCH_PP_STATUS));
 785
 786         pp &= ~(PANEL_UNLOCK_REGS);
 787         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 788         I915_WRITE(PCH_PP_CONTROL, pp);
 789         POSTING_READ(PCH_PP_CONTROL);
 790
 791         return false;
 792 }
 793
 794 static void ironlake_edp_panel_off (struct drm_device *dev)
 795 {
 796         struct drm_i915_private *dev_priv = dev->dev_private;
 797         u32 pp;
 798
 799         pp = I915_READ(PCH_PP_CONTROL);
 800
 801         /* ILK workaround: disable reset around power sequence */
 802         pp &= ~PANEL_POWER_RESET;
 803         I915_WRITE(PCH_PP_CONTROL, pp);
 804         POSTING_READ(PCH_PP_CONTROL);
 805
 806         pp &= ~POWER_TARGET_ON;
 807         I915_WRITE(PCH_PP_CONTROL, pp);
 808
 809         if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000))
 810                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 811                           I915_READ(PCH_PP_STATUS));
 812
 813         /* Make sure VDD is enabled so DP AUX will work */
 814         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 815         I915_WRITE(PCH_PP_CONTROL, pp);
 816         POSTING_READ(PCH_PP_CONTROL);
 817 }
 818
 819 static void ironlake_edp_panel_vdd_on(struct drm_device *dev)
 820 {
 821         struct drm_i915_private *dev_priv = dev->dev_private;
 822         u32 pp;
 823
 824         pp = I915_READ(PCH_PP_CONTROL);
 825         pp |= EDP_FORCE_VDD;
 826         I915_WRITE(PCH_PP_CONTROL, pp);
 827         POSTING_READ(PCH_PP_CONTROL);
 828 }
 829
 830 static void ironlake_edp_panel_vdd_off(struct drm_device *dev)
 831 {
 832         struct drm_i915_private *dev_priv = dev->dev_private;
 833         u32 pp;
 834
 835         pp = I915_READ(PCH_PP_CONTROL);
 836         pp &= ~EDP_FORCE_VDD;
 837         I915_WRITE(PCH_PP_CONTROL, pp);
 838         POSTING_READ(PCH_PP_CONTROL);
 839 }
 840
 841 static void ironlake_edp_backlight_on (struct drm_device *dev)
 842 {
 843         struct drm_i915_private *dev_priv = dev->dev_private;
 844         u32 pp;
 845
 846         DRM_DEBUG_KMS("\n");
 847         pp = I915_READ(PCH_PP_CONTROL);
 848         pp |= EDP_BLC_ENABLE;
 849         I915_WRITE(PCH_PP_CONTROL, pp);
 850 }
 851
 852 static void ironlake_edp_backlight_off (struct drm_device *dev)
 853 {
 854         struct drm_i915_private *dev_priv = dev->dev_private;
 855         u32 pp;
 856
 857         DRM_DEBUG_KMS("\n");
 858         pp = I915_READ(PCH_PP_CONTROL);
 859         pp &= ~EDP_BLC_ENABLE;
 860         I915_WRITE(PCH_PP_CONTROL, pp);
 861 }
 862
 863 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 864 {
 865         struct drm_device *dev = encoder->dev;
 866         struct drm_i915_private *dev_priv = dev->dev_private;
 867         u32 dpa_ctl;
 868
 869         DRM_DEBUG_KMS("\n");
 870         dpa_ctl = I915_READ(DP_A);
 871         dpa_ctl &= ~DP_PLL_ENABLE;
 872         I915_WRITE(DP_A, dpa_ctl);
 873 }
 874
 875 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 876 {
 877         struct drm_device *dev = encoder->dev;
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         u32 dpa_ctl;
 880
 881         dpa_ctl = I915_READ(DP_A);
 882         dpa_ctl |= DP_PLL_ENABLE;
 883         I915_WRITE(DP_A, dpa_ctl);
 884         udelay(200);
 885 }
 886
 887 static void intel_dp_prepare(struct drm_encoder *encoder)
 888 {
 889         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 890         struct drm_device *dev = encoder->dev;
 891         struct drm_i915_private *dev_priv = dev->dev_private;
 892         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 893
 894         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
 895                 ironlake_edp_backlight_off(dev);
 896                 ironlake_edp_panel_vdd_on(dev);
 897                 ironlake_edp_pll_on(encoder);
 898         }
 899         if (dp_reg & DP_PORT_EN)
 900                 intel_dp_link_down(intel_dp);
 901 }
 902
 903 static void intel_dp_commit(struct drm_encoder *encoder)
 904 {
 905         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 906         struct drm_device *dev = encoder->dev;
 907
 908         intel_dp_start_link_train(intel_dp);
 909
 910         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 911                 ironlake_edp_panel_on(dev);
 912
 913         intel_dp_complete_link_train(intel_dp);
 914
 915         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 916                 ironlake_edp_backlight_on(dev);
 917 }
 918
 919 static void
 920 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 921 {
 922         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 923         struct drm_device *dev = encoder->dev;
 924         struct drm_i915_private *dev_priv = dev->dev_private;
 925         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 926
 927         if (mode != DRM_MODE_DPMS_ON) {
 928                 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
 929                         ironlake_edp_backlight_off(dev);
 930                         ironlake_edp_panel_off(dev);
 931                 }
 932                 if (dp_reg & DP_PORT_EN)
 933                         intel_dp_link_down(intel_dp);
 934                 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 935                         ironlake_edp_pll_off(encoder);
 936         } else {
 937                 if (!(dp_reg & DP_PORT_EN)) {
 938                         intel_dp_start_link_train(intel_dp);
 939                         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 940                                 ironlake_edp_panel_on(dev);
 941                         intel_dp_complete_link_train(intel_dp);
 942                         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 943                                 ironlake_edp_backlight_on(dev);
 944                 }
 945         }
 946         intel_dp->dpms_mode = mode;
 947 }
 948
 949 /*
 950  * Fetch AUX CH registers 0x202 - 0x207 which contain
 951  * link status information
 952  */
 953 static bool
 954 intel_dp_get_link_status(struct intel_dp *intel_dp)
 955 {
 956         int ret;
 957
 958         ret = intel_dp_aux_native_read(intel_dp,
 959                                        DP_LANE0_1_STATUS,
 960                                        intel_dp->link_status, DP_LINK_STATUS_SIZE);
 961         if (ret != DP_LINK_STATUS_SIZE)
 962                 return false;
 963         return true;
 964 }
 965
 966 static uint8_t
 967 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 968                      int r)
 969 {
 970         return link_status[r - DP_LANE0_1_STATUS];
 971 }
 972
 973 static uint8_t
 974 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 975                                  int lane)
 976 {
 977         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 978         int         s = ((lane & 1) ?
 979                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 980                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 981         uint8_t l = intel_dp_link_status(link_status, i);
 982
 983         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 984 }
 985
 986 static uint8_t
 987 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 988                                       int lane)
 989 {
 990         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 991         int         s = ((lane & 1) ?
 992                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 993                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 994         uint8_t l = intel_dp_link_status(link_status, i);
 995
 996         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 997 }
 998
 999
1000 #if 0
1001 static char     *voltage_names[] = {
1002         "0.4V", "0.6V", "0.8V", "1.2V"
1003 };
1004 static char     *pre_emph_names[] = {
1005         "0dB", "3.5dB", "6dB", "9.5dB"
1006 };
1007 static char     *link_train_names[] = {
1008         "pattern 1", "pattern 2", "idle", "off"
1009 };
1010 #endif
1011
1012 /*
1013  * These are source-specific values; current Intel hardware supports
1014  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1015  */
1016 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1017
1018 static uint8_t
1019 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1020 {
1021         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1022         case DP_TRAIN_VOLTAGE_SWING_400:
1023                 return DP_TRAIN_PRE_EMPHASIS_6;
1024         case DP_TRAIN_VOLTAGE_SWING_600:
1025                 return DP_TRAIN_PRE_EMPHASIS_6;
1026         case DP_TRAIN_VOLTAGE_SWING_800:
1027                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1028         case DP_TRAIN_VOLTAGE_SWING_1200:
1029         default:
1030                 return DP_TRAIN_PRE_EMPHASIS_0;
1031         }
1032 }
1033
1034 static void
1035 intel_get_adjust_train(struct intel_dp *intel_dp)
1036 {
1037         uint8_t v = 0;
1038         uint8_t p = 0;
1039         int lane;
1040
1041         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1042                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1043                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1044
1045                 if (this_v > v)
1046                         v = this_v;
1047                 if (this_p > p)
1048                         p = this_p;
1049         }
1050
1051         if (v >= I830_DP_VOLTAGE_MAX)
1052                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1053
1054         if (p >= intel_dp_pre_emphasis_max(v))
1055                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1056
1057         for (lane = 0; lane < 4; lane++)
1058                 intel_dp->train_set[lane] = v | p;
1059 }
1060
1061 static uint32_t
1062 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1063 {
1064         uint32_t        signal_levels = 0;
1065
1066         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1067         case DP_TRAIN_VOLTAGE_SWING_400:
1068         default:
1069                 signal_levels |= DP_VOLTAGE_0_4;
1070                 break;
1071         case DP_TRAIN_VOLTAGE_SWING_600:
1072                 signal_levels |= DP_VOLTAGE_0_6;
1073                 break;
1074         case DP_TRAIN_VOLTAGE_SWING_800:
1075                 signal_levels |= DP_VOLTAGE_0_8;
1076                 break;
1077         case DP_TRAIN_VOLTAGE_SWING_1200:
1078                 signal_levels |= DP_VOLTAGE_1_2;
1079                 break;
1080         }
1081         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1082         case DP_TRAIN_PRE_EMPHASIS_0:
1083         default:
1084                 signal_levels |= DP_PRE_EMPHASIS_0;
1085                 break;
1086         case DP_TRAIN_PRE_EMPHASIS_3_5:
1087                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1088                 break;
1089         case DP_TRAIN_PRE_EMPHASIS_6:
1090                 signal_levels |= DP_PRE_EMPHASIS_6;
1091                 break;
1092         case DP_TRAIN_PRE_EMPHASIS_9_5:
1093                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1094                 break;
1095         }
1096         return signal_levels;
1097 }
1098
1099 /* Gen6's DP voltage swing and pre-emphasis control */
1100 static uint32_t
1101 intel_gen6_edp_signal_levels(uint8_t train_set)
1102 {
1103         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1104         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1105                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1106         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1107                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1108         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1109                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1110         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1111                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1112         default:
1113                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1114                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1115         }
1116 }
1117
1118 static uint8_t
1119 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1120                       int lane)
1121 {
1122         int i = DP_LANE0_1_STATUS + (lane >> 1);
1123         int s = (lane & 1) * 4;
1124         uint8_t l = intel_dp_link_status(link_status, i);
1125
1126         return (l >> s) & 0xf;
1127 }
1128
1129 /* Check for clock recovery is done on all channels */
1130 static bool
1131 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1132 {
1133         int lane;
1134         uint8_t lane_status;
1135
1136         for (lane = 0; lane < lane_count; lane++) {
1137                 lane_status = intel_get_lane_status(link_status, lane);
1138                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1139                         return false;
1140         }
1141         return true;
1142 }
1143
1144 /* Check to see if channel eq is done on all channels */
1145 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1146                          DP_LANE_CHANNEL_EQ_DONE|\
1147                          DP_LANE_SYMBOL_LOCKED)
1148 static bool
1149 intel_channel_eq_ok(struct intel_dp *intel_dp)
1150 {
1151         uint8_t lane_align;
1152         uint8_t lane_status;
1153         int lane;
1154
1155         lane_align = intel_dp_link_status(intel_dp->link_status,
1156                                           DP_LANE_ALIGN_STATUS_UPDATED);
1157         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1158                 return false;
1159         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1160                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1161                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1162                         return false;
1163         }
1164         return true;
1165 }
1166
1167 static bool
1168 intel_dp_set_link_train(struct intel_dp *intel_dp,
1169                         uint32_t dp_reg_value,
1170                         uint8_t dp_train_pat,
1171                         bool first)
1172 {
1173         struct drm_device *dev = intel_dp->base.enc.dev;
1174         struct drm_i915_private *dev_priv = dev->dev_private;
1175         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc);
1176         int ret;
1177
1178         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1179         POSTING_READ(intel_dp->output_reg);
1180         if (first)
1181                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1182
1183         intel_dp_aux_native_write_1(intel_dp,
1184                                     DP_TRAINING_PATTERN_SET,
1185                                     dp_train_pat);
1186
1187         ret = intel_dp_aux_native_write(intel_dp,
1188                                         DP_TRAINING_LANE0_SET, intel_dp->train_set, 4);
1189         if (ret != 4)
1190                 return false;
1191
1192         return true;
1193 }
1194
1195 /* Enable corresponding port and start training pattern 1 */
1196 static void
1197 intel_dp_start_link_train(struct intel_dp *intel_dp)
1198 {
1199         struct drm_device *dev = intel_dp->base.enc.dev;
1200         int i;
1201         uint8_t voltage;
1202         bool clock_recovery = false;
1203         bool first = true;
1204         int tries;
1205         u32 reg;
1206         uint32_t DP = intel_dp->DP;
1207
1208         /* Write the link configuration data */
1209         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1210                                   intel_dp->link_configuration,
1211                                   DP_LINK_CONFIGURATION_SIZE);
1212
1213         DP |= DP_PORT_EN;
1214         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1215                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1216         else
1217                 DP &= ~DP_LINK_TRAIN_MASK;
1218         memset(intel_dp->train_set, 0, 4);
1219         voltage = 0xff;
1220         tries = 0;
1221         clock_recovery = false;
1222         for (;;) {
1223                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1224                 uint32_t    signal_levels;
1225                 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
1226                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1227                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1228                 } else {
1229                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1230                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1231                 }
1232
1233                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1234                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1235                 else
1236                         reg = DP | DP_LINK_TRAIN_PAT_1;
1237
1238                 if (!intel_dp_set_link_train(intel_dp, reg,
1239                                              DP_TRAINING_PATTERN_1, first))
1240                         break;
1241                 first = false;
1242                 /* Set training pattern 1 */
1243
1244                 udelay(100);
1245                 if (!intel_dp_get_link_status(intel_dp))
1246                         break;
1247
1248                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1249                         clock_recovery = true;
1250                         break;
1251                 }
1252
1253                 /* Check to see if we've tried the max voltage */
1254                 for (i = 0; i < intel_dp->lane_count; i++)
1255                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1256                                 break;
1257                 if (i == intel_dp->lane_count)
1258                         break;
1259
1260                 /* Check to see if we've tried the same voltage 5 times */
1261                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1262                         ++tries;
1263                         if (tries == 5)
1264                                 break;
1265                 } else
1266                         tries = 0;
1267                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1268
1269                 /* Compute new intel_dp->train_set as requested by target */
1270                 intel_get_adjust_train(intel_dp);
1271         }
1272
1273         intel_dp->DP = DP;
1274 }
1275
1276 static void
1277 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1278 {
1279         struct drm_device *dev = intel_dp->base.enc.dev;
1280         struct drm_i915_private *dev_priv = dev->dev_private;
1281         bool channel_eq = false;
1282         int tries;
1283         u32 reg;
1284         uint32_t DP = intel_dp->DP;
1285
1286         /* channel equalization */
1287         tries = 0;
1288         channel_eq = false;
1289         for (;;) {
1290                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1291                 uint32_t    signal_levels;
1292
1293                 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
1294                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1295                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1296                 } else {
1297                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1298                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1299                 }
1300
1301                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1302                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1303                 else
1304                         reg = DP | DP_LINK_TRAIN_PAT_2;
1305
1306                 /* channel eq pattern */
1307                 if (!intel_dp_set_link_train(intel_dp, reg,
1308                                              DP_TRAINING_PATTERN_2,
1309                                              false))
1310                         break;
1311
1312                 udelay(400);
1313                 if (!intel_dp_get_link_status(intel_dp))
1314                         break;
1315
1316                 if (intel_channel_eq_ok(intel_dp)) {
1317                         channel_eq = true;
1318                         break;
1319                 }
1320
1321                 /* Try 5 times */
1322                 if (tries > 5)
1323                         break;
1324
1325                 /* Compute new intel_dp->train_set as requested by target */
1326                 intel_get_adjust_train(intel_dp);
1327                 ++tries;
1328         }
1329
1330         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1331                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1332         else
1333                 reg = DP | DP_LINK_TRAIN_OFF;
1334
1335         I915_WRITE(intel_dp->output_reg, reg);
1336         POSTING_READ(intel_dp->output_reg);
1337         intel_dp_aux_native_write_1(intel_dp,
1338                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1339 }
1340
1341 static void
1342 intel_dp_link_down(struct intel_dp *intel_dp)
1343 {
1344         struct drm_device *dev = intel_dp->base.enc.dev;
1345         struct drm_i915_private *dev_priv = dev->dev_private;
1346         uint32_t DP = intel_dp->DP;
1347
1348         DRM_DEBUG_KMS("\n");
1349
1350         if (IS_eDP(intel_dp)) {
1351                 DP &= ~DP_PLL_ENABLE;
1352                 I915_WRITE(intel_dp->output_reg, DP);
1353                 POSTING_READ(intel_dp->output_reg);
1354                 udelay(100);
1355         }
1356
1357         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) {
1358                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1359                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1360                 POSTING_READ(intel_dp->output_reg);
1361         } else {
1362                 DP &= ~DP_LINK_TRAIN_MASK;
1363                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1364                 POSTING_READ(intel_dp->output_reg);
1365         }
1366
1367         udelay(17000);
1368
1369         if (IS_eDP(intel_dp))
1370                 DP |= DP_LINK_TRAIN_OFF;
1371         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1372         POSTING_READ(intel_dp->output_reg);
1373 }
1374
1375 /*
1376  * According to DP spec
1377  * 5.1.2:
1378  *  1. Read DPCD
1379  *  2. Configure link according to Receiver Capabilities
1380  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1381  *  4. Check link status on receipt of hot-plug interrupt
1382  */
1383
1384 static void
1385 intel_dp_check_link_status(struct intel_dp *intel_dp)
1386 {
1387         if (!intel_dp->base.enc.crtc)
1388                 return;
1389
1390         if (!intel_dp_get_link_status(intel_dp)) {
1391                 intel_dp_link_down(intel_dp);
1392                 return;
1393         }
1394
1395         if (!intel_channel_eq_ok(intel_dp)) {
1396                 intel_dp_start_link_train(intel_dp);
1397                 intel_dp_complete_link_train(intel_dp);
1398         }
1399 }
1400
1401 static enum drm_connector_status
1402 ironlake_dp_detect(struct drm_connector *connector)
1403 {
1404         struct drm_encoder *encoder = intel_attached_encoder(connector);
1405         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1406         enum drm_connector_status status;
1407
1408         /* Panel needs power for AUX to work */
1409         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
1410                 ironlake_edp_panel_vdd_on(connector->dev);
1411         status = connector_status_disconnected;
1412         if (intel_dp_aux_native_read(intel_dp,
1413                                      0x000, intel_dp->dpcd,
1414                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1415         {
1416                 if (intel_dp->dpcd[0] != 0)
1417                         status = connector_status_connected;
1418         }
1419         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1420                       intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1421         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
1422                 ironlake_edp_panel_vdd_off(connector->dev);
1423         return status;
1424 }
1425
1426 /**
1427  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1428  *
1429  * \return true if DP port is connected.
1430  * \return false if DP port is disconnected.
1431  */
1432 static enum drm_connector_status
1433 intel_dp_detect(struct drm_connector *connector)
1434 {
1435         struct drm_encoder *encoder = intel_attached_encoder(connector);
1436         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1437         struct drm_device *dev = intel_dp->base.enc.dev;
1438         struct drm_i915_private *dev_priv = dev->dev_private;
1439         uint32_t temp, bit;
1440         enum drm_connector_status status;
1441
1442         intel_dp->has_audio = false;
1443
1444         if (HAS_PCH_SPLIT(dev))
1445                 return ironlake_dp_detect(connector);
1446
1447         switch (intel_dp->output_reg) {
1448         case DP_B:
1449                 bit = DPB_HOTPLUG_INT_STATUS;
1450                 break;
1451         case DP_C:
1452                 bit = DPC_HOTPLUG_INT_STATUS;
1453                 break;
1454         case DP_D:
1455                 bit = DPD_HOTPLUG_INT_STATUS;
1456                 break;
1457         default:
1458                 return connector_status_unknown;
1459         }
1460
1461         temp = I915_READ(PORT_HOTPLUG_STAT);
1462
1463         if ((temp & bit) == 0)
1464                 return connector_status_disconnected;
1465
1466         status = connector_status_disconnected;
1467         if (intel_dp_aux_native_read(intel_dp,
1468                                      0x000, intel_dp->dpcd,
1469                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1470         {
1471                 if (intel_dp->dpcd[0] != 0)
1472                         status = connector_status_connected;
1473         }
1474         return status;
1475 }
1476
1477 static int intel_dp_get_modes(struct drm_connector *connector)
1478 {
1479         struct drm_encoder *encoder = intel_attached_encoder(connector);
1480         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1481         struct drm_device *dev = intel_dp->base.enc.dev;
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483         int ret;
1484
1485         /* We should parse the EDID data and find out if it has an audio sink
1486          */
1487
1488         ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus);
1489         if (ret) {
1490                 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
1491                     !dev_priv->panel_fixed_mode) {
1492                         struct drm_display_mode *newmode;
1493                         list_for_each_entry(newmode, &connector->probed_modes,
1494                                             head) {
1495                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1496                                         dev_priv->panel_fixed_mode =
1497                                                 drm_mode_duplicate(dev, newmode);
1498                                         break;
1499                                 }
1500                         }
1501                 }
1502
1503                 return ret;
1504         }
1505
1506         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1507         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
1508                 if (dev_priv->panel_fixed_mode != NULL) {
1509                         struct drm_display_mode *mode;
1510                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1511                         drm_mode_probed_add(connector, mode);
1512                         return 1;
1513                 }
1514         }
1515         return 0;
1516 }
1517
1518 static void
1519 intel_dp_destroy (struct drm_connector *connector)
1520 {
1521         drm_sysfs_connector_remove(connector);
1522         drm_connector_cleanup(connector);
1523         kfree(connector);
1524 }
1525
1526 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1527 {
1528         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1529
1530         i2c_del_adapter(&intel_dp->adapter);
1531         drm_encoder_cleanup(encoder);
1532         kfree(intel_dp);
1533 }
1534
1535 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1536         .dpms = intel_dp_dpms,
1537         .mode_fixup = intel_dp_mode_fixup,
1538         .prepare = intel_dp_prepare,
1539         .mode_set = intel_dp_mode_set,
1540         .commit = intel_dp_commit,
1541 };
1542
1543 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1544         .dpms = drm_helper_connector_dpms,
1545         .detect = intel_dp_detect,
1546         .fill_modes = drm_helper_probe_single_connector_modes,
1547         .destroy = intel_dp_destroy,
1548 };
1549
1550 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1551         .get_modes = intel_dp_get_modes,
1552         .mode_valid = intel_dp_mode_valid,
1553         .best_encoder = intel_attached_encoder,
1554 };
1555
1556 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1557         .destroy = intel_dp_encoder_destroy,
1558 };
1559
1560 static void
1561 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1562 {
1563         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1564
1565         if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1566                 intel_dp_check_link_status(intel_dp);
1567 }
1568
1569 /* Return which DP Port should be selected for Transcoder DP control */
1570 int
1571 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1572 {
1573         struct drm_device *dev = crtc->dev;
1574         struct drm_mode_config *mode_config = &dev->mode_config;
1575         struct drm_encoder *encoder;
1576
1577         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1578                 struct intel_dp *intel_dp;
1579
1580                 if (encoder->crtc != crtc)
1581                         continue;
1582
1583                 intel_dp = enc_to_intel_dp(encoder);
1584                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1585                         return intel_dp->output_reg;
1586         }
1587
1588         return -1;
1589 }
1590
1591 /* check the VBT to see whether the eDP is on DP-D port */
1592 bool intel_dpd_is_edp(struct drm_device *dev)
1593 {
1594         struct drm_i915_private *dev_priv = dev->dev_private;
1595         struct child_device_config *p_child;
1596         int i;
1597
1598         if (!dev_priv->child_dev_num)
1599                 return false;
1600
1601         for (i = 0; i < dev_priv->child_dev_num; i++) {
1602                 p_child = dev_priv->child_dev + i;
1603
1604                 if (p_child->dvo_port == PORT_IDPD &&
1605                     p_child->device_type == DEVICE_TYPE_eDP)
1606                         return true;
1607         }
1608         return false;
1609 }
1610
1611 void
1612 intel_dp_init(struct drm_device *dev, int output_reg)
1613 {
1614         struct drm_i915_private *dev_priv = dev->dev_private;
1615         struct drm_connector *connector;
1616         struct intel_dp *intel_dp;
1617         struct intel_encoder *intel_encoder;
1618         struct intel_connector *intel_connector;
1619         const char *name = NULL;
1620         int type;
1621
1622         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1623         if (!intel_dp)
1624                 return;
1625
1626         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1627         if (!intel_connector) {
1628                 kfree(intel_dp);
1629                 return;
1630         }
1631         intel_encoder = &intel_dp->base;
1632
1633         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1634                 if (intel_dpd_is_edp(dev))
1635                         intel_dp->is_pch_edp = true;
1636
1637         if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
1638                 type = DRM_MODE_CONNECTOR_eDP;
1639                 intel_encoder->type = INTEL_OUTPUT_EDP;
1640         } else {
1641                 type = DRM_MODE_CONNECTOR_DisplayPort;
1642                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1643         }
1644
1645         connector = &intel_connector->base;
1646         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1647         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1648
1649         connector->polled = DRM_CONNECTOR_POLL_HPD;
1650
1651         if (output_reg == DP_B || output_reg == PCH_DP_B)
1652                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1653         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1654                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1655         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1656                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1657
1658         if (IS_eDP(intel_dp))
1659                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1660
1661         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1662         connector->interlace_allowed = true;
1663         connector->doublescan_allowed = 0;
1664
1665         intel_dp->output_reg = output_reg;
1666         intel_dp->has_audio = false;
1667         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1668
1669         drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1670                          DRM_MODE_ENCODER_TMDS);
1671         drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1672
1673         drm_mode_connector_attach_encoder(&intel_connector->base,
1674                                           &intel_encoder->enc);
1675         drm_sysfs_connector_add(connector);
1676
1677         /* Set up the DDC bus. */
1678         switch (output_reg) {
1679                 case DP_A:
1680                         name = "DPDDC-A";
1681                         break;
1682                 case DP_B:
1683                 case PCH_DP_B:
1684                         dev_priv->hotplug_supported_mask |=
1685                                 HDMIB_HOTPLUG_INT_STATUS;
1686                         name = "DPDDC-B";
1687                         break;
1688                 case DP_C:
1689                 case PCH_DP_C:
1690                         dev_priv->hotplug_supported_mask |=
1691                                 HDMIC_HOTPLUG_INT_STATUS;
1692                         name = "DPDDC-C";
1693                         break;
1694                 case DP_D:
1695                 case PCH_DP_D:
1696                         dev_priv->hotplug_supported_mask |=
1697                                 HDMID_HOTPLUG_INT_STATUS;
1698                         name = "DPDDC-D";
1699                         break;
1700         }
1701
1702         intel_dp_i2c_init(intel_dp, intel_connector, name);
1703
1704         intel_encoder->ddc_bus = &intel_dp->adapter;
1705         intel_encoder->hot_plug = intel_dp_hot_plug;
1706
1707         if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
1708                 /* initialize panel mode from VBT if available for eDP */
1709                 if (dev_priv->lfp_lvds_vbt_mode) {
1710                         dev_priv->panel_fixed_mode =
1711                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1712                         if (dev_priv->panel_fixed_mode) {
1713                                 dev_priv->panel_fixed_mode->type |=
1714                                         DRM_MODE_TYPE_PREFERRED;
1715                         }
1716                 }
1717         }
1718
1719         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1720          * 0xd.  Failure to do so will result in spurious interrupts being
1721          * generated on the port when a cable is not attached.
1722          */
1723         if (IS_G4X(dev) && !IS_GM45(dev)) {
1724                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1725                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1726         }
1727 }