2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
92 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
95 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
98 static inline u32 /* units of 100MHz */
99 intel_fdi_link_freq(struct drm_device *dev)
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
119 .find_pll = intel_find_best_PLL,
122 static const intel_limit_t intel_limits_i8xx_lvds = {
123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
133 .find_pll = intel_find_best_PLL,
136 static const intel_limit_t intel_limits_i9xx_sdvo = {
137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 8, .max = 18 },
142 .m2 = { .min = 3, .max = 7 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
147 .find_pll = intel_find_best_PLL,
150 static const intel_limit_t intel_limits_i9xx_lvds = {
151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
161 .find_pll = intel_find_best_PLL,
165 static const intel_limit_t intel_limits_g4x_sdvo = {
166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
178 .find_pll = intel_g4x_find_best_PLL,
181 static const intel_limit_t intel_limits_g4x_hdmi = {
182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
192 .find_pll = intel_g4x_find_best_PLL,
195 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
207 .find_pll = intel_g4x_find_best_PLL,
210 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
222 .find_pll = intel_g4x_find_best_PLL,
225 static const intel_limit_t intel_limits_g4x_display_port = {
226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
235 .p2_slow = 10, .p2_fast = 10 },
236 .find_pll = intel_find_pll_g4x_dp,
239 static const intel_limit_t intel_limits_pineview_sdvo = {
240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
242 /* Pineview's Ncounter is a ring counter */
243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
245 /* Pineview only has one combined m divider, which we treat as m2. */
246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
252 .find_pll = intel_find_best_PLL,
255 static const intel_limit_t intel_limits_pineview_lvds = {
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
266 .find_pll = intel_find_best_PLL,
269 /* Ironlake / Sandybridge
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
274 static const intel_limit_t intel_limits_ironlake_dac = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
285 .find_pll = intel_g4x_find_best_PLL,
288 static const intel_limit_t intel_limits_ironlake_single_lvds = {
289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
299 .find_pll = intel_g4x_find_best_PLL,
302 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
313 .find_pll = intel_g4x_find_best_PLL,
316 /* LVDS 100mhz refclk limits. */
317 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 .find_pll = intel_g4x_find_best_PLL,
331 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
339 .p1 = { .min = 2, .max = 6 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
342 .find_pll = intel_g4x_find_best_PLL,
345 static const intel_limit_t intel_limits_ironlake_display_port = {
346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
355 .p2_slow = 10, .p2_fast = 10 },
356 .find_pll = intel_find_pll_ironlake_dp,
359 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
364 if (dev_priv->lvds_val)
365 val = dev_priv->lvds_val;
367 /* BIOS should set the proper LVDS register value at boot, but
368 * in reality, it doesn't set the value when the lid is closed;
369 * we need to check "the value to be set" in VBT when LVDS
370 * register is uninitialized.
372 val = I915_READ(reg);
373 if (!(val & ~LVDS_DETECTED))
374 val = dev_priv->bios_lvds_val;
375 dev_priv->lvds_val = val;
377 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
380 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
383 struct drm_device *dev = crtc->dev;
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 const intel_limit_t *limit;
387 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
388 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
389 /* LVDS dual channel */
390 if (refclk == 100000)
391 limit = &intel_limits_ironlake_dual_lvds_100m;
393 limit = &intel_limits_ironlake_dual_lvds;
395 if (refclk == 100000)
396 limit = &intel_limits_ironlake_single_lvds_100m;
398 limit = &intel_limits_ironlake_single_lvds;
400 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
402 limit = &intel_limits_ironlake_display_port;
404 limit = &intel_limits_ironlake_dac;
409 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
411 struct drm_device *dev = crtc->dev;
412 struct drm_i915_private *dev_priv = dev->dev_private;
413 const intel_limit_t *limit;
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
416 if (is_dual_link_lvds(dev_priv, LVDS))
417 /* LVDS with dual channel */
418 limit = &intel_limits_g4x_dual_channel_lvds;
420 /* LVDS with dual channel */
421 limit = &intel_limits_g4x_single_channel_lvds;
422 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
423 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
424 limit = &intel_limits_g4x_hdmi;
425 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
426 limit = &intel_limits_g4x_sdvo;
427 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
428 limit = &intel_limits_g4x_display_port;
429 } else /* The option is for other outputs */
430 limit = &intel_limits_i9xx_sdvo;
435 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
437 struct drm_device *dev = crtc->dev;
438 const intel_limit_t *limit;
440 if (HAS_PCH_SPLIT(dev))
441 limit = intel_ironlake_limit(crtc, refclk);
442 else if (IS_G4X(dev)) {
443 limit = intel_g4x_limit(crtc);
444 } else if (IS_PINEVIEW(dev)) {
445 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
446 limit = &intel_limits_pineview_lvds;
448 limit = &intel_limits_pineview_sdvo;
449 } else if (!IS_GEN2(dev)) {
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
451 limit = &intel_limits_i9xx_lvds;
453 limit = &intel_limits_i9xx_sdvo;
455 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
456 limit = &intel_limits_i8xx_lvds;
458 limit = &intel_limits_i8xx_dvo;
463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
464 static void pineview_clock(int refclk, intel_clock_t *clock)
466 clock->m = clock->m2 + 2;
467 clock->p = clock->p1 * clock->p2;
468 clock->vco = refclk * clock->m / clock->n;
469 clock->dot = clock->vco / clock->p;
472 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
474 if (IS_PINEVIEW(dev)) {
475 pineview_clock(refclk, clock);
478 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
479 clock->p = clock->p1 * clock->p2;
480 clock->vco = refclk * clock->m / (clock->n + 2);
481 clock->dot = clock->vco / clock->p;
485 * Returns whether any output on the specified pipe is of the specified type
487 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
489 struct drm_device *dev = crtc->dev;
490 struct drm_mode_config *mode_config = &dev->mode_config;
491 struct intel_encoder *encoder;
493 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
494 if (encoder->base.crtc == crtc && encoder->type == type)
500 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
502 * Returns whether the given set of divisors are valid for a given refclk with
503 * the given connectors.
506 static bool intel_PLL_is_valid(struct drm_device *dev,
507 const intel_limit_t *limit,
508 const intel_clock_t *clock)
510 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
511 INTELPllInvalid("p1 out of range\n");
512 if (clock->p < limit->p.min || limit->p.max < clock->p)
513 INTELPllInvalid("p out of range\n");
514 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
515 INTELPllInvalid("m2 out of range\n");
516 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
517 INTELPllInvalid("m1 out of range\n");
518 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
519 INTELPllInvalid("m1 <= m2\n");
520 if (clock->m < limit->m.min || limit->m.max < clock->m)
521 INTELPllInvalid("m out of range\n");
522 if (clock->n < limit->n.min || limit->n.max < clock->n)
523 INTELPllInvalid("n out of range\n");
524 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
525 INTELPllInvalid("vco out of range\n");
526 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
527 * connector, etc., rather than just a single range.
529 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
530 INTELPllInvalid("dot out of range\n");
536 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
537 int target, int refclk, intel_clock_t *best_clock)
540 struct drm_device *dev = crtc->dev;
541 struct drm_i915_private *dev_priv = dev->dev_private;
545 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
546 (I915_READ(LVDS)) != 0) {
548 * For LVDS, if the panel is on, just rely on its current
549 * settings for dual-channel. We haven't figured out how to
550 * reliably set up different single/dual channel state, if we
553 if (is_dual_link_lvds(dev_priv, LVDS))
554 clock.p2 = limit->p2.p2_fast;
556 clock.p2 = limit->p2.p2_slow;
558 if (target < limit->p2.dot_limit)
559 clock.p2 = limit->p2.p2_slow;
561 clock.p2 = limit->p2.p2_fast;
564 memset(best_clock, 0, sizeof(*best_clock));
566 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
568 for (clock.m2 = limit->m2.min;
569 clock.m2 <= limit->m2.max; clock.m2++) {
570 /* m1 is always 0 in Pineview */
571 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
573 for (clock.n = limit->n.min;
574 clock.n <= limit->n.max; clock.n++) {
575 for (clock.p1 = limit->p1.min;
576 clock.p1 <= limit->p1.max; clock.p1++) {
579 intel_clock(dev, refclk, &clock);
580 if (!intel_PLL_is_valid(dev, limit,
584 this_err = abs(clock.dot - target);
585 if (this_err < err) {
594 return (err != target);
598 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
599 int target, int refclk, intel_clock_t *best_clock)
601 struct drm_device *dev = crtc->dev;
602 struct drm_i915_private *dev_priv = dev->dev_private;
606 /* approximately equals target * 0.00585 */
607 int err_most = (target >> 8) + (target >> 9);
610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
613 if (HAS_PCH_SPLIT(dev))
617 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
619 clock.p2 = limit->p2.p2_fast;
621 clock.p2 = limit->p2.p2_slow;
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
626 clock.p2 = limit->p2.p2_fast;
629 memset(best_clock, 0, sizeof(*best_clock));
630 max_n = limit->n.max;
631 /* based on hardware requirement, prefer smaller n to precision */
632 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
633 /* based on hardware requirement, prefere larger m1,m2 */
634 for (clock.m1 = limit->m1.max;
635 clock.m1 >= limit->m1.min; clock.m1--) {
636 for (clock.m2 = limit->m2.max;
637 clock.m2 >= limit->m2.min; clock.m2--) {
638 for (clock.p1 = limit->p1.max;
639 clock.p1 >= limit->p1.min; clock.p1--) {
642 intel_clock(dev, refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
647 this_err = abs(clock.dot - target);
648 if (this_err < err_most) {
662 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
663 int target, int refclk, intel_clock_t *best_clock)
665 struct drm_device *dev = crtc->dev;
668 if (target < 200000) {
681 intel_clock(dev, refclk, &clock);
682 memcpy(best_clock, &clock, sizeof(intel_clock_t));
686 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
688 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
689 int target, int refclk, intel_clock_t *best_clock)
692 if (target < 200000) {
705 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
706 clock.p = (clock.p1 * clock.p2);
707 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
709 memcpy(best_clock, &clock, sizeof(intel_clock_t));
714 * intel_wait_for_vblank - wait for vblank on a given pipe
716 * @pipe: pipe to wait for
718 * Wait for vblank to occur on a given pipe. Needed for various bits of
721 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
723 struct drm_i915_private *dev_priv = dev->dev_private;
724 int pipestat_reg = PIPESTAT(pipe);
726 /* Clear existing vblank status. Note this will clear any other
727 * sticky status fields as well.
729 * This races with i915_driver_irq_handler() with the result
730 * that either function could miss a vblank event. Here it is not
731 * fatal, as we will either wait upon the next vblank interrupt or
732 * timeout. Generally speaking intel_wait_for_vblank() is only
733 * called during modeset at which time the GPU should be idle and
734 * should *not* be performing page flips and thus not waiting on
736 * Currently, the result of us stealing a vblank from the irq
737 * handler is that a single frame will be skipped during swapbuffers.
739 I915_WRITE(pipestat_reg,
740 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
742 /* Wait for vblank interrupt bit to set */
743 if (wait_for(I915_READ(pipestat_reg) &
744 PIPE_VBLANK_INTERRUPT_STATUS,
746 DRM_DEBUG_KMS("vblank wait timed out\n");
750 * intel_wait_for_pipe_off - wait for pipe to turn off
752 * @pipe: pipe to wait for
754 * After disabling a pipe, we can't wait for vblank in the usual way,
755 * spinning on the vblank interrupt status bit, since we won't actually
756 * see an interrupt when the pipe is disabled.
759 * wait for the pipe register state bit to turn off
762 * wait for the display line value to settle (it usually
763 * ends up stopping at the start of the next frame).
766 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
768 struct drm_i915_private *dev_priv = dev->dev_private;
770 if (INTEL_INFO(dev)->gen >= 4) {
771 int reg = PIPECONF(pipe);
773 /* Wait for the Pipe State to go off */
774 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
776 DRM_DEBUG_KMS("pipe_off wait timed out\n");
779 int reg = PIPEDSL(pipe);
780 unsigned long timeout = jiffies + msecs_to_jiffies(100);
782 /* Wait for the display line to settle */
784 last_line = I915_READ(reg) & DSL_LINEMASK;
786 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
787 time_after(timeout, jiffies));
788 if (time_after(jiffies, timeout))
789 DRM_DEBUG_KMS("pipe_off wait timed out\n");
793 static const char *state_string(bool enabled)
795 return enabled ? "on" : "off";
798 /* Only for pre-ILK configs */
799 static void assert_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
807 val = I915_READ(reg);
808 cur_state = !!(val & DPLL_VCO_ENABLE);
809 WARN(cur_state != state,
810 "PLL state assertion failure (expected %s, current %s)\n",
811 state_string(state), state_string(cur_state));
813 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
814 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
817 static void assert_pch_pll(struct drm_i915_private *dev_priv,
818 enum pipe pipe, bool state)
824 if (HAS_PCH_CPT(dev_priv->dev)) {
827 pch_dpll = I915_READ(PCH_DPLL_SEL);
829 /* Make sure the selected PLL is enabled to the transcoder */
830 WARN(!((pch_dpll >> (4 * pipe)) & 8),
831 "transcoder %d PLL not enabled\n", pipe);
833 /* Convert the transcoder pipe number to a pll pipe number */
834 pipe = (pch_dpll >> (4 * pipe)) & 1;
837 reg = PCH_DPLL(pipe);
838 val = I915_READ(reg);
839 cur_state = !!(val & DPLL_VCO_ENABLE);
840 WARN(cur_state != state,
841 "PCH PLL state assertion failure (expected %s, current %s)\n",
842 state_string(state), state_string(cur_state));
844 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
845 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
847 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
848 enum pipe pipe, bool state)
854 reg = FDI_TX_CTL(pipe);
855 val = I915_READ(reg);
856 cur_state = !!(val & FDI_TX_ENABLE);
857 WARN(cur_state != state,
858 "FDI TX state assertion failure (expected %s, current %s)\n",
859 state_string(state), state_string(cur_state));
861 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
862 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
864 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
865 enum pipe pipe, bool state)
871 reg = FDI_RX_CTL(pipe);
872 val = I915_READ(reg);
873 cur_state = !!(val & FDI_RX_ENABLE);
874 WARN(cur_state != state,
875 "FDI RX state assertion failure (expected %s, current %s)\n",
876 state_string(state), state_string(cur_state));
878 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
879 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
881 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
887 /* ILK FDI PLL is always enabled */
888 if (dev_priv->info->gen == 5)
891 reg = FDI_TX_CTL(pipe);
892 val = I915_READ(reg);
893 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
896 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
902 reg = FDI_RX_CTL(pipe);
903 val = I915_READ(reg);
904 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
907 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
910 int pp_reg, lvds_reg;
912 enum pipe panel_pipe = PIPE_A;
915 if (HAS_PCH_SPLIT(dev_priv->dev)) {
916 pp_reg = PCH_PP_CONTROL;
923 val = I915_READ(pp_reg);
924 if (!(val & PANEL_POWER_ON) ||
925 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
928 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
931 WARN(panel_pipe == pipe && locked,
932 "panel assertion failure, pipe %c regs locked\n",
936 static void assert_pipe(struct drm_i915_private *dev_priv,
937 enum pipe pipe, bool state)
943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
945 cur_state = !!(val & PIPECONF_ENABLE);
946 WARN(cur_state != state,
947 "pipe %c assertion failure (expected %s, current %s)\n",
948 pipe_name(pipe), state_string(state), state_string(cur_state));
950 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
951 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
953 static void assert_plane_enabled(struct drm_i915_private *dev_priv,
959 reg = DSPCNTR(plane);
960 val = I915_READ(reg);
961 WARN(!(val & DISPLAY_PLANE_ENABLE),
962 "plane %c assertion failure, should be active but is disabled\n",
966 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
973 /* Planes are fixed to pipes on ILK+ */
974 if (HAS_PCH_SPLIT(dev_priv->dev))
977 /* Need to check both planes against the pipe */
978 for (i = 0; i < 2; i++) {
980 val = I915_READ(reg);
981 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
982 DISPPLANE_SEL_PIPE_SHIFT;
983 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
984 "plane %c assertion failure, should be off on pipe %c but is still active\n",
985 plane_name(i), pipe_name(pipe));
989 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
994 val = I915_READ(PCH_DREF_CONTROL);
995 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
996 DREF_SUPERSPREAD_SOURCE_MASK));
997 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1000 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1007 reg = TRANSCONF(pipe);
1008 val = I915_READ(reg);
1009 enabled = !!(val & TRANS_ENABLE);
1011 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1015 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1016 enum pipe pipe, u32 port_sel, u32 val)
1018 if ((val & DP_PORT_EN) == 0)
1021 if (HAS_PCH_CPT(dev_priv->dev)) {
1022 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1023 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1024 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1027 if ((val & DP_PIPE_MASK) != (pipe << 30))
1033 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1034 enum pipe pipe, u32 val)
1036 if ((val & PORT_ENABLE) == 0)
1039 if (HAS_PCH_CPT(dev_priv->dev)) {
1040 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1043 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1049 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1050 enum pipe pipe, u32 val)
1052 if ((val & LVDS_PORT_EN) == 0)
1055 if (HAS_PCH_CPT(dev_priv->dev)) {
1056 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1059 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1065 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1066 enum pipe pipe, u32 val)
1068 if ((val & ADPA_DAC_ENABLE) == 0)
1070 if (HAS_PCH_CPT(dev_priv->dev)) {
1071 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1074 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1080 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1081 enum pipe pipe, int reg, u32 port_sel)
1083 u32 val = I915_READ(reg);
1084 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1085 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1086 reg, pipe_name(pipe));
1089 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, int reg)
1092 u32 val = I915_READ(reg);
1093 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1094 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1095 reg, pipe_name(pipe));
1098 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1104 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1105 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1106 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1109 val = I915_READ(reg);
1110 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1111 "PCH VGA enabled on transcoder %c, should be disabled\n",
1115 val = I915_READ(reg);
1116 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1117 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1120 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1121 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1122 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1126 * intel_enable_pll - enable a PLL
1127 * @dev_priv: i915 private structure
1128 * @pipe: pipe PLL to enable
1130 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1131 * make sure the PLL reg is writable first though, since the panel write
1132 * protect mechanism may be enabled.
1134 * Note! This is for pre-ILK only.
1136 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1141 /* No really, not for ILK+ */
1142 BUG_ON(dev_priv->info->gen >= 5);
1144 /* PLL is protected by panel, make sure we can write it */
1145 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1146 assert_panel_unlocked(dev_priv, pipe);
1149 val = I915_READ(reg);
1150 val |= DPLL_VCO_ENABLE;
1152 /* We do this three times for luck */
1153 I915_WRITE(reg, val);
1155 udelay(150); /* wait for warmup */
1156 I915_WRITE(reg, val);
1158 udelay(150); /* wait for warmup */
1159 I915_WRITE(reg, val);
1161 udelay(150); /* wait for warmup */
1165 * intel_disable_pll - disable a PLL
1166 * @dev_priv: i915 private structure
1167 * @pipe: pipe PLL to disable
1169 * Disable the PLL for @pipe, making sure the pipe is off first.
1171 * Note! This is for pre-ILK only.
1173 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1178 /* Don't disable pipe A or pipe A PLLs if needed */
1179 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1182 /* Make sure the pipe isn't still relying on us */
1183 assert_pipe_disabled(dev_priv, pipe);
1186 val = I915_READ(reg);
1187 val &= ~DPLL_VCO_ENABLE;
1188 I915_WRITE(reg, val);
1193 * intel_enable_pch_pll - enable PCH PLL
1194 * @dev_priv: i915 private structure
1195 * @pipe: pipe PLL to enable
1197 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1198 * drives the transcoder clock.
1200 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1209 /* PCH only available on ILK+ */
1210 BUG_ON(dev_priv->info->gen < 5);
1212 /* PCH refclock must be enabled first */
1213 assert_pch_refclk_enabled(dev_priv);
1215 reg = PCH_DPLL(pipe);
1216 val = I915_READ(reg);
1217 val |= DPLL_VCO_ENABLE;
1218 I915_WRITE(reg, val);
1223 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1232 /* PCH only available on ILK+ */
1233 BUG_ON(dev_priv->info->gen < 5);
1235 /* Make sure transcoder isn't still depending on us */
1236 assert_transcoder_disabled(dev_priv, pipe);
1238 reg = PCH_DPLL(pipe);
1239 val = I915_READ(reg);
1240 val &= ~DPLL_VCO_ENABLE;
1241 I915_WRITE(reg, val);
1246 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1252 /* PCH only available on ILK+ */
1253 BUG_ON(dev_priv->info->gen < 5);
1255 /* Make sure PCH DPLL is enabled */
1256 assert_pch_pll_enabled(dev_priv, pipe);
1258 /* FDI must be feeding us bits for PCH ports */
1259 assert_fdi_tx_enabled(dev_priv, pipe);
1260 assert_fdi_rx_enabled(dev_priv, pipe);
1262 reg = TRANSCONF(pipe);
1263 val = I915_READ(reg);
1265 if (HAS_PCH_IBX(dev_priv->dev)) {
1267 * make the BPC in transcoder be consistent with
1268 * that in pipeconf reg.
1270 val &= ~PIPE_BPC_MASK;
1271 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1273 I915_WRITE(reg, val | TRANS_ENABLE);
1274 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1275 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1278 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1284 /* FDI relies on the transcoder */
1285 assert_fdi_tx_disabled(dev_priv, pipe);
1286 assert_fdi_rx_disabled(dev_priv, pipe);
1288 /* Ports must be off as well */
1289 assert_pch_ports_disabled(dev_priv, pipe);
1291 reg = TRANSCONF(pipe);
1292 val = I915_READ(reg);
1293 val &= ~TRANS_ENABLE;
1294 I915_WRITE(reg, val);
1295 /* wait for PCH transcoder off, transcoder state */
1296 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1297 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1301 * intel_enable_pipe - enable a pipe, asserting requirements
1302 * @dev_priv: i915 private structure
1303 * @pipe: pipe to enable
1304 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1306 * Enable @pipe, making sure that various hardware specific requirements
1307 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1309 * @pipe should be %PIPE_A or %PIPE_B.
1311 * Will wait until the pipe is actually running (i.e. first vblank) before
1314 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1321 * A pipe without a PLL won't actually be able to drive bits from
1322 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1325 if (!HAS_PCH_SPLIT(dev_priv->dev))
1326 assert_pll_enabled(dev_priv, pipe);
1329 /* if driving the PCH, we need FDI enabled */
1330 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1331 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1333 /* FIXME: assert CPU port conditions for SNB+ */
1336 reg = PIPECONF(pipe);
1337 val = I915_READ(reg);
1338 if (val & PIPECONF_ENABLE)
1341 I915_WRITE(reg, val | PIPECONF_ENABLE);
1342 intel_wait_for_vblank(dev_priv->dev, pipe);
1346 * intel_disable_pipe - disable a pipe, asserting requirements
1347 * @dev_priv: i915 private structure
1348 * @pipe: pipe to disable
1350 * Disable @pipe, making sure that various hardware specific requirements
1351 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1353 * @pipe should be %PIPE_A or %PIPE_B.
1355 * Will wait until the pipe has shut down before returning.
1357 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1364 * Make sure planes won't keep trying to pump pixels to us,
1365 * or we might hang the display.
1367 assert_planes_disabled(dev_priv, pipe);
1369 /* Don't disable pipe A or pipe A PLLs if needed */
1370 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1373 reg = PIPECONF(pipe);
1374 val = I915_READ(reg);
1375 if ((val & PIPECONF_ENABLE) == 0)
1378 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1379 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1383 * Plane regs are double buffered, going from enabled->disabled needs a
1384 * trigger in order to latch. The display address reg provides this.
1386 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1389 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1390 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1394 * intel_enable_plane - enable a display plane on a given pipe
1395 * @dev_priv: i915 private structure
1396 * @plane: plane to enable
1397 * @pipe: pipe being fed
1399 * Enable @plane on @pipe, making sure that @pipe is running first.
1401 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1402 enum plane plane, enum pipe pipe)
1407 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1408 assert_pipe_enabled(dev_priv, pipe);
1410 reg = DSPCNTR(plane);
1411 val = I915_READ(reg);
1412 if (val & DISPLAY_PLANE_ENABLE)
1415 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1416 intel_flush_display_plane(dev_priv, plane);
1417 intel_wait_for_vblank(dev_priv->dev, pipe);
1421 * intel_disable_plane - disable a display plane
1422 * @dev_priv: i915 private structure
1423 * @plane: plane to disable
1424 * @pipe: pipe consuming the data
1426 * Disable @plane; should be an independent operation.
1428 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1429 enum plane plane, enum pipe pipe)
1434 reg = DSPCNTR(plane);
1435 val = I915_READ(reg);
1436 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1439 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1440 intel_flush_display_plane(dev_priv, plane);
1441 intel_wait_for_vblank(dev_priv->dev, pipe);
1444 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1445 enum pipe pipe, int reg, u32 port_sel)
1447 u32 val = I915_READ(reg);
1448 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1449 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1450 I915_WRITE(reg, val & ~DP_PORT_EN);
1454 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1455 enum pipe pipe, int reg)
1457 u32 val = I915_READ(reg);
1458 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1459 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1461 I915_WRITE(reg, val & ~PORT_ENABLE);
1465 /* Disable any ports connected to this transcoder */
1466 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1471 val = I915_READ(PCH_PP_CONTROL);
1472 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1474 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1479 val = I915_READ(reg);
1480 if (adpa_pipe_enabled(dev_priv, pipe, val))
1481 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1484 val = I915_READ(reg);
1485 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1486 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1487 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1492 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1493 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1494 disable_pch_hdmi(dev_priv, pipe, HDMID);
1497 static void i8xx_disable_fbc(struct drm_device *dev)
1499 struct drm_i915_private *dev_priv = dev->dev_private;
1502 /* Disable compression */
1503 fbc_ctl = I915_READ(FBC_CONTROL);
1504 if ((fbc_ctl & FBC_CTL_EN) == 0)
1507 fbc_ctl &= ~FBC_CTL_EN;
1508 I915_WRITE(FBC_CONTROL, fbc_ctl);
1510 /* Wait for compressing bit to clear */
1511 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1512 DRM_DEBUG_KMS("FBC idle timed out\n");
1516 DRM_DEBUG_KMS("disabled FBC\n");
1519 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1521 struct drm_device *dev = crtc->dev;
1522 struct drm_i915_private *dev_priv = dev->dev_private;
1523 struct drm_framebuffer *fb = crtc->fb;
1524 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1525 struct drm_i915_gem_object *obj = intel_fb->obj;
1526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1529 u32 fbc_ctl, fbc_ctl2;
1531 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1532 if (fb->pitch < cfb_pitch)
1533 cfb_pitch = fb->pitch;
1535 /* FBC_CTL wants 64B units */
1536 cfb_pitch = (cfb_pitch / 64) - 1;
1537 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1539 /* Clear old tags */
1540 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1541 I915_WRITE(FBC_TAG + (i * 4), 0);
1544 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1546 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1547 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1550 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1552 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1553 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1554 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1555 fbc_ctl |= obj->fence_reg;
1556 I915_WRITE(FBC_CONTROL, fbc_ctl);
1558 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1559 cfb_pitch, crtc->y, intel_crtc->plane);
1562 static bool i8xx_fbc_enabled(struct drm_device *dev)
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1566 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1569 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1571 struct drm_device *dev = crtc->dev;
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 struct drm_framebuffer *fb = crtc->fb;
1574 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1575 struct drm_i915_gem_object *obj = intel_fb->obj;
1576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1577 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1578 unsigned long stall_watermark = 200;
1581 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1582 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1583 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1585 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1586 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1587 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1588 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1591 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1593 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1596 static void g4x_disable_fbc(struct drm_device *dev)
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1601 /* Disable compression */
1602 dpfc_ctl = I915_READ(DPFC_CONTROL);
1603 if (dpfc_ctl & DPFC_CTL_EN) {
1604 dpfc_ctl &= ~DPFC_CTL_EN;
1605 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1607 DRM_DEBUG_KMS("disabled FBC\n");
1611 static bool g4x_fbc_enabled(struct drm_device *dev)
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1615 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1618 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1623 /* Make sure blitter notifies FBC of writes */
1624 gen6_gt_force_wake_get(dev_priv);
1625 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1626 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1627 GEN6_BLITTER_LOCK_SHIFT;
1628 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1629 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1630 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1631 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1632 GEN6_BLITTER_LOCK_SHIFT);
1633 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1634 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1635 gen6_gt_force_wake_put(dev_priv);
1638 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1640 struct drm_device *dev = crtc->dev;
1641 struct drm_i915_private *dev_priv = dev->dev_private;
1642 struct drm_framebuffer *fb = crtc->fb;
1643 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1644 struct drm_i915_gem_object *obj = intel_fb->obj;
1645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1646 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1647 unsigned long stall_watermark = 200;
1650 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1651 dpfc_ctl &= DPFC_RESERVED;
1652 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1653 /* Set persistent mode for front-buffer rendering, ala X. */
1654 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1655 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1656 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1658 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1659 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1660 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1661 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1662 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1664 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1667 I915_WRITE(SNB_DPFC_CTL_SA,
1668 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1669 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1670 sandybridge_blit_fbc_update(dev);
1673 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1676 static void ironlake_disable_fbc(struct drm_device *dev)
1678 struct drm_i915_private *dev_priv = dev->dev_private;
1681 /* Disable compression */
1682 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1683 if (dpfc_ctl & DPFC_CTL_EN) {
1684 dpfc_ctl &= ~DPFC_CTL_EN;
1685 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1687 DRM_DEBUG_KMS("disabled FBC\n");
1691 static bool ironlake_fbc_enabled(struct drm_device *dev)
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1695 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1698 bool intel_fbc_enabled(struct drm_device *dev)
1700 struct drm_i915_private *dev_priv = dev->dev_private;
1702 if (!dev_priv->display.fbc_enabled)
1705 return dev_priv->display.fbc_enabled(dev);
1708 static void intel_fbc_work_fn(struct work_struct *__work)
1710 struct intel_fbc_work *work =
1711 container_of(to_delayed_work(__work),
1712 struct intel_fbc_work, work);
1713 struct drm_device *dev = work->crtc->dev;
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1716 mutex_lock(&dev->struct_mutex);
1717 if (work == dev_priv->fbc_work) {
1718 /* Double check that we haven't switched fb without cancelling
1721 if (work->crtc->fb == work->fb) {
1722 dev_priv->display.enable_fbc(work->crtc,
1725 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1726 dev_priv->cfb_fb = work->crtc->fb->base.id;
1727 dev_priv->cfb_y = work->crtc->y;
1730 dev_priv->fbc_work = NULL;
1732 mutex_unlock(&dev->struct_mutex);
1737 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1739 if (dev_priv->fbc_work == NULL)
1742 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1744 /* Synchronisation is provided by struct_mutex and checking of
1745 * dev_priv->fbc_work, so we can perform the cancellation
1746 * entirely asynchronously.
1748 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1749 /* tasklet was killed before being run, clean up */
1750 kfree(dev_priv->fbc_work);
1752 /* Mark the work as no longer wanted so that if it does
1753 * wake-up (because the work was already running and waiting
1754 * for our mutex), it will discover that is no longer
1757 dev_priv->fbc_work = NULL;
1760 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1762 struct intel_fbc_work *work;
1763 struct drm_device *dev = crtc->dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1766 if (!dev_priv->display.enable_fbc)
1769 intel_cancel_fbc_work(dev_priv);
1771 work = kzalloc(sizeof *work, GFP_KERNEL);
1773 dev_priv->display.enable_fbc(crtc, interval);
1778 work->fb = crtc->fb;
1779 work->interval = interval;
1780 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1782 dev_priv->fbc_work = work;
1784 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1786 /* Delay the actual enabling to let pageflipping cease and the
1787 * display to settle before starting the compression. Note that
1788 * this delay also serves a second purpose: it allows for a
1789 * vblank to pass after disabling the FBC before we attempt
1790 * to modify the control registers.
1792 * A more complicated solution would involve tracking vblanks
1793 * following the termination of the page-flipping sequence
1794 * and indeed performing the enable as a co-routine and not
1795 * waiting synchronously upon the vblank.
1797 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1800 void intel_disable_fbc(struct drm_device *dev)
1802 struct drm_i915_private *dev_priv = dev->dev_private;
1804 intel_cancel_fbc_work(dev_priv);
1806 if (!dev_priv->display.disable_fbc)
1809 dev_priv->display.disable_fbc(dev);
1810 dev_priv->cfb_plane = -1;
1814 * intel_update_fbc - enable/disable FBC as needed
1815 * @dev: the drm_device
1817 * Set up the framebuffer compression hardware at mode set time. We
1818 * enable it if possible:
1819 * - plane A only (on pre-965)
1820 * - no pixel mulitply/line duplication
1821 * - no alpha buffer discard
1823 * - framebuffer <= 2048 in width, 1536 in height
1825 * We can't assume that any compression will take place (worst case),
1826 * so the compressed buffer has to be the same size as the uncompressed
1827 * one. It also must reside (along with the line length buffer) in
1830 * We need to enable/disable FBC on a global basis.
1832 static void intel_update_fbc(struct drm_device *dev)
1834 struct drm_i915_private *dev_priv = dev->dev_private;
1835 struct drm_crtc *crtc = NULL, *tmp_crtc;
1836 struct intel_crtc *intel_crtc;
1837 struct drm_framebuffer *fb;
1838 struct intel_framebuffer *intel_fb;
1839 struct drm_i915_gem_object *obj;
1842 DRM_DEBUG_KMS("\n");
1844 if (!i915_powersave)
1847 if (!I915_HAS_FBC(dev))
1851 * If FBC is already on, we just have to verify that we can
1852 * keep it that way...
1853 * Need to disable if:
1854 * - more than one pipe is active
1855 * - changing FBC params (stride, fence, mode)
1856 * - new fb is too large to fit in compressed buffer
1857 * - going to an unsupported config (interlace, pixel multiply, etc.)
1859 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1860 if (tmp_crtc->enabled && tmp_crtc->fb) {
1862 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1863 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1870 if (!crtc || crtc->fb == NULL) {
1871 DRM_DEBUG_KMS("no output, disabling\n");
1872 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1876 intel_crtc = to_intel_crtc(crtc);
1878 intel_fb = to_intel_framebuffer(fb);
1879 obj = intel_fb->obj;
1881 enable_fbc = i915_enable_fbc;
1882 if (enable_fbc < 0) {
1883 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1885 if (INTEL_INFO(dev)->gen <= 6)
1889 DRM_DEBUG_KMS("fbc disabled per module param\n");
1890 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1893 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1894 DRM_DEBUG_KMS("framebuffer too large, disabling "
1896 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1899 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1900 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1901 DRM_DEBUG_KMS("mode incompatible with compression, "
1903 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1906 if ((crtc->mode.hdisplay > 2048) ||
1907 (crtc->mode.vdisplay > 1536)) {
1908 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1909 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1912 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1913 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1914 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1918 /* The use of a CPU fence is mandatory in order to detect writes
1919 * by the CPU to the scanout and trigger updates to the FBC.
1921 if (obj->tiling_mode != I915_TILING_X ||
1922 obj->fence_reg == I915_FENCE_REG_NONE) {
1923 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1924 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1928 /* If the kernel debugger is active, always disable compression */
1929 if (in_dbg_master())
1932 /* If the scanout has not changed, don't modify the FBC settings.
1933 * Note that we make the fundamental assumption that the fb->obj
1934 * cannot be unpinned (and have its GTT offset and fence revoked)
1935 * without first being decoupled from the scanout and FBC disabled.
1937 if (dev_priv->cfb_plane == intel_crtc->plane &&
1938 dev_priv->cfb_fb == fb->base.id &&
1939 dev_priv->cfb_y == crtc->y)
1942 if (intel_fbc_enabled(dev)) {
1943 /* We update FBC along two paths, after changing fb/crtc
1944 * configuration (modeswitching) and after page-flipping
1945 * finishes. For the latter, we know that not only did
1946 * we disable the FBC at the start of the page-flip
1947 * sequence, but also more than one vblank has passed.
1949 * For the former case of modeswitching, it is possible
1950 * to switch between two FBC valid configurations
1951 * instantaneously so we do need to disable the FBC
1952 * before we can modify its control registers. We also
1953 * have to wait for the next vblank for that to take
1954 * effect. However, since we delay enabling FBC we can
1955 * assume that a vblank has passed since disabling and
1956 * that we can safely alter the registers in the deferred
1959 * In the scenario that we go from a valid to invalid
1960 * and then back to valid FBC configuration we have
1961 * no strict enforcement that a vblank occurred since
1962 * disabling the FBC. However, along all current pipe
1963 * disabling paths we do need to wait for a vblank at
1964 * some point. And we wait before enabling FBC anyway.
1966 DRM_DEBUG_KMS("disabling active FBC for update\n");
1967 intel_disable_fbc(dev);
1970 intel_enable_fbc(crtc, 500);
1974 /* Multiple disables should be harmless */
1975 if (intel_fbc_enabled(dev)) {
1976 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1977 intel_disable_fbc(dev);
1982 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1983 struct drm_i915_gem_object *obj,
1984 struct intel_ring_buffer *pipelined)
1986 struct drm_i915_private *dev_priv = dev->dev_private;
1990 switch (obj->tiling_mode) {
1991 case I915_TILING_NONE:
1992 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1993 alignment = 128 * 1024;
1994 else if (INTEL_INFO(dev)->gen >= 4)
1995 alignment = 4 * 1024;
1997 alignment = 64 * 1024;
2000 /* pin() will align the object as required by fence */
2004 /* FIXME: Is this true? */
2005 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2011 dev_priv->mm.interruptible = false;
2012 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2014 goto err_interruptible;
2016 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2017 * fence, whereas 965+ only requires a fence if using
2018 * framebuffer compression. For simplicity, we always install
2019 * a fence as the cost is not that onerous.
2021 if (obj->tiling_mode != I915_TILING_NONE) {
2022 ret = i915_gem_object_get_fence(obj, pipelined);
2027 dev_priv->mm.interruptible = true;
2031 i915_gem_object_unpin(obj);
2033 dev_priv->mm.interruptible = true;
2037 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2040 struct drm_device *dev = crtc->dev;
2041 struct drm_i915_private *dev_priv = dev->dev_private;
2042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2043 struct intel_framebuffer *intel_fb;
2044 struct drm_i915_gem_object *obj;
2045 int plane = intel_crtc->plane;
2046 unsigned long Start, Offset;
2055 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2059 intel_fb = to_intel_framebuffer(fb);
2060 obj = intel_fb->obj;
2062 reg = DSPCNTR(plane);
2063 dspcntr = I915_READ(reg);
2064 /* Mask out pixel format bits in case we change it */
2065 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2066 switch (fb->bits_per_pixel) {
2068 dspcntr |= DISPPLANE_8BPP;
2071 if (fb->depth == 15)
2072 dspcntr |= DISPPLANE_15_16BPP;
2074 dspcntr |= DISPPLANE_16BPP;
2078 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2081 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2084 if (INTEL_INFO(dev)->gen >= 4) {
2085 if (obj->tiling_mode != I915_TILING_NONE)
2086 dspcntr |= DISPPLANE_TILED;
2088 dspcntr &= ~DISPPLANE_TILED;
2091 I915_WRITE(reg, dspcntr);
2093 Start = obj->gtt_offset;
2094 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2096 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2097 Start, Offset, x, y, fb->pitch);
2098 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2099 if (INTEL_INFO(dev)->gen >= 4) {
2100 I915_WRITE(DSPSURF(plane), Start);
2101 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2102 I915_WRITE(DSPADDR(plane), Offset);
2104 I915_WRITE(DSPADDR(plane), Start + Offset);
2110 static int ironlake_update_plane(struct drm_crtc *crtc,
2111 struct drm_framebuffer *fb, int x, int y)
2113 struct drm_device *dev = crtc->dev;
2114 struct drm_i915_private *dev_priv = dev->dev_private;
2115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2116 struct intel_framebuffer *intel_fb;
2117 struct drm_i915_gem_object *obj;
2118 int plane = intel_crtc->plane;
2119 unsigned long Start, Offset;
2129 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2133 intel_fb = to_intel_framebuffer(fb);
2134 obj = intel_fb->obj;
2136 reg = DSPCNTR(plane);
2137 dspcntr = I915_READ(reg);
2138 /* Mask out pixel format bits in case we change it */
2139 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2140 switch (fb->bits_per_pixel) {
2142 dspcntr |= DISPPLANE_8BPP;
2145 if (fb->depth != 16)
2148 dspcntr |= DISPPLANE_16BPP;
2152 if (fb->depth == 24)
2153 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2154 else if (fb->depth == 30)
2155 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2160 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2164 if (obj->tiling_mode != I915_TILING_NONE)
2165 dspcntr |= DISPPLANE_TILED;
2167 dspcntr &= ~DISPPLANE_TILED;
2170 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2172 I915_WRITE(reg, dspcntr);
2174 Start = obj->gtt_offset;
2175 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2177 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2178 Start, Offset, x, y, fb->pitch);
2179 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2180 I915_WRITE(DSPSURF(plane), Start);
2181 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2182 I915_WRITE(DSPADDR(plane), Offset);
2188 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2190 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2191 int x, int y, enum mode_set_atomic state)
2193 struct drm_device *dev = crtc->dev;
2194 struct drm_i915_private *dev_priv = dev->dev_private;
2197 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2201 intel_update_fbc(dev);
2202 intel_increase_pllclock(crtc);
2208 intel_finish_fb(struct drm_framebuffer *old_fb)
2210 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2211 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2212 bool was_interruptible = dev_priv->mm.interruptible;
2215 wait_event(dev_priv->pending_flip_queue,
2216 atomic_read(&dev_priv->mm.wedged) ||
2217 atomic_read(&obj->pending_flip) == 0);
2219 /* Big Hammer, we also need to ensure that any pending
2220 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2221 * current scanout is retired before unpinning the old
2224 * This should only fail upon a hung GPU, in which case we
2225 * can safely continue.
2227 dev_priv->mm.interruptible = false;
2228 ret = i915_gem_object_finish_gpu(obj);
2229 dev_priv->mm.interruptible = was_interruptible;
2235 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2236 struct drm_framebuffer *old_fb)
2238 struct drm_device *dev = crtc->dev;
2239 struct drm_i915_master_private *master_priv;
2240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2245 DRM_ERROR("No FB bound\n");
2249 switch (intel_crtc->plane) {
2254 if (IS_IVYBRIDGE(dev))
2256 /* fall through otherwise */
2258 DRM_ERROR("no plane for crtc\n");
2262 mutex_lock(&dev->struct_mutex);
2263 ret = intel_pin_and_fence_fb_obj(dev,
2264 to_intel_framebuffer(crtc->fb)->obj,
2267 mutex_unlock(&dev->struct_mutex);
2268 DRM_ERROR("pin & fence failed\n");
2273 intel_finish_fb(old_fb);
2275 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2276 LEAVE_ATOMIC_MODE_SET);
2278 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2279 mutex_unlock(&dev->struct_mutex);
2280 DRM_ERROR("failed to update base address\n");
2285 intel_wait_for_vblank(dev, intel_crtc->pipe);
2286 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2289 mutex_unlock(&dev->struct_mutex);
2291 if (!dev->primary->master)
2294 master_priv = dev->primary->master->driver_priv;
2295 if (!master_priv->sarea_priv)
2298 if (intel_crtc->pipe) {
2299 master_priv->sarea_priv->pipeB_x = x;
2300 master_priv->sarea_priv->pipeB_y = y;
2302 master_priv->sarea_priv->pipeA_x = x;
2303 master_priv->sarea_priv->pipeA_y = y;
2309 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2315 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2316 dpa_ctl = I915_READ(DP_A);
2317 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2319 if (clock < 200000) {
2321 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2322 /* workaround for 160Mhz:
2323 1) program 0x4600c bits 15:0 = 0x8124
2324 2) program 0x46010 bit 0 = 1
2325 3) program 0x46034 bit 24 = 1
2326 4) program 0x64000 bit 14 = 1
2328 temp = I915_READ(0x4600c);
2330 I915_WRITE(0x4600c, temp | 0x8124);
2332 temp = I915_READ(0x46010);
2333 I915_WRITE(0x46010, temp | 1);
2335 temp = I915_READ(0x46034);
2336 I915_WRITE(0x46034, temp | (1 << 24));
2338 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2340 I915_WRITE(DP_A, dpa_ctl);
2346 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2348 struct drm_device *dev = crtc->dev;
2349 struct drm_i915_private *dev_priv = dev->dev_private;
2350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2351 int pipe = intel_crtc->pipe;
2354 /* enable normal train */
2355 reg = FDI_TX_CTL(pipe);
2356 temp = I915_READ(reg);
2357 if (IS_IVYBRIDGE(dev)) {
2358 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2359 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2361 temp &= ~FDI_LINK_TRAIN_NONE;
2362 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2364 I915_WRITE(reg, temp);
2366 reg = FDI_RX_CTL(pipe);
2367 temp = I915_READ(reg);
2368 if (HAS_PCH_CPT(dev)) {
2369 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2370 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2372 temp &= ~FDI_LINK_TRAIN_NONE;
2373 temp |= FDI_LINK_TRAIN_NONE;
2375 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2377 /* wait one idle pattern time */
2381 /* IVB wants error correction enabled */
2382 if (IS_IVYBRIDGE(dev))
2383 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2384 FDI_FE_ERRC_ENABLE);
2387 /* The FDI link training functions for ILK/Ibexpeak. */
2388 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2390 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 int pipe = intel_crtc->pipe;
2394 int plane = intel_crtc->plane;
2395 u32 reg, temp, tries;
2397 /* FDI needs bits from pipe & plane first */
2398 assert_pipe_enabled(dev_priv, pipe);
2399 assert_plane_enabled(dev_priv, plane);
2401 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2403 reg = FDI_RX_IMR(pipe);
2404 temp = I915_READ(reg);
2405 temp &= ~FDI_RX_SYMBOL_LOCK;
2406 temp &= ~FDI_RX_BIT_LOCK;
2407 I915_WRITE(reg, temp);
2411 /* enable CPU FDI TX and PCH FDI RX */
2412 reg = FDI_TX_CTL(pipe);
2413 temp = I915_READ(reg);
2415 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2416 temp &= ~FDI_LINK_TRAIN_NONE;
2417 temp |= FDI_LINK_TRAIN_PATTERN_1;
2418 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2420 reg = FDI_RX_CTL(pipe);
2421 temp = I915_READ(reg);
2422 temp &= ~FDI_LINK_TRAIN_NONE;
2423 temp |= FDI_LINK_TRAIN_PATTERN_1;
2424 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2429 /* Ironlake workaround, enable clock pointer after FDI enable*/
2430 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2431 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2432 FDI_RX_PHASE_SYNC_POINTER_EN);
2434 reg = FDI_RX_IIR(pipe);
2435 for (tries = 0; tries < 5; tries++) {
2436 temp = I915_READ(reg);
2437 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2439 if ((temp & FDI_RX_BIT_LOCK)) {
2440 DRM_DEBUG_KMS("FDI train 1 done.\n");
2441 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2446 DRM_ERROR("FDI train 1 fail!\n");
2449 reg = FDI_TX_CTL(pipe);
2450 temp = I915_READ(reg);
2451 temp &= ~FDI_LINK_TRAIN_NONE;
2452 temp |= FDI_LINK_TRAIN_PATTERN_2;
2453 I915_WRITE(reg, temp);
2455 reg = FDI_RX_CTL(pipe);
2456 temp = I915_READ(reg);
2457 temp &= ~FDI_LINK_TRAIN_NONE;
2458 temp |= FDI_LINK_TRAIN_PATTERN_2;
2459 I915_WRITE(reg, temp);
2464 reg = FDI_RX_IIR(pipe);
2465 for (tries = 0; tries < 5; tries++) {
2466 temp = I915_READ(reg);
2467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2469 if (temp & FDI_RX_SYMBOL_LOCK) {
2470 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2471 DRM_DEBUG_KMS("FDI train 2 done.\n");
2476 DRM_ERROR("FDI train 2 fail!\n");
2478 DRM_DEBUG_KMS("FDI train done\n");
2482 static const int snb_b_fdi_train_param[] = {
2483 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2484 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2485 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2486 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2489 /* The FDI link training functions for SNB/Cougarpoint. */
2490 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2492 struct drm_device *dev = crtc->dev;
2493 struct drm_i915_private *dev_priv = dev->dev_private;
2494 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2495 int pipe = intel_crtc->pipe;
2498 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2500 reg = FDI_RX_IMR(pipe);
2501 temp = I915_READ(reg);
2502 temp &= ~FDI_RX_SYMBOL_LOCK;
2503 temp &= ~FDI_RX_BIT_LOCK;
2504 I915_WRITE(reg, temp);
2509 /* enable CPU FDI TX and PCH FDI RX */
2510 reg = FDI_TX_CTL(pipe);
2511 temp = I915_READ(reg);
2513 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2514 temp &= ~FDI_LINK_TRAIN_NONE;
2515 temp |= FDI_LINK_TRAIN_PATTERN_1;
2516 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2518 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2519 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2521 reg = FDI_RX_CTL(pipe);
2522 temp = I915_READ(reg);
2523 if (HAS_PCH_CPT(dev)) {
2524 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2525 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2527 temp &= ~FDI_LINK_TRAIN_NONE;
2528 temp |= FDI_LINK_TRAIN_PATTERN_1;
2530 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2535 for (i = 0; i < 4; i++) {
2536 reg = FDI_TX_CTL(pipe);
2537 temp = I915_READ(reg);
2538 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2539 temp |= snb_b_fdi_train_param[i];
2540 I915_WRITE(reg, temp);
2545 reg = FDI_RX_IIR(pipe);
2546 temp = I915_READ(reg);
2547 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2549 if (temp & FDI_RX_BIT_LOCK) {
2550 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2551 DRM_DEBUG_KMS("FDI train 1 done.\n");
2556 DRM_ERROR("FDI train 1 fail!\n");
2559 reg = FDI_TX_CTL(pipe);
2560 temp = I915_READ(reg);
2561 temp &= ~FDI_LINK_TRAIN_NONE;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2;
2564 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2568 I915_WRITE(reg, temp);
2570 reg = FDI_RX_CTL(pipe);
2571 temp = I915_READ(reg);
2572 if (HAS_PCH_CPT(dev)) {
2573 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2574 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2576 temp &= ~FDI_LINK_TRAIN_NONE;
2577 temp |= FDI_LINK_TRAIN_PATTERN_2;
2579 I915_WRITE(reg, temp);
2584 for (i = 0; i < 4; i++) {
2585 reg = FDI_TX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 temp |= snb_b_fdi_train_param[i];
2589 I915_WRITE(reg, temp);
2594 reg = FDI_RX_IIR(pipe);
2595 temp = I915_READ(reg);
2596 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2598 if (temp & FDI_RX_SYMBOL_LOCK) {
2599 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2600 DRM_DEBUG_KMS("FDI train 2 done.\n");
2605 DRM_ERROR("FDI train 2 fail!\n");
2607 DRM_DEBUG_KMS("FDI train done.\n");
2610 /* Manual link training for Ivy Bridge A0 parts */
2611 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2613 struct drm_device *dev = crtc->dev;
2614 struct drm_i915_private *dev_priv = dev->dev_private;
2615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2616 int pipe = intel_crtc->pipe;
2619 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2621 reg = FDI_RX_IMR(pipe);
2622 temp = I915_READ(reg);
2623 temp &= ~FDI_RX_SYMBOL_LOCK;
2624 temp &= ~FDI_RX_BIT_LOCK;
2625 I915_WRITE(reg, temp);
2630 /* enable CPU FDI TX and PCH FDI RX */
2631 reg = FDI_TX_CTL(pipe);
2632 temp = I915_READ(reg);
2634 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2635 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2636 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2637 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2639 temp |= FDI_COMPOSITE_SYNC;
2640 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2642 reg = FDI_RX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_LINK_TRAIN_AUTO;
2645 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2647 temp |= FDI_COMPOSITE_SYNC;
2648 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2653 for (i = 0; i < 4; i++) {
2654 reg = FDI_TX_CTL(pipe);
2655 temp = I915_READ(reg);
2656 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657 temp |= snb_b_fdi_train_param[i];
2658 I915_WRITE(reg, temp);
2663 reg = FDI_RX_IIR(pipe);
2664 temp = I915_READ(reg);
2665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2667 if (temp & FDI_RX_BIT_LOCK ||
2668 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2669 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2670 DRM_DEBUG_KMS("FDI train 1 done.\n");
2675 DRM_ERROR("FDI train 1 fail!\n");
2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2681 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2684 I915_WRITE(reg, temp);
2686 reg = FDI_RX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2689 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2690 I915_WRITE(reg, temp);
2695 for (i = 0; i < 4; i++) {
2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699 temp |= snb_b_fdi_train_param[i];
2700 I915_WRITE(reg, temp);
2705 reg = FDI_RX_IIR(pipe);
2706 temp = I915_READ(reg);
2707 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709 if (temp & FDI_RX_SYMBOL_LOCK) {
2710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711 DRM_DEBUG_KMS("FDI train 2 done.\n");
2716 DRM_ERROR("FDI train 2 fail!\n");
2718 DRM_DEBUG_KMS("FDI train done.\n");
2721 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2723 struct drm_device *dev = crtc->dev;
2724 struct drm_i915_private *dev_priv = dev->dev_private;
2725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726 int pipe = intel_crtc->pipe;
2729 /* Write the TU size bits so error detection works */
2730 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2731 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2733 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2734 reg = FDI_RX_CTL(pipe);
2735 temp = I915_READ(reg);
2736 temp &= ~((0x7 << 19) | (0x7 << 16));
2737 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2738 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2739 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2744 /* Switch from Rawclk to PCDclk */
2745 temp = I915_READ(reg);
2746 I915_WRITE(reg, temp | FDI_PCDCLK);
2751 /* Enable CPU FDI TX PLL, always on for Ironlake */
2752 reg = FDI_TX_CTL(pipe);
2753 temp = I915_READ(reg);
2754 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2755 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2762 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2764 struct drm_device *dev = crtc->dev;
2765 struct drm_i915_private *dev_priv = dev->dev_private;
2766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2767 int pipe = intel_crtc->pipe;
2770 /* disable CPU FDI tx and PCH FDI rx */
2771 reg = FDI_TX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 temp &= ~(0x7 << 16);
2779 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2780 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2785 /* Ironlake workaround, disable clock pointer after downing FDI */
2786 if (HAS_PCH_IBX(dev)) {
2787 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2788 I915_WRITE(FDI_RX_CHICKEN(pipe),
2789 I915_READ(FDI_RX_CHICKEN(pipe) &
2790 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2793 /* still set train pattern 1 */
2794 reg = FDI_TX_CTL(pipe);
2795 temp = I915_READ(reg);
2796 temp &= ~FDI_LINK_TRAIN_NONE;
2797 temp |= FDI_LINK_TRAIN_PATTERN_1;
2798 I915_WRITE(reg, temp);
2800 reg = FDI_RX_CTL(pipe);
2801 temp = I915_READ(reg);
2802 if (HAS_PCH_CPT(dev)) {
2803 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2804 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2806 temp &= ~FDI_LINK_TRAIN_NONE;
2807 temp |= FDI_LINK_TRAIN_PATTERN_1;
2809 /* BPC in FDI rx is consistent with that in PIPECONF */
2810 temp &= ~(0x07 << 16);
2811 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2812 I915_WRITE(reg, temp);
2819 * When we disable a pipe, we need to clear any pending scanline wait events
2820 * to avoid hanging the ring, which we assume we are waiting on.
2822 static void intel_clear_scanline_wait(struct drm_device *dev)
2824 struct drm_i915_private *dev_priv = dev->dev_private;
2825 struct intel_ring_buffer *ring;
2829 /* Can't break the hang on i8xx */
2832 ring = LP_RING(dev_priv);
2833 tmp = I915_READ_CTL(ring);
2834 if (tmp & RING_WAIT)
2835 I915_WRITE_CTL(ring, tmp);
2838 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2840 struct drm_device *dev = crtc->dev;
2841 struct drm_i915_private *dev_priv = dev->dev_private;
2842 unsigned long flags;
2845 if (atomic_read(&dev_priv->mm.wedged))
2848 spin_lock_irqsave(&dev->event_lock, flags);
2849 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2850 spin_unlock_irqrestore(&dev->event_lock, flags);
2855 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2857 struct drm_device *dev = crtc->dev;
2858 struct drm_i915_private *dev_priv = dev->dev_private;
2860 if (crtc->fb == NULL)
2863 wait_event(dev_priv->pending_flip_queue,
2864 !intel_crtc_has_pending_flip(crtc));
2866 mutex_lock(&dev->struct_mutex);
2867 intel_finish_fb(crtc->fb);
2868 mutex_unlock(&dev->struct_mutex);
2871 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2873 struct drm_device *dev = crtc->dev;
2874 struct drm_mode_config *mode_config = &dev->mode_config;
2875 struct intel_encoder *encoder;
2878 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2879 * must be driven by its own crtc; no sharing is possible.
2881 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2882 if (encoder->base.crtc != crtc)
2885 switch (encoder->type) {
2886 case INTEL_OUTPUT_EDP:
2887 if (!intel_encoder_is_pch_edp(&encoder->base))
2897 * Enable PCH resources required for PCH ports:
2899 * - FDI training & RX/TX
2900 * - update transcoder timings
2901 * - DP transcoding bits
2904 static void ironlake_pch_enable(struct drm_crtc *crtc)
2906 struct drm_device *dev = crtc->dev;
2907 struct drm_i915_private *dev_priv = dev->dev_private;
2908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2909 int pipe = intel_crtc->pipe;
2910 u32 reg, temp, transc_sel;
2912 /* For PCH output, training FDI link */
2913 dev_priv->display.fdi_link_train(crtc);
2915 intel_enable_pch_pll(dev_priv, pipe);
2917 if (HAS_PCH_CPT(dev)) {
2918 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2921 /* Be sure PCH DPLL SEL is set */
2922 temp = I915_READ(PCH_DPLL_SEL);
2924 temp &= ~(TRANSA_DPLLB_SEL);
2925 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2926 } else if (pipe == 1) {
2927 temp &= ~(TRANSB_DPLLB_SEL);
2928 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2929 } else if (pipe == 2) {
2930 temp &= ~(TRANSC_DPLLB_SEL);
2931 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2933 I915_WRITE(PCH_DPLL_SEL, temp);
2936 /* set transcoder timing, panel must allow it */
2937 assert_panel_unlocked(dev_priv, pipe);
2938 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2939 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2940 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2942 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2943 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2944 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2946 intel_fdi_normal_train(crtc);
2948 /* For PCH DP, enable TRANS_DP_CTL */
2949 if (HAS_PCH_CPT(dev) &&
2950 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2951 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2952 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2953 reg = TRANS_DP_CTL(pipe);
2954 temp = I915_READ(reg);
2955 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2956 TRANS_DP_SYNC_MASK |
2958 temp |= (TRANS_DP_OUTPUT_ENABLE |
2959 TRANS_DP_ENH_FRAMING);
2960 temp |= bpc << 9; /* same format but at 11:9 */
2962 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2963 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2964 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2965 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2967 switch (intel_trans_dp_port_sel(crtc)) {
2969 temp |= TRANS_DP_PORT_SEL_B;
2972 temp |= TRANS_DP_PORT_SEL_C;
2975 temp |= TRANS_DP_PORT_SEL_D;
2978 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2979 temp |= TRANS_DP_PORT_SEL_B;
2983 I915_WRITE(reg, temp);
2986 intel_enable_transcoder(dev_priv, pipe);
2989 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2991 struct drm_i915_private *dev_priv = dev->dev_private;
2992 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2995 temp = I915_READ(dslreg);
2997 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2998 /* Without this, mode sets may fail silently on FDI */
2999 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3001 I915_WRITE(tc2reg, 0);
3002 if (wait_for(I915_READ(dslreg) != temp, 5))
3003 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3007 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3009 struct drm_device *dev = crtc->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3012 int pipe = intel_crtc->pipe;
3013 int plane = intel_crtc->plane;
3017 if (intel_crtc->active)
3020 intel_crtc->active = true;
3021 intel_update_watermarks(dev);
3023 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3024 temp = I915_READ(PCH_LVDS);
3025 if ((temp & LVDS_PORT_EN) == 0)
3026 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3029 is_pch_port = intel_crtc_driving_pch(crtc);
3032 ironlake_fdi_pll_enable(crtc);
3034 ironlake_fdi_disable(crtc);
3036 /* Enable panel fitting for LVDS */
3037 if (dev_priv->pch_pf_size &&
3038 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3039 /* Force use of hard-coded filter coefficients
3040 * as some pre-programmed values are broken,
3043 if (IS_IVYBRIDGE(dev))
3044 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3045 PF_PIPE_SEL_IVB(pipe));
3047 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3048 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3049 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3053 * On ILK+ LUT must be loaded before the pipe is running but with
3056 intel_crtc_load_lut(crtc);
3058 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3059 intel_enable_plane(dev_priv, plane, pipe);
3062 ironlake_pch_enable(crtc);
3064 mutex_lock(&dev->struct_mutex);
3065 intel_update_fbc(dev);
3066 mutex_unlock(&dev->struct_mutex);
3068 intel_crtc_update_cursor(crtc, true);
3071 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3073 struct drm_device *dev = crtc->dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076 int pipe = intel_crtc->pipe;
3077 int plane = intel_crtc->plane;
3080 if (!intel_crtc->active)
3083 intel_crtc_wait_for_pending_flips(crtc);
3084 drm_vblank_off(dev, pipe);
3085 intel_crtc_update_cursor(crtc, false);
3087 intel_disable_plane(dev_priv, plane, pipe);
3089 if (dev_priv->cfb_plane == plane)
3090 intel_disable_fbc(dev);
3092 intel_disable_pipe(dev_priv, pipe);
3095 I915_WRITE(PF_CTL(pipe), 0);
3096 I915_WRITE(PF_WIN_SZ(pipe), 0);
3098 ironlake_fdi_disable(crtc);
3100 /* This is a horrible layering violation; we should be doing this in
3101 * the connector/encoder ->prepare instead, but we don't always have
3102 * enough information there about the config to know whether it will
3103 * actually be necessary or just cause undesired flicker.
3105 intel_disable_pch_ports(dev_priv, pipe);
3107 intel_disable_transcoder(dev_priv, pipe);
3109 if (HAS_PCH_CPT(dev)) {
3110 /* disable TRANS_DP_CTL */
3111 reg = TRANS_DP_CTL(pipe);
3112 temp = I915_READ(reg);
3113 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3114 temp |= TRANS_DP_PORT_SEL_NONE;
3115 I915_WRITE(reg, temp);
3117 /* disable DPLL_SEL */
3118 temp = I915_READ(PCH_DPLL_SEL);
3121 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3124 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3127 /* C shares PLL A or B */
3128 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3133 I915_WRITE(PCH_DPLL_SEL, temp);
3136 /* disable PCH DPLL */
3137 if (!intel_crtc->no_pll)
3138 intel_disable_pch_pll(dev_priv, pipe);
3140 /* Switch from PCDclk to Rawclk */
3141 reg = FDI_RX_CTL(pipe);
3142 temp = I915_READ(reg);
3143 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3145 /* Disable CPU FDI TX PLL */
3146 reg = FDI_TX_CTL(pipe);
3147 temp = I915_READ(reg);
3148 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3153 reg = FDI_RX_CTL(pipe);
3154 temp = I915_READ(reg);
3155 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3157 /* Wait for the clocks to turn off. */
3161 intel_crtc->active = false;
3162 intel_update_watermarks(dev);
3164 mutex_lock(&dev->struct_mutex);
3165 intel_update_fbc(dev);
3166 intel_clear_scanline_wait(dev);
3167 mutex_unlock(&dev->struct_mutex);
3170 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3173 int pipe = intel_crtc->pipe;
3174 int plane = intel_crtc->plane;
3176 /* XXX: When our outputs are all unaware of DPMS modes other than off
3177 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3180 case DRM_MODE_DPMS_ON:
3181 case DRM_MODE_DPMS_STANDBY:
3182 case DRM_MODE_DPMS_SUSPEND:
3183 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3184 ironlake_crtc_enable(crtc);
3187 case DRM_MODE_DPMS_OFF:
3188 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3189 ironlake_crtc_disable(crtc);
3194 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3196 if (!enable && intel_crtc->overlay) {
3197 struct drm_device *dev = intel_crtc->base.dev;
3198 struct drm_i915_private *dev_priv = dev->dev_private;
3200 mutex_lock(&dev->struct_mutex);
3201 dev_priv->mm.interruptible = false;
3202 (void) intel_overlay_switch_off(intel_crtc->overlay);
3203 dev_priv->mm.interruptible = true;
3204 mutex_unlock(&dev->struct_mutex);
3207 /* Let userspace switch the overlay on again. In most cases userspace
3208 * has to recompute where to put it anyway.
3212 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3214 struct drm_device *dev = crtc->dev;
3215 struct drm_i915_private *dev_priv = dev->dev_private;
3216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3217 int pipe = intel_crtc->pipe;
3218 int plane = intel_crtc->plane;
3220 if (intel_crtc->active)
3223 intel_crtc->active = true;
3224 intel_update_watermarks(dev);
3226 intel_enable_pll(dev_priv, pipe);
3227 intel_enable_pipe(dev_priv, pipe, false);
3228 intel_enable_plane(dev_priv, plane, pipe);
3230 intel_crtc_load_lut(crtc);
3231 intel_update_fbc(dev);
3233 /* Give the overlay scaler a chance to enable if it's on this pipe */
3234 intel_crtc_dpms_overlay(intel_crtc, true);
3235 intel_crtc_update_cursor(crtc, true);
3238 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3240 struct drm_device *dev = crtc->dev;
3241 struct drm_i915_private *dev_priv = dev->dev_private;
3242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243 int pipe = intel_crtc->pipe;
3244 int plane = intel_crtc->plane;
3247 if (!intel_crtc->active)
3250 /* Give the overlay scaler a chance to disable if it's on this pipe */
3251 intel_crtc_wait_for_pending_flips(crtc);
3252 drm_vblank_off(dev, pipe);
3253 intel_crtc_dpms_overlay(intel_crtc, false);
3254 intel_crtc_update_cursor(crtc, false);
3256 if (dev_priv->cfb_plane == plane)
3257 intel_disable_fbc(dev);
3259 intel_disable_plane(dev_priv, plane, pipe);
3260 intel_disable_pipe(dev_priv, pipe);
3262 /* Disable pannel fitter if it is on this pipe. */
3263 pctl = I915_READ(PFIT_CONTROL);
3264 if ((pctl & PFIT_ENABLE) &&
3265 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3266 I915_WRITE(PFIT_CONTROL, 0);
3268 intel_disable_pll(dev_priv, pipe);
3270 intel_crtc->active = false;
3271 intel_update_fbc(dev);
3272 intel_update_watermarks(dev);
3273 intel_clear_scanline_wait(dev);
3276 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3278 /* XXX: When our outputs are all unaware of DPMS modes other than off
3279 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3282 case DRM_MODE_DPMS_ON:
3283 case DRM_MODE_DPMS_STANDBY:
3284 case DRM_MODE_DPMS_SUSPEND:
3285 i9xx_crtc_enable(crtc);
3287 case DRM_MODE_DPMS_OFF:
3288 i9xx_crtc_disable(crtc);
3294 * Sets the power management mode of the pipe and plane.
3296 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3298 struct drm_device *dev = crtc->dev;
3299 struct drm_i915_private *dev_priv = dev->dev_private;
3300 struct drm_i915_master_private *master_priv;
3301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3302 int pipe = intel_crtc->pipe;
3305 if (intel_crtc->dpms_mode == mode)
3308 intel_crtc->dpms_mode = mode;
3310 dev_priv->display.dpms(crtc, mode);
3312 if (!dev->primary->master)
3315 master_priv = dev->primary->master->driver_priv;
3316 if (!master_priv->sarea_priv)
3319 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3323 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3324 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3327 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3328 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3331 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3336 static void intel_crtc_disable(struct drm_crtc *crtc)
3338 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3339 struct drm_device *dev = crtc->dev;
3341 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3344 mutex_lock(&dev->struct_mutex);
3345 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3346 mutex_unlock(&dev->struct_mutex);
3350 /* Prepare for a mode set.
3352 * Note we could be a lot smarter here. We need to figure out which outputs
3353 * will be enabled, which disabled (in short, how the config will changes)
3354 * and perform the minimum necessary steps to accomplish that, e.g. updating
3355 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3356 * panel fitting is in the proper state, etc.
3358 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3360 i9xx_crtc_disable(crtc);
3363 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3365 i9xx_crtc_enable(crtc);
3368 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3370 ironlake_crtc_disable(crtc);
3373 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3375 ironlake_crtc_enable(crtc);
3378 void intel_encoder_prepare(struct drm_encoder *encoder)
3380 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3381 /* lvds has its own version of prepare see intel_lvds_prepare */
3382 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3385 void intel_encoder_commit(struct drm_encoder *encoder)
3387 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3388 struct drm_device *dev = encoder->dev;
3389 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3390 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3392 /* lvds has its own version of commit see intel_lvds_commit */
3393 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3395 if (HAS_PCH_CPT(dev))
3396 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3399 void intel_encoder_destroy(struct drm_encoder *encoder)
3401 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3403 drm_encoder_cleanup(encoder);
3404 kfree(intel_encoder);
3407 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3408 struct drm_display_mode *mode,
3409 struct drm_display_mode *adjusted_mode)
3411 struct drm_device *dev = crtc->dev;
3413 if (HAS_PCH_SPLIT(dev)) {
3414 /* FDI link clock is fixed at 2.7G */
3415 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3419 /* XXX some encoders set the crtcinfo, others don't.
3420 * Obviously we need some form of conflict resolution here...
3422 if (adjusted_mode->crtc_htotal == 0)
3423 drm_mode_set_crtcinfo(adjusted_mode, 0);
3428 static int i945_get_display_clock_speed(struct drm_device *dev)
3433 static int i915_get_display_clock_speed(struct drm_device *dev)
3438 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3443 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3447 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3449 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3452 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3453 case GC_DISPLAY_CLOCK_333_MHZ:
3456 case GC_DISPLAY_CLOCK_190_200_MHZ:
3462 static int i865_get_display_clock_speed(struct drm_device *dev)
3467 static int i855_get_display_clock_speed(struct drm_device *dev)
3470 /* Assume that the hardware is in the high speed state. This
3471 * should be the default.
3473 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3474 case GC_CLOCK_133_200:
3475 case GC_CLOCK_100_200:
3477 case GC_CLOCK_166_250:
3479 case GC_CLOCK_100_133:
3483 /* Shouldn't happen */
3487 static int i830_get_display_clock_speed(struct drm_device *dev)
3501 fdi_reduce_ratio(u32 *num, u32 *den)
3503 while (*num > 0xffffff || *den > 0xffffff) {
3510 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3511 int link_clock, struct fdi_m_n *m_n)
3513 m_n->tu = 64; /* default size */
3515 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3516 m_n->gmch_m = bits_per_pixel * pixel_clock;
3517 m_n->gmch_n = link_clock * nlanes * 8;
3518 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3520 m_n->link_m = pixel_clock;
3521 m_n->link_n = link_clock;
3522 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3526 struct intel_watermark_params {
3527 unsigned long fifo_size;
3528 unsigned long max_wm;
3529 unsigned long default_wm;
3530 unsigned long guard_size;
3531 unsigned long cacheline_size;
3534 /* Pineview has different values for various configs */
3535 static const struct intel_watermark_params pineview_display_wm = {
3536 PINEVIEW_DISPLAY_FIFO,
3540 PINEVIEW_FIFO_LINE_SIZE
3542 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3543 PINEVIEW_DISPLAY_FIFO,
3545 PINEVIEW_DFT_HPLLOFF_WM,
3547 PINEVIEW_FIFO_LINE_SIZE
3549 static const struct intel_watermark_params pineview_cursor_wm = {
3550 PINEVIEW_CURSOR_FIFO,
3551 PINEVIEW_CURSOR_MAX_WM,
3552 PINEVIEW_CURSOR_DFT_WM,
3553 PINEVIEW_CURSOR_GUARD_WM,
3554 PINEVIEW_FIFO_LINE_SIZE,
3556 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3557 PINEVIEW_CURSOR_FIFO,
3558 PINEVIEW_CURSOR_MAX_WM,
3559 PINEVIEW_CURSOR_DFT_WM,
3560 PINEVIEW_CURSOR_GUARD_WM,
3561 PINEVIEW_FIFO_LINE_SIZE
3563 static const struct intel_watermark_params g4x_wm_info = {
3570 static const struct intel_watermark_params g4x_cursor_wm_info = {
3577 static const struct intel_watermark_params i965_cursor_wm_info = {
3582 I915_FIFO_LINE_SIZE,
3584 static const struct intel_watermark_params i945_wm_info = {
3591 static const struct intel_watermark_params i915_wm_info = {
3598 static const struct intel_watermark_params i855_wm_info = {
3605 static const struct intel_watermark_params i830_wm_info = {
3613 static const struct intel_watermark_params ironlake_display_wm_info = {
3620 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3627 static const struct intel_watermark_params ironlake_display_srwm_info = {
3628 ILK_DISPLAY_SR_FIFO,
3629 ILK_DISPLAY_MAX_SRWM,
3630 ILK_DISPLAY_DFT_SRWM,
3634 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3636 ILK_CURSOR_MAX_SRWM,
3637 ILK_CURSOR_DFT_SRWM,
3642 static const struct intel_watermark_params sandybridge_display_wm_info = {
3649 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3656 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3657 SNB_DISPLAY_SR_FIFO,
3658 SNB_DISPLAY_MAX_SRWM,
3659 SNB_DISPLAY_DFT_SRWM,
3663 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3665 SNB_CURSOR_MAX_SRWM,
3666 SNB_CURSOR_DFT_SRWM,
3673 * intel_calculate_wm - calculate watermark level
3674 * @clock_in_khz: pixel clock
3675 * @wm: chip FIFO params
3676 * @pixel_size: display pixel size
3677 * @latency_ns: memory latency for the platform
3679 * Calculate the watermark level (the level at which the display plane will
3680 * start fetching from memory again). Each chip has a different display
3681 * FIFO size and allocation, so the caller needs to figure that out and pass
3682 * in the correct intel_watermark_params structure.
3684 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3685 * on the pixel size. When it reaches the watermark level, it'll start
3686 * fetching FIFO line sized based chunks from memory until the FIFO fills
3687 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3688 * will occur, and a display engine hang could result.
3690 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3691 const struct intel_watermark_params *wm,
3694 unsigned long latency_ns)
3696 long entries_required, wm_size;
3699 * Note: we need to make sure we don't overflow for various clock &
3701 * clocks go from a few thousand to several hundred thousand.
3702 * latency is usually a few thousand
3704 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3706 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3708 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3710 wm_size = fifo_size - (entries_required + wm->guard_size);
3712 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3714 /* Don't promote wm_size to unsigned... */
3715 if (wm_size > (long)wm->max_wm)
3716 wm_size = wm->max_wm;
3718 wm_size = wm->default_wm;
3722 struct cxsr_latency {
3725 unsigned long fsb_freq;
3726 unsigned long mem_freq;
3727 unsigned long display_sr;
3728 unsigned long display_hpll_disable;
3729 unsigned long cursor_sr;
3730 unsigned long cursor_hpll_disable;
3733 static const struct cxsr_latency cxsr_latency_table[] = {
3734 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3735 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3736 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3737 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3738 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3740 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3741 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3742 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3743 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3744 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3746 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3747 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3748 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3749 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3750 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3752 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3753 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3754 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3755 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3756 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3758 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3759 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3760 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3761 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3762 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3764 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3765 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3766 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3767 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3768 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3771 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3776 const struct cxsr_latency *latency;
3779 if (fsb == 0 || mem == 0)
3782 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3783 latency = &cxsr_latency_table[i];
3784 if (is_desktop == latency->is_desktop &&
3785 is_ddr3 == latency->is_ddr3 &&
3786 fsb == latency->fsb_freq && mem == latency->mem_freq)
3790 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3795 static void pineview_disable_cxsr(struct drm_device *dev)
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3799 /* deactivate cxsr */
3800 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3804 * Latency for FIFO fetches is dependent on several factors:
3805 * - memory configuration (speed, channels)
3807 * - current MCH state
3808 * It can be fairly high in some situations, so here we assume a fairly
3809 * pessimal value. It's a tradeoff between extra memory fetches (if we
3810 * set this value too high, the FIFO will fetch frequently to stay full)
3811 * and power consumption (set it too low to save power and we might see
3812 * FIFO underruns and display "flicker").
3814 * A value of 5us seems to be a good balance; safe for very low end
3815 * platforms but not overly aggressive on lower latency configs.
3817 static const int latency_ns = 5000;
3819 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3821 struct drm_i915_private *dev_priv = dev->dev_private;
3822 uint32_t dsparb = I915_READ(DSPARB);
3825 size = dsparb & 0x7f;
3827 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3829 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3830 plane ? "B" : "A", size);
3835 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3838 uint32_t dsparb = I915_READ(DSPARB);
3841 size = dsparb & 0x1ff;
3843 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3844 size >>= 1; /* Convert to cachelines */
3846 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3847 plane ? "B" : "A", size);
3852 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 uint32_t dsparb = I915_READ(DSPARB);
3858 size = dsparb & 0x7f;
3859 size >>= 2; /* Convert to cachelines */
3861 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3868 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3870 struct drm_i915_private *dev_priv = dev->dev_private;
3871 uint32_t dsparb = I915_READ(DSPARB);
3874 size = dsparb & 0x7f;
3875 size >>= 1; /* Convert to cachelines */
3877 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3878 plane ? "B" : "A", size);
3883 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3885 struct drm_crtc *crtc, *enabled = NULL;
3887 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3888 if (crtc->enabled && crtc->fb) {
3898 static void pineview_update_wm(struct drm_device *dev)
3900 struct drm_i915_private *dev_priv = dev->dev_private;
3901 struct drm_crtc *crtc;
3902 const struct cxsr_latency *latency;
3906 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3907 dev_priv->fsb_freq, dev_priv->mem_freq);
3909 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3910 pineview_disable_cxsr(dev);
3914 crtc = single_enabled_crtc(dev);
3916 int clock = crtc->mode.clock;
3917 int pixel_size = crtc->fb->bits_per_pixel / 8;
3920 wm = intel_calculate_wm(clock, &pineview_display_wm,
3921 pineview_display_wm.fifo_size,
3922 pixel_size, latency->display_sr);
3923 reg = I915_READ(DSPFW1);
3924 reg &= ~DSPFW_SR_MASK;
3925 reg |= wm << DSPFW_SR_SHIFT;
3926 I915_WRITE(DSPFW1, reg);
3927 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3930 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3931 pineview_display_wm.fifo_size,
3932 pixel_size, latency->cursor_sr);
3933 reg = I915_READ(DSPFW3);
3934 reg &= ~DSPFW_CURSOR_SR_MASK;
3935 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3936 I915_WRITE(DSPFW3, reg);
3938 /* Display HPLL off SR */
3939 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3940 pineview_display_hplloff_wm.fifo_size,
3941 pixel_size, latency->display_hpll_disable);
3942 reg = I915_READ(DSPFW3);
3943 reg &= ~DSPFW_HPLL_SR_MASK;
3944 reg |= wm & DSPFW_HPLL_SR_MASK;
3945 I915_WRITE(DSPFW3, reg);
3947 /* cursor HPLL off SR */
3948 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3949 pineview_display_hplloff_wm.fifo_size,
3950 pixel_size, latency->cursor_hpll_disable);
3951 reg = I915_READ(DSPFW3);
3952 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3953 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3954 I915_WRITE(DSPFW3, reg);
3955 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3959 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3960 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3962 pineview_disable_cxsr(dev);
3963 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3967 static bool g4x_compute_wm0(struct drm_device *dev,
3969 const struct intel_watermark_params *display,
3970 int display_latency_ns,
3971 const struct intel_watermark_params *cursor,
3972 int cursor_latency_ns,
3976 struct drm_crtc *crtc;
3977 int htotal, hdisplay, clock, pixel_size;
3978 int line_time_us, line_count;
3979 int entries, tlb_miss;
3981 crtc = intel_get_crtc_for_plane(dev, plane);
3982 if (crtc->fb == NULL || !crtc->enabled) {
3983 *cursor_wm = cursor->guard_size;
3984 *plane_wm = display->guard_size;
3988 htotal = crtc->mode.htotal;
3989 hdisplay = crtc->mode.hdisplay;
3990 clock = crtc->mode.clock;
3991 pixel_size = crtc->fb->bits_per_pixel / 8;
3993 /* Use the small buffer method to calculate plane watermark */
3994 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3995 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3997 entries += tlb_miss;
3998 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3999 *plane_wm = entries + display->guard_size;
4000 if (*plane_wm > (int)display->max_wm)
4001 *plane_wm = display->max_wm;
4003 /* Use the large buffer method to calculate cursor watermark */
4004 line_time_us = ((htotal * 1000) / clock);
4005 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4006 entries = line_count * 64 * pixel_size;
4007 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4009 entries += tlb_miss;
4010 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4011 *cursor_wm = entries + cursor->guard_size;
4012 if (*cursor_wm > (int)cursor->max_wm)
4013 *cursor_wm = (int)cursor->max_wm;
4019 * Check the wm result.
4021 * If any calculated watermark values is larger than the maximum value that
4022 * can be programmed into the associated watermark register, that watermark
4025 static bool g4x_check_srwm(struct drm_device *dev,
4026 int display_wm, int cursor_wm,
4027 const struct intel_watermark_params *display,
4028 const struct intel_watermark_params *cursor)
4030 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4031 display_wm, cursor_wm);
4033 if (display_wm > display->max_wm) {
4034 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4035 display_wm, display->max_wm);
4039 if (cursor_wm > cursor->max_wm) {
4040 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4041 cursor_wm, cursor->max_wm);
4045 if (!(display_wm || cursor_wm)) {
4046 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4053 static bool g4x_compute_srwm(struct drm_device *dev,
4056 const struct intel_watermark_params *display,
4057 const struct intel_watermark_params *cursor,
4058 int *display_wm, int *cursor_wm)
4060 struct drm_crtc *crtc;
4061 int hdisplay, htotal, pixel_size, clock;
4062 unsigned long line_time_us;
4063 int line_count, line_size;
4068 *display_wm = *cursor_wm = 0;
4072 crtc = intel_get_crtc_for_plane(dev, plane);
4073 hdisplay = crtc->mode.hdisplay;
4074 htotal = crtc->mode.htotal;
4075 clock = crtc->mode.clock;
4076 pixel_size = crtc->fb->bits_per_pixel / 8;
4078 line_time_us = (htotal * 1000) / clock;
4079 line_count = (latency_ns / line_time_us + 1000) / 1000;
4080 line_size = hdisplay * pixel_size;
4082 /* Use the minimum of the small and large buffer method for primary */
4083 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4084 large = line_count * line_size;
4086 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4087 *display_wm = entries + display->guard_size;
4089 /* calculate the self-refresh watermark for display cursor */
4090 entries = line_count * pixel_size * 64;
4091 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4092 *cursor_wm = entries + cursor->guard_size;
4094 return g4x_check_srwm(dev,
4095 *display_wm, *cursor_wm,
4099 #define single_plane_enabled(mask) is_power_of_2(mask)
4101 static void g4x_update_wm(struct drm_device *dev)
4103 static const int sr_latency_ns = 12000;
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4106 int plane_sr, cursor_sr;
4107 unsigned int enabled = 0;
4109 if (g4x_compute_wm0(dev, 0,
4110 &g4x_wm_info, latency_ns,
4111 &g4x_cursor_wm_info, latency_ns,
4112 &planea_wm, &cursora_wm))
4115 if (g4x_compute_wm0(dev, 1,
4116 &g4x_wm_info, latency_ns,
4117 &g4x_cursor_wm_info, latency_ns,
4118 &planeb_wm, &cursorb_wm))
4121 plane_sr = cursor_sr = 0;
4122 if (single_plane_enabled(enabled) &&
4123 g4x_compute_srwm(dev, ffs(enabled) - 1,
4126 &g4x_cursor_wm_info,
4127 &plane_sr, &cursor_sr))
4128 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4130 I915_WRITE(FW_BLC_SELF,
4131 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4133 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4134 planea_wm, cursora_wm,
4135 planeb_wm, cursorb_wm,
4136 plane_sr, cursor_sr);
4139 (plane_sr << DSPFW_SR_SHIFT) |
4140 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4141 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4144 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4145 (cursora_wm << DSPFW_CURSORA_SHIFT));
4146 /* HPLL off in SR has some issues on G4x... disable it */
4148 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4149 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4152 static void i965_update_wm(struct drm_device *dev)
4154 struct drm_i915_private *dev_priv = dev->dev_private;
4155 struct drm_crtc *crtc;
4159 /* Calc sr entries for one plane configs */
4160 crtc = single_enabled_crtc(dev);
4162 /* self-refresh has much higher latency */
4163 static const int sr_latency_ns = 12000;
4164 int clock = crtc->mode.clock;
4165 int htotal = crtc->mode.htotal;
4166 int hdisplay = crtc->mode.hdisplay;
4167 int pixel_size = crtc->fb->bits_per_pixel / 8;
4168 unsigned long line_time_us;
4171 line_time_us = ((htotal * 1000) / clock);
4173 /* Use ns/us then divide to preserve precision */
4174 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4175 pixel_size * hdisplay;
4176 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4177 srwm = I965_FIFO_SIZE - entries;
4181 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4184 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4186 entries = DIV_ROUND_UP(entries,
4187 i965_cursor_wm_info.cacheline_size);
4188 cursor_sr = i965_cursor_wm_info.fifo_size -
4189 (entries + i965_cursor_wm_info.guard_size);
4191 if (cursor_sr > i965_cursor_wm_info.max_wm)
4192 cursor_sr = i965_cursor_wm_info.max_wm;
4194 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4195 "cursor %d\n", srwm, cursor_sr);
4197 if (IS_CRESTLINE(dev))
4198 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4200 /* Turn off self refresh if both pipes are enabled */
4201 if (IS_CRESTLINE(dev))
4202 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4206 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4209 /* 965 has limitations... */
4210 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4211 (8 << 16) | (8 << 8) | (8 << 0));
4212 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4213 /* update cursor SR watermark */
4214 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4217 static void i9xx_update_wm(struct drm_device *dev)
4219 struct drm_i915_private *dev_priv = dev->dev_private;
4220 const struct intel_watermark_params *wm_info;
4225 int planea_wm, planeb_wm;
4226 struct drm_crtc *crtc, *enabled = NULL;
4229 wm_info = &i945_wm_info;
4230 else if (!IS_GEN2(dev))
4231 wm_info = &i915_wm_info;
4233 wm_info = &i855_wm_info;
4235 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4236 crtc = intel_get_crtc_for_plane(dev, 0);
4237 if (crtc->enabled && crtc->fb) {
4238 planea_wm = intel_calculate_wm(crtc->mode.clock,
4240 crtc->fb->bits_per_pixel / 8,
4244 planea_wm = fifo_size - wm_info->guard_size;
4246 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4247 crtc = intel_get_crtc_for_plane(dev, 1);
4248 if (crtc->enabled && crtc->fb) {
4249 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4251 crtc->fb->bits_per_pixel / 8,
4253 if (enabled == NULL)
4258 planeb_wm = fifo_size - wm_info->guard_size;
4260 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4263 * Overlay gets an aggressive default since video jitter is bad.
4267 /* Play safe and disable self-refresh before adjusting watermarks. */
4268 if (IS_I945G(dev) || IS_I945GM(dev))
4269 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4270 else if (IS_I915GM(dev))
4271 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4273 /* Calc sr entries for one plane configs */
4274 if (HAS_FW_BLC(dev) && enabled) {
4275 /* self-refresh has much higher latency */
4276 static const int sr_latency_ns = 6000;
4277 int clock = enabled->mode.clock;
4278 int htotal = enabled->mode.htotal;
4279 int hdisplay = enabled->mode.hdisplay;
4280 int pixel_size = enabled->fb->bits_per_pixel / 8;
4281 unsigned long line_time_us;
4284 line_time_us = (htotal * 1000) / clock;
4286 /* Use ns/us then divide to preserve precision */
4287 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4288 pixel_size * hdisplay;
4289 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4290 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4291 srwm = wm_info->fifo_size - entries;
4295 if (IS_I945G(dev) || IS_I945GM(dev))
4296 I915_WRITE(FW_BLC_SELF,
4297 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4298 else if (IS_I915GM(dev))
4299 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4302 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4303 planea_wm, planeb_wm, cwm, srwm);
4305 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4306 fwater_hi = (cwm & 0x1f);
4308 /* Set request length to 8 cachelines per fetch */
4309 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4310 fwater_hi = fwater_hi | (1 << 8);
4312 I915_WRITE(FW_BLC, fwater_lo);
4313 I915_WRITE(FW_BLC2, fwater_hi);
4315 if (HAS_FW_BLC(dev)) {
4317 if (IS_I945G(dev) || IS_I945GM(dev))
4318 I915_WRITE(FW_BLC_SELF,
4319 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4320 else if (IS_I915GM(dev))
4321 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4322 DRM_DEBUG_KMS("memory self refresh enabled\n");
4324 DRM_DEBUG_KMS("memory self refresh disabled\n");
4328 static void i830_update_wm(struct drm_device *dev)
4330 struct drm_i915_private *dev_priv = dev->dev_private;
4331 struct drm_crtc *crtc;
4335 crtc = single_enabled_crtc(dev);
4339 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4340 dev_priv->display.get_fifo_size(dev, 0),
4341 crtc->fb->bits_per_pixel / 8,
4343 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4344 fwater_lo |= (3<<8) | planea_wm;
4346 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4348 I915_WRITE(FW_BLC, fwater_lo);
4351 #define ILK_LP0_PLANE_LATENCY 700
4352 #define ILK_LP0_CURSOR_LATENCY 1300
4355 * Check the wm result.
4357 * If any calculated watermark values is larger than the maximum value that
4358 * can be programmed into the associated watermark register, that watermark
4361 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4362 int fbc_wm, int display_wm, int cursor_wm,
4363 const struct intel_watermark_params *display,
4364 const struct intel_watermark_params *cursor)
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4368 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4369 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4371 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4372 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4373 fbc_wm, SNB_FBC_MAX_SRWM, level);
4375 /* fbc has it's own way to disable FBC WM */
4376 I915_WRITE(DISP_ARB_CTL,
4377 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4381 if (display_wm > display->max_wm) {
4382 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4383 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4387 if (cursor_wm > cursor->max_wm) {
4388 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4389 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4393 if (!(fbc_wm || display_wm || cursor_wm)) {
4394 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4402 * Compute watermark values of WM[1-3],
4404 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4406 const struct intel_watermark_params *display,
4407 const struct intel_watermark_params *cursor,
4408 int *fbc_wm, int *display_wm, int *cursor_wm)
4410 struct drm_crtc *crtc;
4411 unsigned long line_time_us;
4412 int hdisplay, htotal, pixel_size, clock;
4413 int line_count, line_size;
4418 *fbc_wm = *display_wm = *cursor_wm = 0;
4422 crtc = intel_get_crtc_for_plane(dev, plane);
4423 hdisplay = crtc->mode.hdisplay;
4424 htotal = crtc->mode.htotal;
4425 clock = crtc->mode.clock;
4426 pixel_size = crtc->fb->bits_per_pixel / 8;
4428 line_time_us = (htotal * 1000) / clock;
4429 line_count = (latency_ns / line_time_us + 1000) / 1000;
4430 line_size = hdisplay * pixel_size;
4432 /* Use the minimum of the small and large buffer method for primary */
4433 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4434 large = line_count * line_size;
4436 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4437 *display_wm = entries + display->guard_size;
4441 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4443 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4445 /* calculate the self-refresh watermark for display cursor */
4446 entries = line_count * pixel_size * 64;
4447 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4448 *cursor_wm = entries + cursor->guard_size;
4450 return ironlake_check_srwm(dev, level,
4451 *fbc_wm, *display_wm, *cursor_wm,
4455 static void ironlake_update_wm(struct drm_device *dev)
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 int fbc_wm, plane_wm, cursor_wm;
4459 unsigned int enabled;
4462 if (g4x_compute_wm0(dev, 0,
4463 &ironlake_display_wm_info,
4464 ILK_LP0_PLANE_LATENCY,
4465 &ironlake_cursor_wm_info,
4466 ILK_LP0_CURSOR_LATENCY,
4467 &plane_wm, &cursor_wm)) {
4468 I915_WRITE(WM0_PIPEA_ILK,
4469 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4470 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4471 " plane %d, " "cursor: %d\n",
4472 plane_wm, cursor_wm);
4476 if (g4x_compute_wm0(dev, 1,
4477 &ironlake_display_wm_info,
4478 ILK_LP0_PLANE_LATENCY,
4479 &ironlake_cursor_wm_info,
4480 ILK_LP0_CURSOR_LATENCY,
4481 &plane_wm, &cursor_wm)) {
4482 I915_WRITE(WM0_PIPEB_ILK,
4483 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4484 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4485 " plane %d, cursor: %d\n",
4486 plane_wm, cursor_wm);
4491 * Calculate and update the self-refresh watermark only when one
4492 * display plane is used.
4494 I915_WRITE(WM3_LP_ILK, 0);
4495 I915_WRITE(WM2_LP_ILK, 0);
4496 I915_WRITE(WM1_LP_ILK, 0);
4498 if (!single_plane_enabled(enabled))
4500 enabled = ffs(enabled) - 1;
4503 if (!ironlake_compute_srwm(dev, 1, enabled,
4504 ILK_READ_WM1_LATENCY() * 500,
4505 &ironlake_display_srwm_info,
4506 &ironlake_cursor_srwm_info,
4507 &fbc_wm, &plane_wm, &cursor_wm))
4510 I915_WRITE(WM1_LP_ILK,
4512 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4513 (fbc_wm << WM1_LP_FBC_SHIFT) |
4514 (plane_wm << WM1_LP_SR_SHIFT) |
4518 if (!ironlake_compute_srwm(dev, 2, enabled,
4519 ILK_READ_WM2_LATENCY() * 500,
4520 &ironlake_display_srwm_info,
4521 &ironlake_cursor_srwm_info,
4522 &fbc_wm, &plane_wm, &cursor_wm))
4525 I915_WRITE(WM2_LP_ILK,
4527 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4528 (fbc_wm << WM1_LP_FBC_SHIFT) |
4529 (plane_wm << WM1_LP_SR_SHIFT) |
4533 * WM3 is unsupported on ILK, probably because we don't have latency
4534 * data for that power state
4538 static void sandybridge_update_wm(struct drm_device *dev)
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4542 int fbc_wm, plane_wm, cursor_wm;
4543 unsigned int enabled;
4546 if (g4x_compute_wm0(dev, 0,
4547 &sandybridge_display_wm_info, latency,
4548 &sandybridge_cursor_wm_info, latency,
4549 &plane_wm, &cursor_wm)) {
4550 I915_WRITE(WM0_PIPEA_ILK,
4551 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4552 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4553 " plane %d, " "cursor: %d\n",
4554 plane_wm, cursor_wm);
4558 if (g4x_compute_wm0(dev, 1,
4559 &sandybridge_display_wm_info, latency,
4560 &sandybridge_cursor_wm_info, latency,
4561 &plane_wm, &cursor_wm)) {
4562 I915_WRITE(WM0_PIPEB_ILK,
4563 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4564 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4565 " plane %d, cursor: %d\n",
4566 plane_wm, cursor_wm);
4570 /* IVB has 3 pipes */
4571 if (IS_IVYBRIDGE(dev) &&
4572 g4x_compute_wm0(dev, 2,
4573 &sandybridge_display_wm_info, latency,
4574 &sandybridge_cursor_wm_info, latency,
4575 &plane_wm, &cursor_wm)) {
4576 I915_WRITE(WM0_PIPEC_IVB,
4577 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4578 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4579 " plane %d, cursor: %d\n",
4580 plane_wm, cursor_wm);
4585 * Calculate and update the self-refresh watermark only when one
4586 * display plane is used.
4588 * SNB support 3 levels of watermark.
4590 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4591 * and disabled in the descending order
4594 I915_WRITE(WM3_LP_ILK, 0);
4595 I915_WRITE(WM2_LP_ILK, 0);
4596 I915_WRITE(WM1_LP_ILK, 0);
4598 if (!single_plane_enabled(enabled))
4600 enabled = ffs(enabled) - 1;
4603 if (!ironlake_compute_srwm(dev, 1, enabled,
4604 SNB_READ_WM1_LATENCY() * 500,
4605 &sandybridge_display_srwm_info,
4606 &sandybridge_cursor_srwm_info,
4607 &fbc_wm, &plane_wm, &cursor_wm))
4610 I915_WRITE(WM1_LP_ILK,
4612 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4613 (fbc_wm << WM1_LP_FBC_SHIFT) |
4614 (plane_wm << WM1_LP_SR_SHIFT) |
4618 if (!ironlake_compute_srwm(dev, 2, enabled,
4619 SNB_READ_WM2_LATENCY() * 500,
4620 &sandybridge_display_srwm_info,
4621 &sandybridge_cursor_srwm_info,
4622 &fbc_wm, &plane_wm, &cursor_wm))
4625 I915_WRITE(WM2_LP_ILK,
4627 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4628 (fbc_wm << WM1_LP_FBC_SHIFT) |
4629 (plane_wm << WM1_LP_SR_SHIFT) |
4633 if (!ironlake_compute_srwm(dev, 3, enabled,
4634 SNB_READ_WM3_LATENCY() * 500,
4635 &sandybridge_display_srwm_info,
4636 &sandybridge_cursor_srwm_info,
4637 &fbc_wm, &plane_wm, &cursor_wm))
4640 I915_WRITE(WM3_LP_ILK,
4642 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4643 (fbc_wm << WM1_LP_FBC_SHIFT) |
4644 (plane_wm << WM1_LP_SR_SHIFT) |
4649 * intel_update_watermarks - update FIFO watermark values based on current modes
4651 * Calculate watermark values for the various WM regs based on current mode
4652 * and plane configuration.
4654 * There are several cases to deal with here:
4655 * - normal (i.e. non-self-refresh)
4656 * - self-refresh (SR) mode
4657 * - lines are large relative to FIFO size (buffer can hold up to 2)
4658 * - lines are small relative to FIFO size (buffer can hold more than 2
4659 * lines), so need to account for TLB latency
4661 * The normal calculation is:
4662 * watermark = dotclock * bytes per pixel * latency
4663 * where latency is platform & configuration dependent (we assume pessimal
4666 * The SR calculation is:
4667 * watermark = (trunc(latency/line time)+1) * surface width *
4670 * line time = htotal / dotclock
4671 * surface width = hdisplay for normal plane and 64 for cursor
4672 * and latency is assumed to be high, as above.
4674 * The final value programmed to the register should always be rounded up,
4675 * and include an extra 2 entries to account for clock crossings.
4677 * We don't use the sprite, so we can ignore that. And on Crestline we have
4678 * to set the non-SR watermarks to 8.
4680 static void intel_update_watermarks(struct drm_device *dev)
4682 struct drm_i915_private *dev_priv = dev->dev_private;
4684 if (dev_priv->display.update_wm)
4685 dev_priv->display.update_wm(dev);
4688 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4690 if (i915_panel_use_ssc >= 0)
4691 return i915_panel_use_ssc != 0;
4692 return dev_priv->lvds_use_ssc
4693 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4697 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4698 * @crtc: CRTC structure
4699 * @mode: requested mode
4701 * A pipe may be connected to one or more outputs. Based on the depth of the
4702 * attached framebuffer, choose a good color depth to use on the pipe.
4704 * If possible, match the pipe depth to the fb depth. In some cases, this
4705 * isn't ideal, because the connected output supports a lesser or restricted
4706 * set of depths. Resolve that here:
4707 * LVDS typically supports only 6bpc, so clamp down in that case
4708 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4709 * Displays may support a restricted set as well, check EDID and clamp as
4711 * DP may want to dither down to 6bpc to fit larger modes
4714 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4715 * true if they don't match).
4717 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4718 unsigned int *pipe_bpp,
4719 struct drm_display_mode *mode)
4721 struct drm_device *dev = crtc->dev;
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723 struct drm_encoder *encoder;
4724 struct drm_connector *connector;
4725 unsigned int display_bpc = UINT_MAX, bpc;
4727 /* Walk the encoders & connectors on this crtc, get min bpc */
4728 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4729 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4731 if (encoder->crtc != crtc)
4734 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4735 unsigned int lvds_bpc;
4737 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4743 if (lvds_bpc < display_bpc) {
4744 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4745 display_bpc = lvds_bpc;
4750 /* Not one of the known troublemakers, check the EDID */
4751 list_for_each_entry(connector, &dev->mode_config.connector_list,
4753 if (connector->encoder != encoder)
4756 /* Don't use an invalid EDID bpc value */
4757 if (connector->display_info.bpc &&
4758 connector->display_info.bpc < display_bpc) {
4759 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4760 display_bpc = connector->display_info.bpc;
4764 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4765 /* Use VBT settings if we have an eDP panel */
4766 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4768 if (edp_bpc && edp_bpc < display_bpc) {
4769 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4770 display_bpc = edp_bpc;
4776 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4777 * through, clamp it down. (Note: >12bpc will be caught below.)
4779 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4780 if (display_bpc > 8 && display_bpc < 12) {
4781 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4784 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4790 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4791 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4796 * We could just drive the pipe at the highest bpc all the time and
4797 * enable dithering as needed, but that costs bandwidth. So choose
4798 * the minimum value that expresses the full color range of the fb but
4799 * also stays within the max display bpc discovered above.
4802 switch (crtc->fb->depth) {
4804 bpc = 8; /* since we go through a colormap */
4808 bpc = 6; /* min is 18bpp */
4820 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4821 bpc = min((unsigned int)8, display_bpc);
4825 display_bpc = min(display_bpc, bpc);
4827 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4830 *pipe_bpp = display_bpc * 3;
4832 return display_bpc != bpc;
4835 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4836 struct drm_display_mode *mode,
4837 struct drm_display_mode *adjusted_mode,
4839 struct drm_framebuffer *old_fb)
4841 struct drm_device *dev = crtc->dev;
4842 struct drm_i915_private *dev_priv = dev->dev_private;
4843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4844 int pipe = intel_crtc->pipe;
4845 int plane = intel_crtc->plane;
4846 int refclk, num_connectors = 0;
4847 intel_clock_t clock, reduced_clock;
4848 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4849 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
4850 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4851 struct drm_mode_config *mode_config = &dev->mode_config;
4852 struct intel_encoder *encoder;
4853 const intel_limit_t *limit;
4858 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4859 if (encoder->base.crtc != crtc)
4862 switch (encoder->type) {
4863 case INTEL_OUTPUT_LVDS:
4866 case INTEL_OUTPUT_SDVO:
4867 case INTEL_OUTPUT_HDMI:
4869 if (encoder->needs_tv_clock)
4872 case INTEL_OUTPUT_DVO:
4875 case INTEL_OUTPUT_TVOUT:
4878 case INTEL_OUTPUT_ANALOG:
4881 case INTEL_OUTPUT_DISPLAYPORT:
4889 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4890 refclk = dev_priv->lvds_ssc_freq * 1000;
4891 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4893 } else if (!IS_GEN2(dev)) {
4900 * Returns a set of divisors for the desired target clock with the given
4901 * refclk, or FALSE. The returned values represent the clock equation:
4902 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4904 limit = intel_limit(crtc, refclk);
4905 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
4907 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4911 /* Ensure that the cursor is valid for the new mode before changing... */
4912 intel_crtc_update_cursor(crtc, true);
4914 if (is_lvds && dev_priv->lvds_downclock_avail) {
4915 has_reduced_clock = limit->find_pll(limit, crtc,
4916 dev_priv->lvds_downclock,
4919 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4921 * If the different P is found, it means that we can't
4922 * switch the display clock by using the FP0/FP1.
4923 * In such case we will disable the LVDS downclock
4926 DRM_DEBUG_KMS("Different P is found for "
4927 "LVDS clock/downclock\n");
4928 has_reduced_clock = 0;
4931 /* SDVO TV has fixed PLL values depend on its clock range,
4932 this mirrors vbios setting. */
4933 if (is_sdvo && is_tv) {
4934 if (adjusted_mode->clock >= 100000
4935 && adjusted_mode->clock < 140500) {
4941 } else if (adjusted_mode->clock >= 140500
4942 && adjusted_mode->clock <= 200000) {
4951 if (IS_PINEVIEW(dev)) {
4952 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4953 if (has_reduced_clock)
4954 fp2 = (1 << reduced_clock.n) << 16 |
4955 reduced_clock.m1 << 8 | reduced_clock.m2;
4957 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4958 if (has_reduced_clock)
4959 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4963 dpll = DPLL_VGA_MODE_DIS;
4965 if (!IS_GEN2(dev)) {
4967 dpll |= DPLLB_MODE_LVDS;
4969 dpll |= DPLLB_MODE_DAC_SERIAL;
4971 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4972 if (pixel_multiplier > 1) {
4973 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4974 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4976 dpll |= DPLL_DVO_HIGH_SPEED;
4979 dpll |= DPLL_DVO_HIGH_SPEED;
4981 /* compute bitmask from p1 value */
4982 if (IS_PINEVIEW(dev))
4983 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4985 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4986 if (IS_G4X(dev) && has_reduced_clock)
4987 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4991 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4994 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4997 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5000 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5003 if (INTEL_INFO(dev)->gen >= 4)
5004 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5007 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5010 dpll |= PLL_P1_DIVIDE_BY_TWO;
5012 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5014 dpll |= PLL_P2_DIVIDE_BY_4;
5018 if (is_sdvo && is_tv)
5019 dpll |= PLL_REF_INPUT_TVCLKINBC;
5021 /* XXX: just matching BIOS for now */
5022 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5024 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5025 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5027 dpll |= PLL_REF_INPUT_DREFCLK;
5029 /* setup pipeconf */
5030 pipeconf = I915_READ(PIPECONF(pipe));
5032 /* Set up the display plane register */
5033 dspcntr = DISPPLANE_GAMMA_ENABLE;
5035 /* Ironlake's plane is forced to pipe, bit 24 is to
5036 enable color space conversion */
5038 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5040 dspcntr |= DISPPLANE_SEL_PIPE_B;
5042 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5043 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5046 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5050 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5051 pipeconf |= PIPECONF_DOUBLE_WIDE;
5053 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5056 /* default to 8bpc */
5057 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5059 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5060 pipeconf |= PIPECONF_BPP_6 |
5061 PIPECONF_DITHER_EN |
5062 PIPECONF_DITHER_TYPE_SP;
5066 dpll |= DPLL_VCO_ENABLE;
5068 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5069 drm_mode_debug_printmodeline(mode);
5071 I915_WRITE(FP0(pipe), fp);
5072 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5074 POSTING_READ(DPLL(pipe));
5077 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5078 * This is an exception to the general rule that mode_set doesn't turn
5082 temp = I915_READ(LVDS);
5083 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5085 temp |= LVDS_PIPEB_SELECT;
5087 temp &= ~LVDS_PIPEB_SELECT;
5089 /* set the corresponsding LVDS_BORDER bit */
5090 temp |= dev_priv->lvds_border_bits;
5091 /* Set the B0-B3 data pairs corresponding to whether we're going to
5092 * set the DPLLs for dual-channel mode or not.
5095 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5097 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5099 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5100 * appropriately here, but we need to look more thoroughly into how
5101 * panels behave in the two modes.
5103 /* set the dithering flag on LVDS as needed */
5104 if (INTEL_INFO(dev)->gen >= 4) {
5105 if (dev_priv->lvds_dither)
5106 temp |= LVDS_ENABLE_DITHER;
5108 temp &= ~LVDS_ENABLE_DITHER;
5110 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5111 lvds_sync |= LVDS_HSYNC_POLARITY;
5112 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5113 lvds_sync |= LVDS_VSYNC_POLARITY;
5114 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5116 char flags[2] = "-+";
5117 DRM_INFO("Changing LVDS panel from "
5118 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5119 flags[!(temp & LVDS_HSYNC_POLARITY)],
5120 flags[!(temp & LVDS_VSYNC_POLARITY)],
5121 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5122 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5123 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5126 I915_WRITE(LVDS, temp);
5130 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5133 I915_WRITE(DPLL(pipe), dpll);
5135 /* Wait for the clocks to stabilize. */
5136 POSTING_READ(DPLL(pipe));
5139 if (INTEL_INFO(dev)->gen >= 4) {
5142 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5144 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5148 I915_WRITE(DPLL_MD(pipe), temp);
5150 /* The pixel multiplier can only be updated once the
5151 * DPLL is enabled and the clocks are stable.
5153 * So write it again.
5155 I915_WRITE(DPLL(pipe), dpll);
5158 intel_crtc->lowfreq_avail = false;
5159 if (is_lvds && has_reduced_clock && i915_powersave) {
5160 I915_WRITE(FP1(pipe), fp2);
5161 intel_crtc->lowfreq_avail = true;
5162 if (HAS_PIPE_CXSR(dev)) {
5163 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5164 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5167 I915_WRITE(FP1(pipe), fp);
5168 if (HAS_PIPE_CXSR(dev)) {
5169 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5170 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5174 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5175 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5176 /* the chip adds 2 halflines automatically */
5177 adjusted_mode->crtc_vdisplay -= 1;
5178 adjusted_mode->crtc_vtotal -= 1;
5179 adjusted_mode->crtc_vblank_start -= 1;
5180 adjusted_mode->crtc_vblank_end -= 1;
5181 adjusted_mode->crtc_vsync_end -= 1;
5182 adjusted_mode->crtc_vsync_start -= 1;
5184 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5186 I915_WRITE(HTOTAL(pipe),
5187 (adjusted_mode->crtc_hdisplay - 1) |
5188 ((adjusted_mode->crtc_htotal - 1) << 16));
5189 I915_WRITE(HBLANK(pipe),
5190 (adjusted_mode->crtc_hblank_start - 1) |
5191 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5192 I915_WRITE(HSYNC(pipe),
5193 (adjusted_mode->crtc_hsync_start - 1) |
5194 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5196 I915_WRITE(VTOTAL(pipe),
5197 (adjusted_mode->crtc_vdisplay - 1) |
5198 ((adjusted_mode->crtc_vtotal - 1) << 16));
5199 I915_WRITE(VBLANK(pipe),
5200 (adjusted_mode->crtc_vblank_start - 1) |
5201 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5202 I915_WRITE(VSYNC(pipe),
5203 (adjusted_mode->crtc_vsync_start - 1) |
5204 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5206 /* pipesrc and dspsize control the size that is scaled from,
5207 * which should always be the user's requested size.
5209 I915_WRITE(DSPSIZE(plane),
5210 ((mode->vdisplay - 1) << 16) |
5211 (mode->hdisplay - 1));
5212 I915_WRITE(DSPPOS(plane), 0);
5213 I915_WRITE(PIPESRC(pipe),
5214 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5216 I915_WRITE(PIPECONF(pipe), pipeconf);
5217 POSTING_READ(PIPECONF(pipe));
5218 intel_enable_pipe(dev_priv, pipe, false);
5220 intel_wait_for_vblank(dev, pipe);
5222 I915_WRITE(DSPCNTR(plane), dspcntr);
5223 POSTING_READ(DSPCNTR(plane));
5224 intel_enable_plane(dev_priv, plane, pipe);
5226 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5228 intel_update_watermarks(dev);
5234 * Initialize reference clocks when the driver loads
5236 void ironlake_init_pch_refclk(struct drm_device *dev)
5238 struct drm_i915_private *dev_priv = dev->dev_private;
5239 struct drm_mode_config *mode_config = &dev->mode_config;
5240 struct intel_encoder *encoder;
5242 bool has_lvds = false;
5243 bool has_cpu_edp = false;
5244 bool has_pch_edp = false;
5245 bool has_panel = false;
5246 bool has_ck505 = false;
5247 bool can_ssc = false;
5249 /* We need to take the global config into account */
5250 list_for_each_entry(encoder, &mode_config->encoder_list,
5252 switch (encoder->type) {
5253 case INTEL_OUTPUT_LVDS:
5257 case INTEL_OUTPUT_EDP:
5259 if (intel_encoder_is_pch_edp(&encoder->base))
5267 if (HAS_PCH_IBX(dev)) {
5268 has_ck505 = dev_priv->display_clock_mode;
5269 can_ssc = has_ck505;
5275 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5276 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5279 /* Ironlake: try to setup display ref clock before DPLL
5280 * enabling. This is only under driver's control after
5281 * PCH B stepping, previous chipset stepping should be
5282 * ignoring this setting.
5284 temp = I915_READ(PCH_DREF_CONTROL);
5285 /* Always enable nonspread source */
5286 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5289 temp |= DREF_NONSPREAD_CK505_ENABLE;
5291 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5294 temp &= ~DREF_SSC_SOURCE_MASK;
5295 temp |= DREF_SSC_SOURCE_ENABLE;
5297 /* SSC must be turned on before enabling the CPU output */
5298 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5299 DRM_DEBUG_KMS("Using SSC on panel\n");
5300 temp |= DREF_SSC1_ENABLE;
5303 /* Get SSC going before enabling the outputs */
5304 I915_WRITE(PCH_DREF_CONTROL, temp);
5305 POSTING_READ(PCH_DREF_CONTROL);
5308 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5310 /* Enable CPU source on CPU attached eDP */
5312 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5313 DRM_DEBUG_KMS("Using SSC on eDP\n");
5314 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5317 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5319 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5321 I915_WRITE(PCH_DREF_CONTROL, temp);
5322 POSTING_READ(PCH_DREF_CONTROL);
5325 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5327 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5329 /* Turn off CPU output */
5330 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5332 I915_WRITE(PCH_DREF_CONTROL, temp);
5333 POSTING_READ(PCH_DREF_CONTROL);
5336 /* Turn off the SSC source */
5337 temp &= ~DREF_SSC_SOURCE_MASK;
5338 temp |= DREF_SSC_SOURCE_DISABLE;
5341 temp &= ~ DREF_SSC1_ENABLE;
5343 I915_WRITE(PCH_DREF_CONTROL, temp);
5344 POSTING_READ(PCH_DREF_CONTROL);
5349 static int ironlake_get_refclk(struct drm_crtc *crtc)
5351 struct drm_device *dev = crtc->dev;
5352 struct drm_i915_private *dev_priv = dev->dev_private;
5353 struct intel_encoder *encoder;
5354 struct drm_mode_config *mode_config = &dev->mode_config;
5355 struct intel_encoder *edp_encoder = NULL;
5356 int num_connectors = 0;
5357 bool is_lvds = false;
5359 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5360 if (encoder->base.crtc != crtc)
5363 switch (encoder->type) {
5364 case INTEL_OUTPUT_LVDS:
5367 case INTEL_OUTPUT_EDP:
5368 edp_encoder = encoder;
5374 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5375 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5376 dev_priv->lvds_ssc_freq);
5377 return dev_priv->lvds_ssc_freq * 1000;
5383 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5384 struct drm_display_mode *mode,
5385 struct drm_display_mode *adjusted_mode,
5387 struct drm_framebuffer *old_fb)
5389 struct drm_device *dev = crtc->dev;
5390 struct drm_i915_private *dev_priv = dev->dev_private;
5391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5392 int pipe = intel_crtc->pipe;
5393 int plane = intel_crtc->plane;
5394 int refclk, num_connectors = 0;
5395 intel_clock_t clock, reduced_clock;
5396 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5397 bool ok, has_reduced_clock = false, is_sdvo = false;
5398 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5399 struct intel_encoder *has_edp_encoder = NULL;
5400 struct drm_mode_config *mode_config = &dev->mode_config;
5401 struct intel_encoder *encoder;
5402 const intel_limit_t *limit;
5404 struct fdi_m_n m_n = {0};
5407 int target_clock, pixel_multiplier, lane, link_bw, factor;
5408 unsigned int pipe_bpp;
5411 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5412 if (encoder->base.crtc != crtc)
5415 switch (encoder->type) {
5416 case INTEL_OUTPUT_LVDS:
5419 case INTEL_OUTPUT_SDVO:
5420 case INTEL_OUTPUT_HDMI:
5422 if (encoder->needs_tv_clock)
5425 case INTEL_OUTPUT_TVOUT:
5428 case INTEL_OUTPUT_ANALOG:
5431 case INTEL_OUTPUT_DISPLAYPORT:
5434 case INTEL_OUTPUT_EDP:
5435 has_edp_encoder = encoder;
5442 refclk = ironlake_get_refclk(crtc);
5445 * Returns a set of divisors for the desired target clock with the given
5446 * refclk, or FALSE. The returned values represent the clock equation:
5447 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5449 limit = intel_limit(crtc, refclk);
5450 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
5452 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5456 /* Ensure that the cursor is valid for the new mode before changing... */
5457 intel_crtc_update_cursor(crtc, true);
5459 if (is_lvds && dev_priv->lvds_downclock_avail) {
5460 has_reduced_clock = limit->find_pll(limit, crtc,
5461 dev_priv->lvds_downclock,
5464 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5466 * If the different P is found, it means that we can't
5467 * switch the display clock by using the FP0/FP1.
5468 * In such case we will disable the LVDS downclock
5471 DRM_DEBUG_KMS("Different P is found for "
5472 "LVDS clock/downclock\n");
5473 has_reduced_clock = 0;
5476 /* SDVO TV has fixed PLL values depend on its clock range,
5477 this mirrors vbios setting. */
5478 if (is_sdvo && is_tv) {
5479 if (adjusted_mode->clock >= 100000
5480 && adjusted_mode->clock < 140500) {
5486 } else if (adjusted_mode->clock >= 140500
5487 && adjusted_mode->clock <= 200000) {
5497 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5499 /* CPU eDP doesn't require FDI link, so just set DP M/N
5500 according to current link config */
5501 if (has_edp_encoder &&
5502 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5503 target_clock = mode->clock;
5504 intel_edp_link_config(has_edp_encoder,
5507 /* [e]DP over FDI requires target mode clock
5508 instead of link clock */
5509 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5510 target_clock = mode->clock;
5512 target_clock = adjusted_mode->clock;
5514 /* FDI is a binary signal running at ~2.7GHz, encoding
5515 * each output octet as 10 bits. The actual frequency
5516 * is stored as a divider into a 100MHz clock, and the
5517 * mode pixel clock is stored in units of 1KHz.
5518 * Hence the bw of each lane in terms of the mode signal
5521 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5524 /* determine panel color depth */
5525 temp = I915_READ(PIPECONF(pipe));
5526 temp &= ~PIPE_BPC_MASK;
5527 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, adjusted_mode);
5542 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5549 intel_crtc->bpp = pipe_bpp;
5550 I915_WRITE(PIPECONF(pipe), temp);
5554 * Account for spread spectrum to avoid
5555 * oversubscribing the link. Max center spread
5556 * is 2.5%; use 5% for safety's sake.
5558 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5559 lane = bps / (link_bw * 8) + 1;
5562 intel_crtc->fdi_lanes = lane;
5564 if (pixel_multiplier > 1)
5565 link_bw *= pixel_multiplier;
5566 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5569 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5570 if (has_reduced_clock)
5571 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5574 /* Enable autotuning of the PLL clock (if permissible) */
5577 if ((intel_panel_use_ssc(dev_priv) &&
5578 dev_priv->lvds_ssc_freq == 100) ||
5579 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5581 } else if (is_sdvo && is_tv)
5584 if (clock.m < factor * clock.n)
5590 dpll |= DPLLB_MODE_LVDS;
5592 dpll |= DPLLB_MODE_DAC_SERIAL;
5594 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5595 if (pixel_multiplier > 1) {
5596 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5598 dpll |= DPLL_DVO_HIGH_SPEED;
5600 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5601 dpll |= DPLL_DVO_HIGH_SPEED;
5603 /* compute bitmask from p1 value */
5604 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5606 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5610 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5613 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5616 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5619 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5623 if (is_sdvo && is_tv)
5624 dpll |= PLL_REF_INPUT_TVCLKINBC;
5626 /* XXX: just matching BIOS for now */
5627 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5629 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5630 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5632 dpll |= PLL_REF_INPUT_DREFCLK;
5634 /* setup pipeconf */
5635 pipeconf = I915_READ(PIPECONF(pipe));
5637 /* Set up the display plane register */
5638 dspcntr = DISPPLANE_GAMMA_ENABLE;
5640 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5641 drm_mode_debug_printmodeline(mode);
5643 /* PCH eDP needs FDI, but CPU eDP does not */
5644 if (!intel_crtc->no_pll) {
5645 if (!has_edp_encoder ||
5646 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5647 I915_WRITE(PCH_FP0(pipe), fp);
5648 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5650 POSTING_READ(PCH_DPLL(pipe));
5654 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5655 fp == I915_READ(PCH_FP0(0))) {
5656 intel_crtc->use_pll_a = true;
5657 DRM_DEBUG_KMS("using pipe a dpll\n");
5658 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5659 fp == I915_READ(PCH_FP0(1))) {
5660 intel_crtc->use_pll_a = false;
5661 DRM_DEBUG_KMS("using pipe b dpll\n");
5663 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5668 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5669 * This is an exception to the general rule that mode_set doesn't turn
5673 temp = I915_READ(PCH_LVDS);
5674 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5675 if (HAS_PCH_CPT(dev)) {
5676 temp &= ~PORT_TRANS_SEL_MASK;
5677 temp |= PORT_TRANS_SEL_CPT(pipe);
5680 temp |= LVDS_PIPEB_SELECT;
5682 temp &= ~LVDS_PIPEB_SELECT;
5685 /* set the corresponsding LVDS_BORDER bit */
5686 temp |= dev_priv->lvds_border_bits;
5687 /* Set the B0-B3 data pairs corresponding to whether we're going to
5688 * set the DPLLs for dual-channel mode or not.
5691 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5693 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5695 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5696 * appropriately here, but we need to look more thoroughly into how
5697 * panels behave in the two modes.
5699 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5700 lvds_sync |= LVDS_HSYNC_POLARITY;
5701 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5702 lvds_sync |= LVDS_VSYNC_POLARITY;
5703 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5705 char flags[2] = "-+";
5706 DRM_INFO("Changing LVDS panel from "
5707 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5708 flags[!(temp & LVDS_HSYNC_POLARITY)],
5709 flags[!(temp & LVDS_VSYNC_POLARITY)],
5710 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5711 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5712 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5715 I915_WRITE(PCH_LVDS, temp);
5718 pipeconf &= ~PIPECONF_DITHER_EN;
5719 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5720 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5721 pipeconf |= PIPECONF_DITHER_EN;
5722 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5724 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5725 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5727 /* For non-DP output, clear any trans DP clock recovery setting.*/
5728 I915_WRITE(TRANSDATA_M1(pipe), 0);
5729 I915_WRITE(TRANSDATA_N1(pipe), 0);
5730 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5731 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5734 if (!intel_crtc->no_pll &&
5735 (!has_edp_encoder ||
5736 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5737 I915_WRITE(PCH_DPLL(pipe), dpll);
5739 /* Wait for the clocks to stabilize. */
5740 POSTING_READ(PCH_DPLL(pipe));
5743 /* The pixel multiplier can only be updated once the
5744 * DPLL is enabled and the clocks are stable.
5746 * So write it again.
5748 I915_WRITE(PCH_DPLL(pipe), dpll);
5751 intel_crtc->lowfreq_avail = false;
5752 if (!intel_crtc->no_pll) {
5753 if (is_lvds && has_reduced_clock && i915_powersave) {
5754 I915_WRITE(PCH_FP1(pipe), fp2);
5755 intel_crtc->lowfreq_avail = true;
5756 if (HAS_PIPE_CXSR(dev)) {
5757 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5758 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5761 I915_WRITE(PCH_FP1(pipe), fp);
5762 if (HAS_PIPE_CXSR(dev)) {
5763 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5764 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5769 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5770 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5771 /* the chip adds 2 halflines automatically */
5772 adjusted_mode->crtc_vdisplay -= 1;
5773 adjusted_mode->crtc_vtotal -= 1;
5774 adjusted_mode->crtc_vblank_start -= 1;
5775 adjusted_mode->crtc_vblank_end -= 1;
5776 adjusted_mode->crtc_vsync_end -= 1;
5777 adjusted_mode->crtc_vsync_start -= 1;
5779 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5781 I915_WRITE(HTOTAL(pipe),
5782 (adjusted_mode->crtc_hdisplay - 1) |
5783 ((adjusted_mode->crtc_htotal - 1) << 16));
5784 I915_WRITE(HBLANK(pipe),
5785 (adjusted_mode->crtc_hblank_start - 1) |
5786 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5787 I915_WRITE(HSYNC(pipe),
5788 (adjusted_mode->crtc_hsync_start - 1) |
5789 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5791 I915_WRITE(VTOTAL(pipe),
5792 (adjusted_mode->crtc_vdisplay - 1) |
5793 ((adjusted_mode->crtc_vtotal - 1) << 16));
5794 I915_WRITE(VBLANK(pipe),
5795 (adjusted_mode->crtc_vblank_start - 1) |
5796 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5797 I915_WRITE(VSYNC(pipe),
5798 (adjusted_mode->crtc_vsync_start - 1) |
5799 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5801 /* pipesrc controls the size that is scaled from, which should
5802 * always be the user's requested size.
5804 I915_WRITE(PIPESRC(pipe),
5805 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5807 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5808 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5809 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5810 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5812 if (has_edp_encoder &&
5813 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5814 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5817 I915_WRITE(PIPECONF(pipe), pipeconf);
5818 POSTING_READ(PIPECONF(pipe));
5820 intel_wait_for_vblank(dev, pipe);
5823 /* enable address swizzle for tiling buffer */
5824 temp = I915_READ(DISP_ARB_CTL);
5825 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5828 I915_WRITE(DSPCNTR(plane), dspcntr);
5829 POSTING_READ(DSPCNTR(plane));
5831 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5833 intel_update_watermarks(dev);
5838 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5839 struct drm_display_mode *mode,
5840 struct drm_display_mode *adjusted_mode,
5842 struct drm_framebuffer *old_fb)
5844 struct drm_device *dev = crtc->dev;
5845 struct drm_i915_private *dev_priv = dev->dev_private;
5846 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5847 int pipe = intel_crtc->pipe;
5850 drm_vblank_pre_modeset(dev, pipe);
5852 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5855 drm_vblank_post_modeset(dev, pipe);
5857 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5862 static void g4x_write_eld(struct drm_connector *connector,
5863 struct drm_crtc *crtc)
5865 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5866 uint8_t *eld = connector->eld;
5871 i = I915_READ(G4X_AUD_VID_DID);
5873 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5874 eldv = G4X_ELDV_DEVCL_DEVBLC;
5876 eldv = G4X_ELDV_DEVCTG;
5878 i = I915_READ(G4X_AUD_CNTL_ST);
5879 i &= ~(eldv | G4X_ELD_ADDR);
5880 len = (i >> 9) & 0x1f; /* ELD buffer size */
5881 I915_WRITE(G4X_AUD_CNTL_ST, i);
5886 len = min_t(uint8_t, eld[2], len);
5887 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5888 for (i = 0; i < len; i++)
5889 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5891 i = I915_READ(G4X_AUD_CNTL_ST);
5893 I915_WRITE(G4X_AUD_CNTL_ST, i);
5896 static void ironlake_write_eld(struct drm_connector *connector,
5897 struct drm_crtc *crtc)
5899 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5900 uint8_t *eld = connector->eld;
5908 if (HAS_PCH_IBX(connector->dev)) {
5909 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5910 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5911 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5913 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5914 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5915 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5918 i = to_intel_crtc(crtc)->pipe;
5919 hdmiw_hdmiedid += i * 0x100;
5920 aud_cntl_st += i * 0x100;
5922 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5924 i = I915_READ(aud_cntl_st);
5925 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5927 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5928 /* operate blindly on all ports */
5929 eldv = GEN5_ELD_VALIDB;
5930 eldv |= GEN5_ELD_VALIDB << 4;
5931 eldv |= GEN5_ELD_VALIDB << 8;
5933 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5934 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5937 i = I915_READ(aud_cntrl_st2);
5939 I915_WRITE(aud_cntrl_st2, i);
5944 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5945 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5946 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5949 i = I915_READ(aud_cntl_st);
5950 i &= ~GEN5_ELD_ADDRESS;
5951 I915_WRITE(aud_cntl_st, i);
5953 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5954 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5955 for (i = 0; i < len; i++)
5956 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5958 i = I915_READ(aud_cntrl_st2);
5960 I915_WRITE(aud_cntrl_st2, i);
5963 void intel_write_eld(struct drm_encoder *encoder,
5964 struct drm_display_mode *mode)
5966 struct drm_crtc *crtc = encoder->crtc;
5967 struct drm_connector *connector;
5968 struct drm_device *dev = encoder->dev;
5969 struct drm_i915_private *dev_priv = dev->dev_private;
5971 connector = drm_select_eld(encoder, mode);
5975 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5977 drm_get_connector_name(connector),
5978 connector->encoder->base.id,
5979 drm_get_encoder_name(connector->encoder));
5981 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5983 if (dev_priv->display.write_eld)
5984 dev_priv->display.write_eld(connector, crtc);
5987 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5988 void intel_crtc_load_lut(struct drm_crtc *crtc)
5990 struct drm_device *dev = crtc->dev;
5991 struct drm_i915_private *dev_priv = dev->dev_private;
5992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5993 int palreg = PALETTE(intel_crtc->pipe);
5996 /* The clocks have to be on to load the palette. */
5997 if (!crtc->enabled || !intel_crtc->active)
6000 /* use legacy palette for Ironlake */
6001 if (HAS_PCH_SPLIT(dev))
6002 palreg = LGC_PALETTE(intel_crtc->pipe);
6004 for (i = 0; i < 256; i++) {
6005 I915_WRITE(palreg + 4 * i,
6006 (intel_crtc->lut_r[i] << 16) |
6007 (intel_crtc->lut_g[i] << 8) |
6008 intel_crtc->lut_b[i]);
6012 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6014 struct drm_device *dev = crtc->dev;
6015 struct drm_i915_private *dev_priv = dev->dev_private;
6016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6017 bool visible = base != 0;
6020 if (intel_crtc->cursor_visible == visible)
6023 cntl = I915_READ(_CURACNTR);
6025 /* On these chipsets we can only modify the base whilst
6026 * the cursor is disabled.
6028 I915_WRITE(_CURABASE, base);
6030 cntl &= ~(CURSOR_FORMAT_MASK);
6031 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6032 cntl |= CURSOR_ENABLE |
6033 CURSOR_GAMMA_ENABLE |
6036 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6037 I915_WRITE(_CURACNTR, cntl);
6039 intel_crtc->cursor_visible = visible;
6042 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6044 struct drm_device *dev = crtc->dev;
6045 struct drm_i915_private *dev_priv = dev->dev_private;
6046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6047 int pipe = intel_crtc->pipe;
6048 bool visible = base != 0;
6050 if (intel_crtc->cursor_visible != visible) {
6051 uint32_t cntl = I915_READ(CURCNTR(pipe));
6053 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6054 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6055 cntl |= pipe << 28; /* Connect to correct pipe */
6057 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6058 cntl |= CURSOR_MODE_DISABLE;
6060 I915_WRITE(CURCNTR(pipe), cntl);
6062 intel_crtc->cursor_visible = visible;
6064 /* and commit changes on next vblank */
6065 I915_WRITE(CURBASE(pipe), base);
6068 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6070 struct drm_device *dev = crtc->dev;
6071 struct drm_i915_private *dev_priv = dev->dev_private;
6072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6073 int pipe = intel_crtc->pipe;
6074 bool visible = base != 0;
6076 if (intel_crtc->cursor_visible != visible) {
6077 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6079 cntl &= ~CURSOR_MODE;
6080 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6082 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6083 cntl |= CURSOR_MODE_DISABLE;
6085 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6087 intel_crtc->cursor_visible = visible;
6089 /* and commit changes on next vblank */
6090 I915_WRITE(CURBASE_IVB(pipe), base);
6093 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6094 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6097 struct drm_device *dev = crtc->dev;
6098 struct drm_i915_private *dev_priv = dev->dev_private;
6099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6100 int pipe = intel_crtc->pipe;
6101 int x = intel_crtc->cursor_x;
6102 int y = intel_crtc->cursor_y;
6108 if (on && crtc->enabled && crtc->fb) {
6109 base = intel_crtc->cursor_addr;
6110 if (x > (int) crtc->fb->width)
6113 if (y > (int) crtc->fb->height)
6119 if (x + intel_crtc->cursor_width < 0)
6122 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6125 pos |= x << CURSOR_X_SHIFT;
6128 if (y + intel_crtc->cursor_height < 0)
6131 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6134 pos |= y << CURSOR_Y_SHIFT;
6136 visible = base != 0;
6137 if (!visible && !intel_crtc->cursor_visible)
6140 if (IS_IVYBRIDGE(dev)) {
6141 I915_WRITE(CURPOS_IVB(pipe), pos);
6142 ivb_update_cursor(crtc, base);
6144 I915_WRITE(CURPOS(pipe), pos);
6145 if (IS_845G(dev) || IS_I865G(dev))
6146 i845_update_cursor(crtc, base);
6148 i9xx_update_cursor(crtc, base);
6152 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6155 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6156 struct drm_file *file,
6158 uint32_t width, uint32_t height)
6160 struct drm_device *dev = crtc->dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6163 struct drm_i915_gem_object *obj;
6167 DRM_DEBUG_KMS("\n");
6169 /* if we want to turn off the cursor ignore width and height */
6171 DRM_DEBUG_KMS("cursor off\n");
6174 mutex_lock(&dev->struct_mutex);
6178 /* Currently we only support 64x64 cursors */
6179 if (width != 64 || height != 64) {
6180 DRM_ERROR("we currently only support 64x64 cursors\n");
6184 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6185 if (&obj->base == NULL)
6188 if (obj->base.size < width * height * 4) {
6189 DRM_ERROR("buffer is to small\n");
6194 /* we only need to pin inside GTT if cursor is non-phy */
6195 mutex_lock(&dev->struct_mutex);
6196 if (!dev_priv->info->cursor_needs_physical) {
6197 if (obj->tiling_mode) {
6198 DRM_ERROR("cursor cannot be tiled\n");
6203 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6205 DRM_ERROR("failed to move cursor bo into the GTT\n");
6209 ret = i915_gem_object_put_fence(obj);
6211 DRM_ERROR("failed to release fence for cursor");
6215 addr = obj->gtt_offset;
6217 int align = IS_I830(dev) ? 16 * 1024 : 256;
6218 ret = i915_gem_attach_phys_object(dev, obj,
6219 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6222 DRM_ERROR("failed to attach phys object\n");
6225 addr = obj->phys_obj->handle->busaddr;
6229 I915_WRITE(CURSIZE, (height << 12) | width);
6232 if (intel_crtc->cursor_bo) {
6233 if (dev_priv->info->cursor_needs_physical) {
6234 if (intel_crtc->cursor_bo != obj)
6235 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6237 i915_gem_object_unpin(intel_crtc->cursor_bo);
6238 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6241 mutex_unlock(&dev->struct_mutex);
6243 intel_crtc->cursor_addr = addr;
6244 intel_crtc->cursor_bo = obj;
6245 intel_crtc->cursor_width = width;
6246 intel_crtc->cursor_height = height;
6248 intel_crtc_update_cursor(crtc, true);
6252 i915_gem_object_unpin(obj);
6254 mutex_unlock(&dev->struct_mutex);
6256 drm_gem_object_unreference_unlocked(&obj->base);
6260 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6264 intel_crtc->cursor_x = x;
6265 intel_crtc->cursor_y = y;
6267 intel_crtc_update_cursor(crtc, true);
6272 /** Sets the color ramps on behalf of RandR */
6273 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6274 u16 blue, int regno)
6276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6278 intel_crtc->lut_r[regno] = red >> 8;
6279 intel_crtc->lut_g[regno] = green >> 8;
6280 intel_crtc->lut_b[regno] = blue >> 8;
6283 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6284 u16 *blue, int regno)
6286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6288 *red = intel_crtc->lut_r[regno] << 8;
6289 *green = intel_crtc->lut_g[regno] << 8;
6290 *blue = intel_crtc->lut_b[regno] << 8;
6293 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6294 u16 *blue, uint32_t start, uint32_t size)
6296 int end = (start + size > 256) ? 256 : start + size, i;
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299 for (i = start; i < end; i++) {
6300 intel_crtc->lut_r[i] = red[i] >> 8;
6301 intel_crtc->lut_g[i] = green[i] >> 8;
6302 intel_crtc->lut_b[i] = blue[i] >> 8;
6305 intel_crtc_load_lut(crtc);
6309 * Get a pipe with a simple mode set on it for doing load-based monitor
6312 * It will be up to the load-detect code to adjust the pipe as appropriate for
6313 * its requirements. The pipe will be connected to no other encoders.
6315 * Currently this code will only succeed if there is a pipe with no encoders
6316 * configured for it. In the future, it could choose to temporarily disable
6317 * some outputs to free up a pipe for its use.
6319 * \return crtc, or NULL if no pipes are available.
6322 /* VESA 640x480x72Hz mode to set on the pipe */
6323 static struct drm_display_mode load_detect_mode = {
6324 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6325 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6328 static struct drm_framebuffer *
6329 intel_framebuffer_create(struct drm_device *dev,
6330 struct drm_mode_fb_cmd *mode_cmd,
6331 struct drm_i915_gem_object *obj)
6333 struct intel_framebuffer *intel_fb;
6336 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6338 drm_gem_object_unreference_unlocked(&obj->base);
6339 return ERR_PTR(-ENOMEM);
6342 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6344 drm_gem_object_unreference_unlocked(&obj->base);
6346 return ERR_PTR(ret);
6349 return &intel_fb->base;
6353 intel_framebuffer_pitch_for_width(int width, int bpp)
6355 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6356 return ALIGN(pitch, 64);
6360 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6362 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6363 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6366 static struct drm_framebuffer *
6367 intel_framebuffer_create_for_mode(struct drm_device *dev,
6368 struct drm_display_mode *mode,
6371 struct drm_i915_gem_object *obj;
6372 struct drm_mode_fb_cmd mode_cmd;
6374 obj = i915_gem_alloc_object(dev,
6375 intel_framebuffer_size_for_mode(mode, bpp));
6377 return ERR_PTR(-ENOMEM);
6379 mode_cmd.width = mode->hdisplay;
6380 mode_cmd.height = mode->vdisplay;
6381 mode_cmd.depth = depth;
6383 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6385 return intel_framebuffer_create(dev, &mode_cmd, obj);
6388 static struct drm_framebuffer *
6389 mode_fits_in_fbdev(struct drm_device *dev,
6390 struct drm_display_mode *mode)
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393 struct drm_i915_gem_object *obj;
6394 struct drm_framebuffer *fb;
6396 if (dev_priv->fbdev == NULL)
6399 obj = dev_priv->fbdev->ifb.obj;
6403 fb = &dev_priv->fbdev->ifb.base;
6404 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6405 fb->bits_per_pixel))
6408 if (obj->base.size < mode->vdisplay * fb->pitch)
6414 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6415 struct drm_connector *connector,
6416 struct drm_display_mode *mode,
6417 struct intel_load_detect_pipe *old)
6419 struct intel_crtc *intel_crtc;
6420 struct drm_crtc *possible_crtc;
6421 struct drm_encoder *encoder = &intel_encoder->base;
6422 struct drm_crtc *crtc = NULL;
6423 struct drm_device *dev = encoder->dev;
6424 struct drm_framebuffer *old_fb;
6427 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6428 connector->base.id, drm_get_connector_name(connector),
6429 encoder->base.id, drm_get_encoder_name(encoder));
6432 * Algorithm gets a little messy:
6434 * - if the connector already has an assigned crtc, use it (but make
6435 * sure it's on first)
6437 * - try to find the first unused crtc that can drive this connector,
6438 * and use that if we find one
6441 /* See if we already have a CRTC for this connector */
6442 if (encoder->crtc) {
6443 crtc = encoder->crtc;
6445 intel_crtc = to_intel_crtc(crtc);
6446 old->dpms_mode = intel_crtc->dpms_mode;
6447 old->load_detect_temp = false;
6449 /* Make sure the crtc and connector are running */
6450 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6451 struct drm_encoder_helper_funcs *encoder_funcs;
6452 struct drm_crtc_helper_funcs *crtc_funcs;
6454 crtc_funcs = crtc->helper_private;
6455 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6457 encoder_funcs = encoder->helper_private;
6458 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6464 /* Find an unused one (if possible) */
6465 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6467 if (!(encoder->possible_crtcs & (1 << i)))
6469 if (!possible_crtc->enabled) {
6470 crtc = possible_crtc;
6476 * If we didn't find an unused CRTC, don't use any.
6479 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6483 encoder->crtc = crtc;
6484 connector->encoder = encoder;
6486 intel_crtc = to_intel_crtc(crtc);
6487 old->dpms_mode = intel_crtc->dpms_mode;
6488 old->load_detect_temp = true;
6489 old->release_fb = NULL;
6492 mode = &load_detect_mode;
6496 /* We need a framebuffer large enough to accommodate all accesses
6497 * that the plane may generate whilst we perform load detection.
6498 * We can not rely on the fbcon either being present (we get called
6499 * during its initialisation to detect all boot displays, or it may
6500 * not even exist) or that it is large enough to satisfy the
6503 crtc->fb = mode_fits_in_fbdev(dev, mode);
6504 if (crtc->fb == NULL) {
6505 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6506 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6507 old->release_fb = crtc->fb;
6509 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6510 if (IS_ERR(crtc->fb)) {
6511 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6516 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6517 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6518 if (old->release_fb)
6519 old->release_fb->funcs->destroy(old->release_fb);
6524 /* let the connector get through one full cycle before testing */
6525 intel_wait_for_vblank(dev, intel_crtc->pipe);
6530 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6531 struct drm_connector *connector,
6532 struct intel_load_detect_pipe *old)
6534 struct drm_encoder *encoder = &intel_encoder->base;
6535 struct drm_device *dev = encoder->dev;
6536 struct drm_crtc *crtc = encoder->crtc;
6537 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6538 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6540 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6541 connector->base.id, drm_get_connector_name(connector),
6542 encoder->base.id, drm_get_encoder_name(encoder));
6544 if (old->load_detect_temp) {
6545 connector->encoder = NULL;
6546 drm_helper_disable_unused_functions(dev);
6548 if (old->release_fb)
6549 old->release_fb->funcs->destroy(old->release_fb);
6554 /* Switch crtc and encoder back off if necessary */
6555 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6556 encoder_funcs->dpms(encoder, old->dpms_mode);
6557 crtc_funcs->dpms(crtc, old->dpms_mode);
6561 /* Returns the clock of the currently programmed mode of the given pipe. */
6562 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6564 struct drm_i915_private *dev_priv = dev->dev_private;
6565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6566 int pipe = intel_crtc->pipe;
6567 u32 dpll = I915_READ(DPLL(pipe));
6569 intel_clock_t clock;
6571 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6572 fp = I915_READ(FP0(pipe));
6574 fp = I915_READ(FP1(pipe));
6576 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6577 if (IS_PINEVIEW(dev)) {
6578 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6579 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6581 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6582 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6585 if (!IS_GEN2(dev)) {
6586 if (IS_PINEVIEW(dev))
6587 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6588 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6590 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6591 DPLL_FPA01_P1_POST_DIV_SHIFT);
6593 switch (dpll & DPLL_MODE_MASK) {
6594 case DPLLB_MODE_DAC_SERIAL:
6595 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6598 case DPLLB_MODE_LVDS:
6599 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6603 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6604 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6608 /* XXX: Handle the 100Mhz refclk */
6609 intel_clock(dev, 96000, &clock);
6611 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6614 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6615 DPLL_FPA01_P1_POST_DIV_SHIFT);
6618 if ((dpll & PLL_REF_INPUT_MASK) ==
6619 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6620 /* XXX: might not be 66MHz */
6621 intel_clock(dev, 66000, &clock);
6623 intel_clock(dev, 48000, &clock);
6625 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6628 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6629 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6631 if (dpll & PLL_P2_DIVIDE_BY_4)
6636 intel_clock(dev, 48000, &clock);
6640 /* XXX: It would be nice to validate the clocks, but we can't reuse
6641 * i830PllIsValid() because it relies on the xf86_config connector
6642 * configuration being accurate, which it isn't necessarily.
6648 /** Returns the currently programmed mode of the given pipe. */
6649 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6650 struct drm_crtc *crtc)
6652 struct drm_i915_private *dev_priv = dev->dev_private;
6653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654 int pipe = intel_crtc->pipe;
6655 struct drm_display_mode *mode;
6656 int htot = I915_READ(HTOTAL(pipe));
6657 int hsync = I915_READ(HSYNC(pipe));
6658 int vtot = I915_READ(VTOTAL(pipe));
6659 int vsync = I915_READ(VSYNC(pipe));
6661 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6665 mode->clock = intel_crtc_clock_get(dev, crtc);
6666 mode->hdisplay = (htot & 0xffff) + 1;
6667 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6668 mode->hsync_start = (hsync & 0xffff) + 1;
6669 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6670 mode->vdisplay = (vtot & 0xffff) + 1;
6671 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6672 mode->vsync_start = (vsync & 0xffff) + 1;
6673 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6675 drm_mode_set_name(mode);
6676 drm_mode_set_crtcinfo(mode, 0);
6681 #define GPU_IDLE_TIMEOUT 500 /* ms */
6683 /* When this timer fires, we've been idle for awhile */
6684 static void intel_gpu_idle_timer(unsigned long arg)
6686 struct drm_device *dev = (struct drm_device *)arg;
6687 drm_i915_private_t *dev_priv = dev->dev_private;
6689 if (!list_empty(&dev_priv->mm.active_list)) {
6690 /* Still processing requests, so just re-arm the timer. */
6691 mod_timer(&dev_priv->idle_timer, jiffies +
6692 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6696 dev_priv->busy = false;
6697 queue_work(dev_priv->wq, &dev_priv->idle_work);
6700 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6702 static void intel_crtc_idle_timer(unsigned long arg)
6704 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6705 struct drm_crtc *crtc = &intel_crtc->base;
6706 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6707 struct intel_framebuffer *intel_fb;
6709 intel_fb = to_intel_framebuffer(crtc->fb);
6710 if (intel_fb && intel_fb->obj->active) {
6711 /* The framebuffer is still being accessed by the GPU. */
6712 mod_timer(&intel_crtc->idle_timer, jiffies +
6713 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6717 intel_crtc->busy = false;
6718 queue_work(dev_priv->wq, &dev_priv->idle_work);
6721 static void intel_increase_pllclock(struct drm_crtc *crtc)
6723 struct drm_device *dev = crtc->dev;
6724 drm_i915_private_t *dev_priv = dev->dev_private;
6725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6726 int pipe = intel_crtc->pipe;
6727 int dpll_reg = DPLL(pipe);
6730 if (HAS_PCH_SPLIT(dev))
6733 if (!dev_priv->lvds_downclock_avail)
6736 dpll = I915_READ(dpll_reg);
6737 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6738 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6740 /* Unlock panel regs */
6741 I915_WRITE(PP_CONTROL,
6742 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6744 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6745 I915_WRITE(dpll_reg, dpll);
6746 intel_wait_for_vblank(dev, pipe);
6748 dpll = I915_READ(dpll_reg);
6749 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6750 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6752 /* ...and lock them again */
6753 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6756 /* Schedule downclock */
6757 mod_timer(&intel_crtc->idle_timer, jiffies +
6758 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6761 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6763 struct drm_device *dev = crtc->dev;
6764 drm_i915_private_t *dev_priv = dev->dev_private;
6765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6766 int pipe = intel_crtc->pipe;
6767 int dpll_reg = DPLL(pipe);
6768 int dpll = I915_READ(dpll_reg);
6770 if (HAS_PCH_SPLIT(dev))
6773 if (!dev_priv->lvds_downclock_avail)
6777 * Since this is called by a timer, we should never get here in
6780 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6781 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6783 /* Unlock panel regs */
6784 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6787 dpll |= DISPLAY_RATE_SELECT_FPA1;
6788 I915_WRITE(dpll_reg, dpll);
6789 intel_wait_for_vblank(dev, pipe);
6790 dpll = I915_READ(dpll_reg);
6791 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6792 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6794 /* ...and lock them again */
6795 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6801 * intel_idle_update - adjust clocks for idleness
6802 * @work: work struct
6804 * Either the GPU or display (or both) went idle. Check the busy status
6805 * here and adjust the CRTC and GPU clocks as necessary.
6807 static void intel_idle_update(struct work_struct *work)
6809 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6811 struct drm_device *dev = dev_priv->dev;
6812 struct drm_crtc *crtc;
6813 struct intel_crtc *intel_crtc;
6815 if (!i915_powersave)
6818 mutex_lock(&dev->struct_mutex);
6820 i915_update_gfx_val(dev_priv);
6822 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6823 /* Skip inactive CRTCs */
6827 intel_crtc = to_intel_crtc(crtc);
6828 if (!intel_crtc->busy)
6829 intel_decrease_pllclock(crtc);
6833 mutex_unlock(&dev->struct_mutex);
6837 * intel_mark_busy - mark the GPU and possibly the display busy
6839 * @obj: object we're operating on
6841 * Callers can use this function to indicate that the GPU is busy processing
6842 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6843 * buffer), we'll also mark the display as busy, so we know to increase its
6846 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
6848 drm_i915_private_t *dev_priv = dev->dev_private;
6849 struct drm_crtc *crtc = NULL;
6850 struct intel_framebuffer *intel_fb;
6851 struct intel_crtc *intel_crtc;
6853 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6856 if (!dev_priv->busy)
6857 dev_priv->busy = true;
6859 mod_timer(&dev_priv->idle_timer, jiffies +
6860 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6862 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6866 intel_crtc = to_intel_crtc(crtc);
6867 intel_fb = to_intel_framebuffer(crtc->fb);
6868 if (intel_fb->obj == obj) {
6869 if (!intel_crtc->busy) {
6870 /* Non-busy -> busy, upclock */
6871 intel_increase_pllclock(crtc);
6872 intel_crtc->busy = true;
6874 /* Busy -> busy, put off timer */
6875 mod_timer(&intel_crtc->idle_timer, jiffies +
6876 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6882 static void intel_crtc_destroy(struct drm_crtc *crtc)
6884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6885 struct drm_device *dev = crtc->dev;
6886 struct intel_unpin_work *work;
6887 unsigned long flags;
6889 spin_lock_irqsave(&dev->event_lock, flags);
6890 work = intel_crtc->unpin_work;
6891 intel_crtc->unpin_work = NULL;
6892 spin_unlock_irqrestore(&dev->event_lock, flags);
6895 cancel_work_sync(&work->work);
6899 drm_crtc_cleanup(crtc);
6904 static void intel_unpin_work_fn(struct work_struct *__work)
6906 struct intel_unpin_work *work =
6907 container_of(__work, struct intel_unpin_work, work);
6909 mutex_lock(&work->dev->struct_mutex);
6910 i915_gem_object_unpin(work->old_fb_obj);
6911 drm_gem_object_unreference(&work->pending_flip_obj->base);
6912 drm_gem_object_unreference(&work->old_fb_obj->base);
6914 intel_update_fbc(work->dev);
6915 mutex_unlock(&work->dev->struct_mutex);
6919 static void do_intel_finish_page_flip(struct drm_device *dev,
6920 struct drm_crtc *crtc)
6922 drm_i915_private_t *dev_priv = dev->dev_private;
6923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6924 struct intel_unpin_work *work;
6925 struct drm_i915_gem_object *obj;
6926 struct drm_pending_vblank_event *e;
6927 struct timeval tnow, tvbl;
6928 unsigned long flags;
6930 /* Ignore early vblank irqs */
6931 if (intel_crtc == NULL)
6934 do_gettimeofday(&tnow);
6936 spin_lock_irqsave(&dev->event_lock, flags);
6937 work = intel_crtc->unpin_work;
6939 /* Ensure we don't miss a work->pending update ... */
6942 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6943 spin_unlock_irqrestore(&dev->event_lock, flags);
6947 /* and that the unpin work is consistent wrt ->pending. */
6950 intel_crtc->unpin_work = NULL;
6954 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6956 /* Called before vblank count and timestamps have
6957 * been updated for the vblank interval of flip
6958 * completion? Need to increment vblank count and
6959 * add one videorefresh duration to returned timestamp
6960 * to account for this. We assume this happened if we
6961 * get called over 0.9 frame durations after the last
6962 * timestamped vblank.
6964 * This calculation can not be used with vrefresh rates
6965 * below 5Hz (10Hz to be on the safe side) without
6966 * promoting to 64 integers.
6968 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6969 9 * crtc->framedur_ns) {
6970 e->event.sequence++;
6971 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6975 e->event.tv_sec = tvbl.tv_sec;
6976 e->event.tv_usec = tvbl.tv_usec;
6978 list_add_tail(&e->base.link,
6979 &e->base.file_priv->event_list);
6980 wake_up_interruptible(&e->base.file_priv->event_wait);
6983 drm_vblank_put(dev, intel_crtc->pipe);
6985 spin_unlock_irqrestore(&dev->event_lock, flags);
6987 obj = work->old_fb_obj;
6989 atomic_clear_mask(1 << intel_crtc->plane,
6990 &obj->pending_flip.counter);
6992 wake_up(&dev_priv->pending_flip_queue);
6993 schedule_work(&work->work);
6995 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6998 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7000 drm_i915_private_t *dev_priv = dev->dev_private;
7001 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7003 do_intel_finish_page_flip(dev, crtc);
7006 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7008 drm_i915_private_t *dev_priv = dev->dev_private;
7009 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7011 do_intel_finish_page_flip(dev, crtc);
7014 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7016 drm_i915_private_t *dev_priv = dev->dev_private;
7017 struct intel_crtc *intel_crtc =
7018 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7019 unsigned long flags;
7021 /* NB: An MMIO update of the plane base pointer will also
7022 * generate a page-flip completion irq, i.e. every modeset
7023 * is also accompanied by a spurious intel_prepare_page_flip().
7025 spin_lock_irqsave(&dev->event_lock, flags);
7026 if (intel_crtc->unpin_work)
7027 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7028 spin_unlock_irqrestore(&dev->event_lock, flags);
7031 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7033 /* Ensure that the work item is consistent when activating it ... */
7035 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7036 /* and that it is marked active as soon as the irq could fire. */
7040 static int intel_gen2_queue_flip(struct drm_device *dev,
7041 struct drm_crtc *crtc,
7042 struct drm_framebuffer *fb,
7043 struct drm_i915_gem_object *obj)
7045 struct drm_i915_private *dev_priv = dev->dev_private;
7046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7047 unsigned long offset;
7051 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7055 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7056 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7058 ret = BEGIN_LP_RING(6);
7062 /* Can't queue multiple flips, so wait for the previous
7063 * one to finish before executing the next.
7065 if (intel_crtc->plane)
7066 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7068 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7069 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7071 OUT_RING(MI_DISPLAY_FLIP |
7072 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7073 OUT_RING(fb->pitch);
7074 OUT_RING(obj->gtt_offset + offset);
7077 intel_mark_page_flip_active(intel_crtc);
7082 i915_gem_object_unpin(obj);
7087 static int intel_gen3_queue_flip(struct drm_device *dev,
7088 struct drm_crtc *crtc,
7089 struct drm_framebuffer *fb,
7090 struct drm_i915_gem_object *obj)
7092 struct drm_i915_private *dev_priv = dev->dev_private;
7093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7094 unsigned long offset;
7098 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7102 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7103 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
7105 ret = BEGIN_LP_RING(6);
7109 if (intel_crtc->plane)
7110 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7112 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7113 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7115 OUT_RING(MI_DISPLAY_FLIP_I915 |
7116 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7117 OUT_RING(fb->pitch);
7118 OUT_RING(obj->gtt_offset + offset);
7121 intel_mark_page_flip_active(intel_crtc);
7126 i915_gem_object_unpin(obj);
7131 static int intel_gen4_queue_flip(struct drm_device *dev,
7132 struct drm_crtc *crtc,
7133 struct drm_framebuffer *fb,
7134 struct drm_i915_gem_object *obj)
7136 struct drm_i915_private *dev_priv = dev->dev_private;
7137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7138 uint32_t pf, pipesrc;
7141 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7145 ret = BEGIN_LP_RING(4);
7149 /* i965+ uses the linear or tiled offsets from the
7150 * Display Registers (which do not change across a page-flip)
7151 * so we need only reprogram the base address.
7153 OUT_RING(MI_DISPLAY_FLIP |
7154 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7155 OUT_RING(fb->pitch);
7156 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7158 /* XXX Enabling the panel-fitter across page-flip is so far
7159 * untested on non-native modes, so ignore it for now.
7160 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7163 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7164 OUT_RING(pf | pipesrc);
7166 intel_mark_page_flip_active(intel_crtc);
7171 i915_gem_object_unpin(obj);
7176 static int intel_gen6_queue_flip(struct drm_device *dev,
7177 struct drm_crtc *crtc,
7178 struct drm_framebuffer *fb,
7179 struct drm_i915_gem_object *obj)
7181 struct drm_i915_private *dev_priv = dev->dev_private;
7182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7183 uint32_t pf, pipesrc;
7186 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7190 ret = BEGIN_LP_RING(4);
7194 OUT_RING(MI_DISPLAY_FLIP |
7195 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7196 OUT_RING(fb->pitch | obj->tiling_mode);
7197 OUT_RING(obj->gtt_offset);
7199 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7200 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7201 OUT_RING(pf | pipesrc);
7203 intel_mark_page_flip_active(intel_crtc);
7208 i915_gem_object_unpin(obj);
7214 * On gen7 we currently use the blit ring because (in early silicon at least)
7215 * the render ring doesn't give us interrpts for page flip completion, which
7216 * means clients will hang after the first flip is queued. Fortunately the
7217 * blit ring generates interrupts properly, so use it instead.
7219 static int intel_gen7_queue_flip(struct drm_device *dev,
7220 struct drm_crtc *crtc,
7221 struct drm_framebuffer *fb,
7222 struct drm_i915_gem_object *obj)
7224 struct drm_i915_private *dev_priv = dev->dev_private;
7225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7226 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7227 uint32_t plane_bit = 0;
7230 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7234 switch(intel_crtc->plane) {
7236 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7239 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7242 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7245 WARN_ONCE(1, "unknown plane in flip command\n");
7250 ret = intel_ring_begin(ring, 4);
7254 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7255 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7256 intel_ring_emit(ring, (obj->gtt_offset));
7257 intel_ring_emit(ring, (MI_NOOP));
7259 intel_mark_page_flip_active(intel_crtc);
7260 intel_ring_advance(ring);
7264 i915_gem_object_unpin(obj);
7269 static int intel_default_queue_flip(struct drm_device *dev,
7270 struct drm_crtc *crtc,
7271 struct drm_framebuffer *fb,
7272 struct drm_i915_gem_object *obj)
7277 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7278 struct drm_framebuffer *fb,
7279 struct drm_pending_vblank_event *event)
7281 struct drm_device *dev = crtc->dev;
7282 struct drm_i915_private *dev_priv = dev->dev_private;
7283 struct drm_framebuffer *old_fb = crtc->fb;
7284 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7286 struct intel_unpin_work *work;
7287 unsigned long flags;
7290 work = kzalloc(sizeof *work, GFP_KERNEL);
7294 work->event = event;
7295 work->dev = crtc->dev;
7296 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7297 INIT_WORK(&work->work, intel_unpin_work_fn);
7299 ret = drm_vblank_get(dev, intel_crtc->pipe);
7303 /* We borrow the event spin lock for protecting unpin_work */
7304 spin_lock_irqsave(&dev->event_lock, flags);
7305 if (intel_crtc->unpin_work) {
7306 spin_unlock_irqrestore(&dev->event_lock, flags);
7308 drm_vblank_put(dev, intel_crtc->pipe);
7310 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7313 intel_crtc->unpin_work = work;
7314 spin_unlock_irqrestore(&dev->event_lock, flags);
7316 mutex_lock(&dev->struct_mutex);
7318 /* Reference the objects for the scheduled work. */
7319 drm_gem_object_reference(&work->old_fb_obj->base);
7320 drm_gem_object_reference(&obj->base);
7324 work->pending_flip_obj = obj;
7326 work->enable_stall_check = true;
7328 /* Block clients from rendering to the new back buffer until
7329 * the flip occurs and the object is no longer visible.
7331 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7333 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7335 goto cleanup_pending;
7337 intel_disable_fbc(dev);
7338 mutex_unlock(&dev->struct_mutex);
7340 trace_i915_flip_request(intel_crtc->plane, obj);
7345 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7347 drm_gem_object_unreference(&work->old_fb_obj->base);
7348 drm_gem_object_unreference(&obj->base);
7349 mutex_unlock(&dev->struct_mutex);
7351 spin_lock_irqsave(&dev->event_lock, flags);
7352 intel_crtc->unpin_work = NULL;
7353 spin_unlock_irqrestore(&dev->event_lock, flags);
7355 drm_vblank_put(dev, intel_crtc->pipe);
7362 static void intel_sanitize_modesetting(struct drm_device *dev,
7363 int pipe, int plane)
7365 struct drm_i915_private *dev_priv = dev->dev_private;
7369 /* Clear any frame start delays used for debugging left by the BIOS */
7372 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7375 if (HAS_PCH_SPLIT(dev))
7378 /* Who knows what state these registers were left in by the BIOS or
7381 * If we leave the registers in a conflicting state (e.g. with the
7382 * display plane reading from the other pipe than the one we intend
7383 * to use) then when we attempt to teardown the active mode, we will
7384 * not disable the pipes and planes in the correct order -- leaving
7385 * a plane reading from a disabled pipe and possibly leading to
7386 * undefined behaviour.
7389 reg = DSPCNTR(plane);
7390 val = I915_READ(reg);
7392 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7394 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7397 /* This display plane is active and attached to the other CPU pipe. */
7400 /* Disable the plane and wait for it to stop reading from the pipe. */
7401 intel_disable_plane(dev_priv, plane, pipe);
7402 intel_disable_pipe(dev_priv, pipe);
7405 static void intel_crtc_reset(struct drm_crtc *crtc)
7407 struct drm_device *dev = crtc->dev;
7408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7410 /* Reset flags back to the 'unknown' status so that they
7411 * will be correctly set on the initial modeset.
7413 intel_crtc->dpms_mode = -1;
7415 /* We need to fix up any BIOS configuration that conflicts with
7418 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7421 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7422 .dpms = intel_crtc_dpms,
7423 .mode_fixup = intel_crtc_mode_fixup,
7424 .mode_set = intel_crtc_mode_set,
7425 .mode_set_base = intel_pipe_set_base,
7426 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7427 .load_lut = intel_crtc_load_lut,
7428 .disable = intel_crtc_disable,
7431 static const struct drm_crtc_funcs intel_crtc_funcs = {
7432 .reset = intel_crtc_reset,
7433 .cursor_set = intel_crtc_cursor_set,
7434 .cursor_move = intel_crtc_cursor_move,
7435 .gamma_set = intel_crtc_gamma_set,
7436 .set_config = drm_crtc_helper_set_config,
7437 .destroy = intel_crtc_destroy,
7438 .page_flip = intel_crtc_page_flip,
7441 static void intel_crtc_init(struct drm_device *dev, int pipe)
7443 drm_i915_private_t *dev_priv = dev->dev_private;
7444 struct intel_crtc *intel_crtc;
7447 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7448 if (intel_crtc == NULL)
7451 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7453 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7454 for (i = 0; i < 256; i++) {
7455 intel_crtc->lut_r[i] = i;
7456 intel_crtc->lut_g[i] = i;
7457 intel_crtc->lut_b[i] = i;
7460 /* Swap pipes & planes for FBC on pre-965 */
7461 intel_crtc->pipe = pipe;
7462 intel_crtc->plane = pipe;
7463 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7464 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7465 intel_crtc->plane = !pipe;
7468 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7469 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7470 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7471 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7473 intel_crtc_reset(&intel_crtc->base);
7474 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7475 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7477 if (HAS_PCH_SPLIT(dev)) {
7478 if (pipe == 2 && IS_IVYBRIDGE(dev))
7479 intel_crtc->no_pll = true;
7480 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7481 intel_helper_funcs.commit = ironlake_crtc_commit;
7483 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7484 intel_helper_funcs.commit = i9xx_crtc_commit;
7487 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7489 intel_crtc->busy = false;
7491 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7492 (unsigned long)intel_crtc);
7495 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7496 struct drm_file *file)
7498 drm_i915_private_t *dev_priv = dev->dev_private;
7499 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7500 struct drm_mode_object *drmmode_obj;
7501 struct intel_crtc *crtc;
7504 DRM_ERROR("called with no initialization\n");
7508 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7509 DRM_MODE_OBJECT_CRTC);
7512 DRM_ERROR("no such CRTC id\n");
7516 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7517 pipe_from_crtc_id->pipe = crtc->pipe;
7522 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7524 struct intel_encoder *encoder;
7528 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7529 if (type_mask & encoder->clone_mask)
7530 index_mask |= (1 << entry);
7537 static bool has_edp_a(struct drm_device *dev)
7539 struct drm_i915_private *dev_priv = dev->dev_private;
7541 if (!IS_MOBILE(dev))
7544 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7548 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7554 static void intel_setup_outputs(struct drm_device *dev)
7556 struct drm_i915_private *dev_priv = dev->dev_private;
7557 struct intel_encoder *encoder;
7558 bool dpd_is_edp = false;
7559 bool has_lvds = false;
7561 if (IS_MOBILE(dev) && !IS_I830(dev))
7562 has_lvds = intel_lvds_init(dev);
7563 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7564 /* disable the panel fitter on everything but LVDS */
7565 I915_WRITE(PFIT_CONTROL, 0);
7568 if (HAS_PCH_SPLIT(dev)) {
7569 dpd_is_edp = intel_dpd_is_edp(dev);
7572 intel_dp_init(dev, DP_A);
7574 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7575 intel_dp_init(dev, PCH_DP_D);
7578 intel_crt_init(dev);
7580 if (HAS_PCH_SPLIT(dev)) {
7583 if (I915_READ(HDMIB) & PORT_DETECTED) {
7584 /* PCH SDVOB multiplex with HDMIB */
7585 found = intel_sdvo_init(dev, PCH_SDVOB);
7587 intel_hdmi_init(dev, HDMIB);
7588 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7589 intel_dp_init(dev, PCH_DP_B);
7592 if (I915_READ(HDMIC) & PORT_DETECTED)
7593 intel_hdmi_init(dev, HDMIC);
7595 if (I915_READ(HDMID) & PORT_DETECTED)
7596 intel_hdmi_init(dev, HDMID);
7598 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7599 intel_dp_init(dev, PCH_DP_C);
7601 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7602 intel_dp_init(dev, PCH_DP_D);
7604 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7607 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7608 DRM_DEBUG_KMS("probing SDVOB\n");
7609 found = intel_sdvo_init(dev, SDVOB);
7610 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7611 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7612 intel_hdmi_init(dev, SDVOB);
7615 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7616 DRM_DEBUG_KMS("probing DP_B\n");
7617 intel_dp_init(dev, DP_B);
7621 /* Before G4X SDVOC doesn't have its own detect register */
7623 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7624 DRM_DEBUG_KMS("probing SDVOC\n");
7625 found = intel_sdvo_init(dev, SDVOC);
7628 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7630 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7631 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7632 intel_hdmi_init(dev, SDVOC);
7634 if (SUPPORTS_INTEGRATED_DP(dev)) {
7635 DRM_DEBUG_KMS("probing DP_C\n");
7636 intel_dp_init(dev, DP_C);
7640 if (SUPPORTS_INTEGRATED_DP(dev) &&
7641 (I915_READ(DP_D) & DP_DETECTED)) {
7642 DRM_DEBUG_KMS("probing DP_D\n");
7643 intel_dp_init(dev, DP_D);
7645 } else if (IS_GEN2(dev))
7646 intel_dvo_init(dev);
7648 if (SUPPORTS_TV(dev))
7651 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7652 encoder->base.possible_crtcs = encoder->crtc_mask;
7653 encoder->base.possible_clones =
7654 intel_encoder_clones(dev, encoder->clone_mask);
7657 /* disable all the possible outputs/crtcs before entering KMS mode */
7658 drm_helper_disable_unused_functions(dev);
7660 if (HAS_PCH_SPLIT(dev))
7661 ironlake_init_pch_refclk(dev);
7664 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7666 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7668 drm_framebuffer_cleanup(fb);
7669 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7674 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7675 struct drm_file *file,
7676 unsigned int *handle)
7678 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7679 struct drm_i915_gem_object *obj = intel_fb->obj;
7681 return drm_gem_handle_create(file, &obj->base, handle);
7684 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7685 .destroy = intel_user_framebuffer_destroy,
7686 .create_handle = intel_user_framebuffer_create_handle,
7689 int intel_framebuffer_init(struct drm_device *dev,
7690 struct intel_framebuffer *intel_fb,
7691 struct drm_mode_fb_cmd *mode_cmd,
7692 struct drm_i915_gem_object *obj)
7696 if (obj->tiling_mode == I915_TILING_Y)
7699 if (mode_cmd->pitch & 63)
7702 switch (mode_cmd->bpp) {
7705 /* Only pre-ILK can handle 5:5:5 */
7706 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7717 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7719 DRM_ERROR("framebuffer init failed %d\n", ret);
7723 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7724 intel_fb->obj = obj;
7728 static struct drm_framebuffer *
7729 intel_user_framebuffer_create(struct drm_device *dev,
7730 struct drm_file *filp,
7731 struct drm_mode_fb_cmd *mode_cmd)
7733 struct drm_i915_gem_object *obj;
7735 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
7736 if (&obj->base == NULL)
7737 return ERR_PTR(-ENOENT);
7739 return intel_framebuffer_create(dev, mode_cmd, obj);
7742 static const struct drm_mode_config_funcs intel_mode_funcs = {
7743 .fb_create = intel_user_framebuffer_create,
7744 .output_poll_changed = intel_fb_output_poll_changed,
7747 static struct drm_i915_gem_object *
7748 intel_alloc_context_page(struct drm_device *dev)
7750 struct drm_i915_gem_object *ctx;
7753 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7755 ctx = i915_gem_alloc_object(dev, 4096);
7757 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7761 ret = i915_gem_object_pin(ctx, 4096, true);
7763 DRM_ERROR("failed to pin power context: %d\n", ret);
7767 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7769 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7776 i915_gem_object_unpin(ctx);
7778 drm_gem_object_unreference(&ctx->base);
7779 mutex_unlock(&dev->struct_mutex);
7783 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7785 struct drm_i915_private *dev_priv = dev->dev_private;
7788 rgvswctl = I915_READ16(MEMSWCTL);
7789 if (rgvswctl & MEMCTL_CMD_STS) {
7790 DRM_DEBUG("gpu busy, RCS change rejected\n");
7791 return false; /* still busy with another command */
7794 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7795 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7796 I915_WRITE16(MEMSWCTL, rgvswctl);
7797 POSTING_READ16(MEMSWCTL);
7799 rgvswctl |= MEMCTL_CMD_STS;
7800 I915_WRITE16(MEMSWCTL, rgvswctl);
7805 void ironlake_enable_drps(struct drm_device *dev)
7807 struct drm_i915_private *dev_priv = dev->dev_private;
7808 u32 rgvmodectl = I915_READ(MEMMODECTL);
7809 u8 fmax, fmin, fstart, vstart;
7811 /* Enable temp reporting */
7812 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7813 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7815 /* 100ms RC evaluation intervals */
7816 I915_WRITE(RCUPEI, 100000);
7817 I915_WRITE(RCDNEI, 100000);
7819 /* Set max/min thresholds to 90ms and 80ms respectively */
7820 I915_WRITE(RCBMAXAVG, 90000);
7821 I915_WRITE(RCBMINAVG, 80000);
7823 I915_WRITE(MEMIHYST, 1);
7825 /* Set up min, max, and cur for interrupt handling */
7826 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7827 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7828 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7829 MEMMODE_FSTART_SHIFT;
7831 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7834 dev_priv->fmax = fmax; /* IPS callback will increase this */
7835 dev_priv->fstart = fstart;
7837 dev_priv->max_delay = fstart;
7838 dev_priv->min_delay = fmin;
7839 dev_priv->cur_delay = fstart;
7841 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7842 fmax, fmin, fstart);
7844 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7847 * Interrupts will be enabled in ironlake_irq_postinstall
7850 I915_WRITE(VIDSTART, vstart);
7851 POSTING_READ(VIDSTART);
7853 rgvmodectl |= MEMMODE_SWMODE_EN;
7854 I915_WRITE(MEMMODECTL, rgvmodectl);
7856 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
7857 DRM_ERROR("stuck trying to change perf mode\n");
7860 ironlake_set_drps(dev, fstart);
7862 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7864 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7865 dev_priv->last_count2 = I915_READ(0x112f4);
7866 getrawmonotonic(&dev_priv->last_time2);
7869 void ironlake_disable_drps(struct drm_device *dev)
7871 struct drm_i915_private *dev_priv = dev->dev_private;
7872 u16 rgvswctl = I915_READ16(MEMSWCTL);
7874 /* Ack interrupts, disable EFC interrupt */
7875 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7876 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7877 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7878 I915_WRITE(DEIIR, DE_PCU_EVENT);
7879 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7881 /* Go back to the starting frequency */
7882 ironlake_set_drps(dev, dev_priv->fstart);
7884 rgvswctl |= MEMCTL_CMD_STS;
7885 I915_WRITE(MEMSWCTL, rgvswctl);
7890 void gen6_set_rps(struct drm_device *dev, u8 val)
7892 struct drm_i915_private *dev_priv = dev->dev_private;
7895 swreq = (val & 0x3ff) << 25;
7896 I915_WRITE(GEN6_RPNSWREQ, swreq);
7899 void gen6_disable_rps(struct drm_device *dev)
7901 struct drm_i915_private *dev_priv = dev->dev_private;
7903 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7904 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7905 I915_WRITE(GEN6_PMIER, 0);
7906 /* Complete PM interrupt masking here doesn't race with the rps work
7907 * item again unmasking PM interrupts because that is using a different
7908 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7909 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
7911 spin_lock_irq(&dev_priv->rps_lock);
7912 dev_priv->pm_iir = 0;
7913 spin_unlock_irq(&dev_priv->rps_lock);
7915 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7918 static unsigned long intel_pxfreq(u32 vidfreq)
7921 int div = (vidfreq & 0x3f0000) >> 16;
7922 int post = (vidfreq & 0x3000) >> 12;
7923 int pre = (vidfreq & 0x7);
7928 freq = ((div * 133333) / ((1<<post) * pre));
7933 void intel_init_emon(struct drm_device *dev)
7935 struct drm_i915_private *dev_priv = dev->dev_private;
7940 /* Disable to program */
7944 /* Program energy weights for various events */
7945 I915_WRITE(SDEW, 0x15040d00);
7946 I915_WRITE(CSIEW0, 0x007f0000);
7947 I915_WRITE(CSIEW1, 0x1e220004);
7948 I915_WRITE(CSIEW2, 0x04000004);
7950 for (i = 0; i < 5; i++)
7951 I915_WRITE(PEW + (i * 4), 0);
7952 for (i = 0; i < 3; i++)
7953 I915_WRITE(DEW + (i * 4), 0);
7955 /* Program P-state weights to account for frequency power adjustment */
7956 for (i = 0; i < 16; i++) {
7957 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7958 unsigned long freq = intel_pxfreq(pxvidfreq);
7959 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7964 val *= (freq / 1000);
7966 val /= (127*127*900);
7968 DRM_ERROR("bad pxval: %ld\n", val);
7971 /* Render standby states get 0 weight */
7975 for (i = 0; i < 4; i++) {
7976 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7977 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7978 I915_WRITE(PXW + (i * 4), val);
7981 /* Adjust magic regs to magic values (more experimental results) */
7982 I915_WRITE(OGW0, 0);
7983 I915_WRITE(OGW1, 0);
7984 I915_WRITE(EG0, 0x00007f00);
7985 I915_WRITE(EG1, 0x0000000e);
7986 I915_WRITE(EG2, 0x000e0000);
7987 I915_WRITE(EG3, 0x68000300);
7988 I915_WRITE(EG4, 0x42000000);
7989 I915_WRITE(EG5, 0x00140031);
7993 for (i = 0; i < 8; i++)
7994 I915_WRITE(PXWL + (i * 4), 0);
7996 /* Enable PMON + select events */
7997 I915_WRITE(ECR, 0x80000019);
7999 lcfuse = I915_READ(LCFUSE02);
8001 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8004 static bool intel_enable_rc6(struct drm_device *dev)
8007 * Respect the kernel parameter if it is set
8009 if (i915_enable_rc6 >= 0)
8010 return i915_enable_rc6;
8013 * Disable RC6 on Ironlake
8015 if (INTEL_INFO(dev)->gen == 5)
8019 * Disable rc6 on Sandybridge
8021 if (INTEL_INFO(dev)->gen == 6) {
8022 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8025 DRM_DEBUG_DRIVER("RC6 enabled\n");
8029 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8031 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8032 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8033 u32 pcu_mbox, rc6_mask = 0;
8034 int cur_freq, min_freq, max_freq;
8037 /* Here begins a magic sequence of register writes to enable
8038 * auto-downclocking.
8040 * Perhaps there might be some value in exposing these to
8043 I915_WRITE(GEN6_RC_STATE, 0);
8044 mutex_lock(&dev_priv->dev->struct_mutex);
8045 gen6_gt_force_wake_get(dev_priv);
8047 /* disable the counters and set deterministic thresholds */
8048 I915_WRITE(GEN6_RC_CONTROL, 0);
8050 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8051 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8052 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8053 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8054 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8056 for (i = 0; i < I915_NUM_RINGS; i++)
8057 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8059 I915_WRITE(GEN6_RC_SLEEP, 0);
8060 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8061 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8062 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
8063 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8065 if (intel_enable_rc6(dev_priv->dev))
8066 rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
8067 ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0);
8069 I915_WRITE(GEN6_RC_CONTROL,
8071 GEN6_RC_CTL_EI_MODE(1) |
8072 GEN6_RC_CTL_HW_ENABLE);
8074 I915_WRITE(GEN6_RPNSWREQ,
8075 GEN6_FREQUENCY(10) |
8077 GEN6_AGGRESSIVE_TURBO);
8078 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8079 GEN6_FREQUENCY(12));
8081 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8082 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8085 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8086 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8087 I915_WRITE(GEN6_RP_UP_EI, 100000);
8088 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8089 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8090 I915_WRITE(GEN6_RP_CONTROL,
8091 GEN6_RP_MEDIA_TURBO |
8092 GEN6_RP_MEDIA_HW_NORMAL_MODE |
8093 GEN6_RP_MEDIA_IS_GFX |
8095 GEN6_RP_UP_BUSY_AVG |
8096 GEN6_RP_DOWN_IDLE_CONT);
8098 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8100 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8102 I915_WRITE(GEN6_PCODE_DATA, 0);
8103 I915_WRITE(GEN6_PCODE_MAILBOX,
8105 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8106 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8108 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8110 min_freq = (rp_state_cap & 0xff0000) >> 16;
8111 max_freq = rp_state_cap & 0xff;
8112 cur_freq = (gt_perf_status & 0xff00) >> 8;
8114 /* Check for overclock support */
8115 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8117 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8118 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8119 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8120 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8122 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8123 if (pcu_mbox & (1<<31)) { /* OC supported */
8124 max_freq = pcu_mbox & 0xff;
8125 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8128 /* In units of 100MHz */
8129 dev_priv->max_delay = max_freq;
8130 dev_priv->min_delay = min_freq;
8131 dev_priv->cur_delay = cur_freq;
8133 /* requires MSI enabled */
8134 I915_WRITE(GEN6_PMIER,
8135 GEN6_PM_MBOX_EVENT |
8136 GEN6_PM_THERMAL_EVENT |
8137 GEN6_PM_RP_DOWN_TIMEOUT |
8138 GEN6_PM_RP_UP_THRESHOLD |
8139 GEN6_PM_RP_DOWN_THRESHOLD |
8140 GEN6_PM_RP_UP_EI_EXPIRED |
8141 GEN6_PM_RP_DOWN_EI_EXPIRED);
8142 spin_lock_irq(&dev_priv->rps_lock);
8143 WARN_ON(dev_priv->pm_iir != 0);
8144 I915_WRITE(GEN6_PMIMR, 0);
8145 spin_unlock_irq(&dev_priv->rps_lock);
8146 /* enable all PM interrupts */
8147 I915_WRITE(GEN6_PMINTRMSK, 0);
8149 gen6_gt_force_wake_put(dev_priv);
8150 mutex_unlock(&dev_priv->dev->struct_mutex);
8153 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8156 int gpu_freq, ia_freq, max_ia_freq;
8157 int scaling_factor = 180;
8159 max_ia_freq = cpufreq_quick_get_max(0);
8161 * Default to measured freq if none found, PCU will ensure we don't go
8165 max_ia_freq = tsc_khz;
8167 /* Convert from kHz to MHz */
8168 max_ia_freq /= 1000;
8170 mutex_lock(&dev_priv->dev->struct_mutex);
8173 * For each potential GPU frequency, load a ring frequency we'd like
8174 * to use for memory access. We do this by specifying the IA frequency
8175 * the PCU should use as a reference to determine the ring frequency.
8177 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8179 int diff = dev_priv->max_delay - gpu_freq;
8182 * For GPU frequencies less than 750MHz, just use the lowest
8185 if (gpu_freq < min_freq)
8188 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8189 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8191 I915_WRITE(GEN6_PCODE_DATA,
8192 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8194 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8195 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8196 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8197 GEN6_PCODE_READY) == 0, 10)) {
8198 DRM_ERROR("pcode write of freq table timed out\n");
8203 mutex_unlock(&dev_priv->dev->struct_mutex);
8206 static void ironlake_init_clock_gating(struct drm_device *dev)
8208 struct drm_i915_private *dev_priv = dev->dev_private;
8209 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8211 /* Required for FBC */
8212 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8213 DPFCRUNIT_CLOCK_GATE_DISABLE |
8214 DPFDUNIT_CLOCK_GATE_DISABLE;
8215 /* Required for CxSR */
8216 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8218 I915_WRITE(PCH_3DCGDIS0,
8219 MARIUNIT_CLOCK_GATE_DISABLE |
8220 SVSMUNIT_CLOCK_GATE_DISABLE);
8221 I915_WRITE(PCH_3DCGDIS1,
8222 VFMUNIT_CLOCK_GATE_DISABLE);
8224 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8227 * According to the spec the following bits should be set in
8228 * order to enable memory self-refresh
8229 * The bit 22/21 of 0x42004
8230 * The bit 5 of 0x42020
8231 * The bit 15 of 0x45000
8233 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8234 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8235 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8236 I915_WRITE(ILK_DSPCLK_GATE,
8237 (I915_READ(ILK_DSPCLK_GATE) |
8238 ILK_DPARB_CLK_GATE));
8239 I915_WRITE(DISP_ARB_CTL,
8240 (I915_READ(DISP_ARB_CTL) |
8242 I915_WRITE(WM3_LP_ILK, 0);
8243 I915_WRITE(WM2_LP_ILK, 0);
8244 I915_WRITE(WM1_LP_ILK, 0);
8247 * Based on the document from hardware guys the following bits
8248 * should be set unconditionally in order to enable FBC.
8249 * The bit 22 of 0x42000
8250 * The bit 22 of 0x42004
8251 * The bit 7,8,9 of 0x42020.
8253 if (IS_IRONLAKE_M(dev)) {
8254 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8255 I915_READ(ILK_DISPLAY_CHICKEN1) |
8257 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8258 I915_READ(ILK_DISPLAY_CHICKEN2) |
8260 I915_WRITE(ILK_DSPCLK_GATE,
8261 I915_READ(ILK_DSPCLK_GATE) |
8267 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8268 I915_READ(ILK_DISPLAY_CHICKEN2) |
8269 ILK_ELPIN_409_SELECT);
8270 I915_WRITE(_3D_CHICKEN2,
8271 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8272 _3D_CHICKEN2_WM_READ_PIPELINED);
8275 static void gen6_init_clock_gating(struct drm_device *dev)
8277 struct drm_i915_private *dev_priv = dev->dev_private;
8279 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8281 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8283 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8284 I915_READ(ILK_DISPLAY_CHICKEN2) |
8285 ILK_ELPIN_409_SELECT);
8287 /* WaDisableHiZPlanesWhenMSAAEnabled */
8288 I915_WRITE(_3D_CHICKEN,
8289 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
8291 I915_WRITE(WM3_LP_ILK, 0);
8292 I915_WRITE(WM2_LP_ILK, 0);
8293 I915_WRITE(WM1_LP_ILK, 0);
8295 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8296 * gating disable must be set. Failure to set it results in
8297 * flickering pixels due to Z write ordering failures after
8298 * some amount of runtime in the Mesa "fire" demo, and Unigine
8299 * Sanctuary and Tropics, and apparently anything else with
8300 * alpha test or pixel discard.
8302 * According to the spec, bit 11 (RCCUNIT) must also be set,
8303 * but we didn't debug actual testcases to find it out.
8305 I915_WRITE(GEN6_UCGCTL2,
8306 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8307 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8310 * According to the spec the following bits should be
8311 * set in order to enable memory self-refresh and fbc:
8312 * The bit21 and bit22 of 0x42000
8313 * The bit21 and bit22 of 0x42004
8314 * The bit5 and bit7 of 0x42020
8315 * The bit14 of 0x70180
8316 * The bit14 of 0x71180
8318 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8319 I915_READ(ILK_DISPLAY_CHICKEN1) |
8320 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8321 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8322 I915_READ(ILK_DISPLAY_CHICKEN2) |
8323 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8324 I915_WRITE(ILK_DSPCLK_GATE,
8325 I915_READ(ILK_DSPCLK_GATE) |
8326 ILK_DPARB_CLK_GATE |
8329 for_each_pipe(pipe) {
8330 I915_WRITE(DSPCNTR(pipe),
8331 I915_READ(DSPCNTR(pipe)) |
8332 DISPPLANE_TRICKLE_FEED_DISABLE);
8333 intel_flush_display_plane(dev_priv, pipe);
8336 /* The default value should be 0x200 according to docs, but the two
8337 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
8338 I915_WRITE(GEN6_GT_MODE, 0xffff << 16);
8339 I915_WRITE(GEN6_GT_MODE, GEN6_GT_MODE_HI << 16 | GEN6_GT_MODE_HI);
8342 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
8344 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
8346 reg &= ~GEN7_FF_SCHED_MASK;
8347 reg |= GEN7_FF_TS_SCHED_HW;
8348 reg |= GEN7_FF_VS_SCHED_HW;
8349 reg |= GEN7_FF_DS_SCHED_HW;
8351 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
8354 static void ivybridge_init_clock_gating(struct drm_device *dev)
8356 struct drm_i915_private *dev_priv = dev->dev_private;
8358 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8360 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8362 I915_WRITE(WM3_LP_ILK, 0);
8363 I915_WRITE(WM2_LP_ILK, 0);
8364 I915_WRITE(WM1_LP_ILK, 0);
8366 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8367 * This implements the WaDisableRCZUnitClockGating workaround.
8369 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
8371 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8373 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8374 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
8375 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
8377 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8378 I915_WRITE(GEN7_L3CNTLREG1,
8379 GEN7_WA_FOR_GEN7_L3_CONTROL);
8380 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8381 GEN7_WA_L3_CHICKEN_MODE);
8383 /* This is required by WaCatErrorRejectionIssue */
8384 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
8385 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
8386 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
8388 for_each_pipe(pipe) {
8389 I915_WRITE(DSPCNTR(pipe),
8390 I915_READ(DSPCNTR(pipe)) |
8391 DISPPLANE_TRICKLE_FEED_DISABLE);
8392 intel_flush_display_plane(dev_priv, pipe);
8395 gen7_setup_fixed_func_scheduler(dev_priv);
8398 static void g4x_init_clock_gating(struct drm_device *dev)
8400 struct drm_i915_private *dev_priv = dev->dev_private;
8401 uint32_t dspclk_gate;
8403 I915_WRITE(RENCLK_GATE_D1, 0);
8404 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8405 GS_UNIT_CLOCK_GATE_DISABLE |
8406 CL_UNIT_CLOCK_GATE_DISABLE);
8407 I915_WRITE(RAMCLK_GATE_D, 0);
8408 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8409 OVRUNIT_CLOCK_GATE_DISABLE |
8410 OVCUNIT_CLOCK_GATE_DISABLE;
8412 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8413 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8416 static void crestline_init_clock_gating(struct drm_device *dev)
8418 struct drm_i915_private *dev_priv = dev->dev_private;
8420 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8421 I915_WRITE(RENCLK_GATE_D2, 0);
8422 I915_WRITE(DSPCLK_GATE_D, 0);
8423 I915_WRITE(RAMCLK_GATE_D, 0);
8424 I915_WRITE16(DEUC, 0);
8427 static void broadwater_init_clock_gating(struct drm_device *dev)
8429 struct drm_i915_private *dev_priv = dev->dev_private;
8431 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8432 I965_RCC_CLOCK_GATE_DISABLE |
8433 I965_RCPB_CLOCK_GATE_DISABLE |
8434 I965_ISC_CLOCK_GATE_DISABLE |
8435 I965_FBC_CLOCK_GATE_DISABLE);
8436 I915_WRITE(RENCLK_GATE_D2, 0);
8439 static void gen3_init_clock_gating(struct drm_device *dev)
8441 struct drm_i915_private *dev_priv = dev->dev_private;
8442 u32 dstate = I915_READ(D_STATE);
8444 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8445 DSTATE_DOT_CLOCK_GATING;
8446 I915_WRITE(D_STATE, dstate);
8449 static void i85x_init_clock_gating(struct drm_device *dev)
8451 struct drm_i915_private *dev_priv = dev->dev_private;
8453 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8456 static void i830_init_clock_gating(struct drm_device *dev)
8458 struct drm_i915_private *dev_priv = dev->dev_private;
8460 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8463 static void ibx_init_clock_gating(struct drm_device *dev)
8465 struct drm_i915_private *dev_priv = dev->dev_private;
8468 * On Ibex Peak and Cougar Point, we need to disable clock
8469 * gating for the panel power sequencer or it will fail to
8470 * start up when no ports are active.
8472 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8475 static void cpt_init_clock_gating(struct drm_device *dev)
8477 struct drm_i915_private *dev_priv = dev->dev_private;
8481 * On Ibex Peak and Cougar Point, we need to disable clock
8482 * gating for the panel power sequencer or it will fail to
8483 * start up when no ports are active.
8485 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8486 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8487 DPLS_EDP_PPS_FIX_DIS);
8488 /* Without this, mode sets may fail silently on FDI */
8490 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8493 static void ironlake_teardown_rc6(struct drm_device *dev)
8495 struct drm_i915_private *dev_priv = dev->dev_private;
8497 if (dev_priv->renderctx) {
8498 i915_gem_object_unpin(dev_priv->renderctx);
8499 drm_gem_object_unreference(&dev_priv->renderctx->base);
8500 dev_priv->renderctx = NULL;
8503 if (dev_priv->pwrctx) {
8504 i915_gem_object_unpin(dev_priv->pwrctx);
8505 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8506 dev_priv->pwrctx = NULL;
8510 static void ironlake_disable_rc6(struct drm_device *dev)
8512 struct drm_i915_private *dev_priv = dev->dev_private;
8514 if (I915_READ(PWRCTXA)) {
8515 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8516 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8517 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8520 I915_WRITE(PWRCTXA, 0);
8521 POSTING_READ(PWRCTXA);
8523 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8524 POSTING_READ(RSTDBYCTL);
8527 ironlake_teardown_rc6(dev);
8530 static int ironlake_setup_rc6(struct drm_device *dev)
8532 struct drm_i915_private *dev_priv = dev->dev_private;
8534 if (dev_priv->renderctx == NULL)
8535 dev_priv->renderctx = intel_alloc_context_page(dev);
8536 if (!dev_priv->renderctx)
8539 if (dev_priv->pwrctx == NULL)
8540 dev_priv->pwrctx = intel_alloc_context_page(dev);
8541 if (!dev_priv->pwrctx) {
8542 ironlake_teardown_rc6(dev);
8549 void ironlake_enable_rc6(struct drm_device *dev)
8551 struct drm_i915_private *dev_priv = dev->dev_private;
8554 /* rc6 disabled by default due to repeated reports of hanging during
8557 if (!intel_enable_rc6(dev))
8560 mutex_lock(&dev->struct_mutex);
8561 ret = ironlake_setup_rc6(dev);
8563 mutex_unlock(&dev->struct_mutex);
8568 * GPU can automatically power down the render unit if given a page
8571 ret = BEGIN_LP_RING(6);
8573 ironlake_teardown_rc6(dev);
8574 mutex_unlock(&dev->struct_mutex);
8578 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8579 OUT_RING(MI_SET_CONTEXT);
8580 OUT_RING(dev_priv->renderctx->gtt_offset |
8582 MI_SAVE_EXT_STATE_EN |
8583 MI_RESTORE_EXT_STATE_EN |
8584 MI_RESTORE_INHIBIT);
8585 OUT_RING(MI_SUSPEND_FLUSH);
8591 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8592 * does an implicit flush, combined with MI_FLUSH above, it should be
8593 * safe to assume that renderctx is valid
8595 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8597 DRM_ERROR("failed to enable ironlake power power savings\n");
8598 ironlake_teardown_rc6(dev);
8599 mutex_unlock(&dev->struct_mutex);
8603 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8604 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8605 mutex_unlock(&dev->struct_mutex);
8608 void intel_init_clock_gating(struct drm_device *dev)
8610 struct drm_i915_private *dev_priv = dev->dev_private;
8612 dev_priv->display.init_clock_gating(dev);
8614 if (dev_priv->display.init_pch_clock_gating)
8615 dev_priv->display.init_pch_clock_gating(dev);
8618 /* Set up chip specific display functions */
8619 static void intel_init_display(struct drm_device *dev)
8621 struct drm_i915_private *dev_priv = dev->dev_private;
8623 /* We always want a DPMS function */
8624 if (HAS_PCH_SPLIT(dev)) {
8625 dev_priv->display.dpms = ironlake_crtc_dpms;
8626 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8627 dev_priv->display.update_plane = ironlake_update_plane;
8629 dev_priv->display.dpms = i9xx_crtc_dpms;
8630 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8631 dev_priv->display.update_plane = i9xx_update_plane;
8634 if (I915_HAS_FBC(dev)) {
8635 if (HAS_PCH_SPLIT(dev)) {
8636 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8637 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8638 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8639 } else if (IS_GM45(dev)) {
8640 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8641 dev_priv->display.enable_fbc = g4x_enable_fbc;
8642 dev_priv->display.disable_fbc = g4x_disable_fbc;
8643 } else if (IS_CRESTLINE(dev)) {
8644 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8645 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8646 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8648 /* 855GM needs testing */
8651 /* Returns the core display clock speed */
8652 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8653 dev_priv->display.get_display_clock_speed =
8654 i945_get_display_clock_speed;
8655 else if (IS_I915G(dev))
8656 dev_priv->display.get_display_clock_speed =
8657 i915_get_display_clock_speed;
8658 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8659 dev_priv->display.get_display_clock_speed =
8660 i9xx_misc_get_display_clock_speed;
8661 else if (IS_I915GM(dev))
8662 dev_priv->display.get_display_clock_speed =
8663 i915gm_get_display_clock_speed;
8664 else if (IS_I865G(dev))
8665 dev_priv->display.get_display_clock_speed =
8666 i865_get_display_clock_speed;
8667 else if (IS_I85X(dev))
8668 dev_priv->display.get_display_clock_speed =
8669 i855_get_display_clock_speed;
8671 dev_priv->display.get_display_clock_speed =
8672 i830_get_display_clock_speed;
8674 /* For FIFO watermark updates */
8675 if (HAS_PCH_SPLIT(dev)) {
8676 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8677 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8679 /* IVB configs may use multi-threaded forcewake */
8680 if (IS_IVYBRIDGE(dev)) {
8683 mutex_lock(&dev->struct_mutex);
8684 __gen6_gt_force_wake_mt_get(dev_priv);
8685 ecobus = I915_READ(ECOBUS);
8686 __gen6_gt_force_wake_mt_put(dev_priv);
8687 mutex_unlock(&dev->struct_mutex);
8689 if (ecobus & FORCEWAKE_MT_ENABLE) {
8690 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8691 dev_priv->display.force_wake_get =
8692 __gen6_gt_force_wake_mt_get;
8693 dev_priv->display.force_wake_put =
8694 __gen6_gt_force_wake_mt_put;
8698 if (HAS_PCH_IBX(dev))
8699 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8700 else if (HAS_PCH_CPT(dev))
8701 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8704 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8705 dev_priv->display.update_wm = ironlake_update_wm;
8707 DRM_DEBUG_KMS("Failed to get proper latency. "
8709 dev_priv->display.update_wm = NULL;
8711 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8712 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8713 dev_priv->display.write_eld = ironlake_write_eld;
8714 } else if (IS_GEN6(dev)) {
8715 if (SNB_READ_WM0_LATENCY()) {
8716 dev_priv->display.update_wm = sandybridge_update_wm;
8718 DRM_DEBUG_KMS("Failed to read display plane latency. "
8720 dev_priv->display.update_wm = NULL;
8722 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8723 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8724 dev_priv->display.write_eld = ironlake_write_eld;
8725 } else if (IS_IVYBRIDGE(dev)) {
8726 /* FIXME: detect B0+ stepping and use auto training */
8727 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8728 if (SNB_READ_WM0_LATENCY()) {
8729 dev_priv->display.update_wm = sandybridge_update_wm;
8731 DRM_DEBUG_KMS("Failed to read display plane latency. "
8733 dev_priv->display.update_wm = NULL;
8735 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8736 dev_priv->display.write_eld = ironlake_write_eld;
8738 dev_priv->display.update_wm = NULL;
8739 } else if (IS_PINEVIEW(dev)) {
8740 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8743 dev_priv->mem_freq)) {
8744 DRM_INFO("failed to find known CxSR latency "
8745 "(found ddr%s fsb freq %d, mem freq %d), "
8747 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8748 dev_priv->fsb_freq, dev_priv->mem_freq);
8749 /* Disable CxSR and never update its watermark again */
8750 pineview_disable_cxsr(dev);
8751 dev_priv->display.update_wm = NULL;
8753 dev_priv->display.update_wm = pineview_update_wm;
8754 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8755 } else if (IS_G4X(dev)) {
8756 dev_priv->display.write_eld = g4x_write_eld;
8757 dev_priv->display.update_wm = g4x_update_wm;
8758 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8759 } else if (IS_GEN4(dev)) {
8760 dev_priv->display.update_wm = i965_update_wm;
8761 if (IS_CRESTLINE(dev))
8762 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8763 else if (IS_BROADWATER(dev))
8764 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8765 } else if (IS_GEN3(dev)) {
8766 dev_priv->display.update_wm = i9xx_update_wm;
8767 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8768 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8769 } else if (IS_I865G(dev)) {
8770 dev_priv->display.update_wm = i830_update_wm;
8771 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8772 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8773 } else if (IS_I85X(dev)) {
8774 dev_priv->display.update_wm = i9xx_update_wm;
8775 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8776 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8778 dev_priv->display.update_wm = i830_update_wm;
8779 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8781 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8783 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8786 /* Default just returns -ENODEV to indicate unsupported */
8787 dev_priv->display.queue_flip = intel_default_queue_flip;
8789 switch (INTEL_INFO(dev)->gen) {
8791 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8795 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8800 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8804 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8807 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8813 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8814 * resume, or other times. This quirk makes sure that's the case for
8817 static void quirk_pipea_force(struct drm_device *dev)
8819 struct drm_i915_private *dev_priv = dev->dev_private;
8821 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8822 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8826 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8828 static void quirk_ssc_force_disable(struct drm_device *dev)
8830 struct drm_i915_private *dev_priv = dev->dev_private;
8831 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8835 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8838 static void quirk_invert_brightness(struct drm_device *dev)
8840 struct drm_i915_private *dev_priv = dev->dev_private;
8841 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8844 struct intel_quirk {
8846 int subsystem_vendor;
8847 int subsystem_device;
8848 void (*hook)(struct drm_device *dev);
8851 struct intel_quirk intel_quirks[] = {
8852 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8853 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8854 /* HP Mini needs pipe A force quirk (LP: #322104) */
8855 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8857 /* Thinkpad R31 needs pipe A force quirk */
8858 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8859 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8860 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8862 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8863 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8864 /* ThinkPad X40 needs pipe A force quirk */
8866 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8867 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8869 /* 855 & before need to leave pipe A & dpll A up */
8870 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8871 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8873 /* Lenovo U160 cannot use SSC on LVDS */
8874 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8876 /* Sony Vaio Y cannot use SSC on LVDS */
8877 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8879 /* Acer Aspire 5734Z must invert backlight brightness */
8880 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8883 static void intel_init_quirks(struct drm_device *dev)
8885 struct pci_dev *d = dev->pdev;
8888 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8889 struct intel_quirk *q = &intel_quirks[i];
8891 if (d->device == q->device &&
8892 (d->subsystem_vendor == q->subsystem_vendor ||
8893 q->subsystem_vendor == PCI_ANY_ID) &&
8894 (d->subsystem_device == q->subsystem_device ||
8895 q->subsystem_device == PCI_ANY_ID))
8900 /* Disable the VGA plane that we never use */
8901 static void i915_disable_vga(struct drm_device *dev)
8903 struct drm_i915_private *dev_priv = dev->dev_private;
8907 if (HAS_PCH_SPLIT(dev))
8908 vga_reg = CPU_VGACNTRL;
8912 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8913 outb(1, VGA_SR_INDEX);
8914 sr1 = inb(VGA_SR_DATA);
8915 outb(sr1 | 1<<5, VGA_SR_DATA);
8916 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8919 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8920 POSTING_READ(vga_reg);
8923 void i915_redisable_vga(struct drm_device *dev)
8925 struct drm_i915_private *dev_priv = dev->dev_private;
8928 if (HAS_PCH_SPLIT(dev))
8929 vga_reg = CPU_VGACNTRL;
8933 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
8934 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
8935 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8936 POSTING_READ(vga_reg);
8940 void intel_modeset_init(struct drm_device *dev)
8942 struct drm_i915_private *dev_priv = dev->dev_private;
8945 drm_mode_config_init(dev);
8947 dev->mode_config.min_width = 0;
8948 dev->mode_config.min_height = 0;
8950 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8952 intel_init_quirks(dev);
8954 intel_init_display(dev);
8957 dev->mode_config.max_width = 2048;
8958 dev->mode_config.max_height = 2048;
8959 } else if (IS_GEN3(dev)) {
8960 dev->mode_config.max_width = 4096;
8961 dev->mode_config.max_height = 4096;
8963 dev->mode_config.max_width = 8192;
8964 dev->mode_config.max_height = 8192;
8966 dev->mode_config.fb_base = dev->agp->base;
8968 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8969 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8971 for (i = 0; i < dev_priv->num_pipe; i++) {
8972 intel_crtc_init(dev, i);
8975 /* Just disable it once at startup */
8976 i915_disable_vga(dev);
8977 intel_setup_outputs(dev);
8979 intel_init_clock_gating(dev);
8981 if (IS_IRONLAKE_M(dev)) {
8982 ironlake_enable_drps(dev);
8983 intel_init_emon(dev);
8986 if (IS_GEN6(dev) || IS_GEN7(dev)) {
8987 gen6_enable_rps(dev_priv);
8988 gen6_update_ring_freq(dev_priv);
8991 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8992 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8993 (unsigned long)dev);
8996 void intel_modeset_gem_init(struct drm_device *dev)
8998 if (IS_IRONLAKE_M(dev))
8999 ironlake_enable_rc6(dev);
9001 intel_setup_overlay(dev);
9004 void intel_modeset_cleanup(struct drm_device *dev)
9006 struct drm_i915_private *dev_priv = dev->dev_private;
9007 struct drm_crtc *crtc;
9008 struct intel_crtc *intel_crtc;
9010 drm_kms_helper_poll_fini(dev);
9011 mutex_lock(&dev->struct_mutex);
9013 intel_unregister_dsm_handler();
9016 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9017 /* Skip inactive CRTCs */
9021 intel_crtc = to_intel_crtc(crtc);
9022 intel_increase_pllclock(crtc);
9025 intel_disable_fbc(dev);
9027 if (IS_IRONLAKE_M(dev))
9028 ironlake_disable_drps(dev);
9029 if (IS_GEN6(dev) || IS_GEN7(dev))
9030 gen6_disable_rps(dev);
9032 if (IS_IRONLAKE_M(dev))
9033 ironlake_disable_rc6(dev);
9035 mutex_unlock(&dev->struct_mutex);
9037 /* Disable the irq before mode object teardown, for the irq might
9038 * enqueue unpin/hotplug work. */
9039 drm_irq_uninstall(dev);
9040 cancel_work_sync(&dev_priv->hotplug_work);
9041 cancel_work_sync(&dev_priv->rps_work);
9043 /* flush any delayed tasks or pending work */
9044 flush_scheduled_work();
9046 /* Shut off idle work before the crtcs get freed. */
9047 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9048 intel_crtc = to_intel_crtc(crtc);
9049 del_timer_sync(&intel_crtc->idle_timer);
9051 del_timer_sync(&dev_priv->idle_timer);
9052 cancel_work_sync(&dev_priv->idle_work);
9054 drm_mode_config_cleanup(dev);
9058 * Return which encoder is currently attached for connector.
9060 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9062 return &intel_attached_encoder(connector)->base;
9065 void intel_connector_attach_encoder(struct intel_connector *connector,
9066 struct intel_encoder *encoder)
9068 connector->encoder = encoder;
9069 drm_mode_connector_attach_encoder(&connector->base,
9074 * set vga decode state - true == enable VGA decode
9076 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9078 struct drm_i915_private *dev_priv = dev->dev_private;
9081 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9083 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9085 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9086 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9090 #ifdef CONFIG_DEBUG_FS
9091 #include <linux/seq_file.h>
9093 struct intel_display_error_state {
9094 struct intel_cursor_error_state {
9101 struct intel_pipe_error_state {
9113 struct intel_plane_error_state {
9124 struct intel_display_error_state *
9125 intel_display_capture_error_state(struct drm_device *dev)
9127 drm_i915_private_t *dev_priv = dev->dev_private;
9128 struct intel_display_error_state *error;
9131 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9135 for (i = 0; i < 2; i++) {
9136 error->cursor[i].control = I915_READ(CURCNTR(i));
9137 error->cursor[i].position = I915_READ(CURPOS(i));
9138 error->cursor[i].base = I915_READ(CURBASE(i));
9140 error->plane[i].control = I915_READ(DSPCNTR(i));
9141 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9142 error->plane[i].size = I915_READ(DSPSIZE(i));
9143 error->plane[i].pos = I915_READ(DSPPOS(i));
9144 error->plane[i].addr = I915_READ(DSPADDR(i));
9145 if (INTEL_INFO(dev)->gen >= 4) {
9146 error->plane[i].surface = I915_READ(DSPSURF(i));
9147 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9150 error->pipe[i].conf = I915_READ(PIPECONF(i));
9151 error->pipe[i].source = I915_READ(PIPESRC(i));
9152 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9153 error->pipe[i].hblank = I915_READ(HBLANK(i));
9154 error->pipe[i].hsync = I915_READ(HSYNC(i));
9155 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9156 error->pipe[i].vblank = I915_READ(VBLANK(i));
9157 error->pipe[i].vsync = I915_READ(VSYNC(i));
9164 intel_display_print_error_state(struct seq_file *m,
9165 struct drm_device *dev,
9166 struct intel_display_error_state *error)
9170 for (i = 0; i < 2; i++) {
9171 seq_printf(m, "Pipe [%d]:\n", i);
9172 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9173 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9174 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9175 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9176 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9177 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9178 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9179 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9181 seq_printf(m, "Plane [%d]:\n", i);
9182 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9183 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9184 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9185 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9186 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9187 if (INTEL_INFO(dev)->gen >= 4) {
9188 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9189 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9192 seq_printf(m, "Cursor [%d]:\n", i);
9193 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9194 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9195 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);