drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 350 }
 351
 352 static const intel_limit_t intel_limits_i8xx_dvo = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i8xx_lvds = {
 367         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 368         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 369         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 370         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 371         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 372         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 373         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 374         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 375         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 376                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_sdvo = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 390                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 391         .find_pll = intel_find_best_PLL,
 392 };
 393
 394 static const intel_limit_t intel_limits_i9xx_lvds = {
 395         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 396         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 397         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 398         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 399         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 400         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 401         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 402         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 403         /* The single-channel range is 25-112Mhz, and dual-channel
 404          * is 80-224Mhz.  Prefer single channel as much as possible.
 405          */
 406         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 407                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 408         .find_pll = intel_find_best_PLL,
 409 };
 410
 411     /* below parameter and function is for G4X Chipset Family*/
 412 static const intel_limit_t intel_limits_g4x_sdvo = {
 413         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 414         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 415         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 416         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 417         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 418         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 419         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 420         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 421         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 422                  .p2_slow = G4X_P2_SDVO_SLOW,
 423                  .p2_fast = G4X_P2_SDVO_FAST
 424         },
 425         .find_pll = intel_g4x_find_best_PLL,
 426 };
 427
 428 static const intel_limit_t intel_limits_g4x_hdmi = {
 429         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 430         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 431         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 432         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 433         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 434         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 435         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 436         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 437         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 438                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 439                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 440         },
 441         .find_pll = intel_g4x_find_best_PLL,
 442 };
 443
 444 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 445         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 447         .vco = { .min = G4X_VCO_MIN,
 448                  .max = G4X_VCO_MAX },
 449         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 450                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 451         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 452                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 453         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 454                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 455         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 456                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 457         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 458                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 459         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 460                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 461         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 462                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 463                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 464         },
 465         .find_pll = intel_g4x_find_best_PLL,
 466 };
 467
 468 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 469         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 471         .vco = { .min = G4X_VCO_MIN,
 472                  .max = G4X_VCO_MAX },
 473         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 474                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 475         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 476                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 477         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 478                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 479         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 480                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 481         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 482                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 483         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 484                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 485         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 486                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 487                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 488         },
 489         .find_pll = intel_g4x_find_best_PLL,
 490 };
 491
 492 static const intel_limit_t intel_limits_g4x_display_port = {
 493         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 494                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 495         .vco = { .min = G4X_VCO_MIN,
 496                  .max = G4X_VCO_MAX},
 497         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 498                  .max = G4X_N_DISPLAY_PORT_MAX },
 499         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 500                  .max = G4X_M_DISPLAY_PORT_MAX },
 501         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 502                  .max = G4X_M1_DISPLAY_PORT_MAX },
 503         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 504                  .max = G4X_M2_DISPLAY_PORT_MAX },
 505         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 506                  .max = G4X_P_DISPLAY_PORT_MAX },
 507         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 508                  .max = G4X_P1_DISPLAY_PORT_MAX},
 509         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 510                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 511                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 512         .find_pll = intel_find_pll_g4x_dp,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_sdvo = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 525                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 526         .find_pll = intel_find_best_PLL,
 527 };
 528
 529 static const intel_limit_t intel_limits_pineview_lvds = {
 530         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 531         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 532         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 533         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 534         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 535         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 536         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 537         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 538         /* Pineview only supports single-channel mode. */
 539         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 540                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 541         .find_pll = intel_find_best_PLL,
 542 };
 543
 544 static const intel_limit_t intel_limits_ironlake_dac = {
 545         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 546         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 547         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 548         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 549         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 550         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 551         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 552         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 553         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 554                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 555                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 556         .find_pll = intel_g4x_find_best_PLL,
 557 };
 558
 559 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 560         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 561         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 562         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 563         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 564         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 565         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 566         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 567         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 568         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 569                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 570                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 571         .find_pll = intel_g4x_find_best_PLL,
 572 };
 573
 574 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 575         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 576         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 577         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 578         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 579         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 580         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 581         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 582         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 583         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 584                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 585                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 586         .find_pll = intel_g4x_find_best_PLL,
 587 };
 588
 589 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 590         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 591         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 592         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 593         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 594         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 595         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 596         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 597         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 598         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 599                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 600                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 601         .find_pll = intel_g4x_find_best_PLL,
 602 };
 603
 604 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 605         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 606         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 607         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 608         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 609         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 610         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 611         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 612         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 613         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 614                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 615                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 616         .find_pll = intel_g4x_find_best_PLL,
 617 };
 618
 619 static const intel_limit_t intel_limits_ironlake_display_port = {
 620         .dot = { .min = IRONLAKE_DOT_MIN,
 621                  .max = IRONLAKE_DOT_MAX },
 622         .vco = { .min = IRONLAKE_VCO_MIN,
 623                  .max = IRONLAKE_VCO_MAX},
 624         .n   = { .min = IRONLAKE_DP_N_MIN,
 625                  .max = IRONLAKE_DP_N_MAX },
 626         .m   = { .min = IRONLAKE_DP_M_MIN,
 627                  .max = IRONLAKE_DP_M_MAX },
 628         .m1  = { .min = IRONLAKE_M1_MIN,
 629                  .max = IRONLAKE_M1_MAX },
 630         .m2  = { .min = IRONLAKE_M2_MIN,
 631                  .max = IRONLAKE_M2_MAX },
 632         .p   = { .min = IRONLAKE_DP_P_MIN,
 633                  .max = IRONLAKE_DP_P_MAX },
 634         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 635                  .max = IRONLAKE_DP_P1_MAX},
 636         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 637                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 638                  .p2_fast = IRONLAKE_DP_P2_FAST },
 639         .find_pll = intel_find_pll_ironlake_dp,
 640 };
 641
 642 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         struct drm_i915_private *dev_priv = dev->dev_private;
 646         const intel_limit_t *limit;
 647         int refclk = 120;
 648
 649         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 650                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 651                         refclk = 100;
 652
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_i9xx_lvds;
 714                 else
 715                         limit = &intel_limits_i9xx_sdvo;
 716         } else if (IS_PINEVIEW(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_pineview_lvds;
 719                 else
 720                         limit = &intel_limits_pineview_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 774 {
 775         const intel_limit_t *limit = intel_limit (crtc);
 776         struct drm_device *dev = crtc->dev;
 777
 778         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 779                 INTELPllInvalid ("p1 out of range\n");
 780         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 781                 INTELPllInvalid ("p out of range\n");
 782         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 783                 INTELPllInvalid ("m2 out of range\n");
 784         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 785                 INTELPllInvalid ("m1 out of range\n");
 786         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 787                 INTELPllInvalid ("m1 <= m2\n");
 788         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 789                 INTELPllInvalid ("m out of range\n");
 790         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 791                 INTELPllInvalid ("n out of range\n");
 792         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 793                 INTELPllInvalid ("vco out of range\n");
 794         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 795          * connector, etc., rather than just a single range.
 796          */
 797         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 798                 INTELPllInvalid ("dot out of range\n");
 799
 800         return true;
 801 }
 802
 803 static bool
 804 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 805                     int target, int refclk, intel_clock_t *best_clock)
 806
 807 {
 808         struct drm_device *dev = crtc->dev;
 809         struct drm_i915_private *dev_priv = dev->dev_private;
 810         intel_clock_t clock;
 811         int err = target;
 812
 813         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 814             (I915_READ(LVDS)) != 0) {
 815                 /*
 816                  * For LVDS, if the panel is on, just rely on its current
 817                  * settings for dual-channel.  We haven't figured out how to
 818                  * reliably set up different single/dual channel state, if we
 819                  * even can.
 820                  */
 821                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 822                     LVDS_CLKB_POWER_UP)
 823                         clock.p2 = limit->p2.p2_fast;
 824                 else
 825                         clock.p2 = limit->p2.p2_slow;
 826         } else {
 827                 if (target < limit->p2.dot_limit)
 828                         clock.p2 = limit->p2.p2_slow;
 829                 else
 830                         clock.p2 = limit->p2.p2_fast;
 831         }
 832
 833         memset (best_clock, 0, sizeof (*best_clock));
 834
 835         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 836              clock.m1++) {
 837                 for (clock.m2 = limit->m2.min;
 838                      clock.m2 <= limit->m2.max; clock.m2++) {
 839                         /* m1 is always 0 in Pineview */
 840                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 841                                 break;
 842                         for (clock.n = limit->n.min;
 843                              clock.n <= limit->n.max; clock.n++) {
 844                                 for (clock.p1 = limit->p1.min;
 845                                         clock.p1 <= limit->p1.max; clock.p1++) {
 846                                         int this_err;
 847
 848                                         intel_clock(dev, refclk, &clock);
 849
 850                                         if (!intel_PLL_is_valid(crtc, &clock))
 851                                                 continue;
 852
 853                                         this_err = abs(clock.dot - target);
 854                                         if (this_err < err) {
 855                                                 *best_clock = clock;
 856                                                 err = this_err;
 857                                         }
 858                                 }
 859                         }
 860                 }
 861         }
 862
 863         return (err != target);
 864 }
 865
 866 static bool
 867 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 868                         int target, int refclk, intel_clock_t *best_clock)
 869 {
 870         struct drm_device *dev = crtc->dev;
 871         struct drm_i915_private *dev_priv = dev->dev_private;
 872         intel_clock_t clock;
 873         int max_n;
 874         bool found;
 875         /* approximately equals target * 0.00585 */
 876         int err_most = (target >> 8) + (target >> 9);
 877         found = false;
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 int lvds_reg;
 881
 882                 if (HAS_PCH_SPLIT(dev))
 883                         lvds_reg = PCH_LVDS;
 884                 else
 885                         lvds_reg = LVDS;
 886                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 887                     LVDS_CLKB_POWER_UP)
 888                         clock.p2 = limit->p2.p2_fast;
 889                 else
 890                         clock.p2 = limit->p2.p2_slow;
 891         } else {
 892                 if (target < limit->p2.dot_limit)
 893                         clock.p2 = limit->p2.p2_slow;
 894                 else
 895                         clock.p2 = limit->p2.p2_fast;
 896         }
 897
 898         memset(best_clock, 0, sizeof(*best_clock));
 899         max_n = limit->n.max;
 900         /* based on hardware requirement, prefer smaller n to precision */
 901         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 902                 /* based on hardware requirement, prefere larger m1,m2 */
 903                 for (clock.m1 = limit->m1.max;
 904                      clock.m1 >= limit->m1.min; clock.m1--) {
 905                         for (clock.m2 = limit->m2.max;
 906                              clock.m2 >= limit->m2.min; clock.m2--) {
 907                                 for (clock.p1 = limit->p1.max;
 908                                      clock.p1 >= limit->p1.min; clock.p1--) {
 909                                         int this_err;
 910
 911                                         intel_clock(dev, refclk, &clock);
 912                                         if (!intel_PLL_is_valid(crtc, &clock))
 913                                                 continue;
 914                                         this_err = abs(clock.dot - target) ;
 915                                         if (this_err < err_most) {
 916                                                 *best_clock = clock;
 917                                                 err_most = this_err;
 918                                                 max_n = clock.n;
 919                                                 found = true;
 920                                         }
 921                                 }
 922                         }
 923                 }
 924         }
 925         return found;
 926 }
 927
 928 static bool
 929 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 930                            int target, int refclk, intel_clock_t *best_clock)
 931 {
 932         struct drm_device *dev = crtc->dev;
 933         intel_clock_t clock;
 934
 935         /* return directly when it is eDP */
 936         if (HAS_eDP)
 937                 return true;
 938
 939         if (target < 200000) {
 940                 clock.n = 1;
 941                 clock.p1 = 2;
 942                 clock.p2 = 10;
 943                 clock.m1 = 12;
 944                 clock.m2 = 9;
 945         } else {
 946                 clock.n = 2;
 947                 clock.p1 = 1;
 948                 clock.p2 = 10;
 949                 clock.m1 = 14;
 950                 clock.m2 = 8;
 951         }
 952         intel_clock(dev, refclk, &clock);
 953         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 954         return true;
 955 }
 956
 957 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 958 static bool
 959 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 960                       int target, int refclk, intel_clock_t *best_clock)
 961 {
 962         intel_clock_t clock;
 963         if (target < 200000) {
 964                 clock.p1 = 2;
 965                 clock.p2 = 10;
 966                 clock.n = 2;
 967                 clock.m1 = 23;
 968                 clock.m2 = 8;
 969         } else {
 970                 clock.p1 = 1;
 971                 clock.p2 = 10;
 972                 clock.n = 1;
 973                 clock.m1 = 14;
 974                 clock.m2 = 2;
 975         }
 976         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 977         clock.p = (clock.p1 * clock.p2);
 978         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 979         clock.vco = 0;
 980         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 981         return true;
 982 }
 983
 984 /**
 985  * intel_wait_for_vblank - wait for vblank on a given pipe
 986  * @dev: drm device
 987  * @pipe: pipe to wait for
 988  *
 989  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 990  * mode setting code.
 991  */
 992 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 993 {
 994         struct drm_i915_private *dev_priv = dev->dev_private;
 995         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 996
 997         /* Clear existing vblank status. Note this will clear any other
 998          * sticky status fields as well.
 999          *
1000          * This races with i915_driver_irq_handler() with the result
1001          * that either function could miss a vblank event.  Here it is not
1002          * fatal, as we will either wait upon the next vblank interrupt or
1003          * timeout.  Generally speaking intel_wait_for_vblank() is only
1004          * called during modeset at which time the GPU should be idle and
1005          * should *not* be performing page flips and thus not waiting on
1006          * vblanks...
1007          * Currently, the result of us stealing a vblank from the irq
1008          * handler is that a single frame will be skipped during swapbuffers.
1009          */
1010         I915_WRITE(pipestat_reg,
1011                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1012
1013         /* Wait for vblank interrupt bit to set */
1014         if (wait_for(I915_READ(pipestat_reg) &
1015                      PIPE_VBLANK_INTERRUPT_STATUS,
1016                      50))
1017                 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 }
1019
1020 /**
1021  * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1022  * @dev: drm device
1023  * @pipe: pipe to wait for
1024  *
1025  * After disabling a pipe, we can't wait for vblank in the usual way,
1026  * spinning on the vblank interrupt status bit, since we won't actually
1027  * see an interrupt when the pipe is disabled.
1028  *
1029  * So this function waits for the display line value to settle (it
1030  * usually ends up stopping at the start of the next frame).
1031  */
1032 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1033 {
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1036         unsigned long timeout = jiffies + msecs_to_jiffies(100);
1037         u32 last_line, line;
1038
1039         /* Wait for the display line to settle */
1040         line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1041         do {
1042                 last_line = line;
1043                 MSLEEP(5);
1044                 line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1045         } while (line != last_line && time_after(timeout, jiffies));
1046
1047         if (line != last_line)
1048                 DRM_DEBUG_KMS("vblank wait timed out\n");
1049 }
1050
1051 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1052 {
1053         struct drm_device *dev = crtc->dev;
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055         struct drm_framebuffer *fb = crtc->fb;
1056         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1057         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1059         int plane, i;
1060         u32 fbc_ctl, fbc_ctl2;
1061
1062         if (fb->pitch == dev_priv->cfb_pitch &&
1063             obj_priv->fence_reg == dev_priv->cfb_fence &&
1064             intel_crtc->plane == dev_priv->cfb_plane &&
1065             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1066                 return;
1067
1068         i8xx_disable_fbc(dev);
1069
1070         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1071
1072         if (fb->pitch < dev_priv->cfb_pitch)
1073                 dev_priv->cfb_pitch = fb->pitch;
1074
1075         /* FBC_CTL wants 64B units */
1076         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1077         dev_priv->cfb_fence = obj_priv->fence_reg;
1078         dev_priv->cfb_plane = intel_crtc->plane;
1079         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1080
1081         /* Clear old tags */
1082         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1083                 I915_WRITE(FBC_TAG + (i * 4), 0);
1084
1085         /* Set it up... */
1086         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1087         if (obj_priv->tiling_mode != I915_TILING_NONE)
1088                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1089         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1090         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1091
1092         /* enable it... */
1093         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1094         if (IS_I945GM(dev))
1095                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1096         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1097         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1098         if (obj_priv->tiling_mode != I915_TILING_NONE)
1099                 fbc_ctl |= dev_priv->cfb_fence;
1100         I915_WRITE(FBC_CONTROL, fbc_ctl);
1101
1102         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1103                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1104 }
1105
1106 void i8xx_disable_fbc(struct drm_device *dev)
1107 {
1108         struct drm_i915_private *dev_priv = dev->dev_private;
1109         u32 fbc_ctl;
1110
1111         /* Disable compression */
1112         fbc_ctl = I915_READ(FBC_CONTROL);
1113         fbc_ctl &= ~FBC_CTL_EN;
1114         I915_WRITE(FBC_CONTROL, fbc_ctl);
1115
1116         /* Wait for compressing bit to clear */
1117         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1118                 DRM_DEBUG_KMS("FBC idle timed out\n");
1119                 return;
1120         }
1121
1122         DRM_DEBUG_KMS("disabled FBC\n");
1123 }
1124
1125 static bool i8xx_fbc_enabled(struct drm_device *dev)
1126 {
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1130 }
1131
1132 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1133 {
1134         struct drm_device *dev = crtc->dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136         struct drm_framebuffer *fb = crtc->fb;
1137         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1138         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1140         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1141         unsigned long stall_watermark = 200;
1142         u32 dpfc_ctl;
1143
1144         dpfc_ctl = I915_READ(DPFC_CONTROL);
1145         if (dpfc_ctl & DPFC_CTL_EN) {
1146                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1147                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1148                     dev_priv->cfb_plane == intel_crtc->plane &&
1149                     dev_priv->cfb_y == crtc->y)
1150                         return;
1151
1152                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1153                 POSTING_READ(DPFC_CONTROL);
1154                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1155         }
1156
1157         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1158         dev_priv->cfb_fence = obj_priv->fence_reg;
1159         dev_priv->cfb_plane = intel_crtc->plane;
1160         dev_priv->cfb_y = crtc->y;
1161
1162         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1163         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1164                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1165                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1166         } else {
1167                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1168         }
1169
1170         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1171                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1172                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1173         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1174
1175         /* enable it... */
1176         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1177
1178         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1179 }
1180
1181 void g4x_disable_fbc(struct drm_device *dev)
1182 {
1183         struct drm_i915_private *dev_priv = dev->dev_private;
1184         u32 dpfc_ctl;
1185
1186         /* Disable compression */
1187         dpfc_ctl = I915_READ(DPFC_CONTROL);
1188         if (dpfc_ctl & DPFC_CTL_EN) {
1189                 dpfc_ctl &= ~DPFC_CTL_EN;
1190                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1191
1192                 DRM_DEBUG_KMS("disabled FBC\n");
1193         }
1194 }
1195
1196 static bool g4x_fbc_enabled(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199
1200         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1201 }
1202
1203 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1204 {
1205         struct drm_device *dev = crtc->dev;
1206         struct drm_i915_private *dev_priv = dev->dev_private;
1207         struct drm_framebuffer *fb = crtc->fb;
1208         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1209         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1211         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1212         unsigned long stall_watermark = 200;
1213         u32 dpfc_ctl;
1214
1215         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1216         if (dpfc_ctl & DPFC_CTL_EN) {
1217                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1218                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1219                     dev_priv->cfb_plane == intel_crtc->plane &&
1220                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1221                     dev_priv->cfb_y == crtc->y)
1222                         return;
1223
1224                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1225                 POSTING_READ(ILK_DPFC_CONTROL);
1226                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1227         }
1228
1229         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1230         dev_priv->cfb_fence = obj_priv->fence_reg;
1231         dev_priv->cfb_plane = intel_crtc->plane;
1232         dev_priv->cfb_offset = obj_priv->gtt_offset;
1233         dev_priv->cfb_y = crtc->y;
1234
1235         dpfc_ctl &= DPFC_RESERVED;
1236         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1237         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1238                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1239                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1240         } else {
1241                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1242         }
1243
1244         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1245                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1246                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1247         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1248         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1249         /* enable it... */
1250         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1251
1252         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1253 }
1254
1255 void ironlake_disable_fbc(struct drm_device *dev)
1256 {
1257         struct drm_i915_private *dev_priv = dev->dev_private;
1258         u32 dpfc_ctl;
1259
1260         /* Disable compression */
1261         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1262         if (dpfc_ctl & DPFC_CTL_EN) {
1263                 dpfc_ctl &= ~DPFC_CTL_EN;
1264                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1265
1266                 DRM_DEBUG_KMS("disabled FBC\n");
1267         }
1268 }
1269
1270 static bool ironlake_fbc_enabled(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273
1274         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1275 }
1276
1277 bool intel_fbc_enabled(struct drm_device *dev)
1278 {
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280
1281         if (!dev_priv->display.fbc_enabled)
1282                 return false;
1283
1284         return dev_priv->display.fbc_enabled(dev);
1285 }
1286
1287 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1288 {
1289         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1290
1291         if (!dev_priv->display.enable_fbc)
1292                 return;
1293
1294         dev_priv->display.enable_fbc(crtc, interval);
1295 }
1296
1297 void intel_disable_fbc(struct drm_device *dev)
1298 {
1299         struct drm_i915_private *dev_priv = dev->dev_private;
1300
1301         if (!dev_priv->display.disable_fbc)
1302                 return;
1303
1304         dev_priv->display.disable_fbc(dev);
1305 }
1306
1307 /**
1308  * intel_update_fbc - enable/disable FBC as needed
1309  * @dev: the drm_device
1310  *
1311  * Set up the framebuffer compression hardware at mode set time.  We
1312  * enable it if possible:
1313  *   - plane A only (on pre-965)
1314  *   - no pixel mulitply/line duplication
1315  *   - no alpha buffer discard
1316  *   - no dual wide
1317  *   - framebuffer <= 2048 in width, 1536 in height
1318  *
1319  * We can't assume that any compression will take place (worst case),
1320  * so the compressed buffer has to be the same size as the uncompressed
1321  * one.  It also must reside (along with the line length buffer) in
1322  * stolen memory.
1323  *
1324  * We need to enable/disable FBC on a global basis.
1325  */
1326 static void intel_update_fbc(struct drm_device *dev)
1327 {
1328         struct drm_i915_private *dev_priv = dev->dev_private;
1329         struct drm_crtc *crtc = NULL, *tmp_crtc;
1330         struct intel_crtc *intel_crtc;
1331         struct drm_framebuffer *fb;
1332         struct intel_framebuffer *intel_fb;
1333         struct drm_i915_gem_object *obj_priv;
1334
1335         DRM_DEBUG_KMS("\n");
1336
1337         if (!i915_powersave)
1338                 return;
1339
1340         if (!I915_HAS_FBC(dev))
1341                 return;
1342
1343         /*
1344          * If FBC is already on, we just have to verify that we can
1345          * keep it that way...
1346          * Need to disable if:
1347          *   - more than one pipe is active
1348          *   - changing FBC params (stride, fence, mode)
1349          *   - new fb is too large to fit in compressed buffer
1350          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1351          */
1352         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1353                 if (tmp_crtc->enabled) {
1354                         if (crtc) {
1355                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1356                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1357                                 goto out_disable;
1358                         }
1359                         crtc = tmp_crtc;
1360                 }
1361         }
1362
1363         if (!crtc || crtc->fb == NULL) {
1364                 DRM_DEBUG_KMS("no output, disabling\n");
1365                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1366                 goto out_disable;
1367         }
1368
1369         intel_crtc = to_intel_crtc(crtc);
1370         fb = crtc->fb;
1371         intel_fb = to_intel_framebuffer(fb);
1372         obj_priv = to_intel_bo(intel_fb->obj);
1373
1374         if (intel_fb->obj->size > dev_priv->cfb_size) {
1375                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1376                               "compression\n");
1377                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1378                 goto out_disable;
1379         }
1380         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1381             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1382                 DRM_DEBUG_KMS("mode incompatible with compression, "
1383                               "disabling\n");
1384                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1385                 goto out_disable;
1386         }
1387         if ((crtc->mode.hdisplay > 2048) ||
1388             (crtc->mode.vdisplay > 1536)) {
1389                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1390                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1391                 goto out_disable;
1392         }
1393         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1394                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1395                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1396                 goto out_disable;
1397         }
1398         if (obj_priv->tiling_mode != I915_TILING_X) {
1399                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1400                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1401                 goto out_disable;
1402         }
1403
1404         /* If the kernel debugger is active, always disable compression */
1405         if (in_dbg_master())
1406                 goto out_disable;
1407
1408         intel_enable_fbc(crtc, 500);
1409         return;
1410
1411 out_disable:
1412         /* Multiple disables should be harmless */
1413         if (intel_fbc_enabled(dev)) {
1414                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1415                 intel_disable_fbc(dev);
1416         }
1417 }
1418
1419 int
1420 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1421                            struct drm_gem_object *obj,
1422                            bool pipelined)
1423 {
1424         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1425         u32 alignment;
1426         int ret;
1427
1428         switch (obj_priv->tiling_mode) {
1429         case I915_TILING_NONE:
1430                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1431                         alignment = 128 * 1024;
1432                 else if (IS_I965G(dev))
1433                         alignment = 4 * 1024;
1434                 else
1435                         alignment = 64 * 1024;
1436                 break;
1437         case I915_TILING_X:
1438                 /* pin() will align the object as required by fence */
1439                 alignment = 0;
1440                 break;
1441         case I915_TILING_Y:
1442                 /* FIXME: Is this true? */
1443                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1444                 return -EINVAL;
1445         default:
1446                 BUG();
1447         }
1448
1449         ret = i915_gem_object_pin(obj, alignment);
1450         if (ret)
1451                 return ret;
1452
1453         ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1454         if (ret)
1455                 goto err_unpin;
1456
1457         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1458          * fence, whereas 965+ only requires a fence if using
1459          * framebuffer compression.  For simplicity, we always install
1460          * a fence as the cost is not that onerous.
1461          */
1462         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1463             obj_priv->tiling_mode != I915_TILING_NONE) {
1464                 ret = i915_gem_object_get_fence_reg(obj, false);
1465                 if (ret)
1466                         goto err_unpin;
1467         }
1468
1469         return 0;
1470
1471 err_unpin:
1472         i915_gem_object_unpin(obj);
1473         return ret;
1474 }
1475
1476 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1477 static int
1478 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1479                            int x, int y)
1480 {
1481         struct drm_device *dev = crtc->dev;
1482         struct drm_i915_private *dev_priv = dev->dev_private;
1483         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1484         struct intel_framebuffer *intel_fb;
1485         struct drm_i915_gem_object *obj_priv;
1486         struct drm_gem_object *obj;
1487         int plane = intel_crtc->plane;
1488         unsigned long Start, Offset;
1489         u32 dspcntr;
1490         u32 reg;
1491
1492         switch (plane) {
1493         case 0:
1494         case 1:
1495                 break;
1496         default:
1497                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1498                 return -EINVAL;
1499         }
1500
1501         intel_fb = to_intel_framebuffer(fb);
1502         obj = intel_fb->obj;
1503         obj_priv = to_intel_bo(obj);
1504
1505         reg = DSPCNTR(plane);
1506         dspcntr = I915_READ(reg);
1507         /* Mask out pixel format bits in case we change it */
1508         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1509         switch (fb->bits_per_pixel) {
1510         case 8:
1511                 dspcntr |= DISPPLANE_8BPP;
1512                 break;
1513         case 16:
1514                 if (fb->depth == 15)
1515                         dspcntr |= DISPPLANE_15_16BPP;
1516                 else
1517                         dspcntr |= DISPPLANE_16BPP;
1518                 break;
1519         case 24:
1520         case 32:
1521                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1522                 break;
1523         default:
1524                 DRM_ERROR("Unknown color depth\n");
1525                 return -EINVAL;
1526         }
1527         if (IS_I965G(dev)) {
1528                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1529                         dspcntr |= DISPPLANE_TILED;
1530                 else
1531                         dspcntr &= ~DISPPLANE_TILED;
1532         }
1533
1534         if (HAS_PCH_SPLIT(dev))
1535                 /* must disable */
1536                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1537
1538         I915_WRITE(reg, dspcntr);
1539
1540         Start = obj_priv->gtt_offset;
1541         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1542
1543         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1544                       Start, Offset, x, y, fb->pitch);
1545         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1546         if (IS_I965G(dev)) {
1547                 I915_WRITE(DSPSURF(plane), Start);
1548                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1549                 I915_WRITE(DSPADDR(plane), Offset);
1550         } else
1551                 I915_WRITE(DSPADDR(plane), Start + Offset);
1552         POSTING_READ(reg);
1553
1554         intel_update_fbc(dev);
1555         intel_increase_pllclock(crtc);
1556
1557         return 0;
1558 }
1559
1560 static int
1561 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1562                     struct drm_framebuffer *old_fb)
1563 {
1564         struct drm_device *dev = crtc->dev;
1565         struct drm_i915_master_private *master_priv;
1566         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1567         struct intel_framebuffer *intel_fb;
1568         struct drm_i915_gem_object *obj_priv;
1569         struct drm_gem_object *obj;
1570         int pipe = intel_crtc->pipe;
1571         int plane = intel_crtc->plane;
1572         int ret;
1573
1574         /* no fb bound */
1575         if (!crtc->fb) {
1576                 DRM_DEBUG_KMS("No FB bound\n");
1577                 return 0;
1578         }
1579
1580         switch (plane) {
1581         case 0:
1582         case 1:
1583                 break;
1584         default:
1585                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1586                 return -EINVAL;
1587         }
1588
1589         intel_fb = to_intel_framebuffer(crtc->fb);
1590         obj = intel_fb->obj;
1591         obj_priv = to_intel_bo(obj);
1592
1593         mutex_lock(&dev->struct_mutex);
1594         ret = intel_pin_and_fence_fb_obj(dev, obj, false);
1595         if (ret != 0) {
1596                 mutex_unlock(&dev->struct_mutex);
1597                 return ret;
1598         }
1599
1600         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1601         if (ret) {
1602                 i915_gem_object_unpin(obj);
1603                 mutex_unlock(&dev->struct_mutex);
1604                 return ret;
1605         }
1606
1607         if (old_fb) {
1608                 intel_fb = to_intel_framebuffer(old_fb);
1609                 obj_priv = to_intel_bo(intel_fb->obj);
1610                 i915_gem_object_unpin(intel_fb->obj);
1611         }
1612
1613         mutex_unlock(&dev->struct_mutex);
1614
1615         if (!dev->primary->master)
1616                 return 0;
1617
1618         master_priv = dev->primary->master->driver_priv;
1619         if (!master_priv->sarea_priv)
1620                 return 0;
1621
1622         if (pipe) {
1623                 master_priv->sarea_priv->pipeB_x = x;
1624                 master_priv->sarea_priv->pipeB_y = y;
1625         } else {
1626                 master_priv->sarea_priv->pipeA_x = x;
1627                 master_priv->sarea_priv->pipeA_y = y;
1628         }
1629
1630         return 0;
1631 }
1632
1633 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1634 {
1635         struct drm_device *dev = crtc->dev;
1636         struct drm_i915_private *dev_priv = dev->dev_private;
1637         u32 dpa_ctl;
1638
1639         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1640         dpa_ctl = I915_READ(DP_A);
1641         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1642
1643         if (clock < 200000) {
1644                 u32 temp;
1645                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1646                 /* workaround for 160Mhz:
1647                    1) program 0x4600c bits 15:0 = 0x8124
1648                    2) program 0x46010 bit 0 = 1
1649                    3) program 0x46034 bit 24 = 1
1650                    4) program 0x64000 bit 14 = 1
1651                    */
1652                 temp = I915_READ(0x4600c);
1653                 temp &= 0xffff0000;
1654                 I915_WRITE(0x4600c, temp | 0x8124);
1655
1656                 temp = I915_READ(0x46010);
1657                 I915_WRITE(0x46010, temp | 1);
1658
1659                 temp = I915_READ(0x46034);
1660                 I915_WRITE(0x46034, temp | (1 << 24));
1661         } else {
1662                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1663         }
1664         I915_WRITE(DP_A, dpa_ctl);
1665
1666         POSTING_READ(DP_A);
1667         udelay(500);
1668 }
1669
1670 /* The FDI link training functions for ILK/Ibexpeak. */
1671 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1672 {
1673         struct drm_device *dev = crtc->dev;
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1676         int pipe = intel_crtc->pipe;
1677         u32 reg, temp, tries;
1678
1679         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1680            for train result */
1681         reg = FDI_RX_IMR(pipe);
1682         temp = I915_READ(reg);
1683         temp &= ~FDI_RX_SYMBOL_LOCK;
1684         temp &= ~FDI_RX_BIT_LOCK;
1685         I915_WRITE(reg, temp);
1686         I915_READ(reg);
1687         udelay(150);
1688
1689         /* enable CPU FDI TX and PCH FDI RX */
1690         reg = FDI_TX_CTL(pipe);
1691         temp = I915_READ(reg);
1692         temp &= ~(7 << 19);
1693         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1694         temp &= ~FDI_LINK_TRAIN_NONE;
1695         temp |= FDI_LINK_TRAIN_PATTERN_1;
1696         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1697
1698         reg = FDI_RX_CTL(pipe);
1699         temp = I915_READ(reg);
1700         temp &= ~FDI_LINK_TRAIN_NONE;
1701         temp |= FDI_LINK_TRAIN_PATTERN_1;
1702         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1703
1704         POSTING_READ(reg);
1705         udelay(150);
1706
1707         reg = FDI_RX_IIR(pipe);
1708         for (tries = 0; tries < 5; tries++) {
1709                 temp = I915_READ(reg);
1710                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1711
1712                 if ((temp & FDI_RX_BIT_LOCK)) {
1713                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1714                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1715                         break;
1716                 }
1717         }
1718         if (tries == 5)
1719                 DRM_ERROR("FDI train 1 fail!\n");
1720
1721         /* Train 2 */
1722         reg = FDI_TX_CTL(pipe);
1723         temp = I915_READ(reg);
1724         temp &= ~FDI_LINK_TRAIN_NONE;
1725         temp |= FDI_LINK_TRAIN_PATTERN_2;
1726         I915_WRITE(reg, temp);
1727
1728         reg = FDI_RX_CTL(pipe);
1729         temp = I915_READ(reg);
1730         temp &= ~FDI_LINK_TRAIN_NONE;
1731         temp |= FDI_LINK_TRAIN_PATTERN_2;
1732         I915_WRITE(reg, temp);
1733
1734         POSTING_READ(reg);
1735         udelay(150);
1736
1737         reg = FDI_RX_IIR(pipe);
1738         for (tries = 0; tries < 5; tries++) {
1739                 temp = I915_READ(reg);
1740                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1741
1742                 if (temp & FDI_RX_SYMBOL_LOCK) {
1743                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1744                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1745                         break;
1746                 }
1747         }
1748         if (tries == 5)
1749                 DRM_ERROR("FDI train 2 fail!\n");
1750
1751         DRM_DEBUG_KMS("FDI train done\n");
1752 }
1753
1754 static const int const snb_b_fdi_train_param [] = {
1755         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1756         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1757         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1758         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1759 };
1760
1761 /* The FDI link training functions for SNB/Cougarpoint. */
1762 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1763 {
1764         struct drm_device *dev = crtc->dev;
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1767         int pipe = intel_crtc->pipe;
1768         u32 reg, temp, i;
1769
1770         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1771            for train result */
1772         reg = FDI_RX_IMR(pipe);
1773         temp = I915_READ(reg);
1774         temp &= ~FDI_RX_SYMBOL_LOCK;
1775         temp &= ~FDI_RX_BIT_LOCK;
1776         I915_WRITE(reg, temp);
1777
1778         POSTING_READ(reg);
1779         udelay(150);
1780
1781         /* enable CPU FDI TX and PCH FDI RX */
1782         reg = FDI_TX_CTL(pipe);
1783         temp = I915_READ(reg);
1784         temp &= ~(7 << 19);
1785         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1786         temp &= ~FDI_LINK_TRAIN_NONE;
1787         temp |= FDI_LINK_TRAIN_PATTERN_1;
1788         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1789         /* SNB-B */
1790         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1791         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1792
1793         reg = FDI_RX_CTL(pipe);
1794         temp = I915_READ(reg);
1795         if (HAS_PCH_CPT(dev)) {
1796                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1797                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1798         } else {
1799                 temp &= ~FDI_LINK_TRAIN_NONE;
1800                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1801         }
1802         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1803
1804         POSTING_READ(reg);
1805         udelay(150);
1806
1807         for (i = 0; i < 4; i++ ) {
1808                 reg = FDI_TX_CTL(pipe);
1809                 temp = I915_READ(reg);
1810                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1811                 temp |= snb_b_fdi_train_param[i];
1812                 I915_WRITE(reg, temp);
1813
1814                 POSTING_READ(reg);
1815                 udelay(500);
1816
1817                 reg = FDI_RX_IIR(pipe);
1818                 temp = I915_READ(reg);
1819                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1820
1821                 if (temp & FDI_RX_BIT_LOCK) {
1822                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1823                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1824                         break;
1825                 }
1826         }
1827         if (i == 4)
1828                 DRM_ERROR("FDI train 1 fail!\n");
1829
1830         /* Train 2 */
1831         reg = FDI_TX_CTL(pipe);
1832         temp = I915_READ(reg);
1833         temp &= ~FDI_LINK_TRAIN_NONE;
1834         temp |= FDI_LINK_TRAIN_PATTERN_2;
1835         if (IS_GEN6(dev)) {
1836                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1837                 /* SNB-B */
1838                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1839         }
1840         I915_WRITE(reg, temp);
1841
1842         reg = FDI_RX_CTL(pipe);
1843         temp = I915_READ(reg);
1844         if (HAS_PCH_CPT(dev)) {
1845                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1846                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1847         } else {
1848                 temp &= ~FDI_LINK_TRAIN_NONE;
1849                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1850         }
1851         I915_WRITE(reg, temp);
1852
1853         POSTING_READ(reg);
1854         udelay(150);
1855
1856         for (i = 0; i < 4; i++ ) {
1857                 reg = FDI_TX_CTL(pipe);
1858                 temp = I915_READ(reg);
1859                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1860                 temp |= snb_b_fdi_train_param[i];
1861                 I915_WRITE(reg, temp);
1862
1863                 POSTING_READ(reg);
1864                 udelay(500);
1865
1866                 reg = FDI_RX_IIR(pipe);
1867                 temp = I915_READ(reg);
1868                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1869
1870                 if (temp & FDI_RX_SYMBOL_LOCK) {
1871                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1872                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1873                         break;
1874                 }
1875         }
1876         if (i == 4)
1877                 DRM_ERROR("FDI train 2 fail!\n");
1878
1879         DRM_DEBUG_KMS("FDI train done.\n");
1880 }
1881
1882 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1883 {
1884         struct drm_device *dev = crtc->dev;
1885         struct drm_i915_private *dev_priv = dev->dev_private;
1886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1887         int pipe = intel_crtc->pipe;
1888         u32 reg, temp;
1889
1890         /* Write the TU size bits so error detection works */
1891         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1892                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1893
1894         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1895         reg = FDI_RX_CTL(pipe);
1896         temp = I915_READ(reg);
1897         temp &= ~((0x7 << 19) | (0x7 << 16));
1898         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1899         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1900         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1901
1902         POSTING_READ(reg);
1903         udelay(200);
1904
1905         /* Switch from Rawclk to PCDclk */
1906         temp = I915_READ(reg);
1907         I915_WRITE(reg, temp | FDI_PCDCLK);
1908
1909         POSTING_READ(reg);
1910         udelay(200);
1911
1912         /* Enable CPU FDI TX PLL, always on for Ironlake */
1913         reg = FDI_TX_CTL(pipe);
1914         temp = I915_READ(reg);
1915         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1916                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1917
1918                 POSTING_READ(reg);
1919                 udelay(100);
1920         }
1921 }
1922
1923 static void intel_flush_display_plane(struct drm_device *dev,
1924                                       int plane)
1925 {
1926         struct drm_i915_private *dev_priv = dev->dev_private;
1927         u32 reg = DSPADDR(plane);
1928         I915_WRITE(reg, I915_READ(reg));
1929 }
1930
1931 /*
1932  * When we disable a pipe, we need to clear any pending scanline wait events
1933  * to avoid hanging the ring, which we assume we are waiting on.
1934  */
1935 static void intel_clear_scanline_wait(struct drm_device *dev)
1936 {
1937         struct drm_i915_private *dev_priv = dev->dev_private;
1938         u32 tmp;
1939
1940         if (IS_GEN2(dev))
1941                 /* Can't break the hang on i8xx */
1942                 return;
1943
1944         tmp = I915_READ(PRB0_CTL);
1945         if (tmp & RING_WAIT) {
1946                 I915_WRITE(PRB0_CTL, tmp);
1947                 POSTING_READ(PRB0_CTL);
1948         }
1949 }
1950
1951 static void ironlake_crtc_enable(struct drm_crtc *crtc)
1952 {
1953         struct drm_device *dev = crtc->dev;
1954         struct drm_i915_private *dev_priv = dev->dev_private;
1955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956         int pipe = intel_crtc->pipe;
1957         int plane = intel_crtc->plane;
1958         u32 reg, temp;
1959
1960         if (intel_crtc->active)
1961                 return;
1962
1963         intel_crtc->active = true;
1964         intel_update_watermarks(dev);
1965
1966         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1967                 temp = I915_READ(PCH_LVDS);
1968                 if ((temp & LVDS_PORT_EN) == 0)
1969                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1970         }
1971
1972         ironlake_fdi_enable(crtc);
1973
1974         /* Enable panel fitting for LVDS */
1975         if (dev_priv->pch_pf_size &&
1976             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1977              || HAS_eDP || intel_pch_has_edp(crtc))) {
1978                 /* Force use of hard-coded filter coefficients
1979                  * as some pre-programmed values are broken,
1980                  * e.g. x201.
1981                  */
1982                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1983                            PF_ENABLE | PF_FILTER_MED_3x3);
1984                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1985                            dev_priv->pch_pf_pos);
1986                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1987                            dev_priv->pch_pf_size);
1988         }
1989
1990         /* Enable CPU pipe */
1991         reg = PIPECONF(pipe);
1992         temp = I915_READ(reg);
1993         if ((temp & PIPECONF_ENABLE) == 0) {
1994                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
1995                 POSTING_READ(reg);
1996                 udelay(100);
1997         }
1998
1999         /* configure and enable CPU plane */
2000         reg = DSPCNTR(plane);
2001         temp = I915_READ(reg);
2002         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2003                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2004                 intel_flush_display_plane(dev, plane);
2005         }
2006
2007         /* For PCH output, training FDI link */
2008         if (IS_GEN6(dev))
2009                 gen6_fdi_link_train(crtc);
2010         else
2011                 ironlake_fdi_link_train(crtc);
2012
2013         /* enable PCH DPLL */
2014         reg = PCH_DPLL(pipe);
2015         temp = I915_READ(reg);
2016         if ((temp & DPLL_VCO_ENABLE) == 0) {
2017                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2018                 POSTING_READ(reg);
2019                 udelay(200);
2020         }
2021
2022         if (HAS_PCH_CPT(dev)) {
2023                 /* Be sure PCH DPLL SEL is set */
2024                 temp = I915_READ(PCH_DPLL_SEL);
2025                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2026                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2027                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2028                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2029                 I915_WRITE(PCH_DPLL_SEL, temp);
2030         }
2031
2032         /* set transcoder timing */
2033         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2034         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2035         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2036
2037         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2038         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2039         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2040
2041         /* enable normal train */
2042         reg = FDI_TX_CTL(pipe);
2043         temp = I915_READ(reg);
2044         temp &= ~FDI_LINK_TRAIN_NONE;
2045         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2046         I915_WRITE(reg, temp);
2047
2048         reg = FDI_RX_CTL(pipe);
2049         temp = I915_READ(reg);
2050         if (HAS_PCH_CPT(dev)) {
2051                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2052                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2053         } else {
2054                 temp &= ~FDI_LINK_TRAIN_NONE;
2055                 temp |= FDI_LINK_TRAIN_NONE;
2056         }
2057         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2058
2059         /* wait one idle pattern time */
2060         POSTING_READ(reg);
2061         udelay(100);
2062
2063         /* For PCH DP, enable TRANS_DP_CTL */
2064         if (HAS_PCH_CPT(dev) &&
2065             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2066                 reg = TRANS_DP_CTL(pipe);
2067                 temp = I915_READ(reg);
2068                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2069                           TRANS_DP_SYNC_MASK);
2070                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2071                          TRANS_DP_ENH_FRAMING);
2072
2073                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2074                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2075                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2076                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2077
2078                 switch (intel_trans_dp_port_sel(crtc)) {
2079                 case PCH_DP_B:
2080                         temp |= TRANS_DP_PORT_SEL_B;
2081                         break;
2082                 case PCH_DP_C:
2083                         temp |= TRANS_DP_PORT_SEL_C;
2084                         break;
2085                 case PCH_DP_D:
2086                         temp |= TRANS_DP_PORT_SEL_D;
2087                         break;
2088                 default:
2089                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2090                         temp |= TRANS_DP_PORT_SEL_B;
2091                         break;
2092                 }
2093
2094                 I915_WRITE(reg, temp);
2095         }
2096
2097         /* enable PCH transcoder */
2098         reg = TRANSCONF(pipe);
2099         temp = I915_READ(reg);
2100         /*
2101          * make the BPC in transcoder be consistent with
2102          * that in pipeconf reg.
2103          */
2104         temp &= ~PIPE_BPC_MASK;
2105         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2106         I915_WRITE(reg, temp | TRANS_ENABLE);
2107         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2108                 DRM_ERROR("failed to enable transcoder\n");
2109
2110         intel_crtc_load_lut(crtc);
2111         intel_update_fbc(dev);
2112         intel_crtc_update_cursor(crtc, true);
2113 }
2114
2115 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2116 {
2117         struct drm_device *dev = crtc->dev;
2118         struct drm_i915_private *dev_priv = dev->dev_private;
2119         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2120         int pipe = intel_crtc->pipe;
2121         int plane = intel_crtc->plane;
2122         u32 reg, temp;
2123
2124         if (!intel_crtc->active)
2125                 return;
2126
2127         drm_vblank_off(dev, pipe);
2128         intel_crtc_update_cursor(crtc, false);
2129
2130         /* Disable display plane */
2131         reg = DSPCNTR(plane);
2132         temp = I915_READ(reg);
2133         if (temp & DISPLAY_PLANE_ENABLE) {
2134                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2135                 intel_flush_display_plane(dev, plane);
2136         }
2137
2138         if (dev_priv->cfb_plane == plane &&
2139             dev_priv->display.disable_fbc)
2140                 dev_priv->display.disable_fbc(dev);
2141
2142         /* disable cpu pipe, disable after all planes disabled */
2143         reg = PIPECONF(pipe);
2144         temp = I915_READ(reg);
2145         if (temp & PIPECONF_ENABLE) {
2146                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2147                 /* wait for cpu pipe off, pipe state */
2148                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2149                         DRM_ERROR("failed to turn off cpu pipe\n");
2150         }
2151
2152         /* Disable PF */
2153         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2154         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2155
2156         /* disable CPU FDI tx and PCH FDI rx */
2157         reg = FDI_TX_CTL(pipe);
2158         temp = I915_READ(reg);
2159         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2160         POSTING_READ(reg);
2161
2162         reg = FDI_RX_CTL(pipe);
2163         temp = I915_READ(reg);
2164         temp &= ~(0x7 << 16);
2165         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2166         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2167
2168         POSTING_READ(reg);
2169         udelay(100);
2170
2171         /* still set train pattern 1 */
2172         reg = FDI_TX_CTL(pipe);
2173         temp = I915_READ(reg);
2174         temp &= ~FDI_LINK_TRAIN_NONE;
2175         temp |= FDI_LINK_TRAIN_PATTERN_1;
2176         I915_WRITE(reg, temp);
2177
2178         reg = FDI_RX_CTL(pipe);
2179         temp = I915_READ(reg);
2180         if (HAS_PCH_CPT(dev)) {
2181                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2182                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2183         } else {
2184                 temp &= ~FDI_LINK_TRAIN_NONE;
2185                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2186         }
2187         /* BPC in FDI rx is consistent with that in PIPECONF */
2188         temp &= ~(0x07 << 16);
2189         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2190         I915_WRITE(reg, temp);
2191
2192         POSTING_READ(reg);
2193         udelay(100);
2194
2195         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2196                 temp = I915_READ(PCH_LVDS);
2197                 if (temp & LVDS_PORT_EN) {
2198                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2199                         POSTING_READ(PCH_LVDS);
2200                         udelay(100);
2201                 }
2202         }
2203
2204         /* disable PCH transcoder */
2205         reg = TRANSCONF(plane);
2206         temp = I915_READ(reg);
2207         if (temp & TRANS_ENABLE) {
2208                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2209                 /* wait for PCH transcoder off, transcoder state */
2210                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2211                         DRM_ERROR("failed to disable transcoder\n");
2212         }
2213
2214         if (HAS_PCH_CPT(dev)) {
2215                 /* disable TRANS_DP_CTL */
2216                 reg = TRANS_DP_CTL(pipe);
2217                 temp = I915_READ(reg);
2218                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2219                 I915_WRITE(reg, temp);
2220
2221                 /* disable DPLL_SEL */
2222                 temp = I915_READ(PCH_DPLL_SEL);
2223                 if (pipe == 0)
2224                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2225                 else
2226                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2227                 I915_WRITE(PCH_DPLL_SEL, temp);
2228         }
2229
2230         /* disable PCH DPLL */
2231         reg = PCH_DPLL(pipe);
2232         temp = I915_READ(reg);
2233         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2234
2235         /* Switch from PCDclk to Rawclk */
2236         reg = FDI_RX_CTL(pipe);
2237         temp = I915_READ(reg);
2238         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2239
2240         /* Disable CPU FDI TX PLL */
2241         reg = FDI_TX_CTL(pipe);
2242         temp = I915_READ(reg);
2243         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2244
2245         POSTING_READ(reg);
2246         udelay(100);
2247
2248         reg = FDI_RX_CTL(pipe);
2249         temp = I915_READ(reg);
2250         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2251
2252         /* Wait for the clocks to turn off. */
2253         POSTING_READ(reg);
2254         udelay(100);
2255
2256         intel_crtc->active = false;
2257         intel_update_watermarks(dev);
2258         intel_update_fbc(dev);
2259         intel_clear_scanline_wait(dev);
2260 }
2261
2262 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2263 {
2264         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2265         int pipe = intel_crtc->pipe;
2266         int plane = intel_crtc->plane;
2267
2268         /* XXX: When our outputs are all unaware of DPMS modes other than off
2269          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2270          */
2271         switch (mode) {
2272         case DRM_MODE_DPMS_ON:
2273         case DRM_MODE_DPMS_STANDBY:
2274         case DRM_MODE_DPMS_SUSPEND:
2275                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2276                 ironlake_crtc_enable(crtc);
2277                 break;
2278
2279         case DRM_MODE_DPMS_OFF:
2280                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2281                 ironlake_crtc_disable(crtc);
2282                 break;
2283         }
2284 }
2285
2286 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2287 {
2288         if (!enable && intel_crtc->overlay) {
2289                 struct drm_device *dev = intel_crtc->base.dev;
2290
2291                 mutex_lock(&dev->struct_mutex);
2292                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2293                 mutex_unlock(&dev->struct_mutex);
2294         }
2295
2296         /* Let userspace switch the overlay on again. In most cases userspace
2297          * has to recompute where to put it anyway.
2298          */
2299 }
2300
2301 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2302 {
2303         struct drm_device *dev = crtc->dev;
2304         struct drm_i915_private *dev_priv = dev->dev_private;
2305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2306         int pipe = intel_crtc->pipe;
2307         int plane = intel_crtc->plane;
2308         u32 reg, temp;
2309
2310         if (intel_crtc->active)
2311                 return;
2312
2313         intel_crtc->active = true;
2314         intel_update_watermarks(dev);
2315
2316         /* Enable the DPLL */
2317         reg = DPLL(pipe);
2318         temp = I915_READ(reg);
2319         if ((temp & DPLL_VCO_ENABLE) == 0) {
2320                 I915_WRITE(reg, temp);
2321
2322                 /* Wait for the clocks to stabilize. */
2323                 POSTING_READ(reg);
2324                 udelay(150);
2325
2326                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2327
2328                 /* Wait for the clocks to stabilize. */
2329                 POSTING_READ(reg);
2330                 udelay(150);
2331
2332                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2333
2334                 /* Wait for the clocks to stabilize. */
2335                 POSTING_READ(reg);
2336                 udelay(150);
2337         }
2338
2339         /* Enable the pipe */
2340         reg = PIPECONF(pipe);
2341         temp = I915_READ(reg);
2342         if ((temp & PIPECONF_ENABLE) == 0)
2343                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2344
2345         /* Enable the plane */
2346         reg = DSPCNTR(plane);
2347         temp = I915_READ(reg);
2348         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2349                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2350                 intel_flush_display_plane(dev, plane);
2351         }
2352
2353         intel_crtc_load_lut(crtc);
2354         intel_update_fbc(dev);
2355
2356         /* Give the overlay scaler a chance to enable if it's on this pipe */
2357         intel_crtc_dpms_overlay(intel_crtc, true);
2358         intel_crtc_update_cursor(crtc, true);
2359 }
2360
2361 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2362 {
2363         struct drm_device *dev = crtc->dev;
2364         struct drm_i915_private *dev_priv = dev->dev_private;
2365         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366         int pipe = intel_crtc->pipe;
2367         int plane = intel_crtc->plane;
2368         u32 reg, temp;
2369
2370         if (!intel_crtc->active)
2371                 return;
2372
2373         /* Give the overlay scaler a chance to disable if it's on this pipe */
2374         intel_crtc_dpms_overlay(intel_crtc, false);
2375         intel_crtc_update_cursor(crtc, false);
2376         drm_vblank_off(dev, pipe);
2377
2378         if (dev_priv->cfb_plane == plane &&
2379             dev_priv->display.disable_fbc)
2380                 dev_priv->display.disable_fbc(dev);
2381
2382         /* Disable display plane */
2383         reg = DSPCNTR(plane);
2384         temp = I915_READ(reg);
2385         if (temp & DISPLAY_PLANE_ENABLE) {
2386                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2387                 /* Flush the plane changes */
2388                 intel_flush_display_plane(dev, plane);
2389
2390                 /* Wait for vblank for the disable to take effect */
2391                 if (!IS_I9XX(dev))
2392                         intel_wait_for_vblank_off(dev, pipe);
2393         }
2394
2395         /* Don't disable pipe A or pipe A PLLs if needed */
2396         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2397                 goto done;
2398
2399         /* Next, disable display pipes */
2400         reg = PIPECONF(pipe);
2401         temp = I915_READ(reg);
2402         if (temp & PIPECONF_ENABLE) {
2403                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2404
2405                 /* Wait for vblank for the disable to take effect. */
2406                 POSTING_READ(reg);
2407                 intel_wait_for_vblank_off(dev, pipe);
2408         }
2409
2410         reg = DPLL(pipe);
2411         temp = I915_READ(reg);
2412         if (temp & DPLL_VCO_ENABLE) {
2413                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2414
2415                 /* Wait for the clocks to turn off. */
2416                 POSTING_READ(reg);
2417                 udelay(150);
2418         }
2419
2420 done:
2421         intel_crtc->active = false;
2422         intel_update_fbc(dev);
2423         intel_update_watermarks(dev);
2424         intel_clear_scanline_wait(dev);
2425 }
2426
2427 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2428 {
2429         /* XXX: When our outputs are all unaware of DPMS modes other than off
2430          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2431          */
2432         switch (mode) {
2433         case DRM_MODE_DPMS_ON:
2434         case DRM_MODE_DPMS_STANDBY:
2435         case DRM_MODE_DPMS_SUSPEND:
2436                 i9xx_crtc_enable(crtc);
2437                 break;
2438         case DRM_MODE_DPMS_OFF:
2439                 i9xx_crtc_disable(crtc);
2440                 break;
2441         }
2442 }
2443
2444 /**
2445  * Sets the power management mode of the pipe and plane.
2446  */
2447 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2448 {
2449         struct drm_device *dev = crtc->dev;
2450         struct drm_i915_private *dev_priv = dev->dev_private;
2451         struct drm_i915_master_private *master_priv;
2452         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2453         int pipe = intel_crtc->pipe;
2454         bool enabled;
2455
2456         if (intel_crtc->dpms_mode == mode)
2457                 return;
2458
2459         intel_crtc->dpms_mode = mode;
2460
2461         dev_priv->display.dpms(crtc, mode);
2462
2463         if (!dev->primary->master)
2464                 return;
2465
2466         master_priv = dev->primary->master->driver_priv;
2467         if (!master_priv->sarea_priv)
2468                 return;
2469
2470         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2471
2472         switch (pipe) {
2473         case 0:
2474                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2475                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2476                 break;
2477         case 1:
2478                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2479                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2480                 break;
2481         default:
2482                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2483                 break;
2484         }
2485 }
2486
2487 /* Prepare for a mode set.
2488  *
2489  * Note we could be a lot smarter here.  We need to figure out which outputs
2490  * will be enabled, which disabled (in short, how the config will changes)
2491  * and perform the minimum necessary steps to accomplish that, e.g. updating
2492  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2493  * panel fitting is in the proper state, etc.
2494  */
2495 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2496 {
2497         i9xx_crtc_disable(crtc);
2498 }
2499
2500 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2501 {
2502         i9xx_crtc_enable(crtc);
2503 }
2504
2505 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2506 {
2507         ironlake_crtc_disable(crtc);
2508 }
2509
2510 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2511 {
2512         ironlake_crtc_enable(crtc);
2513 }
2514
2515 void intel_encoder_prepare (struct drm_encoder *encoder)
2516 {
2517         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2518         /* lvds has its own version of prepare see intel_lvds_prepare */
2519         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2520 }
2521
2522 void intel_encoder_commit (struct drm_encoder *encoder)
2523 {
2524         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2525         /* lvds has its own version of commit see intel_lvds_commit */
2526         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2527 }
2528
2529 void intel_encoder_destroy(struct drm_encoder *encoder)
2530 {
2531         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2532
2533         drm_encoder_cleanup(encoder);
2534         kfree(intel_encoder);
2535 }
2536
2537 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2538                                   struct drm_display_mode *mode,
2539                                   struct drm_display_mode *adjusted_mode)
2540 {
2541         struct drm_device *dev = crtc->dev;
2542
2543         if (HAS_PCH_SPLIT(dev)) {
2544                 /* FDI link clock is fixed at 2.7G */
2545                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2546                         return false;
2547         }
2548
2549         /* XXX some encoders set the crtcinfo, others don't.
2550          * Obviously we need some form of conflict resolution here...
2551          */
2552         if (adjusted_mode->crtc_htotal == 0)
2553                 drm_mode_set_crtcinfo(adjusted_mode, 0);
2554
2555         return true;
2556 }
2557
2558 static int i945_get_display_clock_speed(struct drm_device *dev)
2559 {
2560         return 400000;
2561 }
2562
2563 static int i915_get_display_clock_speed(struct drm_device *dev)
2564 {
2565         return 333000;
2566 }
2567
2568 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2569 {
2570         return 200000;
2571 }
2572
2573 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2574 {
2575         u16 gcfgc = 0;
2576
2577         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2578
2579         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2580                 return 133000;
2581         else {
2582                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2583                 case GC_DISPLAY_CLOCK_333_MHZ:
2584                         return 333000;
2585                 default:
2586                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2587                         return 190000;
2588                 }
2589         }
2590 }
2591
2592 static int i865_get_display_clock_speed(struct drm_device *dev)
2593 {
2594         return 266000;
2595 }
2596
2597 static int i855_get_display_clock_speed(struct drm_device *dev)
2598 {
2599         u16 hpllcc = 0;
2600         /* Assume that the hardware is in the high speed state.  This
2601          * should be the default.
2602          */
2603         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2604         case GC_CLOCK_133_200:
2605         case GC_CLOCK_100_200:
2606                 return 200000;
2607         case GC_CLOCK_166_250:
2608                 return 250000;
2609         case GC_CLOCK_100_133:
2610                 return 133000;
2611         }
2612
2613         /* Shouldn't happen */
2614         return 0;
2615 }
2616
2617 static int i830_get_display_clock_speed(struct drm_device *dev)
2618 {
2619         return 133000;
2620 }
2621
2622 struct fdi_m_n {
2623         u32        tu;
2624         u32        gmch_m;
2625         u32        gmch_n;
2626         u32        link_m;
2627         u32        link_n;
2628 };
2629
2630 static void
2631 fdi_reduce_ratio(u32 *num, u32 *den)
2632 {
2633         while (*num > 0xffffff || *den > 0xffffff) {
2634                 *num >>= 1;
2635                 *den >>= 1;
2636         }
2637 }
2638
2639 #define DATA_N 0x800000
2640 #define LINK_N 0x80000
2641
2642 static void
2643 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2644                      int link_clock, struct fdi_m_n *m_n)
2645 {
2646         u64 temp;
2647
2648         m_n->tu = 64; /* default size */
2649
2650         temp = (u64) DATA_N * pixel_clock;
2651         temp = div_u64(temp, link_clock);
2652         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2653         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2654         m_n->gmch_n = DATA_N;
2655         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2656
2657         temp = (u64) LINK_N * pixel_clock;
2658         m_n->link_m = div_u64(temp, link_clock);
2659         m_n->link_n = LINK_N;
2660         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2661 }
2662
2663
2664 struct intel_watermark_params {
2665         unsigned long fifo_size;
2666         unsigned long max_wm;
2667         unsigned long default_wm;
2668         unsigned long guard_size;
2669         unsigned long cacheline_size;
2670 };
2671
2672 /* Pineview has different values for various configs */
2673 static struct intel_watermark_params pineview_display_wm = {
2674         PINEVIEW_DISPLAY_FIFO,
2675         PINEVIEW_MAX_WM,
2676         PINEVIEW_DFT_WM,
2677         PINEVIEW_GUARD_WM,
2678         PINEVIEW_FIFO_LINE_SIZE
2679 };
2680 static struct intel_watermark_params pineview_display_hplloff_wm = {
2681         PINEVIEW_DISPLAY_FIFO,
2682         PINEVIEW_MAX_WM,
2683         PINEVIEW_DFT_HPLLOFF_WM,
2684         PINEVIEW_GUARD_WM,
2685         PINEVIEW_FIFO_LINE_SIZE
2686 };
2687 static struct intel_watermark_params pineview_cursor_wm = {
2688         PINEVIEW_CURSOR_FIFO,
2689         PINEVIEW_CURSOR_MAX_WM,
2690         PINEVIEW_CURSOR_DFT_WM,
2691         PINEVIEW_CURSOR_GUARD_WM,
2692         PINEVIEW_FIFO_LINE_SIZE,
2693 };
2694 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2695         PINEVIEW_CURSOR_FIFO,
2696         PINEVIEW_CURSOR_MAX_WM,
2697         PINEVIEW_CURSOR_DFT_WM,
2698         PINEVIEW_CURSOR_GUARD_WM,
2699         PINEVIEW_FIFO_LINE_SIZE
2700 };
2701 static struct intel_watermark_params g4x_wm_info = {
2702         G4X_FIFO_SIZE,
2703         G4X_MAX_WM,
2704         G4X_MAX_WM,
2705         2,
2706         G4X_FIFO_LINE_SIZE,
2707 };
2708 static struct intel_watermark_params g4x_cursor_wm_info = {
2709         I965_CURSOR_FIFO,
2710         I965_CURSOR_MAX_WM,
2711         I965_CURSOR_DFT_WM,
2712         2,
2713         G4X_FIFO_LINE_SIZE,
2714 };
2715 static struct intel_watermark_params i965_cursor_wm_info = {
2716         I965_CURSOR_FIFO,
2717         I965_CURSOR_MAX_WM,
2718         I965_CURSOR_DFT_WM,
2719         2,
2720         I915_FIFO_LINE_SIZE,
2721 };
2722 static struct intel_watermark_params i945_wm_info = {
2723         I945_FIFO_SIZE,
2724         I915_MAX_WM,
2725         1,
2726         2,
2727         I915_FIFO_LINE_SIZE
2728 };
2729 static struct intel_watermark_params i915_wm_info = {
2730         I915_FIFO_SIZE,
2731         I915_MAX_WM,
2732         1,
2733         2,
2734         I915_FIFO_LINE_SIZE
2735 };
2736 static struct intel_watermark_params i855_wm_info = {
2737         I855GM_FIFO_SIZE,
2738         I915_MAX_WM,
2739         1,
2740         2,
2741         I830_FIFO_LINE_SIZE
2742 };
2743 static struct intel_watermark_params i830_wm_info = {
2744         I830_FIFO_SIZE,
2745         I915_MAX_WM,
2746         1,
2747         2,
2748         I830_FIFO_LINE_SIZE
2749 };
2750
2751 static struct intel_watermark_params ironlake_display_wm_info = {
2752         ILK_DISPLAY_FIFO,
2753         ILK_DISPLAY_MAXWM,
2754         ILK_DISPLAY_DFTWM,
2755         2,
2756         ILK_FIFO_LINE_SIZE
2757 };
2758
2759 static struct intel_watermark_params ironlake_cursor_wm_info = {
2760         ILK_CURSOR_FIFO,
2761         ILK_CURSOR_MAXWM,
2762         ILK_CURSOR_DFTWM,
2763         2,
2764         ILK_FIFO_LINE_SIZE
2765 };
2766
2767 static struct intel_watermark_params ironlake_display_srwm_info = {
2768         ILK_DISPLAY_SR_FIFO,
2769         ILK_DISPLAY_MAX_SRWM,
2770         ILK_DISPLAY_DFT_SRWM,
2771         2,
2772         ILK_FIFO_LINE_SIZE
2773 };
2774
2775 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2776         ILK_CURSOR_SR_FIFO,
2777         ILK_CURSOR_MAX_SRWM,
2778         ILK_CURSOR_DFT_SRWM,
2779         2,
2780         ILK_FIFO_LINE_SIZE
2781 };
2782
2783 /**
2784  * intel_calculate_wm - calculate watermark level
2785  * @clock_in_khz: pixel clock
2786  * @wm: chip FIFO params
2787  * @pixel_size: display pixel size
2788  * @latency_ns: memory latency for the platform
2789  *
2790  * Calculate the watermark level (the level at which the display plane will
2791  * start fetching from memory again).  Each chip has a different display
2792  * FIFO size and allocation, so the caller needs to figure that out and pass
2793  * in the correct intel_watermark_params structure.
2794  *
2795  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2796  * on the pixel size.  When it reaches the watermark level, it'll start
2797  * fetching FIFO line sized based chunks from memory until the FIFO fills
2798  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2799  * will occur, and a display engine hang could result.
2800  */
2801 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2802                                         struct intel_watermark_params *wm,
2803                                         int pixel_size,
2804                                         unsigned long latency_ns)
2805 {
2806         long entries_required, wm_size;
2807
2808         /*
2809          * Note: we need to make sure we don't overflow for various clock &
2810          * latency values.
2811          * clocks go from a few thousand to several hundred thousand.
2812          * latency is usually a few thousand
2813          */
2814         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2815                 1000;
2816         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2817
2818         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2819
2820         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2821
2822         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2823
2824         /* Don't promote wm_size to unsigned... */
2825         if (wm_size > (long)wm->max_wm)
2826                 wm_size = wm->max_wm;
2827         if (wm_size <= 0)
2828                 wm_size = wm->default_wm;
2829         return wm_size;
2830 }
2831
2832 struct cxsr_latency {
2833         int is_desktop;
2834         int is_ddr3;
2835         unsigned long fsb_freq;
2836         unsigned long mem_freq;
2837         unsigned long display_sr;
2838         unsigned long display_hpll_disable;
2839         unsigned long cursor_sr;
2840         unsigned long cursor_hpll_disable;
2841 };
2842
2843 static const struct cxsr_latency cxsr_latency_table[] = {
2844         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2845         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2846         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2847         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2848         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2849
2850         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2851         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2852         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2853         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2854         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2855
2856         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2857         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2858         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2859         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2860         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2861
2862         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2863         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2864         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2865         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2866         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2867
2868         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2869         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2870         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2871         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2872         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2873
2874         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2875         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2876         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2877         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2878         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2879 };
2880
2881 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2882                                                          int is_ddr3,
2883                                                          int fsb,
2884                                                          int mem)
2885 {
2886         const struct cxsr_latency *latency;
2887         int i;
2888
2889         if (fsb == 0 || mem == 0)
2890                 return NULL;
2891
2892         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2893                 latency = &cxsr_latency_table[i];
2894                 if (is_desktop == latency->is_desktop &&
2895                     is_ddr3 == latency->is_ddr3 &&
2896                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2897                         return latency;
2898         }
2899
2900         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2901
2902         return NULL;
2903 }
2904
2905 static void pineview_disable_cxsr(struct drm_device *dev)
2906 {
2907         struct drm_i915_private *dev_priv = dev->dev_private;
2908
2909         /* deactivate cxsr */
2910         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2911 }
2912
2913 /*
2914  * Latency for FIFO fetches is dependent on several factors:
2915  *   - memory configuration (speed, channels)
2916  *   - chipset
2917  *   - current MCH state
2918  * It can be fairly high in some situations, so here we assume a fairly
2919  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2920  * set this value too high, the FIFO will fetch frequently to stay full)
2921  * and power consumption (set it too low to save power and we might see
2922  * FIFO underruns and display "flicker").
2923  *
2924  * A value of 5us seems to be a good balance; safe for very low end
2925  * platforms but not overly aggressive on lower latency configs.
2926  */
2927 static const int latency_ns = 5000;
2928
2929 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2930 {
2931         struct drm_i915_private *dev_priv = dev->dev_private;
2932         uint32_t dsparb = I915_READ(DSPARB);
2933         int size;
2934
2935         size = dsparb & 0x7f;
2936         if (plane)
2937                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2938
2939         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2940                       plane ? "B" : "A", size);
2941
2942         return size;
2943 }
2944
2945 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2946 {
2947         struct drm_i915_private *dev_priv = dev->dev_private;
2948         uint32_t dsparb = I915_READ(DSPARB);
2949         int size;
2950
2951         size = dsparb & 0x1ff;
2952         if (plane)
2953                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2954         size >>= 1; /* Convert to cachelines */
2955
2956         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2957                       plane ? "B" : "A", size);
2958
2959         return size;
2960 }
2961
2962 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2963 {
2964         struct drm_i915_private *dev_priv = dev->dev_private;
2965         uint32_t dsparb = I915_READ(DSPARB);
2966         int size;
2967
2968         size = dsparb & 0x7f;
2969         size >>= 2; /* Convert to cachelines */
2970
2971         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2972                       plane ? "B" : "A",
2973                       size);
2974
2975         return size;
2976 }
2977
2978 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2979 {
2980         struct drm_i915_private *dev_priv = dev->dev_private;
2981         uint32_t dsparb = I915_READ(DSPARB);
2982         int size;
2983
2984         size = dsparb & 0x7f;
2985         size >>= 1; /* Convert to cachelines */
2986
2987         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2988                       plane ? "B" : "A", size);
2989
2990         return size;
2991 }
2992
2993 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
2994                                int planeb_clock, int sr_hdisplay, int unused,
2995                                int pixel_size)
2996 {
2997         struct drm_i915_private *dev_priv = dev->dev_private;
2998         const struct cxsr_latency *latency;
2999         u32 reg;
3000         unsigned long wm;
3001         int sr_clock;
3002
3003         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3004                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3005         if (!latency) {
3006                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3007                 pineview_disable_cxsr(dev);
3008                 return;
3009         }
3010
3011         if (!planea_clock || !planeb_clock) {
3012                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3013
3014                 /* Display SR */
3015                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3016                                         pixel_size, latency->display_sr);
3017                 reg = I915_READ(DSPFW1);
3018                 reg &= ~DSPFW_SR_MASK;
3019                 reg |= wm << DSPFW_SR_SHIFT;
3020                 I915_WRITE(DSPFW1, reg);
3021                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3022
3023                 /* cursor SR */
3024                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3025                                         pixel_size, latency->cursor_sr);
3026                 reg = I915_READ(DSPFW3);
3027                 reg &= ~DSPFW_CURSOR_SR_MASK;
3028                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3029                 I915_WRITE(DSPFW3, reg);
3030
3031                 /* Display HPLL off SR */
3032                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3033                                         pixel_size, latency->display_hpll_disable);
3034                 reg = I915_READ(DSPFW3);
3035                 reg &= ~DSPFW_HPLL_SR_MASK;
3036                 reg |= wm & DSPFW_HPLL_SR_MASK;
3037                 I915_WRITE(DSPFW3, reg);
3038
3039                 /* cursor HPLL off SR */
3040                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3041                                         pixel_size, latency->cursor_hpll_disable);
3042                 reg = I915_READ(DSPFW3);
3043                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3044                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3045                 I915_WRITE(DSPFW3, reg);
3046                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3047
3048                 /* activate cxsr */
3049                 I915_WRITE(DSPFW3,
3050                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3051                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3052         } else {
3053                 pineview_disable_cxsr(dev);
3054                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3055         }
3056 }
3057
3058 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3059                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3060                           int pixel_size)
3061 {
3062         struct drm_i915_private *dev_priv = dev->dev_private;
3063         int total_size, cacheline_size;
3064         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3065         struct intel_watermark_params planea_params, planeb_params;
3066         unsigned long line_time_us;
3067         int sr_clock, sr_entries = 0, entries_required;
3068
3069         /* Create copies of the base settings for each pipe */
3070         planea_params = planeb_params = g4x_wm_info;
3071
3072         /* Grab a couple of global values before we overwrite them */
3073         total_size = planea_params.fifo_size;
3074         cacheline_size = planea_params.cacheline_size;
3075
3076         /*
3077          * Note: we need to make sure we don't overflow for various clock &
3078          * latency values.
3079          * clocks go from a few thousand to several hundred thousand.
3080          * latency is usually a few thousand
3081          */
3082         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3083                 1000;
3084         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3085         planea_wm = entries_required + planea_params.guard_size;
3086
3087         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3088                 1000;
3089         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3090         planeb_wm = entries_required + planeb_params.guard_size;
3091
3092         cursora_wm = cursorb_wm = 16;
3093         cursor_sr = 32;
3094
3095         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3096
3097         /* Calc sr entries for one plane configs */
3098         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3099                 /* self-refresh has much higher latency */
3100                 static const int sr_latency_ns = 12000;
3101
3102                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3103                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3104
3105                 /* Use ns/us then divide to preserve precision */
3106                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3107                         pixel_size * sr_hdisplay;
3108                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3109
3110                 entries_required = (((sr_latency_ns / line_time_us) +
3111                                      1000) / 1000) * pixel_size * 64;
3112                 entries_required = DIV_ROUND_UP(entries_required,
3113                                                 g4x_cursor_wm_info.cacheline_size);
3114                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3115
3116                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3117                         cursor_sr = g4x_cursor_wm_info.max_wm;
3118                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3119                               "cursor %d\n", sr_entries, cursor_sr);
3120
3121                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3122         } else {
3123                 /* Turn off self refresh if both pipes are enabled */
3124                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3125                            & ~FW_BLC_SELF_EN);
3126         }
3127
3128         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3129                   planea_wm, planeb_wm, sr_entries);
3130
3131         planea_wm &= 0x3f;
3132         planeb_wm &= 0x3f;
3133
3134         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3135                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3136                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3137         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3138                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3139         /* HPLL off in SR has some issues on G4x... disable it */
3140         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3141                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3142 }
3143
3144 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3145                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3146                            int pixel_size)
3147 {
3148         struct drm_i915_private *dev_priv = dev->dev_private;
3149         unsigned long line_time_us;
3150         int sr_clock, sr_entries, srwm = 1;
3151         int cursor_sr = 16;
3152
3153         /* Calc sr entries for one plane configs */
3154         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3155                 /* self-refresh has much higher latency */
3156                 static const int sr_latency_ns = 12000;
3157
3158                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3159                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3160
3161                 /* Use ns/us then divide to preserve precision */
3162                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3163                         pixel_size * sr_hdisplay;
3164                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3165                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3166                 srwm = I965_FIFO_SIZE - sr_entries;
3167                 if (srwm < 0)
3168                         srwm = 1;
3169                 srwm &= 0x1ff;
3170
3171                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3172                         pixel_size * 64;
3173                 sr_entries = DIV_ROUND_UP(sr_entries,
3174                                           i965_cursor_wm_info.cacheline_size);
3175                 cursor_sr = i965_cursor_wm_info.fifo_size -
3176                         (sr_entries + i965_cursor_wm_info.guard_size);
3177
3178                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3179                         cursor_sr = i965_cursor_wm_info.max_wm;
3180
3181                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3182                               "cursor %d\n", srwm, cursor_sr);
3183
3184                 if (IS_I965GM(dev))
3185                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3186         } else {
3187                 /* Turn off self refresh if both pipes are enabled */
3188                 if (IS_I965GM(dev))
3189                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3190                                    & ~FW_BLC_SELF_EN);
3191         }
3192
3193         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3194                       srwm);
3195
3196         /* 965 has limitations... */
3197         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3198                    (8 << 0));
3199         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3200         /* update cursor SR watermark */
3201         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3202 }
3203
3204 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3205                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3206                            int pixel_size)
3207 {
3208         struct drm_i915_private *dev_priv = dev->dev_private;
3209         uint32_t fwater_lo;
3210         uint32_t fwater_hi;
3211         int total_size, cacheline_size, cwm, srwm = 1;
3212         int planea_wm, planeb_wm;
3213         struct intel_watermark_params planea_params, planeb_params;
3214         unsigned long line_time_us;
3215         int sr_clock, sr_entries = 0;
3216
3217         /* Create copies of the base settings for each pipe */
3218         if (IS_I965GM(dev) || IS_I945GM(dev))
3219                 planea_params = planeb_params = i945_wm_info;
3220         else if (IS_I9XX(dev))
3221                 planea_params = planeb_params = i915_wm_info;
3222         else
3223                 planea_params = planeb_params = i855_wm_info;
3224
3225         /* Grab a couple of global values before we overwrite them */
3226         total_size = planea_params.fifo_size;
3227         cacheline_size = planea_params.cacheline_size;
3228
3229         /* Update per-plane FIFO sizes */
3230         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3231         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3232
3233         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3234                                        pixel_size, latency_ns);
3235         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3236                                        pixel_size, latency_ns);
3237         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3238
3239         /*
3240          * Overlay gets an aggressive default since video jitter is bad.
3241          */
3242         cwm = 2;
3243
3244         /* Calc sr entries for one plane configs */
3245         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3246             (!planea_clock || !planeb_clock)) {
3247                 /* self-refresh has much higher latency */
3248                 static const int sr_latency_ns = 6000;
3249
3250                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3251                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3252
3253                 /* Use ns/us then divide to preserve precision */
3254                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3255                         pixel_size * sr_hdisplay;
3256                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3257                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3258                 srwm = total_size - sr_entries;
3259                 if (srwm < 0)
3260                         srwm = 1;
3261
3262                 if (IS_I945G(dev) || IS_I945GM(dev))
3263                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3264                 else if (IS_I915GM(dev)) {
3265                         /* 915M has a smaller SRWM field */
3266                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3267                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3268                 }
3269         } else {
3270                 /* Turn off self refresh if both pipes are enabled */
3271                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3272                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3273                                    & ~FW_BLC_SELF_EN);
3274                 } else if (IS_I915GM(dev)) {
3275                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3276                 }
3277         }
3278
3279         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3280                       planea_wm, planeb_wm, cwm, srwm);
3281
3282         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3283         fwater_hi = (cwm & 0x1f);
3284
3285         /* Set request length to 8 cachelines per fetch */
3286         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3287         fwater_hi = fwater_hi | (1 << 8);
3288
3289         I915_WRITE(FW_BLC, fwater_lo);
3290         I915_WRITE(FW_BLC2, fwater_hi);
3291 }
3292
3293 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3294                            int unused2, int unused3, int pixel_size)
3295 {
3296         struct drm_i915_private *dev_priv = dev->dev_private;
3297         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3298         int planea_wm;
3299
3300         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3301
3302         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3303                                        pixel_size, latency_ns);
3304         fwater_lo |= (3<<8) | planea_wm;
3305
3306         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3307
3308         I915_WRITE(FW_BLC, fwater_lo);
3309 }
3310
3311 #define ILK_LP0_PLANE_LATENCY           700
3312 #define ILK_LP0_CURSOR_LATENCY          1300
3313
3314 static bool ironlake_compute_wm0(struct drm_device *dev,
3315                                  int pipe,
3316                                  int *plane_wm,
3317                                  int *cursor_wm)
3318 {
3319         struct drm_crtc *crtc;
3320         int htotal, hdisplay, clock, pixel_size = 0;
3321         int line_time_us, line_count, entries;
3322
3323         crtc = intel_get_crtc_for_pipe(dev, pipe);
3324         if (crtc->fb == NULL || !crtc->enabled)
3325                 return false;
3326
3327         htotal = crtc->mode.htotal;
3328         hdisplay = crtc->mode.hdisplay;
3329         clock = crtc->mode.clock;
3330         pixel_size = crtc->fb->bits_per_pixel / 8;
3331
3332         /* Use the small buffer method to calculate plane watermark */
3333         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3334         entries = DIV_ROUND_UP(entries,
3335                                ironlake_display_wm_info.cacheline_size);
3336         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3337         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3338                 *plane_wm = ironlake_display_wm_info.max_wm;
3339
3340         /* Use the large buffer method to calculate cursor watermark */
3341         line_time_us = ((htotal * 1000) / clock);
3342         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3343         entries = line_count * 64 * pixel_size;
3344         entries = DIV_ROUND_UP(entries,
3345                                ironlake_cursor_wm_info.cacheline_size);
3346         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3347         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3348                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3349
3350         return true;
3351 }
3352
3353 static void ironlake_update_wm(struct drm_device *dev,
3354                                int planea_clock, int planeb_clock,
3355                                int sr_hdisplay, int sr_htotal,
3356                                int pixel_size)
3357 {
3358         struct drm_i915_private *dev_priv = dev->dev_private;
3359         int plane_wm, cursor_wm, enabled;
3360         int tmp;
3361
3362         enabled = 0;
3363         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3364                 I915_WRITE(WM0_PIPEA_ILK,
3365                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3366                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3367                               " plane %d, " "cursor: %d\n",
3368                               plane_wm, cursor_wm);
3369                 enabled++;
3370         }
3371
3372         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3373                 I915_WRITE(WM0_PIPEB_ILK,
3374                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3375                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3376                               " plane %d, cursor: %d\n",
3377                               plane_wm, cursor_wm);
3378                 enabled++;
3379         }
3380
3381         /*
3382          * Calculate and update the self-refresh watermark only when one
3383          * display plane is used.
3384          */
3385         tmp = 0;
3386         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3387                 unsigned long line_time_us;
3388                 int small, large, plane_fbc;
3389                 int sr_clock, entries;
3390                 int line_count, line_size;
3391                 /* Read the self-refresh latency. The unit is 0.5us */
3392                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3393
3394                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3395                 line_time_us = (sr_htotal * 1000) / sr_clock;
3396
3397                 /* Use ns/us then divide to preserve precision */
3398                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3399                         / 1000;
3400                 line_size = sr_hdisplay * pixel_size;
3401
3402                 /* Use the minimum of the small and large buffer method for primary */
3403                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3404                 large = line_count * line_size;
3405
3406                 entries = DIV_ROUND_UP(min(small, large),
3407                                        ironlake_display_srwm_info.cacheline_size);
3408
3409                 plane_fbc = entries * 64;
3410                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3411
3412                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3413                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3414                         plane_wm = ironlake_display_srwm_info.max_wm;
3415
3416                 /* calculate the self-refresh watermark for display cursor */
3417                 entries = line_count * pixel_size * 64;
3418                 entries = DIV_ROUND_UP(entries,
3419                                        ironlake_cursor_srwm_info.cacheline_size);
3420
3421                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3422                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3423                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3424
3425                 /* configure watermark and enable self-refresh */
3426                 tmp = (WM1_LP_SR_EN |
3427                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3428                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3429                        (plane_wm << WM1_LP_SR_SHIFT) |
3430                        cursor_wm);
3431                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3432                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3433         }
3434         I915_WRITE(WM1_LP_ILK, tmp);
3435         /* XXX setup WM2 and WM3 */
3436 }
3437
3438 /**
3439  * intel_update_watermarks - update FIFO watermark values based on current modes
3440  *
3441  * Calculate watermark values for the various WM regs based on current mode
3442  * and plane configuration.
3443  *
3444  * There are several cases to deal with here:
3445  *   - normal (i.e. non-self-refresh)
3446  *   - self-refresh (SR) mode
3447  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3448  *   - lines are small relative to FIFO size (buffer can hold more than 2
3449  *     lines), so need to account for TLB latency
3450  *
3451  *   The normal calculation is:
3452  *     watermark = dotclock * bytes per pixel * latency
3453  *   where latency is platform & configuration dependent (we assume pessimal
3454  *   values here).
3455  *
3456  *   The SR calculation is:
3457  *     watermark = (trunc(latency/line time)+1) * surface width *
3458  *       bytes per pixel
3459  *   where
3460  *     line time = htotal / dotclock
3461  *     surface width = hdisplay for normal plane and 64 for cursor
3462  *   and latency is assumed to be high, as above.
3463  *
3464  * The final value programmed to the register should always be rounded up,
3465  * and include an extra 2 entries to account for clock crossings.
3466  *
3467  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3468  * to set the non-SR watermarks to 8.
3469  */
3470 static void intel_update_watermarks(struct drm_device *dev)
3471 {
3472         struct drm_i915_private *dev_priv = dev->dev_private;
3473         struct drm_crtc *crtc;
3474         int sr_hdisplay = 0;
3475         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3476         int enabled = 0, pixel_size = 0;
3477         int sr_htotal = 0;
3478
3479         if (!dev_priv->display.update_wm)
3480                 return;
3481
3482         /* Get the clock config from both planes */
3483         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3484                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3485                 if (intel_crtc->active) {
3486                         enabled++;
3487                         if (intel_crtc->plane == 0) {
3488                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3489                                               intel_crtc->pipe, crtc->mode.clock);
3490                                 planea_clock = crtc->mode.clock;
3491                         } else {
3492                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3493                                               intel_crtc->pipe, crtc->mode.clock);
3494                                 planeb_clock = crtc->mode.clock;
3495                         }
3496                         sr_hdisplay = crtc->mode.hdisplay;
3497                         sr_clock = crtc->mode.clock;
3498                         sr_htotal = crtc->mode.htotal;
3499                         if (crtc->fb)
3500                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3501                         else
3502                                 pixel_size = 4; /* by default */
3503                 }
3504         }
3505
3506         if (enabled <= 0)
3507                 return;
3508
3509         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3510                                     sr_hdisplay, sr_htotal, pixel_size);
3511 }
3512
3513 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3514                                struct drm_display_mode *mode,
3515                                struct drm_display_mode *adjusted_mode,
3516                                int x, int y,
3517                                struct drm_framebuffer *old_fb)
3518 {
3519         struct drm_device *dev = crtc->dev;
3520         struct drm_i915_private *dev_priv = dev->dev_private;
3521         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3522         int pipe = intel_crtc->pipe;
3523         int plane = intel_crtc->plane;
3524         u32 fp_reg, dpll_reg;
3525         int refclk, num_connectors = 0;
3526         intel_clock_t clock, reduced_clock;
3527         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3528         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3529         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3530         struct intel_encoder *has_edp_encoder = NULL;
3531         struct drm_mode_config *mode_config = &dev->mode_config;
3532         struct intel_encoder *encoder;
3533         const intel_limit_t *limit;
3534         int ret;
3535         struct fdi_m_n m_n = {0};
3536         u32 reg, temp;
3537         int target_clock;
3538
3539         drm_vblank_pre_modeset(dev, pipe);
3540
3541         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3542                 if (encoder->base.crtc != crtc)
3543                         continue;
3544
3545                 switch (encoder->type) {
3546                 case INTEL_OUTPUT_LVDS:
3547                         is_lvds = true;
3548                         break;
3549                 case INTEL_OUTPUT_SDVO:
3550                 case INTEL_OUTPUT_HDMI:
3551                         is_sdvo = true;
3552                         if (encoder->needs_tv_clock)
3553                                 is_tv = true;
3554                         break;
3555                 case INTEL_OUTPUT_DVO:
3556                         is_dvo = true;
3557                         break;
3558                 case INTEL_OUTPUT_TVOUT:
3559                         is_tv = true;
3560                         break;
3561                 case INTEL_OUTPUT_ANALOG:
3562                         is_crt = true;
3563                         break;
3564                 case INTEL_OUTPUT_DISPLAYPORT:
3565                         is_dp = true;
3566                         break;
3567                 case INTEL_OUTPUT_EDP:
3568                         has_edp_encoder = encoder;
3569                         break;
3570                 }
3571
3572                 num_connectors++;
3573         }
3574
3575         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3576                 refclk = dev_priv->lvds_ssc_freq * 1000;
3577                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3578                               refclk / 1000);
3579         } else if (IS_I9XX(dev)) {
3580                 refclk = 96000;
3581                 if (HAS_PCH_SPLIT(dev))
3582                         refclk = 120000; /* 120Mhz refclk */
3583         } else {
3584                 refclk = 48000;
3585         }
3586
3587         /*
3588          * Returns a set of divisors for the desired target clock with the given
3589          * refclk, or FALSE.  The returned values represent the clock equation:
3590          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3591          */
3592         limit = intel_limit(crtc);
3593         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3594         if (!ok) {
3595                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3596                 drm_vblank_post_modeset(dev, pipe);
3597                 return -EINVAL;
3598         }
3599
3600         /* Ensure that the cursor is valid for the new mode before changing... */
3601         intel_crtc_update_cursor(crtc, true);
3602
3603         if (is_lvds && dev_priv->lvds_downclock_avail) {
3604                 has_reduced_clock = limit->find_pll(limit, crtc,
3605                                                     dev_priv->lvds_downclock,
3606                                                     refclk,
3607                                                     &reduced_clock);
3608                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3609                         /*
3610                          * If the different P is found, it means that we can't
3611                          * switch the display clock by using the FP0/FP1.
3612                          * In such case we will disable the LVDS downclock
3613                          * feature.
3614                          */
3615                         DRM_DEBUG_KMS("Different P is found for "
3616                                       "LVDS clock/downclock\n");
3617                         has_reduced_clock = 0;
3618                 }
3619         }
3620         /* SDVO TV has fixed PLL values depend on its clock range,
3621            this mirrors vbios setting. */
3622         if (is_sdvo && is_tv) {
3623                 if (adjusted_mode->clock >= 100000
3624                     && adjusted_mode->clock < 140500) {
3625                         clock.p1 = 2;
3626                         clock.p2 = 10;
3627                         clock.n = 3;
3628                         clock.m1 = 16;
3629                         clock.m2 = 8;
3630                 } else if (adjusted_mode->clock >= 140500
3631                            && adjusted_mode->clock <= 200000) {
3632                         clock.p1 = 1;
3633                         clock.p2 = 10;
3634                         clock.n = 6;
3635                         clock.m1 = 12;
3636                         clock.m2 = 8;
3637                 }
3638         }
3639
3640         /* FDI link */
3641         if (HAS_PCH_SPLIT(dev)) {
3642                 int lane = 0, link_bw, bpp;
3643                 /* eDP doesn't require FDI link, so just set DP M/N
3644                    according to current link config */
3645                 if (has_edp_encoder) {
3646                         target_clock = mode->clock;
3647                         intel_edp_link_config(has_edp_encoder,
3648                                               &lane, &link_bw);
3649                 } else {
3650                         /* DP over FDI requires target mode clock
3651                            instead of link clock */
3652                         if (is_dp)
3653                                 target_clock = mode->clock;
3654                         else
3655                                 target_clock = adjusted_mode->clock;
3656
3657                         /* FDI is a binary signal running at ~2.7GHz, encoding
3658                          * each output octet as 10 bits. The actual frequency
3659                          * is stored as a divider into a 100MHz clock, and the
3660                          * mode pixel clock is stored in units of 1KHz.
3661                          * Hence the bw of each lane in terms of the mode signal
3662                          * is:
3663                          */
3664                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3665                 }
3666
3667                 /* determine panel color depth */
3668                 temp = I915_READ(PIPECONF(pipe));
3669                 temp &= ~PIPE_BPC_MASK;
3670                 if (is_lvds) {
3671                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3672                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3673                                 temp |= PIPE_8BPC;
3674                         else
3675                                 temp |= PIPE_6BPC;
3676                 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3677                         switch (dev_priv->edp_bpp/3) {
3678                         case 8:
3679                                 temp |= PIPE_8BPC;
3680                                 break;
3681                         case 10:
3682                                 temp |= PIPE_10BPC;
3683                                 break;
3684                         case 6:
3685                                 temp |= PIPE_6BPC;
3686                                 break;
3687                         case 12:
3688                                 temp |= PIPE_12BPC;
3689                                 break;
3690                         }
3691                 } else
3692                         temp |= PIPE_8BPC;
3693                 I915_WRITE(PIPECONF(pipe), temp);
3694
3695                 switch (temp & PIPE_BPC_MASK) {
3696                 case PIPE_8BPC:
3697                         bpp = 24;
3698                         break;
3699                 case PIPE_10BPC:
3700                         bpp = 30;
3701                         break;
3702                 case PIPE_6BPC:
3703                         bpp = 18;
3704                         break;
3705                 case PIPE_12BPC:
3706                         bpp = 36;
3707                         break;
3708                 default:
3709                         DRM_ERROR("unknown pipe bpc value\n");
3710                         bpp = 24;
3711                 }
3712
3713                 if (!lane) {
3714                         /*
3715                          * Account for spread spectrum to avoid
3716                          * oversubscribing the link. Max center spread
3717                          * is 2.5%; use 5% for safety's sake.
3718                          */
3719                         u32 bps = target_clock * bpp * 21 / 20;
3720                         lane = bps / (link_bw * 8) + 1;
3721                 }
3722
3723                 intel_crtc->fdi_lanes = lane;
3724
3725                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3726         }
3727
3728         /* Ironlake: try to setup display ref clock before DPLL
3729          * enabling. This is only under driver's control after
3730          * PCH B stepping, previous chipset stepping should be
3731          * ignoring this setting.
3732          */
3733         if (HAS_PCH_SPLIT(dev)) {
3734                 temp = I915_READ(PCH_DREF_CONTROL);
3735                 /* Always enable nonspread source */
3736                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3737                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3738                 temp &= ~DREF_SSC_SOURCE_MASK;
3739                 temp |= DREF_SSC_SOURCE_ENABLE;
3740                 I915_WRITE(PCH_DREF_CONTROL, temp);
3741
3742                 POSTING_READ(PCH_DREF_CONTROL);
3743                 udelay(200);
3744
3745                 if (has_edp_encoder) {
3746                         if (dev_priv->lvds_use_ssc) {
3747                                 temp |= DREF_SSC1_ENABLE;
3748                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3749
3750                                 POSTING_READ(PCH_DREF_CONTROL);
3751                                 udelay(200);
3752
3753                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3754                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3755                         } else {
3756                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3757                         }
3758                         I915_WRITE(PCH_DREF_CONTROL, temp);
3759                 }
3760         }
3761
3762         if (IS_PINEVIEW(dev)) {
3763                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3764                 if (has_reduced_clock)
3765                         fp2 = (1 << reduced_clock.n) << 16 |
3766                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3767         } else {
3768                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3769                 if (has_reduced_clock)
3770                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3771                                 reduced_clock.m2;
3772         }
3773
3774         dpll = 0;
3775         if (!HAS_PCH_SPLIT(dev))
3776                 dpll = DPLL_VGA_MODE_DIS;
3777
3778         if (IS_I9XX(dev)) {
3779                 if (is_lvds)
3780                         dpll |= DPLLB_MODE_LVDS;
3781                 else
3782                         dpll |= DPLLB_MODE_DAC_SERIAL;
3783                 if (is_sdvo) {
3784                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3785                         if (pixel_multiplier > 1) {
3786                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3787                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3788                                 else if (HAS_PCH_SPLIT(dev))
3789                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3790                         }
3791                         dpll |= DPLL_DVO_HIGH_SPEED;
3792                 }
3793                 if (is_dp)
3794                         dpll |= DPLL_DVO_HIGH_SPEED;
3795
3796                 /* compute bitmask from p1 value */
3797                 if (IS_PINEVIEW(dev))
3798                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3799                 else {
3800                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3801                         /* also FPA1 */
3802                         if (HAS_PCH_SPLIT(dev))
3803                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3804                         if (IS_G4X(dev) && has_reduced_clock)
3805                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3806                 }
3807                 switch (clock.p2) {
3808                 case 5:
3809                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3810                         break;
3811                 case 7:
3812                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3813                         break;
3814                 case 10:
3815                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3816                         break;
3817                 case 14:
3818                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3819                         break;
3820                 }
3821                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3822                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3823         } else {
3824                 if (is_lvds) {
3825                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3826                 } else {
3827                         if (clock.p1 == 2)
3828                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3829                         else
3830                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3831                         if (clock.p2 == 4)
3832                                 dpll |= PLL_P2_DIVIDE_BY_4;
3833                 }
3834         }
3835
3836         if (is_sdvo && is_tv)
3837                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3838         else if (is_tv)
3839                 /* XXX: just matching BIOS for now */
3840                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3841                 dpll |= 3;
3842         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3843                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3844         else
3845                 dpll |= PLL_REF_INPUT_DREFCLK;
3846
3847         /* setup pipeconf */
3848         pipeconf = I915_READ(PIPECONF(pipe));
3849
3850         /* Set up the display plane register */
3851         dspcntr = DISPPLANE_GAMMA_ENABLE;
3852
3853         /* Ironlake's plane is forced to pipe, bit 24 is to
3854            enable color space conversion */
3855         if (!HAS_PCH_SPLIT(dev)) {
3856                 if (pipe == 0)
3857                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3858                 else
3859                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3860         }
3861
3862         if (pipe == 0 && !IS_I965G(dev)) {
3863                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3864                  * core speed.
3865                  *
3866                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3867                  * pipe == 0 check?
3868                  */
3869                 if (mode->clock >
3870                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3871                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3872                 else
3873                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3874         }
3875
3876         dspcntr |= DISPLAY_PLANE_ENABLE;
3877         pipeconf |= PIPECONF_ENABLE;
3878         dpll |= DPLL_VCO_ENABLE;
3879
3880         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3881         drm_mode_debug_printmodeline(mode);
3882
3883         /* assign to Ironlake registers */
3884         if (HAS_PCH_SPLIT(dev)) {
3885                 fp_reg = PCH_FP0(pipe);
3886                 dpll_reg = PCH_DPLL(pipe);
3887         } else {
3888                 fp_reg = FP0(pipe);
3889                 dpll_reg = DPLL(pipe);
3890         }
3891
3892         if (!has_edp_encoder) {
3893                 I915_WRITE(fp_reg, fp);
3894                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3895
3896                 POSTING_READ(dpll_reg);
3897                 udelay(150);
3898         }
3899
3900         /* enable transcoder DPLL */
3901         if (HAS_PCH_CPT(dev)) {
3902                 temp = I915_READ(PCH_DPLL_SEL);
3903                 if (pipe == 0)
3904                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3905                 else
3906                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3907                 I915_WRITE(PCH_DPLL_SEL, temp);
3908
3909                 POSTING_READ(PCH_DPLL_SEL);
3910                 udelay(150);
3911         }
3912
3913         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3914          * This is an exception to the general rule that mode_set doesn't turn
3915          * things on.
3916          */
3917         if (is_lvds) {
3918                 reg = LVDS;
3919                 if (HAS_PCH_SPLIT(dev))
3920                         reg = PCH_LVDS;
3921
3922                 temp = I915_READ(reg);
3923                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3924                 if (pipe == 1) {
3925                         if (HAS_PCH_CPT(dev))
3926                                 temp |= PORT_TRANS_B_SEL_CPT;
3927                         else
3928                                 temp |= LVDS_PIPEB_SELECT;
3929                 } else {
3930                         if (HAS_PCH_CPT(dev))
3931                                 temp &= ~PORT_TRANS_SEL_MASK;
3932                         else
3933                                 temp &= ~LVDS_PIPEB_SELECT;
3934                 }
3935                 /* set the corresponsding LVDS_BORDER bit */
3936                 temp |= dev_priv->lvds_border_bits;
3937                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3938                  * set the DPLLs for dual-channel mode or not.
3939                  */
3940                 if (clock.p2 == 7)
3941                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3942                 else
3943                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3944
3945                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3946                  * appropriately here, but we need to look more thoroughly into how
3947                  * panels behave in the two modes.
3948                  */
3949                 /* set the dithering flag on non-PCH LVDS as needed */
3950                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3951                         if (dev_priv->lvds_dither)
3952                                 temp |= LVDS_ENABLE_DITHER;
3953                         else
3954                                 temp &= ~LVDS_ENABLE_DITHER;
3955                 }
3956                 I915_WRITE(reg, temp);
3957         }
3958
3959         /* set the dithering flag and clear for anything other than a panel. */
3960         if (HAS_PCH_SPLIT(dev)) {
3961                 pipeconf &= ~PIPECONF_DITHER_EN;
3962                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
3963                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
3964                         pipeconf |= PIPECONF_DITHER_EN;
3965                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
3966                 }
3967         }
3968
3969         if (is_dp)
3970                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3971         else if (HAS_PCH_SPLIT(dev)) {
3972                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3973                 if (pipe == 0) {
3974                         I915_WRITE(TRANSA_DATA_M1, 0);
3975                         I915_WRITE(TRANSA_DATA_N1, 0);
3976                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3977                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3978                 } else {
3979                         I915_WRITE(TRANSB_DATA_M1, 0);
3980                         I915_WRITE(TRANSB_DATA_N1, 0);
3981                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3982                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
3983                 }
3984         }
3985
3986         if (!has_edp_encoder) {
3987                 I915_WRITE(fp_reg, fp);
3988                 I915_WRITE(dpll_reg, dpll);
3989
3990                 /* Wait for the clocks to stabilize. */
3991                 POSTING_READ(dpll_reg);
3992                 udelay(150);
3993
3994                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3995                         temp = 0;
3996                         if (is_sdvo) {
3997                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3998                                 if (temp > 1)
3999                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4000                                 else
4001                                         temp = 0;
4002                         }
4003                         I915_WRITE(DPLL_MD(pipe), temp);
4004                 } else {
4005                         /* write it again -- the BIOS does, after all */
4006                         I915_WRITE(dpll_reg, dpll);
4007                 }
4008
4009                 /* Wait for the clocks to stabilize. */
4010                 POSTING_READ(dpll_reg);
4011                 udelay(150);
4012         }
4013
4014         intel_crtc->lowfreq_avail = false;
4015         if (is_lvds && has_reduced_clock && i915_powersave) {
4016                 I915_WRITE(fp_reg + 4, fp2);
4017                 intel_crtc->lowfreq_avail = true;
4018                 if (HAS_PIPE_CXSR(dev)) {
4019                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4020                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4021                 }
4022         } else {
4023                 I915_WRITE(fp_reg + 4, fp);
4024                 if (HAS_PIPE_CXSR(dev)) {
4025                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4026                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4027                 }
4028         }
4029
4030         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4031                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4032                 /* the chip adds 2 halflines automatically */
4033                 adjusted_mode->crtc_vdisplay -= 1;
4034                 adjusted_mode->crtc_vtotal -= 1;
4035                 adjusted_mode->crtc_vblank_start -= 1;
4036                 adjusted_mode->crtc_vblank_end -= 1;
4037                 adjusted_mode->crtc_vsync_end -= 1;
4038                 adjusted_mode->crtc_vsync_start -= 1;
4039         } else
4040                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4041
4042         I915_WRITE(HTOTAL(pipe),
4043                    (adjusted_mode->crtc_hdisplay - 1) |
4044                    ((adjusted_mode->crtc_htotal - 1) << 16));
4045         I915_WRITE(HBLANK(pipe),
4046                    (adjusted_mode->crtc_hblank_start - 1) |
4047                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4048         I915_WRITE(HSYNC(pipe),
4049                    (adjusted_mode->crtc_hsync_start - 1) |
4050                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4051
4052         I915_WRITE(VTOTAL(pipe),
4053                    (adjusted_mode->crtc_vdisplay - 1) |
4054                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4055         I915_WRITE(VBLANK(pipe),
4056                    (adjusted_mode->crtc_vblank_start - 1) |
4057                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4058         I915_WRITE(VSYNC(pipe),
4059                    (adjusted_mode->crtc_vsync_start - 1) |
4060                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4061
4062         /* pipesrc and dspsize control the size that is scaled from,
4063          * which should always be the user's requested size.
4064          */
4065         if (!HAS_PCH_SPLIT(dev)) {
4066                 I915_WRITE(DSPSIZE(plane),
4067                            ((mode->vdisplay - 1) << 16) |
4068                            (mode->hdisplay - 1));
4069                 I915_WRITE(DSPPOS(plane), 0);
4070         }
4071         I915_WRITE(PIPESRC(pipe),
4072                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4073
4074         if (HAS_PCH_SPLIT(dev)) {
4075                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4076                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4077                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4078                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4079
4080                 if (has_edp_encoder) {
4081                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4082                 } else {
4083                         /* enable FDI RX PLL too */
4084                         reg = FDI_RX_CTL(pipe);
4085                         temp = I915_READ(reg);
4086                         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4087
4088                         POSTING_READ(reg);
4089                         udelay(200);
4090
4091                         /* enable FDI TX PLL too */
4092                         reg = FDI_TX_CTL(pipe);
4093                         temp = I915_READ(reg);
4094                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4095
4096                         /* enable FDI RX PCDCLK */
4097                         reg = FDI_RX_CTL(pipe);
4098                         temp = I915_READ(reg);
4099                         I915_WRITE(reg, temp | FDI_PCDCLK);
4100
4101                         POSTING_READ(reg);
4102                         udelay(200);
4103                 }
4104         }
4105
4106         I915_WRITE(PIPECONF(pipe), pipeconf);
4107         POSTING_READ(PIPECONF(pipe));
4108
4109         intel_wait_for_vblank(dev, pipe);
4110
4111         if (IS_IRONLAKE(dev)) {
4112                 /* enable address swizzle for tiling buffer */
4113                 temp = I915_READ(DISP_ARB_CTL);
4114                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4115         }
4116
4117         I915_WRITE(DSPCNTR(plane), dspcntr);
4118
4119         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4120
4121         intel_update_watermarks(dev);
4122
4123         drm_vblank_post_modeset(dev, pipe);
4124
4125         return ret;
4126 }
4127
4128 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4129 void intel_crtc_load_lut(struct drm_crtc *crtc)
4130 {
4131         struct drm_device *dev = crtc->dev;
4132         struct drm_i915_private *dev_priv = dev->dev_private;
4133         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4134         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4135         int i;
4136
4137         /* The clocks have to be on to load the palette. */
4138         if (!crtc->enabled)
4139                 return;
4140
4141         /* use legacy palette for Ironlake */
4142         if (HAS_PCH_SPLIT(dev))
4143                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4144                                                    LGC_PALETTE_B;
4145
4146         for (i = 0; i < 256; i++) {
4147                 I915_WRITE(palreg + 4 * i,
4148                            (intel_crtc->lut_r[i] << 16) |
4149                            (intel_crtc->lut_g[i] << 8) |
4150                            intel_crtc->lut_b[i]);
4151         }
4152 }
4153
4154 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4155 {
4156         struct drm_device *dev = crtc->dev;
4157         struct drm_i915_private *dev_priv = dev->dev_private;
4158         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4159         bool visible = base != 0;
4160         u32 cntl;
4161
4162         if (intel_crtc->cursor_visible == visible)
4163                 return;
4164
4165         cntl = I915_READ(CURACNTR);
4166         if (visible) {
4167                 /* On these chipsets we can only modify the base whilst
4168                  * the cursor is disabled.
4169                  */
4170                 I915_WRITE(CURABASE, base);
4171
4172                 cntl &= ~(CURSOR_FORMAT_MASK);
4173                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4174                 cntl |= CURSOR_ENABLE |
4175                         CURSOR_GAMMA_ENABLE |
4176                         CURSOR_FORMAT_ARGB;
4177         } else
4178                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4179         I915_WRITE(CURACNTR, cntl);
4180
4181         intel_crtc->cursor_visible = visible;
4182 }
4183
4184 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4185 {
4186         struct drm_device *dev = crtc->dev;
4187         struct drm_i915_private *dev_priv = dev->dev_private;
4188         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4189         int pipe = intel_crtc->pipe;
4190         bool visible = base != 0;
4191
4192         if (intel_crtc->cursor_visible != visible) {
4193                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4194                 if (base) {
4195                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4196                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4197                         cntl |= pipe << 28; /* Connect to correct pipe */
4198                 } else {
4199                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4200                         cntl |= CURSOR_MODE_DISABLE;
4201                 }
4202                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4203
4204                 intel_crtc->cursor_visible = visible;
4205         }
4206         /* and commit changes on next vblank */
4207         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4208 }
4209
4210 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4211 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4212                                      bool on)
4213 {
4214         struct drm_device *dev = crtc->dev;
4215         struct drm_i915_private *dev_priv = dev->dev_private;
4216         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217         int pipe = intel_crtc->pipe;
4218         int x = intel_crtc->cursor_x;
4219         int y = intel_crtc->cursor_y;
4220         u32 base, pos;
4221         bool visible;
4222
4223         pos = 0;
4224
4225         if (on && crtc->enabled && crtc->fb) {
4226                 base = intel_crtc->cursor_addr;
4227                 if (x > (int) crtc->fb->width)
4228                         base = 0;
4229
4230                 if (y > (int) crtc->fb->height)
4231                         base = 0;
4232         } else
4233                 base = 0;
4234
4235         if (x < 0) {
4236                 if (x + intel_crtc->cursor_width < 0)
4237                         base = 0;
4238
4239                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4240                 x = -x;
4241         }
4242         pos |= x << CURSOR_X_SHIFT;
4243
4244         if (y < 0) {
4245                 if (y + intel_crtc->cursor_height < 0)
4246                         base = 0;
4247
4248                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4249                 y = -y;
4250         }
4251         pos |= y << CURSOR_Y_SHIFT;
4252
4253         visible = base != 0;
4254         if (!visible && !intel_crtc->cursor_visible)
4255                 return;
4256
4257         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4258         if (IS_845G(dev) || IS_I865G(dev))
4259                 i845_update_cursor(crtc, base);
4260         else
4261                 i9xx_update_cursor(crtc, base);
4262
4263         if (visible)
4264                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4265 }
4266
4267 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4268                                  struct drm_file *file_priv,
4269                                  uint32_t handle,
4270                                  uint32_t width, uint32_t height)
4271 {
4272         struct drm_device *dev = crtc->dev;
4273         struct drm_i915_private *dev_priv = dev->dev_private;
4274         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4275         struct drm_gem_object *bo;
4276         struct drm_i915_gem_object *obj_priv;
4277         uint32_t addr;
4278         int ret;
4279
4280         DRM_DEBUG_KMS("\n");
4281
4282         /* if we want to turn off the cursor ignore width and height */
4283         if (!handle) {
4284                 DRM_DEBUG_KMS("cursor off\n");
4285                 addr = 0;
4286                 bo = NULL;
4287                 mutex_lock(&dev->struct_mutex);
4288                 goto finish;
4289         }
4290
4291         /* Currently we only support 64x64 cursors */
4292         if (width != 64 || height != 64) {
4293                 DRM_ERROR("we currently only support 64x64 cursors\n");
4294                 return -EINVAL;
4295         }
4296
4297         bo = drm_gem_object_lookup(dev, file_priv, handle);
4298         if (!bo)
4299                 return -ENOENT;
4300
4301         obj_priv = to_intel_bo(bo);
4302
4303         if (bo->size < width * height * 4) {
4304                 DRM_ERROR("buffer is to small\n");
4305                 ret = -ENOMEM;
4306                 goto fail;
4307         }
4308
4309         /* we only need to pin inside GTT if cursor is non-phy */
4310         mutex_lock(&dev->struct_mutex);
4311         if (!dev_priv->info->cursor_needs_physical) {
4312                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4313                 if (ret) {
4314                         DRM_ERROR("failed to pin cursor bo\n");
4315                         goto fail_locked;
4316                 }
4317
4318                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4319                 if (ret) {
4320                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4321                         goto fail_unpin;
4322                 }
4323
4324                 addr = obj_priv->gtt_offset;
4325         } else {
4326                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4327                 ret = i915_gem_attach_phys_object(dev, bo,
4328                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4329                                                   align);
4330                 if (ret) {
4331                         DRM_ERROR("failed to attach phys object\n");
4332                         goto fail_locked;
4333                 }
4334                 addr = obj_priv->phys_obj->handle->busaddr;
4335         }
4336
4337         if (!IS_I9XX(dev))
4338                 I915_WRITE(CURSIZE, (height << 12) | width);
4339
4340  finish:
4341         if (intel_crtc->cursor_bo) {
4342                 if (dev_priv->info->cursor_needs_physical) {
4343                         if (intel_crtc->cursor_bo != bo)
4344                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4345                 } else
4346                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4347                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4348         }
4349
4350         mutex_unlock(&dev->struct_mutex);
4351
4352         intel_crtc->cursor_addr = addr;
4353         intel_crtc->cursor_bo = bo;
4354         intel_crtc->cursor_width = width;
4355         intel_crtc->cursor_height = height;
4356
4357         intel_crtc_update_cursor(crtc, true);
4358
4359         return 0;
4360 fail_unpin:
4361         i915_gem_object_unpin(bo);
4362 fail_locked:
4363         mutex_unlock(&dev->struct_mutex);
4364 fail:
4365         drm_gem_object_unreference_unlocked(bo);
4366         return ret;
4367 }
4368
4369 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4370 {
4371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4372
4373         intel_crtc->cursor_x = x;
4374         intel_crtc->cursor_y = y;
4375
4376         intel_crtc_update_cursor(crtc, true);
4377
4378         return 0;
4379 }
4380
4381 /** Sets the color ramps on behalf of RandR */
4382 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4383                                  u16 blue, int regno)
4384 {
4385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4386
4387         intel_crtc->lut_r[regno] = red >> 8;
4388         intel_crtc->lut_g[regno] = green >> 8;
4389         intel_crtc->lut_b[regno] = blue >> 8;
4390 }
4391
4392 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4393                              u16 *blue, int regno)
4394 {
4395         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4396
4397         *red = intel_crtc->lut_r[regno] << 8;
4398         *green = intel_crtc->lut_g[regno] << 8;
4399         *blue = intel_crtc->lut_b[regno] << 8;
4400 }
4401
4402 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4403                                  u16 *blue, uint32_t start, uint32_t size)
4404 {
4405         int end = (start + size > 256) ? 256 : start + size, i;
4406         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4407
4408         for (i = start; i < end; i++) {
4409                 intel_crtc->lut_r[i] = red[i] >> 8;
4410                 intel_crtc->lut_g[i] = green[i] >> 8;
4411                 intel_crtc->lut_b[i] = blue[i] >> 8;
4412         }
4413
4414         intel_crtc_load_lut(crtc);
4415 }
4416
4417 /**
4418  * Get a pipe with a simple mode set on it for doing load-based monitor
4419  * detection.
4420  *
4421  * It will be up to the load-detect code to adjust the pipe as appropriate for
4422  * its requirements.  The pipe will be connected to no other encoders.
4423  *
4424  * Currently this code will only succeed if there is a pipe with no encoders
4425  * configured for it.  In the future, it could choose to temporarily disable
4426  * some outputs to free up a pipe for its use.
4427  *
4428  * \return crtc, or NULL if no pipes are available.
4429  */
4430
4431 /* VESA 640x480x72Hz mode to set on the pipe */
4432 static struct drm_display_mode load_detect_mode = {
4433         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4434                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4435 };
4436
4437 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4438                                             struct drm_connector *connector,
4439                                             struct drm_display_mode *mode,
4440                                             int *dpms_mode)
4441 {
4442         struct intel_crtc *intel_crtc;
4443         struct drm_crtc *possible_crtc;
4444         struct drm_crtc *supported_crtc =NULL;
4445         struct drm_encoder *encoder = &intel_encoder->base;
4446         struct drm_crtc *crtc = NULL;
4447         struct drm_device *dev = encoder->dev;
4448         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4449         struct drm_crtc_helper_funcs *crtc_funcs;
4450         int i = -1;
4451
4452         /*
4453          * Algorithm gets a little messy:
4454          *   - if the connector already has an assigned crtc, use it (but make
4455          *     sure it's on first)
4456          *   - try to find the first unused crtc that can drive this connector,
4457          *     and use that if we find one
4458          *   - if there are no unused crtcs available, try to use the first
4459          *     one we found that supports the connector
4460          */
4461
4462         /* See if we already have a CRTC for this connector */
4463         if (encoder->crtc) {
4464                 crtc = encoder->crtc;
4465                 /* Make sure the crtc and connector are running */
4466                 intel_crtc = to_intel_crtc(crtc);
4467                 *dpms_mode = intel_crtc->dpms_mode;
4468                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4469                         crtc_funcs = crtc->helper_private;
4470                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4471                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4472                 }
4473                 return crtc;
4474         }
4475
4476         /* Find an unused one (if possible) */
4477         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4478                 i++;
4479                 if (!(encoder->possible_crtcs & (1 << i)))
4480                         continue;
4481                 if (!possible_crtc->enabled) {
4482                         crtc = possible_crtc;
4483                         break;
4484                 }
4485                 if (!supported_crtc)
4486                         supported_crtc = possible_crtc;
4487         }
4488
4489         /*
4490          * If we didn't find an unused CRTC, don't use any.
4491          */
4492         if (!crtc) {
4493                 return NULL;
4494         }
4495
4496         encoder->crtc = crtc;
4497         connector->encoder = encoder;
4498         intel_encoder->load_detect_temp = true;
4499
4500         intel_crtc = to_intel_crtc(crtc);
4501         *dpms_mode = intel_crtc->dpms_mode;
4502
4503         if (!crtc->enabled) {
4504                 if (!mode)
4505                         mode = &load_detect_mode;
4506                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4507         } else {
4508                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4509                         crtc_funcs = crtc->helper_private;
4510                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4511                 }
4512
4513                 /* Add this connector to the crtc */
4514                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4515                 encoder_funcs->commit(encoder);
4516         }
4517         /* let the connector get through one full cycle before testing */
4518         intel_wait_for_vblank(dev, intel_crtc->pipe);
4519
4520         return crtc;
4521 }
4522
4523 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4524                                     struct drm_connector *connector, int dpms_mode)
4525 {
4526         struct drm_encoder *encoder = &intel_encoder->base;
4527         struct drm_device *dev = encoder->dev;
4528         struct drm_crtc *crtc = encoder->crtc;
4529         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4530         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4531
4532         if (intel_encoder->load_detect_temp) {
4533                 encoder->crtc = NULL;
4534                 connector->encoder = NULL;
4535                 intel_encoder->load_detect_temp = false;
4536                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4537                 drm_helper_disable_unused_functions(dev);
4538         }
4539
4540         /* Switch crtc and encoder back off if necessary */
4541         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4542                 if (encoder->crtc == crtc)
4543                         encoder_funcs->dpms(encoder, dpms_mode);
4544                 crtc_funcs->dpms(crtc, dpms_mode);
4545         }
4546 }
4547
4548 /* Returns the clock of the currently programmed mode of the given pipe. */
4549 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4550 {
4551         struct drm_i915_private *dev_priv = dev->dev_private;
4552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4553         int pipe = intel_crtc->pipe;
4554         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4555         u32 fp;
4556         intel_clock_t clock;
4557
4558         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4559                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4560         else
4561                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4562
4563         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4564         if (IS_PINEVIEW(dev)) {
4565                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4566                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4567         } else {
4568                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4569                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4570         }
4571
4572         if (IS_I9XX(dev)) {
4573                 if (IS_PINEVIEW(dev))
4574                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4575                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4576                 else
4577                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4578                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4579
4580                 switch (dpll & DPLL_MODE_MASK) {
4581                 case DPLLB_MODE_DAC_SERIAL:
4582                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4583                                 5 : 10;
4584                         break;
4585                 case DPLLB_MODE_LVDS:
4586                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4587                                 7 : 14;
4588                         break;
4589                 default:
4590                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4591                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4592                         return 0;
4593                 }
4594
4595                 /* XXX: Handle the 100Mhz refclk */
4596                 intel_clock(dev, 96000, &clock);
4597         } else {
4598                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4599
4600                 if (is_lvds) {
4601                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4602                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4603                         clock.p2 = 14;
4604
4605                         if ((dpll & PLL_REF_INPUT_MASK) ==
4606                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4607                                 /* XXX: might not be 66MHz */
4608                                 intel_clock(dev, 66000, &clock);
4609                         } else
4610                                 intel_clock(dev, 48000, &clock);
4611                 } else {
4612                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4613                                 clock.p1 = 2;
4614                         else {
4615                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4616                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4617                         }
4618                         if (dpll & PLL_P2_DIVIDE_BY_4)
4619                                 clock.p2 = 4;
4620                         else
4621                                 clock.p2 = 2;
4622
4623                         intel_clock(dev, 48000, &clock);
4624                 }
4625         }
4626
4627         /* XXX: It would be nice to validate the clocks, but we can't reuse
4628          * i830PllIsValid() because it relies on the xf86_config connector
4629          * configuration being accurate, which it isn't necessarily.
4630          */
4631
4632         return clock.dot;
4633 }
4634
4635 /** Returns the currently programmed mode of the given pipe. */
4636 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4637                                              struct drm_crtc *crtc)
4638 {
4639         struct drm_i915_private *dev_priv = dev->dev_private;
4640         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4641         int pipe = intel_crtc->pipe;
4642         struct drm_display_mode *mode;
4643         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4644         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4645         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4646         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4647
4648         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4649         if (!mode)
4650                 return NULL;
4651
4652         mode->clock = intel_crtc_clock_get(dev, crtc);
4653         mode->hdisplay = (htot & 0xffff) + 1;
4654         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4655         mode->hsync_start = (hsync & 0xffff) + 1;
4656         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4657         mode->vdisplay = (vtot & 0xffff) + 1;
4658         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4659         mode->vsync_start = (vsync & 0xffff) + 1;
4660         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4661
4662         drm_mode_set_name(mode);
4663         drm_mode_set_crtcinfo(mode, 0);
4664
4665         return mode;
4666 }
4667
4668 #define GPU_IDLE_TIMEOUT 500 /* ms */
4669
4670 /* When this timer fires, we've been idle for awhile */
4671 static void intel_gpu_idle_timer(unsigned long arg)
4672 {
4673         struct drm_device *dev = (struct drm_device *)arg;
4674         drm_i915_private_t *dev_priv = dev->dev_private;
4675
4676         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4677
4678         dev_priv->busy = false;
4679
4680         queue_work(dev_priv->wq, &dev_priv->idle_work);
4681 }
4682
4683 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4684
4685 static void intel_crtc_idle_timer(unsigned long arg)
4686 {
4687         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4688         struct drm_crtc *crtc = &intel_crtc->base;
4689         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4690
4691         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4692
4693         intel_crtc->busy = false;
4694
4695         queue_work(dev_priv->wq, &dev_priv->idle_work);
4696 }
4697
4698 static void intel_increase_pllclock(struct drm_crtc *crtc)
4699 {
4700         struct drm_device *dev = crtc->dev;
4701         drm_i915_private_t *dev_priv = dev->dev_private;
4702         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4703         int pipe = intel_crtc->pipe;
4704         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4705         int dpll = I915_READ(dpll_reg);
4706
4707         if (HAS_PCH_SPLIT(dev))
4708                 return;
4709
4710         if (!dev_priv->lvds_downclock_avail)
4711                 return;
4712
4713         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4714                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4715
4716                 /* Unlock panel regs */
4717                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4718                            PANEL_UNLOCK_REGS);
4719
4720                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4721                 I915_WRITE(dpll_reg, dpll);
4722                 dpll = I915_READ(dpll_reg);
4723                 intel_wait_for_vblank(dev, pipe);
4724                 dpll = I915_READ(dpll_reg);
4725                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4726                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4727
4728                 /* ...and lock them again */
4729                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4730         }
4731
4732         /* Schedule downclock */
4733         mod_timer(&intel_crtc->idle_timer, jiffies +
4734                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4735 }
4736
4737 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4738 {
4739         struct drm_device *dev = crtc->dev;
4740         drm_i915_private_t *dev_priv = dev->dev_private;
4741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4742         int pipe = intel_crtc->pipe;
4743         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4744         int dpll = I915_READ(dpll_reg);
4745
4746         if (HAS_PCH_SPLIT(dev))
4747                 return;
4748
4749         if (!dev_priv->lvds_downclock_avail)
4750                 return;
4751
4752         /*
4753          * Since this is called by a timer, we should never get here in
4754          * the manual case.
4755          */
4756         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4757                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4758
4759                 /* Unlock panel regs */
4760                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4761                            PANEL_UNLOCK_REGS);
4762
4763                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4764                 I915_WRITE(dpll_reg, dpll);
4765                 dpll = I915_READ(dpll_reg);
4766                 intel_wait_for_vblank(dev, pipe);
4767                 dpll = I915_READ(dpll_reg);
4768                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4769                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4770
4771                 /* ...and lock them again */
4772                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4773         }
4774
4775 }
4776
4777 /**
4778  * intel_idle_update - adjust clocks for idleness
4779  * @work: work struct
4780  *
4781  * Either the GPU or display (or both) went idle.  Check the busy status
4782  * here and adjust the CRTC and GPU clocks as necessary.
4783  */
4784 static void intel_idle_update(struct work_struct *work)
4785 {
4786         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4787                                                     idle_work);
4788         struct drm_device *dev = dev_priv->dev;
4789         struct drm_crtc *crtc;
4790         struct intel_crtc *intel_crtc;
4791         int enabled = 0;
4792
4793         if (!i915_powersave)
4794                 return;
4795
4796         mutex_lock(&dev->struct_mutex);
4797
4798         i915_update_gfx_val(dev_priv);
4799
4800         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4801                 /* Skip inactive CRTCs */
4802                 if (!crtc->fb)
4803                         continue;
4804
4805                 enabled++;
4806                 intel_crtc = to_intel_crtc(crtc);
4807                 if (!intel_crtc->busy)
4808                         intel_decrease_pllclock(crtc);
4809         }
4810
4811         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4812                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4813                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4814         }
4815
4816         mutex_unlock(&dev->struct_mutex);
4817 }
4818
4819 /**
4820  * intel_mark_busy - mark the GPU and possibly the display busy
4821  * @dev: drm device
4822  * @obj: object we're operating on
4823  *
4824  * Callers can use this function to indicate that the GPU is busy processing
4825  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4826  * buffer), we'll also mark the display as busy, so we know to increase its
4827  * clock frequency.
4828  */
4829 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4830 {
4831         drm_i915_private_t *dev_priv = dev->dev_private;
4832         struct drm_crtc *crtc = NULL;
4833         struct intel_framebuffer *intel_fb;
4834         struct intel_crtc *intel_crtc;
4835
4836         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4837                 return;
4838
4839         if (!dev_priv->busy) {
4840                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4841                         u32 fw_blc_self;
4842
4843                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4844                         fw_blc_self = I915_READ(FW_BLC_SELF);
4845                         fw_blc_self &= ~FW_BLC_SELF_EN;
4846                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4847                 }
4848                 dev_priv->busy = true;
4849         } else
4850                 mod_timer(&dev_priv->idle_timer, jiffies +
4851                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4852
4853         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4854                 if (!crtc->fb)
4855                         continue;
4856
4857                 intel_crtc = to_intel_crtc(crtc);
4858                 intel_fb = to_intel_framebuffer(crtc->fb);
4859                 if (intel_fb->obj == obj) {
4860                         if (!intel_crtc->busy) {
4861                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4862                                         u32 fw_blc_self;
4863
4864                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4865                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4866                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4867                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4868                                 }
4869                                 /* Non-busy -> busy, upclock */
4870                                 intel_increase_pllclock(crtc);
4871                                 intel_crtc->busy = true;
4872                         } else {
4873                                 /* Busy -> busy, put off timer */
4874                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4875                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4876                         }
4877                 }
4878         }
4879 }
4880
4881 static void intel_crtc_destroy(struct drm_crtc *crtc)
4882 {
4883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4884         struct drm_device *dev = crtc->dev;
4885         struct intel_unpin_work *work;
4886         unsigned long flags;
4887
4888         spin_lock_irqsave(&dev->event_lock, flags);
4889         work = intel_crtc->unpin_work;
4890         intel_crtc->unpin_work = NULL;
4891         spin_unlock_irqrestore(&dev->event_lock, flags);
4892
4893         if (work) {
4894                 cancel_work_sync(&work->work);
4895                 kfree(work);
4896         }
4897
4898         drm_crtc_cleanup(crtc);
4899
4900         kfree(intel_crtc);
4901 }
4902
4903 static void intel_unpin_work_fn(struct work_struct *__work)
4904 {
4905         struct intel_unpin_work *work =
4906                 container_of(__work, struct intel_unpin_work, work);
4907
4908         mutex_lock(&work->dev->struct_mutex);
4909         i915_gem_object_unpin(work->old_fb_obj);
4910         drm_gem_object_unreference(work->pending_flip_obj);
4911         drm_gem_object_unreference(work->old_fb_obj);
4912         mutex_unlock(&work->dev->struct_mutex);
4913         kfree(work);
4914 }
4915
4916 static void do_intel_finish_page_flip(struct drm_device *dev,
4917                                       struct drm_crtc *crtc)
4918 {
4919         drm_i915_private_t *dev_priv = dev->dev_private;
4920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921         struct intel_unpin_work *work;
4922         struct drm_i915_gem_object *obj_priv;
4923         struct drm_pending_vblank_event *e;
4924         struct timeval now;
4925         unsigned long flags;
4926
4927         /* Ignore early vblank irqs */
4928         if (intel_crtc == NULL)
4929                 return;
4930
4931         spin_lock_irqsave(&dev->event_lock, flags);
4932         work = intel_crtc->unpin_work;
4933         if (work == NULL || !work->pending) {
4934                 spin_unlock_irqrestore(&dev->event_lock, flags);
4935                 return;
4936         }
4937
4938         intel_crtc->unpin_work = NULL;
4939         drm_vblank_put(dev, intel_crtc->pipe);
4940
4941         if (work->event) {
4942                 e = work->event;
4943                 do_gettimeofday(&now);
4944                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4945                 e->event.tv_sec = now.tv_sec;
4946                 e->event.tv_usec = now.tv_usec;
4947                 list_add_tail(&e->base.link,
4948                               &e->base.file_priv->event_list);
4949                 wake_up_interruptible(&e->base.file_priv->event_wait);
4950         }
4951
4952         spin_unlock_irqrestore(&dev->event_lock, flags);
4953
4954         obj_priv = to_intel_bo(work->pending_flip_obj);
4955
4956         /* Initial scanout buffer will have a 0 pending flip count */
4957         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4958             atomic_dec_and_test(&obj_priv->pending_flip))
4959                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4960         schedule_work(&work->work);
4961
4962         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4963 }
4964
4965 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4966 {
4967         drm_i915_private_t *dev_priv = dev->dev_private;
4968         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4969
4970         do_intel_finish_page_flip(dev, crtc);
4971 }
4972
4973 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4974 {
4975         drm_i915_private_t *dev_priv = dev->dev_private;
4976         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4977
4978         do_intel_finish_page_flip(dev, crtc);
4979 }
4980
4981 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4982 {
4983         drm_i915_private_t *dev_priv = dev->dev_private;
4984         struct intel_crtc *intel_crtc =
4985                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4986         unsigned long flags;
4987
4988         spin_lock_irqsave(&dev->event_lock, flags);
4989         if (intel_crtc->unpin_work) {
4990                 if ((++intel_crtc->unpin_work->pending) > 1)
4991                         DRM_ERROR("Prepared flip multiple times\n");
4992         } else {
4993                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4994         }
4995         spin_unlock_irqrestore(&dev->event_lock, flags);
4996 }
4997
4998 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4999                                 struct drm_framebuffer *fb,
5000                                 struct drm_pending_vblank_event *event)
5001 {
5002         struct drm_device *dev = crtc->dev;
5003         struct drm_i915_private *dev_priv = dev->dev_private;
5004         struct intel_framebuffer *intel_fb;
5005         struct drm_i915_gem_object *obj_priv;
5006         struct drm_gem_object *obj;
5007         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5008         struct intel_unpin_work *work;
5009         unsigned long flags, offset;
5010         int pipe = intel_crtc->pipe;
5011         u32 was_dirty, pf, pipesrc;
5012         int ret;
5013
5014         work = kzalloc(sizeof *work, GFP_KERNEL);
5015         if (work == NULL)
5016                 return -ENOMEM;
5017
5018         work->event = event;
5019         work->dev = crtc->dev;
5020         intel_fb = to_intel_framebuffer(crtc->fb);
5021         work->old_fb_obj = intel_fb->obj;
5022         INIT_WORK(&work->work, intel_unpin_work_fn);
5023
5024         /* We borrow the event spin lock for protecting unpin_work */
5025         spin_lock_irqsave(&dev->event_lock, flags);
5026         if (intel_crtc->unpin_work) {
5027                 spin_unlock_irqrestore(&dev->event_lock, flags);
5028                 kfree(work);
5029
5030                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5031                 return -EBUSY;
5032         }
5033         intel_crtc->unpin_work = work;
5034         spin_unlock_irqrestore(&dev->event_lock, flags);
5035
5036         intel_fb = to_intel_framebuffer(fb);
5037         obj = intel_fb->obj;
5038
5039         mutex_lock(&dev->struct_mutex);
5040         was_dirty = obj->write_domain & I915_GEM_GPU_DOMAINS;
5041         ret = intel_pin_and_fence_fb_obj(dev, obj, true);
5042         if (ret)
5043                 goto cleanup_work;
5044
5045         /* Reference the objects for the scheduled work. */
5046         drm_gem_object_reference(work->old_fb_obj);
5047         drm_gem_object_reference(obj);
5048
5049         crtc->fb = fb;
5050
5051         ret = drm_vblank_get(dev, intel_crtc->pipe);
5052         if (ret)
5053                 goto cleanup_objs;
5054
5055         obj_priv = to_intel_bo(obj);
5056         atomic_inc(&obj_priv->pending_flip);
5057         work->pending_flip_obj = obj;
5058
5059         if (was_dirty || IS_GEN3(dev) || IS_GEN2(dev)) {
5060                 BEGIN_LP_RING(2);
5061                 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5062                         u32 flip_mask;
5063
5064                         /* Can't queue multiple flips, so wait for the previous
5065                          * one to finish before executing the next.
5066                          */
5067
5068                         if (intel_crtc->plane)
5069                                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5070                         else
5071                                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5072
5073                         OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5074                 } else
5075                         OUT_RING(MI_NOOP);
5076                 OUT_RING(MI_FLUSH);
5077                 ADVANCE_LP_RING();
5078         }
5079
5080         work->enable_stall_check = true;
5081
5082         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5083         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5084
5085         BEGIN_LP_RING(4);
5086         switch(INTEL_INFO(dev)->gen) {
5087         case 2:
5088                 OUT_RING(MI_DISPLAY_FLIP |
5089                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5090                 OUT_RING(fb->pitch);
5091                 OUT_RING(obj_priv->gtt_offset + offset);
5092                 OUT_RING(MI_NOOP);
5093                 break;
5094
5095         case 3:
5096                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5097                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5098                 OUT_RING(fb->pitch);
5099                 OUT_RING(obj_priv->gtt_offset + offset);
5100                 OUT_RING(MI_NOOP);
5101                 break;
5102
5103         case 4:
5104         case 5:
5105                 /* i965+ uses the linear or tiled offsets from the
5106                  * Display Registers (which do not change across a page-flip)
5107                  * so we need only reprogram the base address.
5108                  */
5109                 OUT_RING(MI_DISPLAY_FLIP |
5110                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5111                 OUT_RING(fb->pitch);
5112                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5113
5114                 /* XXX Enabling the panel-fitter across page-flip is so far
5115                  * untested on non-native modes, so ignore it for now.
5116                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5117                  */
5118                 pf = 0;
5119                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5120                 OUT_RING(pf | pipesrc);
5121                 break;
5122
5123         case 6:
5124                 OUT_RING(MI_DISPLAY_FLIP |
5125                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5126                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5127                 OUT_RING(obj_priv->gtt_offset);
5128
5129                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5130                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5131                 OUT_RING(pf | pipesrc);
5132                 break;
5133         }
5134         ADVANCE_LP_RING();
5135
5136         mutex_unlock(&dev->struct_mutex);
5137
5138         trace_i915_flip_request(intel_crtc->plane, obj);
5139
5140         return 0;
5141
5142 cleanup_objs:
5143         drm_gem_object_unreference(work->old_fb_obj);
5144         drm_gem_object_unreference(obj);
5145 cleanup_work:
5146         mutex_unlock(&dev->struct_mutex);
5147
5148         spin_lock_irqsave(&dev->event_lock, flags);
5149         intel_crtc->unpin_work = NULL;
5150         spin_unlock_irqrestore(&dev->event_lock, flags);
5151
5152         kfree(work);
5153
5154         return ret;
5155 }
5156
5157 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5158         .dpms = intel_crtc_dpms,
5159         .mode_fixup = intel_crtc_mode_fixup,
5160         .mode_set = intel_crtc_mode_set,
5161         .mode_set_base = intel_pipe_set_base,
5162         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5163         .load_lut = intel_crtc_load_lut,
5164 };
5165
5166 static const struct drm_crtc_funcs intel_crtc_funcs = {
5167         .cursor_set = intel_crtc_cursor_set,
5168         .cursor_move = intel_crtc_cursor_move,
5169         .gamma_set = intel_crtc_gamma_set,
5170         .set_config = drm_crtc_helper_set_config,
5171         .destroy = intel_crtc_destroy,
5172         .page_flip = intel_crtc_page_flip,
5173 };
5174
5175
5176 static void intel_crtc_init(struct drm_device *dev, int pipe)
5177 {
5178         drm_i915_private_t *dev_priv = dev->dev_private;
5179         struct intel_crtc *intel_crtc;
5180         int i;
5181
5182         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5183         if (intel_crtc == NULL)
5184                 return;
5185
5186         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5187
5188         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5189         for (i = 0; i < 256; i++) {
5190                 intel_crtc->lut_r[i] = i;
5191                 intel_crtc->lut_g[i] = i;
5192                 intel_crtc->lut_b[i] = i;
5193         }
5194
5195         /* Swap pipes & planes for FBC on pre-965 */
5196         intel_crtc->pipe = pipe;
5197         intel_crtc->plane = pipe;
5198         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5199                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5200                 intel_crtc->plane = !pipe;
5201         }
5202
5203         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5204                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5205         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5206         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5207
5208         intel_crtc->cursor_addr = 0;
5209         intel_crtc->dpms_mode = -1;
5210         intel_crtc->active = true; /* force the pipe off on setup_init_config */
5211
5212         if (HAS_PCH_SPLIT(dev)) {
5213                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5214                 intel_helper_funcs.commit = ironlake_crtc_commit;
5215         } else {
5216                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5217                 intel_helper_funcs.commit = i9xx_crtc_commit;
5218         }
5219
5220         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5221
5222         intel_crtc->busy = false;
5223
5224         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5225                     (unsigned long)intel_crtc);
5226 }
5227
5228 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5229                                 struct drm_file *file_priv)
5230 {
5231         drm_i915_private_t *dev_priv = dev->dev_private;
5232         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5233         struct drm_mode_object *drmmode_obj;
5234         struct intel_crtc *crtc;
5235
5236         if (!dev_priv) {
5237                 DRM_ERROR("called with no initialization\n");
5238                 return -EINVAL;
5239         }
5240
5241         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5242                         DRM_MODE_OBJECT_CRTC);
5243
5244         if (!drmmode_obj) {
5245                 DRM_ERROR("no such CRTC id\n");
5246                 return -EINVAL;
5247         }
5248
5249         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5250         pipe_from_crtc_id->pipe = crtc->pipe;
5251
5252         return 0;
5253 }
5254
5255 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5256 {
5257         struct intel_encoder *encoder;
5258         int index_mask = 0;
5259         int entry = 0;
5260
5261         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5262                 if (type_mask & encoder->clone_mask)
5263                         index_mask |= (1 << entry);
5264                 entry++;
5265         }
5266
5267         return index_mask;
5268 }
5269
5270 static void intel_setup_outputs(struct drm_device *dev)
5271 {
5272         struct drm_i915_private *dev_priv = dev->dev_private;
5273         struct intel_encoder *encoder;
5274         bool dpd_is_edp = false;
5275
5276         if (IS_MOBILE(dev) && !IS_I830(dev))
5277                 intel_lvds_init(dev);
5278
5279         if (HAS_PCH_SPLIT(dev)) {
5280                 dpd_is_edp = intel_dpd_is_edp(dev);
5281
5282                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5283                         intel_dp_init(dev, DP_A);
5284
5285                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5286                         intel_dp_init(dev, PCH_DP_D);
5287         }
5288
5289         intel_crt_init(dev);
5290
5291         if (HAS_PCH_SPLIT(dev)) {
5292                 int found;
5293
5294                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5295                         /* PCH SDVOB multiplex with HDMIB */
5296                         found = intel_sdvo_init(dev, PCH_SDVOB);
5297                         if (!found)
5298                                 intel_hdmi_init(dev, HDMIB);
5299                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5300                                 intel_dp_init(dev, PCH_DP_B);
5301                 }
5302
5303                 if (I915_READ(HDMIC) & PORT_DETECTED)
5304                         intel_hdmi_init(dev, HDMIC);
5305
5306                 if (I915_READ(HDMID) & PORT_DETECTED)
5307                         intel_hdmi_init(dev, HDMID);
5308
5309                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5310                         intel_dp_init(dev, PCH_DP_C);
5311
5312                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5313                         intel_dp_init(dev, PCH_DP_D);
5314
5315         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5316                 bool found = false;
5317
5318                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5319                         DRM_DEBUG_KMS("probing SDVOB\n");
5320                         found = intel_sdvo_init(dev, SDVOB);
5321                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5322                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5323                                 intel_hdmi_init(dev, SDVOB);
5324                         }
5325
5326                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5327                                 DRM_DEBUG_KMS("probing DP_B\n");
5328                                 intel_dp_init(dev, DP_B);
5329                         }
5330                 }
5331
5332                 /* Before G4X SDVOC doesn't have its own detect register */
5333
5334                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5335                         DRM_DEBUG_KMS("probing SDVOC\n");
5336                         found = intel_sdvo_init(dev, SDVOC);
5337                 }
5338
5339                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5340
5341                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5342                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5343                                 intel_hdmi_init(dev, SDVOC);
5344                         }
5345                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5346                                 DRM_DEBUG_KMS("probing DP_C\n");
5347                                 intel_dp_init(dev, DP_C);
5348                         }
5349                 }
5350
5351                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5352                     (I915_READ(DP_D) & DP_DETECTED)) {
5353                         DRM_DEBUG_KMS("probing DP_D\n");
5354                         intel_dp_init(dev, DP_D);
5355                 }
5356         } else if (IS_GEN2(dev))
5357                 intel_dvo_init(dev);
5358
5359         if (SUPPORTS_TV(dev))
5360                 intel_tv_init(dev);
5361
5362         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5363                 encoder->base.possible_crtcs = encoder->crtc_mask;
5364                 encoder->base.possible_clones =
5365                         intel_encoder_clones(dev, encoder->clone_mask);
5366         }
5367 }
5368
5369 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5370 {
5371         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5372
5373         drm_framebuffer_cleanup(fb);
5374         drm_gem_object_unreference_unlocked(intel_fb->obj);
5375
5376         kfree(intel_fb);
5377 }
5378
5379 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5380                                                 struct drm_file *file_priv,
5381                                                 unsigned int *handle)
5382 {
5383         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5384         struct drm_gem_object *object = intel_fb->obj;
5385
5386         return drm_gem_handle_create(file_priv, object, handle);
5387 }
5388
5389 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5390         .destroy = intel_user_framebuffer_destroy,
5391         .create_handle = intel_user_framebuffer_create_handle,
5392 };
5393
5394 int intel_framebuffer_init(struct drm_device *dev,
5395                            struct intel_framebuffer *intel_fb,
5396                            struct drm_mode_fb_cmd *mode_cmd,
5397                            struct drm_gem_object *obj)
5398 {
5399         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5400         int ret;
5401
5402         if (obj_priv->tiling_mode == I915_TILING_Y)
5403                 return -EINVAL;
5404
5405         if (mode_cmd->pitch & 63)
5406                 return -EINVAL;
5407
5408         switch (mode_cmd->bpp) {
5409         case 8:
5410         case 16:
5411         case 24:
5412         case 32:
5413                 break;
5414         default:
5415                 return -EINVAL;
5416         }
5417
5418         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5419         if (ret) {
5420                 DRM_ERROR("framebuffer init failed %d\n", ret);
5421                 return ret;
5422         }
5423
5424         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5425         intel_fb->obj = obj;
5426         return 0;
5427 }
5428
5429 static struct drm_framebuffer *
5430 intel_user_framebuffer_create(struct drm_device *dev,
5431                               struct drm_file *filp,
5432                               struct drm_mode_fb_cmd *mode_cmd)
5433 {
5434         struct drm_gem_object *obj;
5435         struct intel_framebuffer *intel_fb;
5436         int ret;
5437
5438         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5439         if (!obj)
5440                 return ERR_PTR(-ENOENT);
5441
5442         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5443         if (!intel_fb)
5444                 return ERR_PTR(-ENOMEM);
5445
5446         ret = intel_framebuffer_init(dev, intel_fb,
5447                                      mode_cmd, obj);
5448         if (ret) {
5449                 drm_gem_object_unreference_unlocked(obj);
5450                 kfree(intel_fb);
5451                 return ERR_PTR(ret);
5452         }
5453
5454         return &intel_fb->base;
5455 }
5456
5457 static const struct drm_mode_config_funcs intel_mode_funcs = {
5458         .fb_create = intel_user_framebuffer_create,
5459         .output_poll_changed = intel_fb_output_poll_changed,
5460 };
5461
5462 static struct drm_gem_object *
5463 intel_alloc_context_page(struct drm_device *dev)
5464 {
5465         struct drm_gem_object *ctx;
5466         int ret;
5467
5468         ctx = i915_gem_alloc_object(dev, 4096);
5469         if (!ctx) {
5470                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5471                 return NULL;
5472         }
5473
5474         mutex_lock(&dev->struct_mutex);
5475         ret = i915_gem_object_pin(ctx, 4096);
5476         if (ret) {
5477                 DRM_ERROR("failed to pin power context: %d\n", ret);
5478                 goto err_unref;
5479         }
5480
5481         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5482         if (ret) {
5483                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5484                 goto err_unpin;
5485         }
5486         mutex_unlock(&dev->struct_mutex);
5487
5488         return ctx;
5489
5490 err_unpin:
5491         i915_gem_object_unpin(ctx);
5492 err_unref:
5493         drm_gem_object_unreference(ctx);
5494         mutex_unlock(&dev->struct_mutex);
5495         return NULL;
5496 }
5497
5498 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5499 {
5500         struct drm_i915_private *dev_priv = dev->dev_private;
5501         u16 rgvswctl;
5502
5503         rgvswctl = I915_READ16(MEMSWCTL);
5504         if (rgvswctl & MEMCTL_CMD_STS) {
5505                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5506                 return false; /* still busy with another command */
5507         }
5508
5509         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5510                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5511         I915_WRITE16(MEMSWCTL, rgvswctl);
5512         POSTING_READ16(MEMSWCTL);
5513
5514         rgvswctl |= MEMCTL_CMD_STS;
5515         I915_WRITE16(MEMSWCTL, rgvswctl);
5516
5517         return true;
5518 }
5519
5520 void ironlake_enable_drps(struct drm_device *dev)
5521 {
5522         struct drm_i915_private *dev_priv = dev->dev_private;
5523         u32 rgvmodectl = I915_READ(MEMMODECTL);
5524         u8 fmax, fmin, fstart, vstart;
5525
5526         /* Enable temp reporting */
5527         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5528         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5529
5530         /* 100ms RC evaluation intervals */
5531         I915_WRITE(RCUPEI, 100000);
5532         I915_WRITE(RCDNEI, 100000);
5533
5534         /* Set max/min thresholds to 90ms and 80ms respectively */
5535         I915_WRITE(RCBMAXAVG, 90000);
5536         I915_WRITE(RCBMINAVG, 80000);
5537
5538         I915_WRITE(MEMIHYST, 1);
5539
5540         /* Set up min, max, and cur for interrupt handling */
5541         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5542         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5543         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5544                 MEMMODE_FSTART_SHIFT;
5545         fstart = fmax;
5546
5547         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5548                 PXVFREQ_PX_SHIFT;
5549
5550         dev_priv->fmax = fstart; /* IPS callback will increase this */
5551         dev_priv->fstart = fstart;
5552
5553         dev_priv->max_delay = fmax;
5554         dev_priv->min_delay = fmin;
5555         dev_priv->cur_delay = fstart;
5556
5557         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5558                          fstart);
5559
5560         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5561
5562         /*
5563          * Interrupts will be enabled in ironlake_irq_postinstall
5564          */
5565
5566         I915_WRITE(VIDSTART, vstart);
5567         POSTING_READ(VIDSTART);
5568
5569         rgvmodectl |= MEMMODE_SWMODE_EN;
5570         I915_WRITE(MEMMODECTL, rgvmodectl);
5571
5572         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5573                 DRM_ERROR("stuck trying to change perf mode\n");
5574         msleep(1);
5575
5576         ironlake_set_drps(dev, fstart);
5577
5578         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5579                 I915_READ(0x112e0);
5580         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5581         dev_priv->last_count2 = I915_READ(0x112f4);
5582         getrawmonotonic(&dev_priv->last_time2);
5583 }
5584
5585 void ironlake_disable_drps(struct drm_device *dev)
5586 {
5587         struct drm_i915_private *dev_priv = dev->dev_private;
5588         u16 rgvswctl = I915_READ16(MEMSWCTL);
5589
5590         /* Ack interrupts, disable EFC interrupt */
5591         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5592         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5593         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5594         I915_WRITE(DEIIR, DE_PCU_EVENT);
5595         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5596
5597         /* Go back to the starting frequency */
5598         ironlake_set_drps(dev, dev_priv->fstart);
5599         msleep(1);
5600         rgvswctl |= MEMCTL_CMD_STS;
5601         I915_WRITE(MEMSWCTL, rgvswctl);
5602         msleep(1);
5603
5604 }
5605
5606 static unsigned long intel_pxfreq(u32 vidfreq)
5607 {
5608         unsigned long freq;
5609         int div = (vidfreq & 0x3f0000) >> 16;
5610         int post = (vidfreq & 0x3000) >> 12;
5611         int pre = (vidfreq & 0x7);
5612
5613         if (!pre)
5614                 return 0;
5615
5616         freq = ((div * 133333) / ((1<<post) * pre));
5617
5618         return freq;
5619 }
5620
5621 void intel_init_emon(struct drm_device *dev)
5622 {
5623         struct drm_i915_private *dev_priv = dev->dev_private;
5624         u32 lcfuse;
5625         u8 pxw[16];
5626         int i;
5627
5628         /* Disable to program */
5629         I915_WRITE(ECR, 0);
5630         POSTING_READ(ECR);
5631
5632         /* Program energy weights for various events */
5633         I915_WRITE(SDEW, 0x15040d00);
5634         I915_WRITE(CSIEW0, 0x007f0000);
5635         I915_WRITE(CSIEW1, 0x1e220004);
5636         I915_WRITE(CSIEW2, 0x04000004);
5637
5638         for (i = 0; i < 5; i++)
5639                 I915_WRITE(PEW + (i * 4), 0);
5640         for (i = 0; i < 3; i++)
5641                 I915_WRITE(DEW + (i * 4), 0);
5642
5643         /* Program P-state weights to account for frequency power adjustment */
5644         for (i = 0; i < 16; i++) {
5645                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5646                 unsigned long freq = intel_pxfreq(pxvidfreq);
5647                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5648                         PXVFREQ_PX_SHIFT;
5649                 unsigned long val;
5650
5651                 val = vid * vid;
5652                 val *= (freq / 1000);
5653                 val *= 255;
5654                 val /= (127*127*900);
5655                 if (val > 0xff)
5656                         DRM_ERROR("bad pxval: %ld\n", val);
5657                 pxw[i] = val;
5658         }
5659         /* Render standby states get 0 weight */
5660         pxw[14] = 0;
5661         pxw[15] = 0;
5662
5663         for (i = 0; i < 4; i++) {
5664                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5665                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5666                 I915_WRITE(PXW + (i * 4), val);
5667         }
5668
5669         /* Adjust magic regs to magic values (more experimental results) */
5670         I915_WRITE(OGW0, 0);
5671         I915_WRITE(OGW1, 0);
5672         I915_WRITE(EG0, 0x00007f00);
5673         I915_WRITE(EG1, 0x0000000e);
5674         I915_WRITE(EG2, 0x000e0000);
5675         I915_WRITE(EG3, 0x68000300);
5676         I915_WRITE(EG4, 0x42000000);
5677         I915_WRITE(EG5, 0x00140031);
5678         I915_WRITE(EG6, 0);
5679         I915_WRITE(EG7, 0);
5680
5681         for (i = 0; i < 8; i++)
5682                 I915_WRITE(PXWL + (i * 4), 0);
5683
5684         /* Enable PMON + select events */
5685         I915_WRITE(ECR, 0x80000019);
5686
5687         lcfuse = I915_READ(LCFUSE02);
5688
5689         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5690 }
5691
5692 void intel_init_clock_gating(struct drm_device *dev)
5693 {
5694         struct drm_i915_private *dev_priv = dev->dev_private;
5695
5696         /*
5697          * Disable clock gating reported to work incorrectly according to the
5698          * specs, but enable as much else as we can.
5699          */
5700         if (HAS_PCH_SPLIT(dev)) {
5701                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5702
5703                 if (IS_IRONLAKE(dev)) {
5704                         /* Required for FBC */
5705                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5706                         /* Required for CxSR */
5707                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5708
5709                         I915_WRITE(PCH_3DCGDIS0,
5710                                    MARIUNIT_CLOCK_GATE_DISABLE |
5711                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5712                 }
5713
5714                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5715
5716                 /*
5717                  * According to the spec the following bits should be set in
5718                  * order to enable memory self-refresh
5719                  * The bit 22/21 of 0x42004
5720                  * The bit 5 of 0x42020
5721                  * The bit 15 of 0x45000
5722                  */
5723                 if (IS_IRONLAKE(dev)) {
5724                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5725                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5726                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5727                         I915_WRITE(ILK_DSPCLK_GATE,
5728                                         (I915_READ(ILK_DSPCLK_GATE) |
5729                                                 ILK_DPARB_CLK_GATE));
5730                         I915_WRITE(DISP_ARB_CTL,
5731                                         (I915_READ(DISP_ARB_CTL) |
5732                                                 DISP_FBC_WM_DIS));
5733                 I915_WRITE(WM3_LP_ILK, 0);
5734                 I915_WRITE(WM2_LP_ILK, 0);
5735                 I915_WRITE(WM1_LP_ILK, 0);
5736                 }
5737                 /*
5738                  * Based on the document from hardware guys the following bits
5739                  * should be set unconditionally in order to enable FBC.
5740                  * The bit 22 of 0x42000
5741                  * The bit 22 of 0x42004
5742                  * The bit 7,8,9 of 0x42020.
5743                  */
5744                 if (IS_IRONLAKE_M(dev)) {
5745                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5746                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5747                                    ILK_FBCQ_DIS);
5748                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5749                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5750                                    ILK_DPARB_GATE);
5751                         I915_WRITE(ILK_DSPCLK_GATE,
5752                                    I915_READ(ILK_DSPCLK_GATE) |
5753                                    ILK_DPFC_DIS1 |
5754                                    ILK_DPFC_DIS2 |
5755                                    ILK_CLK_FBC);
5756                 }
5757                 return;
5758         } else if (IS_G4X(dev)) {
5759                 uint32_t dspclk_gate;
5760                 I915_WRITE(RENCLK_GATE_D1, 0);
5761                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5762                        GS_UNIT_CLOCK_GATE_DISABLE |
5763                        CL_UNIT_CLOCK_GATE_DISABLE);
5764                 I915_WRITE(RAMCLK_GATE_D, 0);
5765                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5766                         OVRUNIT_CLOCK_GATE_DISABLE |
5767                         OVCUNIT_CLOCK_GATE_DISABLE;
5768                 if (IS_GM45(dev))
5769                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5770                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5771         } else if (IS_I965GM(dev)) {
5772                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5773                 I915_WRITE(RENCLK_GATE_D2, 0);
5774                 I915_WRITE(DSPCLK_GATE_D, 0);
5775                 I915_WRITE(RAMCLK_GATE_D, 0);
5776                 I915_WRITE16(DEUC, 0);
5777         } else if (IS_I965G(dev)) {
5778                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5779                        I965_RCC_CLOCK_GATE_DISABLE |
5780                        I965_RCPB_CLOCK_GATE_DISABLE |
5781                        I965_ISC_CLOCK_GATE_DISABLE |
5782                        I965_FBC_CLOCK_GATE_DISABLE);
5783                 I915_WRITE(RENCLK_GATE_D2, 0);
5784         } else if (IS_I9XX(dev)) {
5785                 u32 dstate = I915_READ(D_STATE);
5786
5787                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5788                         DSTATE_DOT_CLOCK_GATING;
5789                 I915_WRITE(D_STATE, dstate);
5790         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5791                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5792         } else if (IS_I830(dev)) {
5793                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5794         }
5795
5796         /*
5797          * GPU can automatically power down the render unit if given a page
5798          * to save state.
5799          */
5800         if (IS_IRONLAKE_M(dev)) {
5801                 if (dev_priv->renderctx == NULL)
5802                         dev_priv->renderctx = intel_alloc_context_page(dev);
5803                 if (dev_priv->renderctx) {
5804                         struct drm_i915_gem_object *obj_priv;
5805                         obj_priv = to_intel_bo(dev_priv->renderctx);
5806                         if (obj_priv) {
5807                                 BEGIN_LP_RING(4);
5808                                 OUT_RING(MI_SET_CONTEXT);
5809                                 OUT_RING(obj_priv->gtt_offset |
5810                                                 MI_MM_SPACE_GTT |
5811                                                 MI_SAVE_EXT_STATE_EN |
5812                                                 MI_RESTORE_EXT_STATE_EN |
5813                                                 MI_RESTORE_INHIBIT);
5814                                 OUT_RING(MI_NOOP);
5815                                 OUT_RING(MI_FLUSH);
5816                                 ADVANCE_LP_RING();
5817                         }
5818                 } else
5819                         DRM_DEBUG_KMS("Failed to allocate render context."
5820                                        "Disable RC6\n");
5821         }
5822
5823         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5824                 struct drm_i915_gem_object *obj_priv = NULL;
5825
5826                 if (dev_priv->pwrctx) {
5827                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5828                 } else {
5829                         struct drm_gem_object *pwrctx;
5830
5831                         pwrctx = intel_alloc_context_page(dev);
5832                         if (pwrctx) {
5833                                 dev_priv->pwrctx = pwrctx;
5834                                 obj_priv = to_intel_bo(pwrctx);
5835                         }
5836                 }
5837
5838                 if (obj_priv) {
5839                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5840                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5841                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5842                 }
5843         }
5844 }
5845
5846 /* Set up chip specific display functions */
5847 static void intel_init_display(struct drm_device *dev)
5848 {
5849         struct drm_i915_private *dev_priv = dev->dev_private;
5850
5851         /* We always want a DPMS function */
5852         if (HAS_PCH_SPLIT(dev))
5853                 dev_priv->display.dpms = ironlake_crtc_dpms;
5854         else
5855                 dev_priv->display.dpms = i9xx_crtc_dpms;
5856
5857         if (I915_HAS_FBC(dev)) {
5858                 if (IS_IRONLAKE_M(dev)) {
5859                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5860                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5861                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5862                 } else if (IS_GM45(dev)) {
5863                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5864                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5865                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5866                 } else if (IS_I965GM(dev)) {
5867                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5868                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5869                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5870                 }
5871                 /* 855GM needs testing */
5872         }
5873
5874         /* Returns the core display clock speed */
5875         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5876                 dev_priv->display.get_display_clock_speed =
5877                         i945_get_display_clock_speed;
5878         else if (IS_I915G(dev))
5879                 dev_priv->display.get_display_clock_speed =
5880                         i915_get_display_clock_speed;
5881         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5882                 dev_priv->display.get_display_clock_speed =
5883                         i9xx_misc_get_display_clock_speed;
5884         else if (IS_I915GM(dev))
5885                 dev_priv->display.get_display_clock_speed =
5886                         i915gm_get_display_clock_speed;
5887         else if (IS_I865G(dev))
5888                 dev_priv->display.get_display_clock_speed =
5889                         i865_get_display_clock_speed;
5890         else if (IS_I85X(dev))
5891                 dev_priv->display.get_display_clock_speed =
5892                         i855_get_display_clock_speed;
5893         else /* 852, 830 */
5894                 dev_priv->display.get_display_clock_speed =
5895                         i830_get_display_clock_speed;
5896
5897         /* For FIFO watermark updates */
5898         if (HAS_PCH_SPLIT(dev)) {
5899                 if (IS_IRONLAKE(dev)) {
5900                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5901                                 dev_priv->display.update_wm = ironlake_update_wm;
5902                         else {
5903                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5904                                               "Disable CxSR\n");
5905                                 dev_priv->display.update_wm = NULL;
5906                         }
5907                 } else
5908                         dev_priv->display.update_wm = NULL;
5909         } else if (IS_PINEVIEW(dev)) {
5910                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5911                                             dev_priv->is_ddr3,
5912                                             dev_priv->fsb_freq,
5913                                             dev_priv->mem_freq)) {
5914                         DRM_INFO("failed to find known CxSR latency "
5915                                  "(found ddr%s fsb freq %d, mem freq %d), "
5916                                  "disabling CxSR\n",
5917                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5918                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5919                         /* Disable CxSR and never update its watermark again */
5920                         pineview_disable_cxsr(dev);
5921                         dev_priv->display.update_wm = NULL;
5922                 } else
5923                         dev_priv->display.update_wm = pineview_update_wm;
5924         } else if (IS_G4X(dev))
5925                 dev_priv->display.update_wm = g4x_update_wm;
5926         else if (IS_I965G(dev))
5927                 dev_priv->display.update_wm = i965_update_wm;
5928         else if (IS_I9XX(dev)) {
5929                 dev_priv->display.update_wm = i9xx_update_wm;
5930                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5931         } else if (IS_I85X(dev)) {
5932                 dev_priv->display.update_wm = i9xx_update_wm;
5933                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5934         } else {
5935                 dev_priv->display.update_wm = i830_update_wm;
5936                 if (IS_845G(dev))
5937                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5938                 else
5939                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5940         }
5941 }
5942
5943 /*
5944  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5945  * resume, or other times.  This quirk makes sure that's the case for
5946  * affected systems.
5947  */
5948 static void quirk_pipea_force (struct drm_device *dev)
5949 {
5950         struct drm_i915_private *dev_priv = dev->dev_private;
5951
5952         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5953         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5954 }
5955
5956 struct intel_quirk {
5957         int device;
5958         int subsystem_vendor;
5959         int subsystem_device;
5960         void (*hook)(struct drm_device *dev);
5961 };
5962
5963 struct intel_quirk intel_quirks[] = {
5964         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5965         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5966         /* HP Mini needs pipe A force quirk (LP: #322104) */
5967         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5968
5969         /* Thinkpad R31 needs pipe A force quirk */
5970         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5971         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5972         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5973
5974         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5975         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5976         /* ThinkPad X40 needs pipe A force quirk */
5977
5978         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5979         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5980
5981         /* 855 & before need to leave pipe A & dpll A up */
5982         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5983         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5984 };
5985
5986 static void intel_init_quirks(struct drm_device *dev)
5987 {
5988         struct pci_dev *d = dev->pdev;
5989         int i;
5990
5991         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
5992                 struct intel_quirk *q = &intel_quirks[i];
5993
5994                 if (d->device == q->device &&
5995                     (d->subsystem_vendor == q->subsystem_vendor ||
5996                      q->subsystem_vendor == PCI_ANY_ID) &&
5997                     (d->subsystem_device == q->subsystem_device ||
5998                      q->subsystem_device == PCI_ANY_ID))
5999                         q->hook(dev);
6000         }
6001 }
6002
6003 /* Disable the VGA plane that we never use */
6004 static void i915_disable_vga(struct drm_device *dev)
6005 {
6006         struct drm_i915_private *dev_priv = dev->dev_private;
6007         u8 sr1;
6008         u32 vga_reg;
6009
6010         if (HAS_PCH_SPLIT(dev))
6011                 vga_reg = CPU_VGACNTRL;
6012         else
6013                 vga_reg = VGACNTRL;
6014
6015         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6016         outb(1, VGA_SR_INDEX);
6017         sr1 = inb(VGA_SR_DATA);
6018         outb(sr1 | 1<<5, VGA_SR_DATA);
6019         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6020         udelay(300);
6021
6022         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6023         POSTING_READ(vga_reg);
6024 }
6025
6026 void intel_modeset_init(struct drm_device *dev)
6027 {
6028         struct drm_i915_private *dev_priv = dev->dev_private;
6029         int i;
6030
6031         drm_mode_config_init(dev);
6032
6033         dev->mode_config.min_width = 0;
6034         dev->mode_config.min_height = 0;
6035
6036         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6037
6038         intel_init_quirks(dev);
6039
6040         intel_init_display(dev);
6041
6042         if (IS_I965G(dev)) {
6043                 dev->mode_config.max_width = 8192;
6044                 dev->mode_config.max_height = 8192;
6045         } else if (IS_I9XX(dev)) {
6046                 dev->mode_config.max_width = 4096;
6047                 dev->mode_config.max_height = 4096;
6048         } else {
6049                 dev->mode_config.max_width = 2048;
6050                 dev->mode_config.max_height = 2048;
6051         }
6052
6053         /* set memory base */
6054         if (IS_I9XX(dev))
6055                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6056         else
6057                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6058
6059         if (IS_MOBILE(dev) || IS_I9XX(dev))
6060                 dev_priv->num_pipe = 2;
6061         else
6062                 dev_priv->num_pipe = 1;
6063         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6064                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6065
6066         for (i = 0; i < dev_priv->num_pipe; i++) {
6067                 intel_crtc_init(dev, i);
6068         }
6069
6070         intel_setup_outputs(dev);
6071
6072         intel_init_clock_gating(dev);
6073
6074         /* Just disable it once at startup */
6075         i915_disable_vga(dev);
6076
6077         if (IS_IRONLAKE_M(dev)) {
6078                 ironlake_enable_drps(dev);
6079                 intel_init_emon(dev);
6080         }
6081
6082         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6083         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6084                     (unsigned long)dev);
6085
6086         intel_setup_overlay(dev);
6087 }
6088
6089 void intel_modeset_cleanup(struct drm_device *dev)
6090 {
6091         struct drm_i915_private *dev_priv = dev->dev_private;
6092         struct drm_crtc *crtc;
6093         struct intel_crtc *intel_crtc;
6094
6095         mutex_lock(&dev->struct_mutex);
6096
6097         drm_kms_helper_poll_fini(dev);
6098         intel_fbdev_fini(dev);
6099
6100         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6101                 /* Skip inactive CRTCs */
6102                 if (!crtc->fb)
6103                         continue;
6104
6105                 intel_crtc = to_intel_crtc(crtc);
6106                 intel_increase_pllclock(crtc);
6107         }
6108
6109         if (dev_priv->display.disable_fbc)
6110                 dev_priv->display.disable_fbc(dev);
6111
6112         if (dev_priv->renderctx) {
6113                 struct drm_i915_gem_object *obj_priv;
6114
6115                 obj_priv = to_intel_bo(dev_priv->renderctx);
6116                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6117                 I915_READ(CCID);
6118                 i915_gem_object_unpin(dev_priv->renderctx);
6119                 drm_gem_object_unreference(dev_priv->renderctx);
6120         }
6121
6122         if (dev_priv->pwrctx) {
6123                 struct drm_i915_gem_object *obj_priv;
6124
6125                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6126                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6127                 I915_READ(PWRCTXA);
6128                 i915_gem_object_unpin(dev_priv->pwrctx);
6129                 drm_gem_object_unreference(dev_priv->pwrctx);
6130         }
6131
6132         if (IS_IRONLAKE_M(dev))
6133                 ironlake_disable_drps(dev);
6134
6135         mutex_unlock(&dev->struct_mutex);
6136
6137         /* Disable the irq before mode object teardown, for the irq might
6138          * enqueue unpin/hotplug work. */
6139         drm_irq_uninstall(dev);
6140         cancel_work_sync(&dev_priv->hotplug_work);
6141
6142         /* Shut off idle work before the crtcs get freed. */
6143         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6144                 intel_crtc = to_intel_crtc(crtc);
6145                 del_timer_sync(&intel_crtc->idle_timer);
6146         }
6147         del_timer_sync(&dev_priv->idle_timer);
6148         cancel_work_sync(&dev_priv->idle_work);
6149
6150         drm_mode_config_cleanup(dev);
6151 }
6152
6153 /*
6154  * Return which encoder is currently attached for connector.
6155  */
6156 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6157 {
6158         return &intel_attached_encoder(connector)->base;
6159 }
6160
6161 void intel_connector_attach_encoder(struct intel_connector *connector,
6162                                     struct intel_encoder *encoder)
6163 {
6164         connector->encoder = encoder;
6165         drm_mode_connector_attach_encoder(&connector->base,
6166                                           &encoder->base);
6167 }
6168
6169 /*
6170  * set vga decode state - true == enable VGA decode
6171  */
6172 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6173 {
6174         struct drm_i915_private *dev_priv = dev->dev_private;
6175         u16 gmch_ctrl;
6176
6177         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6178         if (state)
6179                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6180         else
6181                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6182         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6183         return 0;
6184 }