drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 POSTING_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 POSTING_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 static void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 POSTING_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 POSTING_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 POSTING_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 POSTING_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 POSTING_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 POSTING_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (INTEL_INFO(dev)->gen >= 4)
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low;
 206
 207         if (!i915_pipe_enabled(dev, pipe)) {
 208                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 209                                 "pipe %d\n", pipe);
 210                 return 0;
 211         }
 212
 213         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 214         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 223                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 224                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 225         } while (high1 != high2);
 226
 227         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 228         low >>= PIPE_FRAME_LOW_SHIFT;
 229         return (high1 << 8) | low;
 230 }
 231
 232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 233 {
 234         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 235         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 236
 237         if (!i915_pipe_enabled(dev, pipe)) {
 238                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 239                                         "pipe %d\n", pipe);
 240                 return 0;
 241         }
 242
 243         return I915_READ(reg);
 244 }
 245
 246 /*
 247  * Handle hotplug events outside the interrupt handler proper.
 248  */
 249 static void i915_hotplug_work_func(struct work_struct *work)
 250 {
 251         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 252                                                     hotplug_work);
 253         struct drm_device *dev = dev_priv->dev;
 254         struct drm_mode_config *mode_config = &dev->mode_config;
 255         struct intel_encoder *encoder;
 256
 257         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 258                 if (encoder->hot_plug)
 259                         encoder->hot_plug(encoder);
 260
 261         /* Just fire off a uevent and let userspace tell us what to do */
 262         drm_helper_hpd_irq_event(dev);
 263 }
 264
 265 static void i915_handle_rps_change(struct drm_device *dev)
 266 {
 267         drm_i915_private_t *dev_priv = dev->dev_private;
 268         u32 busy_up, busy_down, max_avg, min_avg;
 269         u8 new_delay = dev_priv->cur_delay;
 270
 271         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 272         busy_up = I915_READ(RCPREVBSYTUPAVG);
 273         busy_down = I915_READ(RCPREVBSYTDNAVG);
 274         max_avg = I915_READ(RCBMAXAVG);
 275         min_avg = I915_READ(RCBMINAVG);
 276
 277         /* Handle RCS change request from hw */
 278         if (busy_up > max_avg) {
 279                 if (dev_priv->cur_delay != dev_priv->max_delay)
 280                         new_delay = dev_priv->cur_delay - 1;
 281                 if (new_delay < dev_priv->max_delay)
 282                         new_delay = dev_priv->max_delay;
 283         } else if (busy_down < min_avg) {
 284                 if (dev_priv->cur_delay != dev_priv->min_delay)
 285                         new_delay = dev_priv->cur_delay + 1;
 286                 if (new_delay > dev_priv->min_delay)
 287                         new_delay = dev_priv->min_delay;
 288         }
 289
 290         if (ironlake_set_drps(dev, new_delay))
 291                 dev_priv->cur_delay = new_delay;
 292
 293         return;
 294 }
 295
 296 static void notify_ring(struct drm_device *dev,
 297                         struct intel_ring_buffer *ring)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         u32 seqno = ring->get_seqno(ring);
 301         ring->irq_seqno = seqno;
 302         trace_i915_gem_request_complete(dev, seqno);
 303         wake_up_all(&ring->irq_queue);
 304         dev_priv->hangcheck_count = 0;
 305         mod_timer(&dev_priv->hangcheck_timer,
 306                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 307 }
 308
 309 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 310 {
 311         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 312         int ret = IRQ_NONE;
 313         u32 de_iir, gt_iir, de_ier, pch_iir;
 314         u32 hotplug_mask;
 315         struct drm_i915_master_private *master_priv;
 316         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 317
 318         if (IS_GEN6(dev))
 319                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 320
 321         /* disable master interrupt before clearing iir  */
 322         de_ier = I915_READ(DEIER);
 323         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 324         POSTING_READ(DEIER);
 325
 326         de_iir = I915_READ(DEIIR);
 327         gt_iir = I915_READ(GTIIR);
 328         pch_iir = I915_READ(SDEIIR);
 329
 330         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 331                 goto done;
 332
 333         if (HAS_PCH_CPT(dev))
 334                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 335         else
 336                 hotplug_mask = SDE_HOTPLUG_MASK;
 337
 338         ret = IRQ_HANDLED;
 339
 340         if (dev->primary->master) {
 341                 master_priv = dev->primary->master->driver_priv;
 342                 if (master_priv->sarea_priv)
 343                         master_priv->sarea_priv->last_dispatch =
 344                                 READ_BREADCRUMB(dev_priv);
 345         }
 346
 347         if (gt_iir & GT_PIPE_NOTIFY)
 348                 notify_ring(dev, &dev_priv->render_ring);
 349         if (gt_iir & bsd_usr_interrupt)
 350                 notify_ring(dev, &dev_priv->bsd_ring);
 351         if (HAS_BLT(dev) && gt_iir & GT_BLT_USER_INTERRUPT)
 352                 notify_ring(dev, &dev_priv->blt_ring);
 353
 354         if (de_iir & DE_GSE)
 355                 intel_opregion_gse_intr(dev);
 356
 357         if (de_iir & DE_PLANEA_FLIP_DONE) {
 358                 intel_prepare_page_flip(dev, 0);
 359                 intel_finish_page_flip_plane(dev, 0);
 360         }
 361
 362         if (de_iir & DE_PLANEB_FLIP_DONE) {
 363                 intel_prepare_page_flip(dev, 1);
 364                 intel_finish_page_flip_plane(dev, 1);
 365         }
 366
 367         if (de_iir & DE_PIPEA_VBLANK)
 368                 drm_handle_vblank(dev, 0);
 369
 370         if (de_iir & DE_PIPEB_VBLANK)
 371                 drm_handle_vblank(dev, 1);
 372
 373         /* check event from PCH */
 374         if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
 375                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 376
 377         if (de_iir & DE_PCU_EVENT) {
 378                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 379                 i915_handle_rps_change(dev);
 380         }
 381
 382         /* should clear PCH hotplug event before clear CPU irq */
 383         I915_WRITE(SDEIIR, pch_iir);
 384         I915_WRITE(GTIIR, gt_iir);
 385         I915_WRITE(DEIIR, de_iir);
 386
 387 done:
 388         I915_WRITE(DEIER, de_ier);
 389         POSTING_READ(DEIER);
 390
 391         return ret;
 392 }
 393
 394 /**
 395  * i915_error_work_func - do process context error handling work
 396  * @work: work struct
 397  *
 398  * Fire an error uevent so userspace can see that a hang or error
 399  * was detected.
 400  */
 401 static void i915_error_work_func(struct work_struct *work)
 402 {
 403         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 404                                                     error_work);
 405         struct drm_device *dev = dev_priv->dev;
 406         char *error_event[] = { "ERROR=1", NULL };
 407         char *reset_event[] = { "RESET=1", NULL };
 408         char *reset_done_event[] = { "ERROR=0", NULL };
 409
 410         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 411
 412         if (atomic_read(&dev_priv->mm.wedged)) {
 413                 DRM_DEBUG_DRIVER("resetting chip\n");
 414                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 415                 if (!i915_reset(dev, GRDOM_RENDER)) {
 416                         atomic_set(&dev_priv->mm.wedged, 0);
 417                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 418                 }
 419                 complete_all(&dev_priv->error_completion);
 420         }
 421 }
 422
 423 #ifdef CONFIG_DEBUG_FS
 424 static struct drm_i915_error_object *
 425 i915_error_object_create(struct drm_device *dev,
 426                          struct drm_i915_gem_object *src)
 427 {
 428         drm_i915_private_t *dev_priv = dev->dev_private;
 429         struct drm_i915_error_object *dst;
 430         int page, page_count;
 431         u32 reloc_offset;
 432
 433         if (src == NULL || src->pages == NULL)
 434                 return NULL;
 435
 436         page_count = src->base.size / PAGE_SIZE;
 437
 438         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 439         if (dst == NULL)
 440                 return NULL;
 441
 442         reloc_offset = src->gtt_offset;
 443         for (page = 0; page < page_count; page++) {
 444                 unsigned long flags;
 445                 void __iomem *s;
 446                 void *d;
 447
 448                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 449                 if (d == NULL)
 450                         goto unwind;
 451
 452                 local_irq_save(flags);
 453                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 454                                              reloc_offset);
 455                 memcpy_fromio(d, s, PAGE_SIZE);
 456                 io_mapping_unmap_atomic(s);
 457                 local_irq_restore(flags);
 458
 459                 dst->pages[page] = d;
 460
 461                 reloc_offset += PAGE_SIZE;
 462         }
 463         dst->page_count = page_count;
 464         dst->gtt_offset = src->gtt_offset;
 465
 466         return dst;
 467
 468 unwind:
 469         while (page--)
 470                 kfree(dst->pages[page]);
 471         kfree(dst);
 472         return NULL;
 473 }
 474
 475 static void
 476 i915_error_object_free(struct drm_i915_error_object *obj)
 477 {
 478         int page;
 479
 480         if (obj == NULL)
 481                 return;
 482
 483         for (page = 0; page < obj->page_count; page++)
 484                 kfree(obj->pages[page]);
 485
 486         kfree(obj);
 487 }
 488
 489 static void
 490 i915_error_state_free(struct drm_device *dev,
 491                       struct drm_i915_error_state *error)
 492 {
 493         i915_error_object_free(error->batchbuffer[0]);
 494         i915_error_object_free(error->batchbuffer[1]);
 495         i915_error_object_free(error->ringbuffer);
 496         kfree(error->active_bo);
 497         kfree(error->overlay);
 498         kfree(error);
 499 }
 500
 501 static u32
 502 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 503 {
 504         u32 cmd;
 505
 506         if (IS_I830(dev) || IS_845G(dev))
 507                 cmd = MI_BATCH_BUFFER;
 508         else if (INTEL_INFO(dev)->gen >= 4)
 509                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 510                        MI_BATCH_NON_SECURE_I965);
 511         else
 512                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 513
 514         return ring[0] == cmd ? ring[1] : 0;
 515 }
 516
 517 static u32
 518 i915_ringbuffer_last_batch(struct drm_device *dev,
 519                            struct intel_ring_buffer *ring)
 520 {
 521         struct drm_i915_private *dev_priv = dev->dev_private;
 522         u32 head, bbaddr;
 523         u32 *val;
 524
 525         /* Locate the current position in the ringbuffer and walk back
 526          * to find the most recently dispatched batch buffer.
 527          */
 528         bbaddr = 0;
 529         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 530         val = (u32 *)(ring->virtual_start + head);
 531
 532         while (--val >= (u32 *)ring->virtual_start) {
 533                 bbaddr = i915_get_bbaddr(dev, val);
 534                 if (bbaddr)
 535                         break;
 536         }
 537
 538         if (bbaddr == 0) {
 539                 val = (u32 *)(ring->virtual_start + ring->size);
 540                 while (--val >= (u32 *)ring->virtual_start) {
 541                         bbaddr = i915_get_bbaddr(dev, val);
 542                         if (bbaddr)
 543                                 break;
 544                 }
 545         }
 546
 547         return bbaddr;
 548 }
 549
 550 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 551                            int count,
 552                            struct list_head *head)
 553 {
 554         struct drm_i915_gem_object *obj;
 555         int i = 0;
 556
 557         list_for_each_entry(obj, head, mm_list) {
 558                 err->size = obj->base.size;
 559                 err->name = obj->base.name;
 560                 err->seqno = obj->last_rendering_seqno;
 561                 err->gtt_offset = obj->gtt_offset;
 562                 err->read_domains = obj->base.read_domains;
 563                 err->write_domain = obj->base.write_domain;
 564                 err->fence_reg = obj->fence_reg;
 565                 err->pinned = 0;
 566                 if (obj->pin_count > 0)
 567                         err->pinned = 1;
 568                 if (obj->user_pin_count > 0)
 569                         err->pinned = -1;
 570                 err->tiling = obj->tiling_mode;
 571                 err->dirty = obj->dirty;
 572                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 573                 err->ring = obj->ring ? obj->ring->id : 0;
 574
 575                 if (++i == count)
 576                         break;
 577
 578                 err++;
 579         }
 580
 581         return i;
 582 }
 583
 584 static void i915_gem_record_fences(struct drm_device *dev,
 585                                    struct drm_i915_error_state *error)
 586 {
 587         struct drm_i915_private *dev_priv = dev->dev_private;
 588         int i;
 589
 590         /* Fences */
 591         switch (INTEL_INFO(dev)->gen) {
 592         case 6:
 593                 for (i = 0; i < 16; i++)
 594                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 595                 break;
 596         case 5:
 597         case 4:
 598                 for (i = 0; i < 16; i++)
 599                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 600                 break;
 601         case 3:
 602                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 603                         for (i = 0; i < 8; i++)
 604                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 605         case 2:
 606                 for (i = 0; i < 8; i++)
 607                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 608                 break;
 609
 610         }
 611 }
 612
 613 /**
 614  * i915_capture_error_state - capture an error record for later analysis
 615  * @dev: drm device
 616  *
 617  * Should be called when an error is detected (either a hang or an error
 618  * interrupt) to capture error state from the time of the error.  Fills
 619  * out a structure which becomes available in debugfs for user level tools
 620  * to pick up.
 621  */
 622 static void i915_capture_error_state(struct drm_device *dev)
 623 {
 624         struct drm_i915_private *dev_priv = dev->dev_private;
 625         struct drm_i915_gem_object *obj;
 626         struct drm_i915_error_state *error;
 627         struct drm_i915_gem_object *batchbuffer[2];
 628         unsigned long flags;
 629         u32 bbaddr;
 630         int count;
 631
 632         spin_lock_irqsave(&dev_priv->error_lock, flags);
 633         error = dev_priv->first_error;
 634         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 635         if (error)
 636                 return;
 637
 638         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 639         if (!error) {
 640                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 641                 return;
 642         }
 643
 644         DRM_DEBUG_DRIVER("generating error event\n");
 645
 646         error->seqno =
 647                 dev_priv->render_ring.get_seqno(&dev_priv->render_ring);
 648         error->eir = I915_READ(EIR);
 649         error->pgtbl_er = I915_READ(PGTBL_ER);
 650         error->pipeastat = I915_READ(PIPEASTAT);
 651         error->pipebstat = I915_READ(PIPEBSTAT);
 652         error->instpm = I915_READ(INSTPM);
 653         error->error = 0;
 654         if (INTEL_INFO(dev)->gen >= 6) {
 655                 error->error = I915_READ(ERROR_GEN6);
 656
 657                 error->bcs_acthd = I915_READ(BCS_ACTHD);
 658                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
 659                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
 660                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
 661                 error->bcs_seqno = 0;
 662                 if (dev_priv->blt_ring.get_seqno)
 663                         error->bcs_seqno = dev_priv->blt_ring.get_seqno(&dev_priv->blt_ring);
 664
 665                 error->vcs_acthd = I915_READ(VCS_ACTHD);
 666                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
 667                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
 668                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
 669                 error->vcs_seqno = 0;
 670                 if (dev_priv->bsd_ring.get_seqno)
 671                         error->vcs_seqno = dev_priv->bsd_ring.get_seqno(&dev_priv->bsd_ring);
 672         }
 673         if (INTEL_INFO(dev)->gen >= 4) {
 674                 error->ipeir = I915_READ(IPEIR_I965);
 675                 error->ipehr = I915_READ(IPEHR_I965);
 676                 error->instdone = I915_READ(INSTDONE_I965);
 677                 error->instps = I915_READ(INSTPS);
 678                 error->instdone1 = I915_READ(INSTDONE1);
 679                 error->acthd = I915_READ(ACTHD_I965);
 680                 error->bbaddr = I915_READ64(BB_ADDR);
 681         } else {
 682                 error->ipeir = I915_READ(IPEIR);
 683                 error->ipehr = I915_READ(IPEHR);
 684                 error->instdone = I915_READ(INSTDONE);
 685                 error->acthd = I915_READ(ACTHD);
 686                 error->bbaddr = 0;
 687         }
 688         i915_gem_record_fences(dev, error);
 689
 690         bbaddr = i915_ringbuffer_last_batch(dev, &dev_priv->render_ring);
 691
 692         /* Grab the current batchbuffer, most likely to have crashed. */
 693         batchbuffer[0] = NULL;
 694         batchbuffer[1] = NULL;
 695         count = 0;
 696         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
 697                 if (batchbuffer[0] == NULL &&
 698                     bbaddr >= obj->gtt_offset &&
 699                     bbaddr < obj->gtt_offset + obj->base.size)
 700                         batchbuffer[0] = obj;
 701
 702                 if (batchbuffer[1] == NULL &&
 703                     error->acthd >= obj->gtt_offset &&
 704                     error->acthd < obj->gtt_offset + obj->base.size)
 705                         batchbuffer[1] = obj;
 706
 707                 count++;
 708         }
 709         /* Scan the other lists for completeness for those bizarre errors. */
 710         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 711                 list_for_each_entry(obj, &dev_priv->mm.flushing_list, mm_list) {
 712                         if (batchbuffer[0] == NULL &&
 713                             bbaddr >= obj->gtt_offset &&
 714                             bbaddr < obj->gtt_offset + obj->base.size)
 715                                 batchbuffer[0] = obj;
 716
 717                         if (batchbuffer[1] == NULL &&
 718                             error->acthd >= obj->gtt_offset &&
 719                             error->acthd < obj->gtt_offset + obj->base.size)
 720                                 batchbuffer[1] = obj;
 721
 722                         if (batchbuffer[0] && batchbuffer[1])
 723                                 break;
 724                 }
 725         }
 726         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 727                 list_for_each_entry(obj, &dev_priv->mm.inactive_list, mm_list) {
 728                         if (batchbuffer[0] == NULL &&
 729                             bbaddr >= obj->gtt_offset &&
 730                             bbaddr < obj->gtt_offset + obj->base.size)
 731                                 batchbuffer[0] = obj;
 732
 733                         if (batchbuffer[1] == NULL &&
 734                             error->acthd >= obj->gtt_offset &&
 735                             error->acthd < obj->gtt_offset + obj->base.size)
 736                                 batchbuffer[1] = obj;
 737
 738                         if (batchbuffer[0] && batchbuffer[1])
 739                                 break;
 740                 }
 741         }
 742
 743         /* We need to copy these to an anonymous buffer as the simplest
 744          * method to avoid being overwritten by userspace.
 745          */
 746         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 747         if (batchbuffer[1] != batchbuffer[0])
 748                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 749         else
 750                 error->batchbuffer[1] = NULL;
 751
 752         /* Record the ringbuffer */
 753         error->ringbuffer = i915_error_object_create(dev,
 754                                                      dev_priv->render_ring.obj);
 755
 756         /* Record buffers on the active and pinned lists. */
 757         error->active_bo = NULL;
 758         error->pinned_bo = NULL;
 759
 760         error->active_bo_count = count;
 761         list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
 762                 count++;
 763         error->pinned_bo_count = count - error->active_bo_count;
 764
 765         if (count) {
 766                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 767                                            GFP_ATOMIC);
 768                 if (error->active_bo)
 769                         error->pinned_bo =
 770                                 error->active_bo + error->active_bo_count;
 771         }
 772
 773         if (error->active_bo)
 774                 error->active_bo_count =
 775                         capture_bo_list(error->active_bo,
 776                                         error->active_bo_count,
 777                                         &dev_priv->mm.active_list);
 778
 779         if (error->pinned_bo)
 780                 error->pinned_bo_count =
 781                         capture_bo_list(error->pinned_bo,
 782                                         error->pinned_bo_count,
 783                                         &dev_priv->mm.pinned_list);
 784
 785         do_gettimeofday(&error->time);
 786
 787         error->overlay = intel_overlay_capture_error_state(dev);
 788         error->display = intel_display_capture_error_state(dev);
 789
 790         spin_lock_irqsave(&dev_priv->error_lock, flags);
 791         if (dev_priv->first_error == NULL) {
 792                 dev_priv->first_error = error;
 793                 error = NULL;
 794         }
 795         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 796
 797         if (error)
 798                 i915_error_state_free(dev, error);
 799 }
 800
 801 void i915_destroy_error_state(struct drm_device *dev)
 802 {
 803         struct drm_i915_private *dev_priv = dev->dev_private;
 804         struct drm_i915_error_state *error;
 805
 806         spin_lock(&dev_priv->error_lock);
 807         error = dev_priv->first_error;
 808         dev_priv->first_error = NULL;
 809         spin_unlock(&dev_priv->error_lock);
 810
 811         if (error)
 812                 i915_error_state_free(dev, error);
 813 }
 814 #else
 815 #define i915_capture_error_state(x)
 816 #endif
 817
 818 static void i915_report_and_clear_eir(struct drm_device *dev)
 819 {
 820         struct drm_i915_private *dev_priv = dev->dev_private;
 821         u32 eir = I915_READ(EIR);
 822
 823         if (!eir)
 824                 return;
 825
 826         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 827                eir);
 828
 829         if (IS_G4X(dev)) {
 830                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 831                         u32 ipeir = I915_READ(IPEIR_I965);
 832
 833                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 834                                I915_READ(IPEIR_I965));
 835                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 836                                I915_READ(IPEHR_I965));
 837                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 838                                I915_READ(INSTDONE_I965));
 839                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 840                                I915_READ(INSTPS));
 841                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 842                                I915_READ(INSTDONE1));
 843                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 844                                I915_READ(ACTHD_I965));
 845                         I915_WRITE(IPEIR_I965, ipeir);
 846                         POSTING_READ(IPEIR_I965);
 847                 }
 848                 if (eir & GM45_ERROR_PAGE_TABLE) {
 849                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 850                         printk(KERN_ERR "page table error\n");
 851                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 852                                pgtbl_err);
 853                         I915_WRITE(PGTBL_ER, pgtbl_err);
 854                         POSTING_READ(PGTBL_ER);
 855                 }
 856         }
 857
 858         if (!IS_GEN2(dev)) {
 859                 if (eir & I915_ERROR_PAGE_TABLE) {
 860                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 861                         printk(KERN_ERR "page table error\n");
 862                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 863                                pgtbl_err);
 864                         I915_WRITE(PGTBL_ER, pgtbl_err);
 865                         POSTING_READ(PGTBL_ER);
 866                 }
 867         }
 868
 869         if (eir & I915_ERROR_MEMORY_REFRESH) {
 870                 u32 pipea_stats = I915_READ(PIPEASTAT);
 871                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 872
 873                 printk(KERN_ERR "memory refresh error\n");
 874                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 875                        pipea_stats);
 876                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 877                        pipeb_stats);
 878                 /* pipestat has already been acked */
 879         }
 880         if (eir & I915_ERROR_INSTRUCTION) {
 881                 printk(KERN_ERR "instruction error\n");
 882                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 883                        I915_READ(INSTPM));
 884                 if (INTEL_INFO(dev)->gen < 4) {
 885                         u32 ipeir = I915_READ(IPEIR);
 886
 887                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 888                                I915_READ(IPEIR));
 889                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 890                                I915_READ(IPEHR));
 891                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 892                                I915_READ(INSTDONE));
 893                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 894                                I915_READ(ACTHD));
 895                         I915_WRITE(IPEIR, ipeir);
 896                         POSTING_READ(IPEIR);
 897                 } else {
 898                         u32 ipeir = I915_READ(IPEIR_I965);
 899
 900                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 901                                I915_READ(IPEIR_I965));
 902                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 903                                I915_READ(IPEHR_I965));
 904                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 905                                I915_READ(INSTDONE_I965));
 906                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 907                                I915_READ(INSTPS));
 908                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 909                                I915_READ(INSTDONE1));
 910                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 911                                I915_READ(ACTHD_I965));
 912                         I915_WRITE(IPEIR_I965, ipeir);
 913                         POSTING_READ(IPEIR_I965);
 914                 }
 915         }
 916
 917         I915_WRITE(EIR, eir);
 918         POSTING_READ(EIR);
 919         eir = I915_READ(EIR);
 920         if (eir) {
 921                 /*
 922                  * some errors might have become stuck,
 923                  * mask them.
 924                  */
 925                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 926                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 927                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 928         }
 929 }
 930
 931 /**
 932  * i915_handle_error - handle an error interrupt
 933  * @dev: drm device
 934  *
 935  * Do some basic checking of regsiter state at error interrupt time and
 936  * dump it to the syslog.  Also call i915_capture_error_state() to make
 937  * sure we get a record and make it available in debugfs.  Fire a uevent
 938  * so userspace knows something bad happened (should trigger collection
 939  * of a ring dump etc.).
 940  */
 941 void i915_handle_error(struct drm_device *dev, bool wedged)
 942 {
 943         struct drm_i915_private *dev_priv = dev->dev_private;
 944
 945         i915_capture_error_state(dev);
 946         i915_report_and_clear_eir(dev);
 947
 948         if (wedged) {
 949                 INIT_COMPLETION(dev_priv->error_completion);
 950                 atomic_set(&dev_priv->mm.wedged, 1);
 951
 952                 /*
 953                  * Wakeup waiting processes so they don't hang
 954                  */
 955                 wake_up_all(&dev_priv->render_ring.irq_queue);
 956                 if (HAS_BSD(dev))
 957                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
 958                 if (HAS_BLT(dev))
 959                         wake_up_all(&dev_priv->blt_ring.irq_queue);
 960         }
 961
 962         queue_work(dev_priv->wq, &dev_priv->error_work);
 963 }
 964
 965 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 966 {
 967         drm_i915_private_t *dev_priv = dev->dev_private;
 968         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 969         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 970         struct drm_i915_gem_object *obj;
 971         struct intel_unpin_work *work;
 972         unsigned long flags;
 973         bool stall_detected;
 974
 975         /* Ignore early vblank irqs */
 976         if (intel_crtc == NULL)
 977                 return;
 978
 979         spin_lock_irqsave(&dev->event_lock, flags);
 980         work = intel_crtc->unpin_work;
 981
 982         if (work == NULL || work->pending || !work->enable_stall_check) {
 983                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 984                 spin_unlock_irqrestore(&dev->event_lock, flags);
 985                 return;
 986         }
 987
 988         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 989         obj = work->pending_flip_obj;
 990         if (INTEL_INFO(dev)->gen >= 4) {
 991                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 992                 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
 993         } else {
 994                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 995                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
 996                                                         crtc->y * crtc->fb->pitch +
 997                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 998         }
 999
1000         spin_unlock_irqrestore(&dev->event_lock, flags);
1001
1002         if (stall_detected) {
1003                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1004                 intel_prepare_page_flip(dev, intel_crtc->plane);
1005         }
1006 }
1007
1008 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1009 {
1010         struct drm_device *dev = (struct drm_device *) arg;
1011         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1012         struct drm_i915_master_private *master_priv;
1013         u32 iir, new_iir;
1014         u32 pipea_stats, pipeb_stats;
1015         u32 vblank_status;
1016         int vblank = 0;
1017         unsigned long irqflags;
1018         int irq_received;
1019         int ret = IRQ_NONE;
1020
1021         atomic_inc(&dev_priv->irq_received);
1022
1023         if (HAS_PCH_SPLIT(dev))
1024                 return ironlake_irq_handler(dev);
1025
1026         iir = I915_READ(IIR);
1027
1028         if (INTEL_INFO(dev)->gen >= 4)
1029                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1030         else
1031                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1032
1033         for (;;) {
1034                 irq_received = iir != 0;
1035
1036                 /* Can't rely on pipestat interrupt bit in iir as it might
1037                  * have been cleared after the pipestat interrupt was received.
1038                  * It doesn't set the bit in iir again, but it still produces
1039                  * interrupts (for non-MSI).
1040                  */
1041                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1042                 pipea_stats = I915_READ(PIPEASTAT);
1043                 pipeb_stats = I915_READ(PIPEBSTAT);
1044
1045                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1046                         i915_handle_error(dev, false);
1047
1048                 /*
1049                  * Clear the PIPE(A|B)STAT regs before the IIR
1050                  */
1051                 if (pipea_stats & 0x8000ffff) {
1052                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1053                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
1054                         I915_WRITE(PIPEASTAT, pipea_stats);
1055                         irq_received = 1;
1056                 }
1057
1058                 if (pipeb_stats & 0x8000ffff) {
1059                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1060                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
1061                         I915_WRITE(PIPEBSTAT, pipeb_stats);
1062                         irq_received = 1;
1063                 }
1064                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1065
1066                 if (!irq_received)
1067                         break;
1068
1069                 ret = IRQ_HANDLED;
1070
1071                 /* Consume port.  Then clear IIR or we'll miss events */
1072                 if ((I915_HAS_HOTPLUG(dev)) &&
1073                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1074                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1075
1076                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1077                                   hotplug_status);
1078                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1079                                 queue_work(dev_priv->wq,
1080                                            &dev_priv->hotplug_work);
1081
1082                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1083                         I915_READ(PORT_HOTPLUG_STAT);
1084                 }
1085
1086                 I915_WRITE(IIR, iir);
1087                 new_iir = I915_READ(IIR); /* Flush posted writes */
1088
1089                 if (dev->primary->master) {
1090                         master_priv = dev->primary->master->driver_priv;
1091                         if (master_priv->sarea_priv)
1092                                 master_priv->sarea_priv->last_dispatch =
1093                                         READ_BREADCRUMB(dev_priv);
1094                 }
1095
1096                 if (iir & I915_USER_INTERRUPT)
1097                         notify_ring(dev, &dev_priv->render_ring);
1098                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1099                         notify_ring(dev, &dev_priv->bsd_ring);
1100
1101                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1102                         intel_prepare_page_flip(dev, 0);
1103                         if (dev_priv->flip_pending_is_done)
1104                                 intel_finish_page_flip_plane(dev, 0);
1105                 }
1106
1107                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1108                         intel_prepare_page_flip(dev, 1);
1109                         if (dev_priv->flip_pending_is_done)
1110                                 intel_finish_page_flip_plane(dev, 1);
1111                 }
1112
1113                 if (pipea_stats & vblank_status) {
1114                         vblank++;
1115                         drm_handle_vblank(dev, 0);
1116                         if (!dev_priv->flip_pending_is_done) {
1117                                 i915_pageflip_stall_check(dev, 0);
1118                                 intel_finish_page_flip(dev, 0);
1119                         }
1120                 }
1121
1122                 if (pipeb_stats & vblank_status) {
1123                         vblank++;
1124                         drm_handle_vblank(dev, 1);
1125                         if (!dev_priv->flip_pending_is_done) {
1126                                 i915_pageflip_stall_check(dev, 1);
1127                                 intel_finish_page_flip(dev, 1);
1128                         }
1129                 }
1130
1131                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1132                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1133                     (iir & I915_ASLE_INTERRUPT))
1134                         intel_opregion_asle_intr(dev);
1135
1136                 /* With MSI, interrupts are only generated when iir
1137                  * transitions from zero to nonzero.  If another bit got
1138                  * set while we were handling the existing iir bits, then
1139                  * we would never get another interrupt.
1140                  *
1141                  * This is fine on non-MSI as well, as if we hit this path
1142                  * we avoid exiting the interrupt handler only to generate
1143                  * another one.
1144                  *
1145                  * Note that for MSI this could cause a stray interrupt report
1146                  * if an interrupt landed in the time between writing IIR and
1147                  * the posting read.  This should be rare enough to never
1148                  * trigger the 99% of 100,000 interrupts test for disabling
1149                  * stray interrupts.
1150                  */
1151                 iir = new_iir;
1152         }
1153
1154         return ret;
1155 }
1156
1157 static int i915_emit_irq(struct drm_device * dev)
1158 {
1159         drm_i915_private_t *dev_priv = dev->dev_private;
1160         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1161
1162         i915_kernel_lost_context(dev);
1163
1164         DRM_DEBUG_DRIVER("\n");
1165
1166         dev_priv->counter++;
1167         if (dev_priv->counter > 0x7FFFFFFFUL)
1168                 dev_priv->counter = 1;
1169         if (master_priv->sarea_priv)
1170                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1171
1172         if (BEGIN_LP_RING(4) == 0) {
1173                 OUT_RING(MI_STORE_DWORD_INDEX);
1174                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1175                 OUT_RING(dev_priv->counter);
1176                 OUT_RING(MI_USER_INTERRUPT);
1177                 ADVANCE_LP_RING();
1178         }
1179
1180         return dev_priv->counter;
1181 }
1182
1183 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1184 {
1185         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1186         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1187
1188         if (dev_priv->trace_irq_seqno == 0)
1189                 render_ring->user_irq_get(render_ring);
1190
1191         dev_priv->trace_irq_seqno = seqno;
1192 }
1193
1194 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1195 {
1196         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1197         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1198         int ret = 0;
1199         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1200
1201         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1202                   READ_BREADCRUMB(dev_priv));
1203
1204         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1205                 if (master_priv->sarea_priv)
1206                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1207                 return 0;
1208         }
1209
1210         if (master_priv->sarea_priv)
1211                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1212
1213         render_ring->user_irq_get(render_ring);
1214         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1215                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1216         render_ring->user_irq_put(render_ring);
1217
1218         if (ret == -EBUSY) {
1219                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1220                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1221         }
1222
1223         return ret;
1224 }
1225
1226 /* Needs the lock as it touches the ring.
1227  */
1228 int i915_irq_emit(struct drm_device *dev, void *data,
1229                          struct drm_file *file_priv)
1230 {
1231         drm_i915_private_t *dev_priv = dev->dev_private;
1232         drm_i915_irq_emit_t *emit = data;
1233         int result;
1234
1235         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1236                 DRM_ERROR("called with no initialization\n");
1237                 return -EINVAL;
1238         }
1239
1240         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1241
1242         mutex_lock(&dev->struct_mutex);
1243         result = i915_emit_irq(dev);
1244         mutex_unlock(&dev->struct_mutex);
1245
1246         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1247                 DRM_ERROR("copy_to_user\n");
1248                 return -EFAULT;
1249         }
1250
1251         return 0;
1252 }
1253
1254 /* Doesn't need the hardware lock.
1255  */
1256 int i915_irq_wait(struct drm_device *dev, void *data,
1257                          struct drm_file *file_priv)
1258 {
1259         drm_i915_private_t *dev_priv = dev->dev_private;
1260         drm_i915_irq_wait_t *irqwait = data;
1261
1262         if (!dev_priv) {
1263                 DRM_ERROR("called with no initialization\n");
1264                 return -EINVAL;
1265         }
1266
1267         return i915_wait_irq(dev, irqwait->irq_seq);
1268 }
1269
1270 /* Called from drm generic code, passed 'crtc' which
1271  * we use as a pipe index
1272  */
1273 int i915_enable_vblank(struct drm_device *dev, int pipe)
1274 {
1275         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1276         unsigned long irqflags;
1277
1278         if (!i915_pipe_enabled(dev, pipe))
1279                 return -EINVAL;
1280
1281         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1282         if (HAS_PCH_SPLIT(dev))
1283                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1284                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1285         else if (INTEL_INFO(dev)->gen >= 4)
1286                 i915_enable_pipestat(dev_priv, pipe,
1287                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1288         else
1289                 i915_enable_pipestat(dev_priv, pipe,
1290                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1291         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1292         return 0;
1293 }
1294
1295 /* Called from drm generic code, passed 'crtc' which
1296  * we use as a pipe index
1297  */
1298 void i915_disable_vblank(struct drm_device *dev, int pipe)
1299 {
1300         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1301         unsigned long irqflags;
1302
1303         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1304         if (HAS_PCH_SPLIT(dev))
1305                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1306                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1307         else
1308                 i915_disable_pipestat(dev_priv, pipe,
1309                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1310                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1311         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1312 }
1313
1314 void i915_enable_interrupt (struct drm_device *dev)
1315 {
1316         struct drm_i915_private *dev_priv = dev->dev_private;
1317
1318         if (!HAS_PCH_SPLIT(dev))
1319                 intel_opregion_enable_asle(dev);
1320         dev_priv->irq_enabled = 1;
1321 }
1322
1323
1324 /* Set the vblank monitor pipe
1325  */
1326 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1327                          struct drm_file *file_priv)
1328 {
1329         drm_i915_private_t *dev_priv = dev->dev_private;
1330
1331         if (!dev_priv) {
1332                 DRM_ERROR("called with no initialization\n");
1333                 return -EINVAL;
1334         }
1335
1336         return 0;
1337 }
1338
1339 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1340                          struct drm_file *file_priv)
1341 {
1342         drm_i915_private_t *dev_priv = dev->dev_private;
1343         drm_i915_vblank_pipe_t *pipe = data;
1344
1345         if (!dev_priv) {
1346                 DRM_ERROR("called with no initialization\n");
1347                 return -EINVAL;
1348         }
1349
1350         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1351
1352         return 0;
1353 }
1354
1355 /**
1356  * Schedule buffer swap at given vertical blank.
1357  */
1358 int i915_vblank_swap(struct drm_device *dev, void *data,
1359                      struct drm_file *file_priv)
1360 {
1361         /* The delayed swap mechanism was fundamentally racy, and has been
1362          * removed.  The model was that the client requested a delayed flip/swap
1363          * from the kernel, then waited for vblank before continuing to perform
1364          * rendering.  The problem was that the kernel might wake the client
1365          * up before it dispatched the vblank swap (since the lock has to be
1366          * held while touching the ringbuffer), in which case the client would
1367          * clear and start the next frame before the swap occurred, and
1368          * flicker would occur in addition to likely missing the vblank.
1369          *
1370          * In the absence of this ioctl, userland falls back to a correct path
1371          * of waiting for a vblank, then dispatching the swap on its own.
1372          * Context switching to userland and back is plenty fast enough for
1373          * meeting the requirements of vblank swapping.
1374          */
1375         return -EINVAL;
1376 }
1377
1378 static u32
1379 ring_last_seqno(struct intel_ring_buffer *ring)
1380 {
1381         return list_entry(ring->request_list.prev,
1382                           struct drm_i915_gem_request, list)->seqno;
1383 }
1384
1385 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1386 {
1387         if (list_empty(&ring->request_list) ||
1388             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1389                 /* Issue a wake-up to catch stuck h/w. */
1390                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1391                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1392                                   ring->name,
1393                                   ring->waiting_seqno,
1394                                   ring->get_seqno(ring));
1395                         wake_up_all(&ring->irq_queue);
1396                         *err = true;
1397                 }
1398                 return true;
1399         }
1400         return false;
1401 }
1402
1403 /**
1404  * This is called when the chip hasn't reported back with completed
1405  * batchbuffers in a long time. The first time this is called we simply record
1406  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1407  * again, we assume the chip is wedged and try to fix it.
1408  */
1409 void i915_hangcheck_elapsed(unsigned long data)
1410 {
1411         struct drm_device *dev = (struct drm_device *)data;
1412         drm_i915_private_t *dev_priv = dev->dev_private;
1413         uint32_t acthd, instdone, instdone1;
1414         bool err = false;
1415
1416         /* If all work is done then ACTHD clearly hasn't advanced. */
1417         if (i915_hangcheck_ring_idle(&dev_priv->render_ring, &err) &&
1418             i915_hangcheck_ring_idle(&dev_priv->bsd_ring, &err) &&
1419             i915_hangcheck_ring_idle(&dev_priv->blt_ring, &err)) {
1420                 dev_priv->hangcheck_count = 0;
1421                 if (err)
1422                         goto repeat;
1423                 return;
1424         }
1425
1426         if (INTEL_INFO(dev)->gen < 4) {
1427                 acthd = I915_READ(ACTHD);
1428                 instdone = I915_READ(INSTDONE);
1429                 instdone1 = 0;
1430         } else {
1431                 acthd = I915_READ(ACTHD_I965);
1432                 instdone = I915_READ(INSTDONE_I965);
1433                 instdone1 = I915_READ(INSTDONE1);
1434         }
1435
1436         if (dev_priv->last_acthd == acthd &&
1437             dev_priv->last_instdone == instdone &&
1438             dev_priv->last_instdone1 == instdone1) {
1439                 if (dev_priv->hangcheck_count++ > 1) {
1440                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1441
1442                         if (!IS_GEN2(dev)) {
1443                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1444                                  * If so we can simply poke the RB_WAIT bit
1445                                  * and break the hang. This should work on
1446                                  * all but the second generation chipsets.
1447                                  */
1448                                 struct intel_ring_buffer *ring = &dev_priv->render_ring;
1449                                 u32 tmp = I915_READ_CTL(ring);
1450                                 if (tmp & RING_WAIT) {
1451                                         I915_WRITE_CTL(ring, tmp);
1452                                         goto repeat;
1453                                 }
1454                         }
1455
1456                         i915_handle_error(dev, true);
1457                         return;
1458                 }
1459         } else {
1460                 dev_priv->hangcheck_count = 0;
1461
1462                 dev_priv->last_acthd = acthd;
1463                 dev_priv->last_instdone = instdone;
1464                 dev_priv->last_instdone1 = instdone1;
1465         }
1466
1467 repeat:
1468         /* Reset timer case chip hangs without another request being added */
1469         mod_timer(&dev_priv->hangcheck_timer,
1470                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1471 }
1472
1473 /* drm_dma.h hooks
1474 */
1475 static void ironlake_irq_preinstall(struct drm_device *dev)
1476 {
1477         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1478
1479         I915_WRITE(HWSTAM, 0xeffe);
1480
1481         /* XXX hotplug from PCH */
1482
1483         I915_WRITE(DEIMR, 0xffffffff);
1484         I915_WRITE(DEIER, 0x0);
1485         POSTING_READ(DEIER);
1486
1487         /* and GT */
1488         I915_WRITE(GTIMR, 0xffffffff);
1489         I915_WRITE(GTIER, 0x0);
1490         POSTING_READ(GTIER);
1491
1492         /* south display irq */
1493         I915_WRITE(SDEIMR, 0xffffffff);
1494         I915_WRITE(SDEIER, 0x0);
1495         POSTING_READ(SDEIER);
1496 }
1497
1498 static int ironlake_irq_postinstall(struct drm_device *dev)
1499 {
1500         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1501         /* enable kind of interrupts always enabled */
1502         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1503                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1504         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1505         u32 hotplug_mask;
1506
1507         dev_priv->irq_mask_reg = ~display_mask;
1508         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1509
1510         /* should always can generate irq */
1511         I915_WRITE(DEIIR, I915_READ(DEIIR));
1512         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1513         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1514         POSTING_READ(DEIER);
1515
1516         if (IS_GEN6(dev)) {
1517                 render_mask =
1518                         GT_PIPE_NOTIFY |
1519                         GT_GEN6_BSD_USER_INTERRUPT |
1520                         GT_BLT_USER_INTERRUPT;
1521         }
1522
1523         dev_priv->gt_irq_mask_reg = ~render_mask;
1524         dev_priv->gt_irq_enable_reg = render_mask;
1525
1526         I915_WRITE(GTIIR, I915_READ(GTIIR));
1527         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1528         if (IS_GEN6(dev)) {
1529                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1530                 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1531                 I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT);
1532         }
1533
1534         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1535         POSTING_READ(GTIER);
1536
1537         if (HAS_PCH_CPT(dev)) {
1538                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1539                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1540         } else {
1541                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1542                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1543         }
1544
1545         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1546         dev_priv->pch_irq_enable_reg = hotplug_mask;
1547
1548         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1549         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1550         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1551         POSTING_READ(SDEIER);
1552
1553         if (IS_IRONLAKE_M(dev)) {
1554                 /* Clear & enable PCU event interrupts */
1555                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1556                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1557                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1558         }
1559
1560         return 0;
1561 }
1562
1563 void i915_driver_irq_preinstall(struct drm_device * dev)
1564 {
1565         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1566
1567         atomic_set(&dev_priv->irq_received, 0);
1568
1569         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1570         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1571
1572         if (HAS_PCH_SPLIT(dev)) {
1573                 ironlake_irq_preinstall(dev);
1574                 return;
1575         }
1576
1577         if (I915_HAS_HOTPLUG(dev)) {
1578                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1579                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1580         }
1581
1582         I915_WRITE(HWSTAM, 0xeffe);
1583         I915_WRITE(PIPEASTAT, 0);
1584         I915_WRITE(PIPEBSTAT, 0);
1585         I915_WRITE(IMR, 0xffffffff);
1586         I915_WRITE(IER, 0x0);
1587         POSTING_READ(IER);
1588 }
1589
1590 /*
1591  * Must be called after intel_modeset_init or hotplug interrupts won't be
1592  * enabled correctly.
1593  */
1594 int i915_driver_irq_postinstall(struct drm_device *dev)
1595 {
1596         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1597         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1598         u32 error_mask;
1599
1600         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1601         if (HAS_BSD(dev))
1602                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1603         if (HAS_BLT(dev))
1604                 DRM_INIT_WAITQUEUE(&dev_priv->blt_ring.irq_queue);
1605
1606         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1607
1608         if (HAS_PCH_SPLIT(dev))
1609                 return ironlake_irq_postinstall(dev);
1610
1611         /* Unmask the interrupts that we always want on. */
1612         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1613
1614         dev_priv->pipestat[0] = 0;
1615         dev_priv->pipestat[1] = 0;
1616
1617         if (I915_HAS_HOTPLUG(dev)) {
1618                 /* Enable in IER... */
1619                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1620                 /* and unmask in IMR */
1621                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1622         }
1623
1624         /*
1625          * Enable some error detection, note the instruction error mask
1626          * bit is reserved, so we leave it masked.
1627          */
1628         if (IS_G4X(dev)) {
1629                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1630                                GM45_ERROR_MEM_PRIV |
1631                                GM45_ERROR_CP_PRIV |
1632                                I915_ERROR_MEMORY_REFRESH);
1633         } else {
1634                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1635                                I915_ERROR_MEMORY_REFRESH);
1636         }
1637         I915_WRITE(EMR, error_mask);
1638
1639         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1640         I915_WRITE(IER, enable_mask);
1641         POSTING_READ(IER);
1642
1643         if (I915_HAS_HOTPLUG(dev)) {
1644                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1645
1646                 /* Note HDMI and DP share bits */
1647                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1648                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1649                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1650                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1651                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1652                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1653                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1654                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1655                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1656                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1657                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1658                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1659
1660                         /* Programming the CRT detection parameters tends
1661                            to generate a spurious hotplug event about three
1662                            seconds later.  So just do it once.
1663                         */
1664                         if (IS_G4X(dev))
1665                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1666                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1667                 }
1668
1669                 /* Ignore TV since it's buggy */
1670
1671                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1672         }
1673
1674         intel_opregion_enable_asle(dev);
1675
1676         return 0;
1677 }
1678
1679 static void ironlake_irq_uninstall(struct drm_device *dev)
1680 {
1681         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1682         I915_WRITE(HWSTAM, 0xffffffff);
1683
1684         I915_WRITE(DEIMR, 0xffffffff);
1685         I915_WRITE(DEIER, 0x0);
1686         I915_WRITE(DEIIR, I915_READ(DEIIR));
1687
1688         I915_WRITE(GTIMR, 0xffffffff);
1689         I915_WRITE(GTIER, 0x0);
1690         I915_WRITE(GTIIR, I915_READ(GTIIR));
1691 }
1692
1693 void i915_driver_irq_uninstall(struct drm_device * dev)
1694 {
1695         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1696
1697         if (!dev_priv)
1698                 return;
1699
1700         dev_priv->vblank_pipe = 0;
1701
1702         if (HAS_PCH_SPLIT(dev)) {
1703                 ironlake_irq_uninstall(dev);
1704                 return;
1705         }
1706
1707         if (I915_HAS_HOTPLUG(dev)) {
1708                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1709                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1710         }
1711
1712         I915_WRITE(HWSTAM, 0xffffffff);
1713         I915_WRITE(PIPEASTAT, 0);
1714         I915_WRITE(PIPEBSTAT, 0);
1715         I915_WRITE(IMR, 0xffffffff);
1716         I915_WRITE(IER, 0x0);
1717
1718         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1719         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1720         I915_WRITE(IIR, I915_READ(IIR));
1721 }