drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 POSTING_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 POSTING_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 static void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 POSTING_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 POSTING_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 POSTING_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 POSTING_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 POSTING_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 POSTING_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (INTEL_INFO(dev)->gen >= 4)
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 195 }
 196
 197 /* Called from drm generic code, passed a 'crtc', which
 198  * we use as a pipe index
 199  */
 200 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203         unsigned long high_frame;
 204         unsigned long low_frame;
 205         u32 high1, high2, low;
 206
 207         if (!i915_pipe_enabled(dev, pipe)) {
 208                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 209                                 "pipe %d\n", pipe);
 210                 return 0;
 211         }
 212
 213         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 214         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 215
 216         /*
 217          * High & low register fields aren't synchronized, so make sure
 218          * we get a low value that's stable across two reads of the high
 219          * register.
 220          */
 221         do {
 222                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 223                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 224                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 225         } while (high1 != high2);
 226
 227         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 228         low >>= PIPE_FRAME_LOW_SHIFT;
 229         return (high1 << 8) | low;
 230 }
 231
 232 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 233 {
 234         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 235         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 236
 237         if (!i915_pipe_enabled(dev, pipe)) {
 238                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 239                                         "pipe %d\n", pipe);
 240                 return 0;
 241         }
 242
 243         return I915_READ(reg);
 244 }
 245
 246 /*
 247  * Handle hotplug events outside the interrupt handler proper.
 248  */
 249 static void i915_hotplug_work_func(struct work_struct *work)
 250 {
 251         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 252                                                     hotplug_work);
 253         struct drm_device *dev = dev_priv->dev;
 254         struct drm_mode_config *mode_config = &dev->mode_config;
 255         struct intel_encoder *encoder;
 256
 257         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 258                 if (encoder->hot_plug)
 259                         encoder->hot_plug(encoder);
 260
 261         /* Just fire off a uevent and let userspace tell us what to do */
 262         drm_helper_hpd_irq_event(dev);
 263 }
 264
 265 static void i915_handle_rps_change(struct drm_device *dev)
 266 {
 267         drm_i915_private_t *dev_priv = dev->dev_private;
 268         u32 busy_up, busy_down, max_avg, min_avg;
 269         u8 new_delay = dev_priv->cur_delay;
 270
 271         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 272         busy_up = I915_READ(RCPREVBSYTUPAVG);
 273         busy_down = I915_READ(RCPREVBSYTDNAVG);
 274         max_avg = I915_READ(RCBMAXAVG);
 275         min_avg = I915_READ(RCBMINAVG);
 276
 277         /* Handle RCS change request from hw */
 278         if (busy_up > max_avg) {
 279                 if (dev_priv->cur_delay != dev_priv->max_delay)
 280                         new_delay = dev_priv->cur_delay - 1;
 281                 if (new_delay < dev_priv->max_delay)
 282                         new_delay = dev_priv->max_delay;
 283         } else if (busy_down < min_avg) {
 284                 if (dev_priv->cur_delay != dev_priv->min_delay)
 285                         new_delay = dev_priv->cur_delay + 1;
 286                 if (new_delay > dev_priv->min_delay)
 287                         new_delay = dev_priv->min_delay;
 288         }
 289
 290         if (ironlake_set_drps(dev, new_delay))
 291                 dev_priv->cur_delay = new_delay;
 292
 293         return;
 294 }
 295
 296 static void notify_ring(struct drm_device *dev,
 297                         struct intel_ring_buffer *ring)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         u32 seqno = ring->get_seqno(ring);
 301         ring->irq_seqno = seqno;
 302         trace_i915_gem_request_complete(dev, seqno);
 303         wake_up_all(&ring->irq_queue);
 304         dev_priv->hangcheck_count = 0;
 305         mod_timer(&dev_priv->hangcheck_timer,
 306                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
 307 }
 308
 309 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 310 {
 311         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 312         int ret = IRQ_NONE;
 313         u32 de_iir, gt_iir, de_ier, pch_iir;
 314         u32 hotplug_mask;
 315         struct drm_i915_master_private *master_priv;
 316         u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
 317
 318         if (IS_GEN6(dev))
 319                 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
 320
 321         /* disable master interrupt before clearing iir  */
 322         de_ier = I915_READ(DEIER);
 323         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 324         POSTING_READ(DEIER);
 325
 326         de_iir = I915_READ(DEIIR);
 327         gt_iir = I915_READ(GTIIR);
 328         pch_iir = I915_READ(SDEIIR);
 329
 330         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 331                 goto done;
 332
 333         if (HAS_PCH_CPT(dev))
 334                 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
 335         else
 336                 hotplug_mask = SDE_HOTPLUG_MASK;
 337
 338         ret = IRQ_HANDLED;
 339
 340         if (dev->primary->master) {
 341                 master_priv = dev->primary->master->driver_priv;
 342                 if (master_priv->sarea_priv)
 343                         master_priv->sarea_priv->last_dispatch =
 344                                 READ_BREADCRUMB(dev_priv);
 345         }
 346
 347         if (gt_iir & GT_PIPE_NOTIFY)
 348                 notify_ring(dev, &dev_priv->render_ring);
 349         if (gt_iir & bsd_usr_interrupt)
 350                 notify_ring(dev, &dev_priv->bsd_ring);
 351         if (HAS_BLT(dev) && gt_iir & GT_BLT_USER_INTERRUPT)
 352                 notify_ring(dev, &dev_priv->blt_ring);
 353
 354         if (de_iir & DE_GSE)
 355                 intel_opregion_gse_intr(dev);
 356
 357         if (de_iir & DE_PLANEA_FLIP_DONE) {
 358                 intel_prepare_page_flip(dev, 0);
 359                 intel_finish_page_flip_plane(dev, 0);
 360         }
 361
 362         if (de_iir & DE_PLANEB_FLIP_DONE) {
 363                 intel_prepare_page_flip(dev, 1);
 364                 intel_finish_page_flip_plane(dev, 1);
 365         }
 366
 367         if (de_iir & DE_PIPEA_VBLANK)
 368                 drm_handle_vblank(dev, 0);
 369
 370         if (de_iir & DE_PIPEB_VBLANK)
 371                 drm_handle_vblank(dev, 1);
 372
 373         /* check event from PCH */
 374         if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask))
 375                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 376
 377         if (de_iir & DE_PCU_EVENT) {
 378                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 379                 i915_handle_rps_change(dev);
 380         }
 381
 382         /* should clear PCH hotplug event before clear CPU irq */
 383         I915_WRITE(SDEIIR, pch_iir);
 384         I915_WRITE(GTIIR, gt_iir);
 385         I915_WRITE(DEIIR, de_iir);
 386
 387 done:
 388         I915_WRITE(DEIER, de_ier);
 389         POSTING_READ(DEIER);
 390
 391         return ret;
 392 }
 393
 394 /**
 395  * i915_error_work_func - do process context error handling work
 396  * @work: work struct
 397  *
 398  * Fire an error uevent so userspace can see that a hang or error
 399  * was detected.
 400  */
 401 static void i915_error_work_func(struct work_struct *work)
 402 {
 403         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 404                                                     error_work);
 405         struct drm_device *dev = dev_priv->dev;
 406         char *error_event[] = { "ERROR=1", NULL };
 407         char *reset_event[] = { "RESET=1", NULL };
 408         char *reset_done_event[] = { "ERROR=0", NULL };
 409
 410         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 411
 412         if (atomic_read(&dev_priv->mm.wedged)) {
 413                 DRM_DEBUG_DRIVER("resetting chip\n");
 414                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 415                 if (!i915_reset(dev, GRDOM_RENDER)) {
 416                         atomic_set(&dev_priv->mm.wedged, 0);
 417                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 418                 }
 419                 complete_all(&dev_priv->error_completion);
 420         }
 421 }
 422
 423 #ifdef CONFIG_DEBUG_FS
 424 static struct drm_i915_error_object *
 425 i915_error_object_create(struct drm_device *dev,
 426                          struct drm_gem_object *src)
 427 {
 428         drm_i915_private_t *dev_priv = dev->dev_private;
 429         struct drm_i915_error_object *dst;
 430         struct drm_i915_gem_object *src_priv;
 431         int page, page_count;
 432         u32 reloc_offset;
 433
 434         if (src == NULL)
 435                 return NULL;
 436
 437         src_priv = to_intel_bo(src);
 438         if (src_priv->pages == NULL)
 439                 return NULL;
 440
 441         page_count = src->size / PAGE_SIZE;
 442
 443         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 444         if (dst == NULL)
 445                 return NULL;
 446
 447         reloc_offset = src_priv->gtt_offset;
 448         for (page = 0; page < page_count; page++) {
 449                 unsigned long flags;
 450                 void __iomem *s;
 451                 void *d;
 452
 453                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 454                 if (d == NULL)
 455                         goto unwind;
 456
 457                 local_irq_save(flags);
 458                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 459                                              reloc_offset);
 460                 memcpy_fromio(d, s, PAGE_SIZE);
 461                 io_mapping_unmap_atomic(s);
 462                 local_irq_restore(flags);
 463
 464                 dst->pages[page] = d;
 465
 466                 reloc_offset += PAGE_SIZE;
 467         }
 468         dst->page_count = page_count;
 469         dst->gtt_offset = src_priv->gtt_offset;
 470
 471         return dst;
 472
 473 unwind:
 474         while (page--)
 475                 kfree(dst->pages[page]);
 476         kfree(dst);
 477         return NULL;
 478 }
 479
 480 static void
 481 i915_error_object_free(struct drm_i915_error_object *obj)
 482 {
 483         int page;
 484
 485         if (obj == NULL)
 486                 return;
 487
 488         for (page = 0; page < obj->page_count; page++)
 489                 kfree(obj->pages[page]);
 490
 491         kfree(obj);
 492 }
 493
 494 static void
 495 i915_error_state_free(struct drm_device *dev,
 496                       struct drm_i915_error_state *error)
 497 {
 498         i915_error_object_free(error->batchbuffer[0]);
 499         i915_error_object_free(error->batchbuffer[1]);
 500         i915_error_object_free(error->ringbuffer);
 501         kfree(error->active_bo);
 502         kfree(error->overlay);
 503         kfree(error);
 504 }
 505
 506 static u32
 507 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 508 {
 509         u32 cmd;
 510
 511         if (IS_I830(dev) || IS_845G(dev))
 512                 cmd = MI_BATCH_BUFFER;
 513         else if (INTEL_INFO(dev)->gen >= 4)
 514                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 515                        MI_BATCH_NON_SECURE_I965);
 516         else
 517                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 518
 519         return ring[0] == cmd ? ring[1] : 0;
 520 }
 521
 522 static u32
 523 i915_ringbuffer_last_batch(struct drm_device *dev,
 524                            struct intel_ring_buffer *ring)
 525 {
 526         struct drm_i915_private *dev_priv = dev->dev_private;
 527         u32 head, bbaddr;
 528         u32 *val;
 529
 530         /* Locate the current position in the ringbuffer and walk back
 531          * to find the most recently dispatched batch buffer.
 532          */
 533         bbaddr = 0;
 534         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 535         val = (u32 *)(ring->virtual_start + head);
 536
 537         while (--val >= (u32 *)ring->virtual_start) {
 538                 bbaddr = i915_get_bbaddr(dev, val);
 539                 if (bbaddr)
 540                         break;
 541         }
 542
 543         if (bbaddr == 0) {
 544                 val = (u32 *)(ring->virtual_start + ring->size);
 545                 while (--val >= (u32 *)ring->virtual_start) {
 546                         bbaddr = i915_get_bbaddr(dev, val);
 547                         if (bbaddr)
 548                                 break;
 549                 }
 550         }
 551
 552         return bbaddr;
 553 }
 554
 555 static u32 capture_bo_list(struct drm_i915_error_buffer *err,
 556                            int count,
 557                            struct list_head *head)
 558 {
 559         struct drm_i915_gem_object *obj;
 560         int i = 0;
 561
 562         list_for_each_entry(obj, head, mm_list) {
 563                 err->size = obj->base.size;
 564                 err->name = obj->base.name;
 565                 err->seqno = obj->last_rendering_seqno;
 566                 err->gtt_offset = obj->gtt_offset;
 567                 err->read_domains = obj->base.read_domains;
 568                 err->write_domain = obj->base.write_domain;
 569                 err->fence_reg = obj->fence_reg;
 570                 err->pinned = 0;
 571                 if (obj->pin_count > 0)
 572                         err->pinned = 1;
 573                 if (obj->user_pin_count > 0)
 574                         err->pinned = -1;
 575                 err->tiling = obj->tiling_mode;
 576                 err->dirty = obj->dirty;
 577                 err->purgeable = obj->madv != I915_MADV_WILLNEED;
 578                 err->ring = obj->ring ? obj->ring->id : 0;
 579
 580                 if (++i == count)
 581                         break;
 582
 583                 err++;
 584         }
 585
 586         return i;
 587 }
 588
 589 /**
 590  * i915_capture_error_state - capture an error record for later analysis
 591  * @dev: drm device
 592  *
 593  * Should be called when an error is detected (either a hang or an error
 594  * interrupt) to capture error state from the time of the error.  Fills
 595  * out a structure which becomes available in debugfs for user level tools
 596  * to pick up.
 597  */
 598 static void i915_capture_error_state(struct drm_device *dev)
 599 {
 600         struct drm_i915_private *dev_priv = dev->dev_private;
 601         struct drm_i915_gem_object *obj_priv;
 602         struct drm_i915_error_state *error;
 603         struct drm_gem_object *batchbuffer[2];
 604         unsigned long flags;
 605         u32 bbaddr;
 606         int count;
 607
 608         spin_lock_irqsave(&dev_priv->error_lock, flags);
 609         error = dev_priv->first_error;
 610         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 611         if (error)
 612                 return;
 613
 614         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 615         if (!error) {
 616                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 617                 return;
 618         }
 619
 620         DRM_DEBUG_DRIVER("generating error event\n");
 621
 622         error->seqno =
 623                 dev_priv->render_ring.get_seqno(&dev_priv->render_ring);
 624         error->eir = I915_READ(EIR);
 625         error->pgtbl_er = I915_READ(PGTBL_ER);
 626         error->pipeastat = I915_READ(PIPEASTAT);
 627         error->pipebstat = I915_READ(PIPEBSTAT);
 628         error->instpm = I915_READ(INSTPM);
 629         error->error = 0;
 630         if (INTEL_INFO(dev)->gen >= 6) {
 631                 error->error = I915_READ(ERROR_GEN6);
 632
 633                 error->bcs_acthd = I915_READ(BCS_ACTHD);
 634                 error->bcs_ipehr = I915_READ(BCS_IPEHR);
 635                 error->bcs_ipeir = I915_READ(BCS_IPEIR);
 636                 error->bcs_instdone = I915_READ(BCS_INSTDONE);
 637                 error->bcs_seqno = 0;
 638                 if (dev_priv->blt_ring.get_seqno)
 639                         error->bcs_seqno = dev_priv->blt_ring.get_seqno(&dev_priv->blt_ring);
 640
 641                 error->vcs_acthd = I915_READ(VCS_ACTHD);
 642                 error->vcs_ipehr = I915_READ(VCS_IPEHR);
 643                 error->vcs_ipeir = I915_READ(VCS_IPEIR);
 644                 error->vcs_instdone = I915_READ(VCS_INSTDONE);
 645                 error->vcs_seqno = 0;
 646                 if (dev_priv->bsd_ring.get_seqno)
 647                         error->vcs_seqno = dev_priv->bsd_ring.get_seqno(&dev_priv->bsd_ring);
 648         }
 649         if (INTEL_INFO(dev)->gen >= 4) {
 650                 error->ipeir = I915_READ(IPEIR_I965);
 651                 error->ipehr = I915_READ(IPEHR_I965);
 652                 error->instdone = I915_READ(INSTDONE_I965);
 653                 error->instps = I915_READ(INSTPS);
 654                 error->instdone1 = I915_READ(INSTDONE1);
 655                 error->acthd = I915_READ(ACTHD_I965);
 656                 error->bbaddr = I915_READ64(BB_ADDR);
 657         } else {
 658                 error->ipeir = I915_READ(IPEIR);
 659                 error->ipehr = I915_READ(IPEHR);
 660                 error->instdone = I915_READ(INSTDONE);
 661                 error->acthd = I915_READ(ACTHD);
 662                 error->bbaddr = 0;
 663         }
 664
 665         bbaddr = i915_ringbuffer_last_batch(dev, &dev_priv->render_ring);
 666
 667         /* Grab the current batchbuffer, most likely to have crashed. */
 668         batchbuffer[0] = NULL;
 669         batchbuffer[1] = NULL;
 670         count = 0;
 671         list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) {
 672                 struct drm_gem_object *obj = &obj_priv->base;
 673
 674                 if (batchbuffer[0] == NULL &&
 675                     bbaddr >= obj_priv->gtt_offset &&
 676                     bbaddr < obj_priv->gtt_offset + obj->size)
 677                         batchbuffer[0] = obj;
 678
 679                 if (batchbuffer[1] == NULL &&
 680                     error->acthd >= obj_priv->gtt_offset &&
 681                     error->acthd < obj_priv->gtt_offset + obj->size)
 682                         batchbuffer[1] = obj;
 683
 684                 count++;
 685         }
 686         /* Scan the other lists for completeness for those bizarre errors. */
 687         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 688                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, mm_list) {
 689                         struct drm_gem_object *obj = &obj_priv->base;
 690
 691                         if (batchbuffer[0] == NULL &&
 692                             bbaddr >= obj_priv->gtt_offset &&
 693                             bbaddr < obj_priv->gtt_offset + obj->size)
 694                                 batchbuffer[0] = obj;
 695
 696                         if (batchbuffer[1] == NULL &&
 697                             error->acthd >= obj_priv->gtt_offset &&
 698                             error->acthd < obj_priv->gtt_offset + obj->size)
 699                                 batchbuffer[1] = obj;
 700
 701                         if (batchbuffer[0] && batchbuffer[1])
 702                                 break;
 703                 }
 704         }
 705         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 706                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, mm_list) {
 707                         struct drm_gem_object *obj = &obj_priv->base;
 708
 709                         if (batchbuffer[0] == NULL &&
 710                             bbaddr >= obj_priv->gtt_offset &&
 711                             bbaddr < obj_priv->gtt_offset + obj->size)
 712                                 batchbuffer[0] = obj;
 713
 714                         if (batchbuffer[1] == NULL &&
 715                             error->acthd >= obj_priv->gtt_offset &&
 716                             error->acthd < obj_priv->gtt_offset + obj->size)
 717                                 batchbuffer[1] = obj;
 718
 719                         if (batchbuffer[0] && batchbuffer[1])
 720                                 break;
 721                 }
 722         }
 723
 724         /* We need to copy these to an anonymous buffer as the simplest
 725          * method to avoid being overwritten by userspace.
 726          */
 727         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 728         if (batchbuffer[1] != batchbuffer[0])
 729                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 730         else
 731                 error->batchbuffer[1] = NULL;
 732
 733         /* Record the ringbuffer */
 734         error->ringbuffer = i915_error_object_create(dev,
 735                         dev_priv->render_ring.gem_object);
 736
 737         /* Record buffers on the active and pinned lists. */
 738         error->active_bo = NULL;
 739         error->pinned_bo = NULL;
 740
 741         error->active_bo_count = count;
 742         list_for_each_entry(obj_priv, &dev_priv->mm.pinned_list, mm_list)
 743                 count++;
 744         error->pinned_bo_count = count - error->active_bo_count;
 745
 746         if (count) {
 747                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 748                                            GFP_ATOMIC);
 749                 if (error->active_bo)
 750                         error->pinned_bo =
 751                                 error->active_bo + error->active_bo_count;
 752         }
 753
 754         if (error->active_bo)
 755                 error->active_bo_count =
 756                         capture_bo_list(error->active_bo,
 757                                         error->active_bo_count,
 758                                         &dev_priv->mm.active_list);
 759
 760         if (error->pinned_bo)
 761                 error->pinned_bo_count =
 762                         capture_bo_list(error->pinned_bo,
 763                                         error->pinned_bo_count,
 764                                         &dev_priv->mm.pinned_list);
 765
 766         do_gettimeofday(&error->time);
 767
 768         error->overlay = intel_overlay_capture_error_state(dev);
 769         error->display = intel_display_capture_error_state(dev);
 770
 771         spin_lock_irqsave(&dev_priv->error_lock, flags);
 772         if (dev_priv->first_error == NULL) {
 773                 dev_priv->first_error = error;
 774                 error = NULL;
 775         }
 776         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 777
 778         if (error)
 779                 i915_error_state_free(dev, error);
 780 }
 781
 782 void i915_destroy_error_state(struct drm_device *dev)
 783 {
 784         struct drm_i915_private *dev_priv = dev->dev_private;
 785         struct drm_i915_error_state *error;
 786
 787         spin_lock(&dev_priv->error_lock);
 788         error = dev_priv->first_error;
 789         dev_priv->first_error = NULL;
 790         spin_unlock(&dev_priv->error_lock);
 791
 792         if (error)
 793                 i915_error_state_free(dev, error);
 794 }
 795 #else
 796 #define i915_capture_error_state(x)
 797 #endif
 798
 799 static void i915_report_and_clear_eir(struct drm_device *dev)
 800 {
 801         struct drm_i915_private *dev_priv = dev->dev_private;
 802         u32 eir = I915_READ(EIR);
 803
 804         if (!eir)
 805                 return;
 806
 807         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 808                eir);
 809
 810         if (IS_G4X(dev)) {
 811                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 812                         u32 ipeir = I915_READ(IPEIR_I965);
 813
 814                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 815                                I915_READ(IPEIR_I965));
 816                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 817                                I915_READ(IPEHR_I965));
 818                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 819                                I915_READ(INSTDONE_I965));
 820                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 821                                I915_READ(INSTPS));
 822                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 823                                I915_READ(INSTDONE1));
 824                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 825                                I915_READ(ACTHD_I965));
 826                         I915_WRITE(IPEIR_I965, ipeir);
 827                         POSTING_READ(IPEIR_I965);
 828                 }
 829                 if (eir & GM45_ERROR_PAGE_TABLE) {
 830                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 831                         printk(KERN_ERR "page table error\n");
 832                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 833                                pgtbl_err);
 834                         I915_WRITE(PGTBL_ER, pgtbl_err);
 835                         POSTING_READ(PGTBL_ER);
 836                 }
 837         }
 838
 839         if (!IS_GEN2(dev)) {
 840                 if (eir & I915_ERROR_PAGE_TABLE) {
 841                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 842                         printk(KERN_ERR "page table error\n");
 843                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 844                                pgtbl_err);
 845                         I915_WRITE(PGTBL_ER, pgtbl_err);
 846                         POSTING_READ(PGTBL_ER);
 847                 }
 848         }
 849
 850         if (eir & I915_ERROR_MEMORY_REFRESH) {
 851                 u32 pipea_stats = I915_READ(PIPEASTAT);
 852                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 853
 854                 printk(KERN_ERR "memory refresh error\n");
 855                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 856                        pipea_stats);
 857                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 858                        pipeb_stats);
 859                 /* pipestat has already been acked */
 860         }
 861         if (eir & I915_ERROR_INSTRUCTION) {
 862                 printk(KERN_ERR "instruction error\n");
 863                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 864                        I915_READ(INSTPM));
 865                 if (INTEL_INFO(dev)->gen < 4) {
 866                         u32 ipeir = I915_READ(IPEIR);
 867
 868                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 869                                I915_READ(IPEIR));
 870                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 871                                I915_READ(IPEHR));
 872                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 873                                I915_READ(INSTDONE));
 874                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 875                                I915_READ(ACTHD));
 876                         I915_WRITE(IPEIR, ipeir);
 877                         POSTING_READ(IPEIR);
 878                 } else {
 879                         u32 ipeir = I915_READ(IPEIR_I965);
 880
 881                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 882                                I915_READ(IPEIR_I965));
 883                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 884                                I915_READ(IPEHR_I965));
 885                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 886                                I915_READ(INSTDONE_I965));
 887                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 888                                I915_READ(INSTPS));
 889                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 890                                I915_READ(INSTDONE1));
 891                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 892                                I915_READ(ACTHD_I965));
 893                         I915_WRITE(IPEIR_I965, ipeir);
 894                         POSTING_READ(IPEIR_I965);
 895                 }
 896         }
 897
 898         I915_WRITE(EIR, eir);
 899         POSTING_READ(EIR);
 900         eir = I915_READ(EIR);
 901         if (eir) {
 902                 /*
 903                  * some errors might have become stuck,
 904                  * mask them.
 905                  */
 906                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 907                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 908                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 909         }
 910 }
 911
 912 /**
 913  * i915_handle_error - handle an error interrupt
 914  * @dev: drm device
 915  *
 916  * Do some basic checking of regsiter state at error interrupt time and
 917  * dump it to the syslog.  Also call i915_capture_error_state() to make
 918  * sure we get a record and make it available in debugfs.  Fire a uevent
 919  * so userspace knows something bad happened (should trigger collection
 920  * of a ring dump etc.).
 921  */
 922 void i915_handle_error(struct drm_device *dev, bool wedged)
 923 {
 924         struct drm_i915_private *dev_priv = dev->dev_private;
 925
 926         i915_capture_error_state(dev);
 927         i915_report_and_clear_eir(dev);
 928
 929         if (wedged) {
 930                 INIT_COMPLETION(dev_priv->error_completion);
 931                 atomic_set(&dev_priv->mm.wedged, 1);
 932
 933                 /*
 934                  * Wakeup waiting processes so they don't hang
 935                  */
 936                 wake_up_all(&dev_priv->render_ring.irq_queue);
 937                 if (HAS_BSD(dev))
 938                         wake_up_all(&dev_priv->bsd_ring.irq_queue);
 939                 if (HAS_BLT(dev))
 940                         wake_up_all(&dev_priv->blt_ring.irq_queue);
 941         }
 942
 943         queue_work(dev_priv->wq, &dev_priv->error_work);
 944 }
 945
 946 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 947 {
 948         drm_i915_private_t *dev_priv = dev->dev_private;
 949         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 950         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 951         struct drm_i915_gem_object *obj_priv;
 952         struct intel_unpin_work *work;
 953         unsigned long flags;
 954         bool stall_detected;
 955
 956         /* Ignore early vblank irqs */
 957         if (intel_crtc == NULL)
 958                 return;
 959
 960         spin_lock_irqsave(&dev->event_lock, flags);
 961         work = intel_crtc->unpin_work;
 962
 963         if (work == NULL || work->pending || !work->enable_stall_check) {
 964                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 965                 spin_unlock_irqrestore(&dev->event_lock, flags);
 966                 return;
 967         }
 968
 969         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 970         obj_priv = to_intel_bo(work->pending_flip_obj);
 971         if (INTEL_INFO(dev)->gen >= 4) {
 972                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 973                 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
 974         } else {
 975                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 976                 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
 977                                                         crtc->y * crtc->fb->pitch +
 978                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 979         }
 980
 981         spin_unlock_irqrestore(&dev->event_lock, flags);
 982
 983         if (stall_detected) {
 984                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 985                 intel_prepare_page_flip(dev, intel_crtc->plane);
 986         }
 987 }
 988
 989 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 990 {
 991         struct drm_device *dev = (struct drm_device *) arg;
 992         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 993         struct drm_i915_master_private *master_priv;
 994         u32 iir, new_iir;
 995         u32 pipea_stats, pipeb_stats;
 996         u32 vblank_status;
 997         int vblank = 0;
 998         unsigned long irqflags;
 999         int irq_received;
1000         int ret = IRQ_NONE;
1001
1002         atomic_inc(&dev_priv->irq_received);
1003
1004         if (HAS_PCH_SPLIT(dev))
1005                 return ironlake_irq_handler(dev);
1006
1007         iir = I915_READ(IIR);
1008
1009         if (INTEL_INFO(dev)->gen >= 4)
1010                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
1011         else
1012                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
1013
1014         for (;;) {
1015                 irq_received = iir != 0;
1016
1017                 /* Can't rely on pipestat interrupt bit in iir as it might
1018                  * have been cleared after the pipestat interrupt was received.
1019                  * It doesn't set the bit in iir again, but it still produces
1020                  * interrupts (for non-MSI).
1021                  */
1022                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1023                 pipea_stats = I915_READ(PIPEASTAT);
1024                 pipeb_stats = I915_READ(PIPEBSTAT);
1025
1026                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
1027                         i915_handle_error(dev, false);
1028
1029                 /*
1030                  * Clear the PIPE(A|B)STAT regs before the IIR
1031                  */
1032                 if (pipea_stats & 0x8000ffff) {
1033                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1034                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
1035                         I915_WRITE(PIPEASTAT, pipea_stats);
1036                         irq_received = 1;
1037                 }
1038
1039                 if (pipeb_stats & 0x8000ffff) {
1040                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
1041                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
1042                         I915_WRITE(PIPEBSTAT, pipeb_stats);
1043                         irq_received = 1;
1044                 }
1045                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1046
1047                 if (!irq_received)
1048                         break;
1049
1050                 ret = IRQ_HANDLED;
1051
1052                 /* Consume port.  Then clear IIR or we'll miss events */
1053                 if ((I915_HAS_HOTPLUG(dev)) &&
1054                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1055                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1056
1057                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1058                                   hotplug_status);
1059                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1060                                 queue_work(dev_priv->wq,
1061                                            &dev_priv->hotplug_work);
1062
1063                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1064                         I915_READ(PORT_HOTPLUG_STAT);
1065                 }
1066
1067                 I915_WRITE(IIR, iir);
1068                 new_iir = I915_READ(IIR); /* Flush posted writes */
1069
1070                 if (dev->primary->master) {
1071                         master_priv = dev->primary->master->driver_priv;
1072                         if (master_priv->sarea_priv)
1073                                 master_priv->sarea_priv->last_dispatch =
1074                                         READ_BREADCRUMB(dev_priv);
1075                 }
1076
1077                 if (iir & I915_USER_INTERRUPT)
1078                         notify_ring(dev, &dev_priv->render_ring);
1079                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1080                         notify_ring(dev, &dev_priv->bsd_ring);
1081
1082                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1083                         intel_prepare_page_flip(dev, 0);
1084                         if (dev_priv->flip_pending_is_done)
1085                                 intel_finish_page_flip_plane(dev, 0);
1086                 }
1087
1088                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1089                         intel_prepare_page_flip(dev, 1);
1090                         if (dev_priv->flip_pending_is_done)
1091                                 intel_finish_page_flip_plane(dev, 1);
1092                 }
1093
1094                 if (pipea_stats & vblank_status) {
1095                         vblank++;
1096                         drm_handle_vblank(dev, 0);
1097                         if (!dev_priv->flip_pending_is_done) {
1098                                 i915_pageflip_stall_check(dev, 0);
1099                                 intel_finish_page_flip(dev, 0);
1100                         }
1101                 }
1102
1103                 if (pipeb_stats & vblank_status) {
1104                         vblank++;
1105                         drm_handle_vblank(dev, 1);
1106                         if (!dev_priv->flip_pending_is_done) {
1107                                 i915_pageflip_stall_check(dev, 1);
1108                                 intel_finish_page_flip(dev, 1);
1109                         }
1110                 }
1111
1112                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1113                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1114                     (iir & I915_ASLE_INTERRUPT))
1115                         intel_opregion_asle_intr(dev);
1116
1117                 /* With MSI, interrupts are only generated when iir
1118                  * transitions from zero to nonzero.  If another bit got
1119                  * set while we were handling the existing iir bits, then
1120                  * we would never get another interrupt.
1121                  *
1122                  * This is fine on non-MSI as well, as if we hit this path
1123                  * we avoid exiting the interrupt handler only to generate
1124                  * another one.
1125                  *
1126                  * Note that for MSI this could cause a stray interrupt report
1127                  * if an interrupt landed in the time between writing IIR and
1128                  * the posting read.  This should be rare enough to never
1129                  * trigger the 99% of 100,000 interrupts test for disabling
1130                  * stray interrupts.
1131                  */
1132                 iir = new_iir;
1133         }
1134
1135         return ret;
1136 }
1137
1138 static int i915_emit_irq(struct drm_device * dev)
1139 {
1140         drm_i915_private_t *dev_priv = dev->dev_private;
1141         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1142
1143         i915_kernel_lost_context(dev);
1144
1145         DRM_DEBUG_DRIVER("\n");
1146
1147         dev_priv->counter++;
1148         if (dev_priv->counter > 0x7FFFFFFFUL)
1149                 dev_priv->counter = 1;
1150         if (master_priv->sarea_priv)
1151                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1152
1153         if (BEGIN_LP_RING(4) == 0) {
1154                 OUT_RING(MI_STORE_DWORD_INDEX);
1155                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1156                 OUT_RING(dev_priv->counter);
1157                 OUT_RING(MI_USER_INTERRUPT);
1158                 ADVANCE_LP_RING();
1159         }
1160
1161         return dev_priv->counter;
1162 }
1163
1164 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1165 {
1166         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1167         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1168
1169         if (dev_priv->trace_irq_seqno == 0)
1170                 render_ring->user_irq_get(render_ring);
1171
1172         dev_priv->trace_irq_seqno = seqno;
1173 }
1174
1175 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1176 {
1177         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1178         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1179         int ret = 0;
1180         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1181
1182         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1183                   READ_BREADCRUMB(dev_priv));
1184
1185         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1186                 if (master_priv->sarea_priv)
1187                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1188                 return 0;
1189         }
1190
1191         if (master_priv->sarea_priv)
1192                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1193
1194         render_ring->user_irq_get(render_ring);
1195         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1196                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1197         render_ring->user_irq_put(render_ring);
1198
1199         if (ret == -EBUSY) {
1200                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1201                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1202         }
1203
1204         return ret;
1205 }
1206
1207 /* Needs the lock as it touches the ring.
1208  */
1209 int i915_irq_emit(struct drm_device *dev, void *data,
1210                          struct drm_file *file_priv)
1211 {
1212         drm_i915_private_t *dev_priv = dev->dev_private;
1213         drm_i915_irq_emit_t *emit = data;
1214         int result;
1215
1216         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1217                 DRM_ERROR("called with no initialization\n");
1218                 return -EINVAL;
1219         }
1220
1221         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1222
1223         mutex_lock(&dev->struct_mutex);
1224         result = i915_emit_irq(dev);
1225         mutex_unlock(&dev->struct_mutex);
1226
1227         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1228                 DRM_ERROR("copy_to_user\n");
1229                 return -EFAULT;
1230         }
1231
1232         return 0;
1233 }
1234
1235 /* Doesn't need the hardware lock.
1236  */
1237 int i915_irq_wait(struct drm_device *dev, void *data,
1238                          struct drm_file *file_priv)
1239 {
1240         drm_i915_private_t *dev_priv = dev->dev_private;
1241         drm_i915_irq_wait_t *irqwait = data;
1242
1243         if (!dev_priv) {
1244                 DRM_ERROR("called with no initialization\n");
1245                 return -EINVAL;
1246         }
1247
1248         return i915_wait_irq(dev, irqwait->irq_seq);
1249 }
1250
1251 /* Called from drm generic code, passed 'crtc' which
1252  * we use as a pipe index
1253  */
1254 int i915_enable_vblank(struct drm_device *dev, int pipe)
1255 {
1256         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1257         unsigned long irqflags;
1258
1259         if (!i915_pipe_enabled(dev, pipe))
1260                 return -EINVAL;
1261
1262         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1263         if (HAS_PCH_SPLIT(dev))
1264                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1265                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1266         else if (INTEL_INFO(dev)->gen >= 4)
1267                 i915_enable_pipestat(dev_priv, pipe,
1268                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1269         else
1270                 i915_enable_pipestat(dev_priv, pipe,
1271                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1272         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1273         return 0;
1274 }
1275
1276 /* Called from drm generic code, passed 'crtc' which
1277  * we use as a pipe index
1278  */
1279 void i915_disable_vblank(struct drm_device *dev, int pipe)
1280 {
1281         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1282         unsigned long irqflags;
1283
1284         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1285         if (HAS_PCH_SPLIT(dev))
1286                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1287                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1288         else
1289                 i915_disable_pipestat(dev_priv, pipe,
1290                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1291                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1292         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1293 }
1294
1295 void i915_enable_interrupt (struct drm_device *dev)
1296 {
1297         struct drm_i915_private *dev_priv = dev->dev_private;
1298
1299         if (!HAS_PCH_SPLIT(dev))
1300                 intel_opregion_enable_asle(dev);
1301         dev_priv->irq_enabled = 1;
1302 }
1303
1304
1305 /* Set the vblank monitor pipe
1306  */
1307 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1308                          struct drm_file *file_priv)
1309 {
1310         drm_i915_private_t *dev_priv = dev->dev_private;
1311
1312         if (!dev_priv) {
1313                 DRM_ERROR("called with no initialization\n");
1314                 return -EINVAL;
1315         }
1316
1317         return 0;
1318 }
1319
1320 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1321                          struct drm_file *file_priv)
1322 {
1323         drm_i915_private_t *dev_priv = dev->dev_private;
1324         drm_i915_vblank_pipe_t *pipe = data;
1325
1326         if (!dev_priv) {
1327                 DRM_ERROR("called with no initialization\n");
1328                 return -EINVAL;
1329         }
1330
1331         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1332
1333         return 0;
1334 }
1335
1336 /**
1337  * Schedule buffer swap at given vertical blank.
1338  */
1339 int i915_vblank_swap(struct drm_device *dev, void *data,
1340                      struct drm_file *file_priv)
1341 {
1342         /* The delayed swap mechanism was fundamentally racy, and has been
1343          * removed.  The model was that the client requested a delayed flip/swap
1344          * from the kernel, then waited for vblank before continuing to perform
1345          * rendering.  The problem was that the kernel might wake the client
1346          * up before it dispatched the vblank swap (since the lock has to be
1347          * held while touching the ringbuffer), in which case the client would
1348          * clear and start the next frame before the swap occurred, and
1349          * flicker would occur in addition to likely missing the vblank.
1350          *
1351          * In the absence of this ioctl, userland falls back to a correct path
1352          * of waiting for a vblank, then dispatching the swap on its own.
1353          * Context switching to userland and back is plenty fast enough for
1354          * meeting the requirements of vblank swapping.
1355          */
1356         return -EINVAL;
1357 }
1358
1359 static u32
1360 ring_last_seqno(struct intel_ring_buffer *ring)
1361 {
1362         return list_entry(ring->request_list.prev,
1363                           struct drm_i915_gem_request, list)->seqno;
1364 }
1365
1366 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1367 {
1368         if (list_empty(&ring->request_list) ||
1369             i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1370                 /* Issue a wake-up to catch stuck h/w. */
1371                 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
1372                         DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1373                                   ring->name,
1374                                   ring->waiting_seqno,
1375                                   ring->get_seqno(ring));
1376                         wake_up_all(&ring->irq_queue);
1377                         *err = true;
1378                 }
1379                 return true;
1380         }
1381         return false;
1382 }
1383
1384 /**
1385  * This is called when the chip hasn't reported back with completed
1386  * batchbuffers in a long time. The first time this is called we simply record
1387  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1388  * again, we assume the chip is wedged and try to fix it.
1389  */
1390 void i915_hangcheck_elapsed(unsigned long data)
1391 {
1392         struct drm_device *dev = (struct drm_device *)data;
1393         drm_i915_private_t *dev_priv = dev->dev_private;
1394         uint32_t acthd, instdone, instdone1;
1395         bool err = false;
1396
1397         /* If all work is done then ACTHD clearly hasn't advanced. */
1398         if (i915_hangcheck_ring_idle(&dev_priv->render_ring, &err) &&
1399             i915_hangcheck_ring_idle(&dev_priv->bsd_ring, &err) &&
1400             i915_hangcheck_ring_idle(&dev_priv->blt_ring, &err)) {
1401                 dev_priv->hangcheck_count = 0;
1402                 if (err)
1403                         goto repeat;
1404                 return;
1405         }
1406
1407         if (INTEL_INFO(dev)->gen < 4) {
1408                 acthd = I915_READ(ACTHD);
1409                 instdone = I915_READ(INSTDONE);
1410                 instdone1 = 0;
1411         } else {
1412                 acthd = I915_READ(ACTHD_I965);
1413                 instdone = I915_READ(INSTDONE_I965);
1414                 instdone1 = I915_READ(INSTDONE1);
1415         }
1416
1417         if (dev_priv->last_acthd == acthd &&
1418             dev_priv->last_instdone == instdone &&
1419             dev_priv->last_instdone1 == instdone1) {
1420                 if (dev_priv->hangcheck_count++ > 1) {
1421                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1422
1423                         if (!IS_GEN2(dev)) {
1424                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1425                                  * If so we can simply poke the RB_WAIT bit
1426                                  * and break the hang. This should work on
1427                                  * all but the second generation chipsets.
1428                                  */
1429                                 struct intel_ring_buffer *ring = &dev_priv->render_ring;
1430                                 u32 tmp = I915_READ_CTL(ring);
1431                                 if (tmp & RING_WAIT) {
1432                                         I915_WRITE_CTL(ring, tmp);
1433                                         goto repeat;
1434                                 }
1435                         }
1436
1437                         i915_handle_error(dev, true);
1438                         return;
1439                 }
1440         } else {
1441                 dev_priv->hangcheck_count = 0;
1442
1443                 dev_priv->last_acthd = acthd;
1444                 dev_priv->last_instdone = instdone;
1445                 dev_priv->last_instdone1 = instdone1;
1446         }
1447
1448 repeat:
1449         /* Reset timer case chip hangs without another request being added */
1450         mod_timer(&dev_priv->hangcheck_timer,
1451                   jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1452 }
1453
1454 /* drm_dma.h hooks
1455 */
1456 static void ironlake_irq_preinstall(struct drm_device *dev)
1457 {
1458         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1459
1460         I915_WRITE(HWSTAM, 0xeffe);
1461
1462         /* XXX hotplug from PCH */
1463
1464         I915_WRITE(DEIMR, 0xffffffff);
1465         I915_WRITE(DEIER, 0x0);
1466         POSTING_READ(DEIER);
1467
1468         /* and GT */
1469         I915_WRITE(GTIMR, 0xffffffff);
1470         I915_WRITE(GTIER, 0x0);
1471         POSTING_READ(GTIER);
1472
1473         /* south display irq */
1474         I915_WRITE(SDEIMR, 0xffffffff);
1475         I915_WRITE(SDEIER, 0x0);
1476         POSTING_READ(SDEIER);
1477 }
1478
1479 static int ironlake_irq_postinstall(struct drm_device *dev)
1480 {
1481         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1482         /* enable kind of interrupts always enabled */
1483         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1484                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1485         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1486         u32 hotplug_mask;
1487
1488         dev_priv->irq_mask_reg = ~display_mask;
1489         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1490
1491         /* should always can generate irq */
1492         I915_WRITE(DEIIR, I915_READ(DEIIR));
1493         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1494         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1495         POSTING_READ(DEIER);
1496
1497         if (IS_GEN6(dev)) {
1498                 render_mask =
1499                         GT_PIPE_NOTIFY |
1500                         GT_GEN6_BSD_USER_INTERRUPT |
1501                         GT_BLT_USER_INTERRUPT;
1502         }
1503
1504         dev_priv->gt_irq_mask_reg = ~render_mask;
1505         dev_priv->gt_irq_enable_reg = render_mask;
1506
1507         I915_WRITE(GTIIR, I915_READ(GTIIR));
1508         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1509         if (IS_GEN6(dev)) {
1510                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1511                 I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT);
1512                 I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT);
1513         }
1514
1515         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1516         POSTING_READ(GTIER);
1517
1518         if (HAS_PCH_CPT(dev)) {
1519                 hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT  |
1520                                SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ;
1521         } else {
1522                 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1523                                SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1524         }
1525
1526         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1527         dev_priv->pch_irq_enable_reg = hotplug_mask;
1528
1529         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1530         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1531         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1532         POSTING_READ(SDEIER);
1533
1534         if (IS_IRONLAKE_M(dev)) {
1535                 /* Clear & enable PCU event interrupts */
1536                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1537                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1538                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1539         }
1540
1541         return 0;
1542 }
1543
1544 void i915_driver_irq_preinstall(struct drm_device * dev)
1545 {
1546         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1547
1548         atomic_set(&dev_priv->irq_received, 0);
1549
1550         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1551         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1552
1553         if (HAS_PCH_SPLIT(dev)) {
1554                 ironlake_irq_preinstall(dev);
1555                 return;
1556         }
1557
1558         if (I915_HAS_HOTPLUG(dev)) {
1559                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1560                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1561         }
1562
1563         I915_WRITE(HWSTAM, 0xeffe);
1564         I915_WRITE(PIPEASTAT, 0);
1565         I915_WRITE(PIPEBSTAT, 0);
1566         I915_WRITE(IMR, 0xffffffff);
1567         I915_WRITE(IER, 0x0);
1568         POSTING_READ(IER);
1569 }
1570
1571 /*
1572  * Must be called after intel_modeset_init or hotplug interrupts won't be
1573  * enabled correctly.
1574  */
1575 int i915_driver_irq_postinstall(struct drm_device *dev)
1576 {
1577         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1578         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1579         u32 error_mask;
1580
1581         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1582         if (HAS_BSD(dev))
1583                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1584         if (HAS_BLT(dev))
1585                 DRM_INIT_WAITQUEUE(&dev_priv->blt_ring.irq_queue);
1586
1587         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1588
1589         if (HAS_PCH_SPLIT(dev))
1590                 return ironlake_irq_postinstall(dev);
1591
1592         /* Unmask the interrupts that we always want on. */
1593         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1594
1595         dev_priv->pipestat[0] = 0;
1596         dev_priv->pipestat[1] = 0;
1597
1598         if (I915_HAS_HOTPLUG(dev)) {
1599                 /* Enable in IER... */
1600                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1601                 /* and unmask in IMR */
1602                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1603         }
1604
1605         /*
1606          * Enable some error detection, note the instruction error mask
1607          * bit is reserved, so we leave it masked.
1608          */
1609         if (IS_G4X(dev)) {
1610                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1611                                GM45_ERROR_MEM_PRIV |
1612                                GM45_ERROR_CP_PRIV |
1613                                I915_ERROR_MEMORY_REFRESH);
1614         } else {
1615                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1616                                I915_ERROR_MEMORY_REFRESH);
1617         }
1618         I915_WRITE(EMR, error_mask);
1619
1620         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1621         I915_WRITE(IER, enable_mask);
1622         POSTING_READ(IER);
1623
1624         if (I915_HAS_HOTPLUG(dev)) {
1625                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1626
1627                 /* Note HDMI and DP share bits */
1628                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1629                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1630                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1631                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1632                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1633                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1634                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1635                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1636                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1637                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1638                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1639                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1640
1641                         /* Programming the CRT detection parameters tends
1642                            to generate a spurious hotplug event about three
1643                            seconds later.  So just do it once.
1644                         */
1645                         if (IS_G4X(dev))
1646                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1647                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1648                 }
1649
1650                 /* Ignore TV since it's buggy */
1651
1652                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1653         }
1654
1655         intel_opregion_enable_asle(dev);
1656
1657         return 0;
1658 }
1659
1660 static void ironlake_irq_uninstall(struct drm_device *dev)
1661 {
1662         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1663         I915_WRITE(HWSTAM, 0xffffffff);
1664
1665         I915_WRITE(DEIMR, 0xffffffff);
1666         I915_WRITE(DEIER, 0x0);
1667         I915_WRITE(DEIIR, I915_READ(DEIIR));
1668
1669         I915_WRITE(GTIMR, 0xffffffff);
1670         I915_WRITE(GTIER, 0x0);
1671         I915_WRITE(GTIIR, I915_READ(GTIIR));
1672 }
1673
1674 void i915_driver_irq_uninstall(struct drm_device * dev)
1675 {
1676         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1677
1678         if (!dev_priv)
1679                 return;
1680
1681         dev_priv->vblank_pipe = 0;
1682
1683         if (HAS_PCH_SPLIT(dev)) {
1684                 ironlake_irq_uninstall(dev);
1685                 return;
1686         }
1687
1688         if (I915_HAS_HOTPLUG(dev)) {
1689                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1690                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1691         }
1692
1693         I915_WRITE(HWSTAM, 0xffffffff);
1694         I915_WRITE(PIPEASTAT, 0);
1695         I915_WRITE(PIPEBSTAT, 0);
1696         I915_WRITE(IMR, 0xffffffff);
1697         I915_WRITE(IER, 0x0);
1698
1699         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1700         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1701         I915_WRITE(IIR, I915_READ(IIR));
1702 }