drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 static void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (IS_I965G(dev))
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 195
 196         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 197                 return 1;
 198
 199         return 0;
 200 }
 201
 202 /* Called from drm generic code, passed a 'crtc', which
 203  * we use as a pipe index
 204  */
 205 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 206 {
 207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 208         unsigned long high_frame;
 209         unsigned long low_frame;
 210         u32 high1, high2, low, count;
 211
 212         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 213         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 214
 215         if (!i915_pipe_enabled(dev, pipe)) {
 216                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 217                                 "pipe %d\n", pipe);
 218                 return 0;
 219         }
 220
 221         /*
 222          * High & low register fields aren't synchronized, so make sure
 223          * we get a low value that's stable across two reads of the high
 224          * register.
 225          */
 226         do {
 227                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 228                          PIPE_FRAME_HIGH_SHIFT);
 229                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 230                         PIPE_FRAME_LOW_SHIFT);
 231                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 232                          PIPE_FRAME_HIGH_SHIFT);
 233         } while (high1 != high2);
 234
 235         count = (high1 << 8) | low;
 236
 237         return count;
 238 }
 239
 240 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 241 {
 242         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 243         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 244
 245         if (!i915_pipe_enabled(dev, pipe)) {
 246                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 247                                         "pipe %d\n", pipe);
 248                 return 0;
 249         }
 250
 251         return I915_READ(reg);
 252 }
 253
 254 /*
 255  * Handle hotplug events outside the interrupt handler proper.
 256  */
 257 static void i915_hotplug_work_func(struct work_struct *work)
 258 {
 259         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 260                                                     hotplug_work);
 261         struct drm_device *dev = dev_priv->dev;
 262         struct drm_mode_config *mode_config = &dev->mode_config;
 263         struct drm_encoder *encoder;
 264
 265         if (mode_config->num_encoder) {
 266                 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 267                         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 268
 269                         if (intel_encoder->hot_plug)
 270                                 (*intel_encoder->hot_plug) (intel_encoder);
 271                 }
 272         }
 273         /* Just fire off a uevent and let userspace tell us what to do */
 274         drm_helper_hpd_irq_event(dev);
 275 }
 276
 277 static void i915_handle_rps_change(struct drm_device *dev)
 278 {
 279         drm_i915_private_t *dev_priv = dev->dev_private;
 280         u32 busy_up, busy_down, max_avg, min_avg;
 281         u8 new_delay = dev_priv->cur_delay;
 282
 283         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 284         busy_up = I915_READ(RCPREVBSYTUPAVG);
 285         busy_down = I915_READ(RCPREVBSYTDNAVG);
 286         max_avg = I915_READ(RCBMAXAVG);
 287         min_avg = I915_READ(RCBMINAVG);
 288
 289         /* Handle RCS change request from hw */
 290         if (busy_up > max_avg) {
 291                 if (dev_priv->cur_delay != dev_priv->max_delay)
 292                         new_delay = dev_priv->cur_delay - 1;
 293                 if (new_delay < dev_priv->max_delay)
 294                         new_delay = dev_priv->max_delay;
 295         } else if (busy_down < min_avg) {
 296                 if (dev_priv->cur_delay != dev_priv->min_delay)
 297                         new_delay = dev_priv->cur_delay + 1;
 298                 if (new_delay > dev_priv->min_delay)
 299                         new_delay = dev_priv->min_delay;
 300         }
 301
 302         if (ironlake_set_drps(dev, new_delay))
 303                 dev_priv->cur_delay = new_delay;
 304
 305         return;
 306 }
 307
 308 static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 309 {
 310         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 311         int ret = IRQ_NONE;
 312         u32 de_iir, gt_iir, de_ier, pch_iir;
 313         struct drm_i915_master_private *master_priv;
 314         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 315
 316         /* disable master interrupt before clearing iir  */
 317         de_ier = I915_READ(DEIER);
 318         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 319         (void)I915_READ(DEIER);
 320
 321         de_iir = I915_READ(DEIIR);
 322         gt_iir = I915_READ(GTIIR);
 323         pch_iir = I915_READ(SDEIIR);
 324
 325         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 326                 goto done;
 327
 328         ret = IRQ_HANDLED;
 329
 330         if (dev->primary->master) {
 331                 master_priv = dev->primary->master->driver_priv;
 332                 if (master_priv->sarea_priv)
 333                         master_priv->sarea_priv->last_dispatch =
 334                                 READ_BREADCRUMB(dev_priv);
 335         }
 336
 337         if (gt_iir & GT_PIPE_NOTIFY) {
 338                 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
 339                 render_ring->irq_gem_seqno = seqno;
 340                 trace_i915_gem_request_complete(dev, seqno);
 341                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 342                 dev_priv->hangcheck_count = 0;
 343                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 344         }
 345         if (gt_iir & GT_BSD_USER_INTERRUPT)
 346                 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 347
 348
 349         if (de_iir & DE_GSE)
 350                 intel_opregion_gse_intr(dev);
 351
 352         if (de_iir & DE_PLANEA_FLIP_DONE) {
 353                 intel_prepare_page_flip(dev, 0);
 354                 intel_finish_page_flip_plane(dev, 0);
 355         }
 356
 357         if (de_iir & DE_PLANEB_FLIP_DONE) {
 358                 intel_prepare_page_flip(dev, 1);
 359                 intel_finish_page_flip_plane(dev, 1);
 360         }
 361
 362         if (de_iir & DE_PIPEA_VBLANK)
 363                 drm_handle_vblank(dev, 0);
 364
 365         if (de_iir & DE_PIPEB_VBLANK)
 366                 drm_handle_vblank(dev, 1);
 367
 368         /* check event from PCH */
 369         if ((de_iir & DE_PCH_EVENT) &&
 370             (pch_iir & SDE_HOTPLUG_MASK)) {
 371                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 372         }
 373
 374         if (de_iir & DE_PCU_EVENT) {
 375                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 376                 i915_handle_rps_change(dev);
 377         }
 378
 379         /* should clear PCH hotplug event before clear CPU irq */
 380         I915_WRITE(SDEIIR, pch_iir);
 381         I915_WRITE(GTIIR, gt_iir);
 382         I915_WRITE(DEIIR, de_iir);
 383
 384 done:
 385         I915_WRITE(DEIER, de_ier);
 386         (void)I915_READ(DEIER);
 387
 388         return ret;
 389 }
 390
 391 /**
 392  * i915_error_work_func - do process context error handling work
 393  * @work: work struct
 394  *
 395  * Fire an error uevent so userspace can see that a hang or error
 396  * was detected.
 397  */
 398 static void i915_error_work_func(struct work_struct *work)
 399 {
 400         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 401                                                     error_work);
 402         struct drm_device *dev = dev_priv->dev;
 403         char *error_event[] = { "ERROR=1", NULL };
 404         char *reset_event[] = { "RESET=1", NULL };
 405         char *reset_done_event[] = { "ERROR=0", NULL };
 406
 407         DRM_DEBUG_DRIVER("generating error event\n");
 408         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 409
 410         if (atomic_read(&dev_priv->mm.wedged)) {
 411                 if (IS_I965G(dev)) {
 412                         DRM_DEBUG_DRIVER("resetting chip\n");
 413                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 414                         if (!i965_reset(dev, GDRST_RENDER)) {
 415                                 atomic_set(&dev_priv->mm.wedged, 0);
 416                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 417                         }
 418                 } else {
 419                         DRM_DEBUG_DRIVER("reboot required\n");
 420                 }
 421         }
 422 }
 423
 424 #ifdef CONFIG_DEBUG_FS
 425 static struct drm_i915_error_object *
 426 i915_error_object_create(struct drm_device *dev,
 427                          struct drm_gem_object *src)
 428 {
 429         drm_i915_private_t *dev_priv = dev->dev_private;
 430         struct drm_i915_error_object *dst;
 431         struct drm_i915_gem_object *src_priv;
 432         int page, page_count;
 433         u32 reloc_offset;
 434
 435         if (src == NULL)
 436                 return NULL;
 437
 438         src_priv = to_intel_bo(src);
 439         if (src_priv->pages == NULL)
 440                 return NULL;
 441
 442         page_count = src->size / PAGE_SIZE;
 443
 444         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 445         if (dst == NULL)
 446                 return NULL;
 447
 448         reloc_offset = src_priv->gtt_offset;
 449         for (page = 0; page < page_count; page++) {
 450                 unsigned long flags;
 451                 void __iomem *s;
 452                 void *d;
 453
 454                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 455                 if (d == NULL)
 456                         goto unwind;
 457
 458                 local_irq_save(flags);
 459                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 460                                              reloc_offset,
 461                                              KM_IRQ0);
 462                 memcpy_fromio(d, s, PAGE_SIZE);
 463                 io_mapping_unmap_atomic(s, KM_IRQ0);
 464                 local_irq_restore(flags);
 465
 466                 dst->pages[page] = d;
 467
 468                 reloc_offset += PAGE_SIZE;
 469         }
 470         dst->page_count = page_count;
 471         dst->gtt_offset = src_priv->gtt_offset;
 472
 473         return dst;
 474
 475 unwind:
 476         while (page--)
 477                 kfree(dst->pages[page]);
 478         kfree(dst);
 479         return NULL;
 480 }
 481
 482 static void
 483 i915_error_object_free(struct drm_i915_error_object *obj)
 484 {
 485         int page;
 486
 487         if (obj == NULL)
 488                 return;
 489
 490         for (page = 0; page < obj->page_count; page++)
 491                 kfree(obj->pages[page]);
 492
 493         kfree(obj);
 494 }
 495
 496 static void
 497 i915_error_state_free(struct drm_device *dev,
 498                       struct drm_i915_error_state *error)
 499 {
 500         i915_error_object_free(error->batchbuffer[0]);
 501         i915_error_object_free(error->batchbuffer[1]);
 502         i915_error_object_free(error->ringbuffer);
 503         kfree(error->active_bo);
 504         kfree(error->overlay);
 505         kfree(error);
 506 }
 507
 508 static u32
 509 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 510 {
 511         u32 cmd;
 512
 513         if (IS_I830(dev) || IS_845G(dev))
 514                 cmd = MI_BATCH_BUFFER;
 515         else if (IS_I965G(dev))
 516                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 517                        MI_BATCH_NON_SECURE_I965);
 518         else
 519                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 520
 521         return ring[0] == cmd ? ring[1] : 0;
 522 }
 523
 524 static u32
 525 i915_ringbuffer_last_batch(struct drm_device *dev)
 526 {
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         u32 head, bbaddr;
 529         u32 *ring;
 530
 531         /* Locate the current position in the ringbuffer and walk back
 532          * to find the most recently dispatched batch buffer.
 533          */
 534         bbaddr = 0;
 535         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 536         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 537
 538         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 539                 bbaddr = i915_get_bbaddr(dev, ring);
 540                 if (bbaddr)
 541                         break;
 542         }
 543
 544         if (bbaddr == 0) {
 545                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 546                                 + dev_priv->render_ring.size);
 547                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 548                         bbaddr = i915_get_bbaddr(dev, ring);
 549                         if (bbaddr)
 550                                 break;
 551                 }
 552         }
 553
 554         return bbaddr;
 555 }
 556
 557 /**
 558  * i915_capture_error_state - capture an error record for later analysis
 559  * @dev: drm device
 560  *
 561  * Should be called when an error is detected (either a hang or an error
 562  * interrupt) to capture error state from the time of the error.  Fills
 563  * out a structure which becomes available in debugfs for user level tools
 564  * to pick up.
 565  */
 566 static void i915_capture_error_state(struct drm_device *dev)
 567 {
 568         struct drm_i915_private *dev_priv = dev->dev_private;
 569         struct drm_i915_gem_object *obj_priv;
 570         struct drm_i915_error_state *error;
 571         struct drm_gem_object *batchbuffer[2];
 572         unsigned long flags;
 573         u32 bbaddr;
 574         int count;
 575
 576         spin_lock_irqsave(&dev_priv->error_lock, flags);
 577         error = dev_priv->first_error;
 578         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 579         if (error)
 580                 return;
 581
 582         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 583         if (!error) {
 584                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 585                 return;
 586         }
 587
 588         error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
 589         error->eir = I915_READ(EIR);
 590         error->pgtbl_er = I915_READ(PGTBL_ER);
 591         error->pipeastat = I915_READ(PIPEASTAT);
 592         error->pipebstat = I915_READ(PIPEBSTAT);
 593         error->instpm = I915_READ(INSTPM);
 594         if (!IS_I965G(dev)) {
 595                 error->ipeir = I915_READ(IPEIR);
 596                 error->ipehr = I915_READ(IPEHR);
 597                 error->instdone = I915_READ(INSTDONE);
 598                 error->acthd = I915_READ(ACTHD);
 599                 error->bbaddr = 0;
 600         } else {
 601                 error->ipeir = I915_READ(IPEIR_I965);
 602                 error->ipehr = I915_READ(IPEHR_I965);
 603                 error->instdone = I915_READ(INSTDONE_I965);
 604                 error->instps = I915_READ(INSTPS);
 605                 error->instdone1 = I915_READ(INSTDONE1);
 606                 error->acthd = I915_READ(ACTHD_I965);
 607                 error->bbaddr = I915_READ64(BB_ADDR);
 608         }
 609
 610         bbaddr = i915_ringbuffer_last_batch(dev);
 611
 612         /* Grab the current batchbuffer, most likely to have crashed. */
 613         batchbuffer[0] = NULL;
 614         batchbuffer[1] = NULL;
 615         count = 0;
 616         list_for_each_entry(obj_priv,
 617                         &dev_priv->render_ring.active_list, list) {
 618
 619                 struct drm_gem_object *obj = &obj_priv->base;
 620
 621                 if (batchbuffer[0] == NULL &&
 622                     bbaddr >= obj_priv->gtt_offset &&
 623                     bbaddr < obj_priv->gtt_offset + obj->size)
 624                         batchbuffer[0] = obj;
 625
 626                 if (batchbuffer[1] == NULL &&
 627                     error->acthd >= obj_priv->gtt_offset &&
 628                     error->acthd < obj_priv->gtt_offset + obj->size)
 629                         batchbuffer[1] = obj;
 630
 631                 count++;
 632         }
 633         /* Scan the other lists for completeness for those bizarre errors. */
 634         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 635                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
 636                         struct drm_gem_object *obj = &obj_priv->base;
 637
 638                         if (batchbuffer[0] == NULL &&
 639                             bbaddr >= obj_priv->gtt_offset &&
 640                             bbaddr < obj_priv->gtt_offset + obj->size)
 641                                 batchbuffer[0] = obj;
 642
 643                         if (batchbuffer[1] == NULL &&
 644                             error->acthd >= obj_priv->gtt_offset &&
 645                             error->acthd < obj_priv->gtt_offset + obj->size)
 646                                 batchbuffer[1] = obj;
 647
 648                         if (batchbuffer[0] && batchbuffer[1])
 649                                 break;
 650                 }
 651         }
 652         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 653                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 654                         struct drm_gem_object *obj = &obj_priv->base;
 655
 656                         if (batchbuffer[0] == NULL &&
 657                             bbaddr >= obj_priv->gtt_offset &&
 658                             bbaddr < obj_priv->gtt_offset + obj->size)
 659                                 batchbuffer[0] = obj;
 660
 661                         if (batchbuffer[1] == NULL &&
 662                             error->acthd >= obj_priv->gtt_offset &&
 663                             error->acthd < obj_priv->gtt_offset + obj->size)
 664                                 batchbuffer[1] = obj;
 665
 666                         if (batchbuffer[0] && batchbuffer[1])
 667                                 break;
 668                 }
 669         }
 670
 671         /* We need to copy these to an anonymous buffer as the simplest
 672          * method to avoid being overwritten by userpace.
 673          */
 674         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 675         if (batchbuffer[1] != batchbuffer[0])
 676                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 677         else
 678                 error->batchbuffer[1] = NULL;
 679
 680         /* Record the ringbuffer */
 681         error->ringbuffer = i915_error_object_create(dev,
 682                         dev_priv->render_ring.gem_object);
 683
 684         /* Record buffers on the active list. */
 685         error->active_bo = NULL;
 686         error->active_bo_count = 0;
 687
 688         if (count)
 689                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 690                                            GFP_ATOMIC);
 691
 692         if (error->active_bo) {
 693                 int i = 0;
 694                 list_for_each_entry(obj_priv,
 695                                 &dev_priv->render_ring.active_list, list) {
 696                         struct drm_gem_object *obj = &obj_priv->base;
 697
 698                         error->active_bo[i].size = obj->size;
 699                         error->active_bo[i].name = obj->name;
 700                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 701                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 702                         error->active_bo[i].read_domains = obj->read_domains;
 703                         error->active_bo[i].write_domain = obj->write_domain;
 704                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 705                         error->active_bo[i].pinned = 0;
 706                         if (obj_priv->pin_count > 0)
 707                                 error->active_bo[i].pinned = 1;
 708                         if (obj_priv->user_pin_count > 0)
 709                                 error->active_bo[i].pinned = -1;
 710                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 711                         error->active_bo[i].dirty = obj_priv->dirty;
 712                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 713
 714                         if (++i == count)
 715                                 break;
 716                 }
 717                 error->active_bo_count = i;
 718         }
 719
 720         do_gettimeofday(&error->time);
 721
 722         error->overlay = intel_overlay_capture_error_state(dev);
 723
 724         spin_lock_irqsave(&dev_priv->error_lock, flags);
 725         if (dev_priv->first_error == NULL) {
 726                 dev_priv->first_error = error;
 727                 error = NULL;
 728         }
 729         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 730
 731         if (error)
 732                 i915_error_state_free(dev, error);
 733 }
 734
 735 void i915_destroy_error_state(struct drm_device *dev)
 736 {
 737         struct drm_i915_private *dev_priv = dev->dev_private;
 738         struct drm_i915_error_state *error;
 739
 740         spin_lock(&dev_priv->error_lock);
 741         error = dev_priv->first_error;
 742         dev_priv->first_error = NULL;
 743         spin_unlock(&dev_priv->error_lock);
 744
 745         if (error)
 746                 i915_error_state_free(dev, error);
 747 }
 748 #else
 749 #define i915_capture_error_state(x)
 750 #endif
 751
 752 static void i915_report_and_clear_eir(struct drm_device *dev)
 753 {
 754         struct drm_i915_private *dev_priv = dev->dev_private;
 755         u32 eir = I915_READ(EIR);
 756
 757         if (!eir)
 758                 return;
 759
 760         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 761                eir);
 762
 763         if (IS_G4X(dev)) {
 764                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 765                         u32 ipeir = I915_READ(IPEIR_I965);
 766
 767                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 768                                I915_READ(IPEIR_I965));
 769                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 770                                I915_READ(IPEHR_I965));
 771                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 772                                I915_READ(INSTDONE_I965));
 773                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 774                                I915_READ(INSTPS));
 775                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 776                                I915_READ(INSTDONE1));
 777                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 778                                I915_READ(ACTHD_I965));
 779                         I915_WRITE(IPEIR_I965, ipeir);
 780                         (void)I915_READ(IPEIR_I965);
 781                 }
 782                 if (eir & GM45_ERROR_PAGE_TABLE) {
 783                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 784                         printk(KERN_ERR "page table error\n");
 785                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 786                                pgtbl_err);
 787                         I915_WRITE(PGTBL_ER, pgtbl_err);
 788                         (void)I915_READ(PGTBL_ER);
 789                 }
 790         }
 791
 792         if (IS_I9XX(dev)) {
 793                 if (eir & I915_ERROR_PAGE_TABLE) {
 794                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 795                         printk(KERN_ERR "page table error\n");
 796                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 797                                pgtbl_err);
 798                         I915_WRITE(PGTBL_ER, pgtbl_err);
 799                         (void)I915_READ(PGTBL_ER);
 800                 }
 801         }
 802
 803         if (eir & I915_ERROR_MEMORY_REFRESH) {
 804                 u32 pipea_stats = I915_READ(PIPEASTAT);
 805                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 806
 807                 printk(KERN_ERR "memory refresh error\n");
 808                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 809                        pipea_stats);
 810                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 811                        pipeb_stats);
 812                 /* pipestat has already been acked */
 813         }
 814         if (eir & I915_ERROR_INSTRUCTION) {
 815                 printk(KERN_ERR "instruction error\n");
 816                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 817                        I915_READ(INSTPM));
 818                 if (!IS_I965G(dev)) {
 819                         u32 ipeir = I915_READ(IPEIR);
 820
 821                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 822                                I915_READ(IPEIR));
 823                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 824                                I915_READ(IPEHR));
 825                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 826                                I915_READ(INSTDONE));
 827                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 828                                I915_READ(ACTHD));
 829                         I915_WRITE(IPEIR, ipeir);
 830                         (void)I915_READ(IPEIR);
 831                 } else {
 832                         u32 ipeir = I915_READ(IPEIR_I965);
 833
 834                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 835                                I915_READ(IPEIR_I965));
 836                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 837                                I915_READ(IPEHR_I965));
 838                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 839                                I915_READ(INSTDONE_I965));
 840                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 841                                I915_READ(INSTPS));
 842                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 843                                I915_READ(INSTDONE1));
 844                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 845                                I915_READ(ACTHD_I965));
 846                         I915_WRITE(IPEIR_I965, ipeir);
 847                         (void)I915_READ(IPEIR_I965);
 848                 }
 849         }
 850
 851         I915_WRITE(EIR, eir);
 852         (void)I915_READ(EIR);
 853         eir = I915_READ(EIR);
 854         if (eir) {
 855                 /*
 856                  * some errors might have become stuck,
 857                  * mask them.
 858                  */
 859                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 860                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 861                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 862         }
 863 }
 864
 865 /**
 866  * i915_handle_error - handle an error interrupt
 867  * @dev: drm device
 868  *
 869  * Do some basic checking of regsiter state at error interrupt time and
 870  * dump it to the syslog.  Also call i915_capture_error_state() to make
 871  * sure we get a record and make it available in debugfs.  Fire a uevent
 872  * so userspace knows something bad happened (should trigger collection
 873  * of a ring dump etc.).
 874  */
 875 static void i915_handle_error(struct drm_device *dev, bool wedged)
 876 {
 877         struct drm_i915_private *dev_priv = dev->dev_private;
 878
 879         i915_capture_error_state(dev);
 880         i915_report_and_clear_eir(dev);
 881
 882         if (wedged) {
 883                 atomic_set(&dev_priv->mm.wedged, 1);
 884
 885                 /*
 886                  * Wakeup waiting processes so they don't hang
 887                  */
 888                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 889         }
 890
 891         queue_work(dev_priv->wq, &dev_priv->error_work);
 892 }
 893
 894 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
 895 {
 896         drm_i915_private_t *dev_priv = dev->dev_private;
 897         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 899         struct drm_i915_gem_object *obj_priv;
 900         struct intel_unpin_work *work;
 901         unsigned long flags;
 902         bool stall_detected;
 903
 904         /* Ignore early vblank irqs */
 905         if (intel_crtc == NULL)
 906                 return;
 907
 908         spin_lock_irqsave(&dev->event_lock, flags);
 909         work = intel_crtc->unpin_work;
 910
 911         if (work == NULL || work->pending || !work->enable_stall_check) {
 912                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
 913                 spin_unlock_irqrestore(&dev->event_lock, flags);
 914                 return;
 915         }
 916
 917         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
 918         obj_priv = to_intel_bo(work->pending_flip_obj);
 919         if(IS_I965G(dev)) {
 920                 int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF;
 921                 stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset;
 922         } else {
 923                 int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR;
 924                 stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset +
 925                                                         crtc->y * crtc->fb->pitch +
 926                                                         crtc->x * crtc->fb->bits_per_pixel/8);
 927         }
 928
 929         spin_unlock_irqrestore(&dev->event_lock, flags);
 930
 931         if (stall_detected) {
 932                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
 933                 intel_prepare_page_flip(dev, intel_crtc->plane);
 934         }
 935 }
 936
 937 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 938 {
 939         struct drm_device *dev = (struct drm_device *) arg;
 940         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 941         struct drm_i915_master_private *master_priv;
 942         u32 iir, new_iir;
 943         u32 pipea_stats, pipeb_stats;
 944         u32 vblank_status;
 945         int vblank = 0;
 946         unsigned long irqflags;
 947         int irq_received;
 948         int ret = IRQ_NONE;
 949         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 950
 951         atomic_inc(&dev_priv->irq_received);
 952
 953         if (HAS_PCH_SPLIT(dev))
 954                 return ironlake_irq_handler(dev);
 955
 956         iir = I915_READ(IIR);
 957
 958         if (IS_I965G(dev))
 959                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 960         else
 961                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 962
 963         for (;;) {
 964                 irq_received = iir != 0;
 965
 966                 /* Can't rely on pipestat interrupt bit in iir as it might
 967                  * have been cleared after the pipestat interrupt was received.
 968                  * It doesn't set the bit in iir again, but it still produces
 969                  * interrupts (for non-MSI).
 970                  */
 971                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 972                 pipea_stats = I915_READ(PIPEASTAT);
 973                 pipeb_stats = I915_READ(PIPEBSTAT);
 974
 975                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 976                         i915_handle_error(dev, false);
 977
 978                 /*
 979                  * Clear the PIPE(A|B)STAT regs before the IIR
 980                  */
 981                 if (pipea_stats & 0x8000ffff) {
 982                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 983                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 984                         I915_WRITE(PIPEASTAT, pipea_stats);
 985                         irq_received = 1;
 986                 }
 987
 988                 if (pipeb_stats & 0x8000ffff) {
 989                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 990                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 991                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 992                         irq_received = 1;
 993                 }
 994                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 995
 996                 if (!irq_received)
 997                         break;
 998
 999                 ret = IRQ_HANDLED;
1000
1001                 /* Consume port.  Then clear IIR or we'll miss events */
1002                 if ((I915_HAS_HOTPLUG(dev)) &&
1003                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1004                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1005
1006                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1007                                   hotplug_status);
1008                         if (hotplug_status & dev_priv->hotplug_supported_mask)
1009                                 queue_work(dev_priv->wq,
1010                                            &dev_priv->hotplug_work);
1011
1012                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1013                         I915_READ(PORT_HOTPLUG_STAT);
1014                 }
1015
1016                 I915_WRITE(IIR, iir);
1017                 new_iir = I915_READ(IIR); /* Flush posted writes */
1018
1019                 if (dev->primary->master) {
1020                         master_priv = dev->primary->master->driver_priv;
1021                         if (master_priv->sarea_priv)
1022                                 master_priv->sarea_priv->last_dispatch =
1023                                         READ_BREADCRUMB(dev_priv);
1024                 }
1025
1026                 if (iir & I915_USER_INTERRUPT) {
1027                         u32 seqno =
1028                                 render_ring->get_gem_seqno(dev, render_ring);
1029                         render_ring->irq_gem_seqno = seqno;
1030                         trace_i915_gem_request_complete(dev, seqno);
1031                         DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1032                         dev_priv->hangcheck_count = 0;
1033                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1034                 }
1035
1036                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
1037                         DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1038
1039                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
1040                         intel_prepare_page_flip(dev, 0);
1041                         if (dev_priv->flip_pending_is_done)
1042                                 intel_finish_page_flip_plane(dev, 0);
1043                 }
1044
1045                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
1046                         intel_prepare_page_flip(dev, 1);
1047                         if (dev_priv->flip_pending_is_done)
1048                                 intel_finish_page_flip_plane(dev, 1);
1049                 }
1050
1051                 if (pipea_stats & vblank_status) {
1052                         vblank++;
1053                         drm_handle_vblank(dev, 0);
1054                         if (!dev_priv->flip_pending_is_done) {
1055                                 i915_pageflip_stall_check(dev, 0);
1056                                 intel_finish_page_flip(dev, 0);
1057                         }
1058                 }
1059
1060                 if (pipeb_stats & vblank_status) {
1061                         vblank++;
1062                         drm_handle_vblank(dev, 1);
1063                         if (!dev_priv->flip_pending_is_done) {
1064                                 i915_pageflip_stall_check(dev, 1);
1065                                 intel_finish_page_flip(dev, 1);
1066                         }
1067                 }
1068
1069                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1070                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1071                     (iir & I915_ASLE_INTERRUPT))
1072                         intel_opregion_asle_intr(dev);
1073
1074                 /* With MSI, interrupts are only generated when iir
1075                  * transitions from zero to nonzero.  If another bit got
1076                  * set while we were handling the existing iir bits, then
1077                  * we would never get another interrupt.
1078                  *
1079                  * This is fine on non-MSI as well, as if we hit this path
1080                  * we avoid exiting the interrupt handler only to generate
1081                  * another one.
1082                  *
1083                  * Note that for MSI this could cause a stray interrupt report
1084                  * if an interrupt landed in the time between writing IIR and
1085                  * the posting read.  This should be rare enough to never
1086                  * trigger the 99% of 100,000 interrupts test for disabling
1087                  * stray interrupts.
1088                  */
1089                 iir = new_iir;
1090         }
1091
1092         return ret;
1093 }
1094
1095 static int i915_emit_irq(struct drm_device * dev)
1096 {
1097         drm_i915_private_t *dev_priv = dev->dev_private;
1098         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1099
1100         i915_kernel_lost_context(dev);
1101
1102         DRM_DEBUG_DRIVER("\n");
1103
1104         dev_priv->counter++;
1105         if (dev_priv->counter > 0x7FFFFFFFUL)
1106                 dev_priv->counter = 1;
1107         if (master_priv->sarea_priv)
1108                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1109
1110         BEGIN_LP_RING(4);
1111         OUT_RING(MI_STORE_DWORD_INDEX);
1112         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1113         OUT_RING(dev_priv->counter);
1114         OUT_RING(MI_USER_INTERRUPT);
1115         ADVANCE_LP_RING();
1116
1117         return dev_priv->counter;
1118 }
1119
1120 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1121 {
1122         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1123         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1124
1125         if (dev_priv->trace_irq_seqno == 0)
1126                 render_ring->user_irq_get(dev, render_ring);
1127
1128         dev_priv->trace_irq_seqno = seqno;
1129 }
1130
1131 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1132 {
1133         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1134         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1135         int ret = 0;
1136         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1137
1138         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1139                   READ_BREADCRUMB(dev_priv));
1140
1141         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1142                 if (master_priv->sarea_priv)
1143                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1144                 return 0;
1145         }
1146
1147         if (master_priv->sarea_priv)
1148                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1149
1150         render_ring->user_irq_get(dev, render_ring);
1151         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1152                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1153         render_ring->user_irq_put(dev, render_ring);
1154
1155         if (ret == -EBUSY) {
1156                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1157                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1158         }
1159
1160         return ret;
1161 }
1162
1163 /* Needs the lock as it touches the ring.
1164  */
1165 int i915_irq_emit(struct drm_device *dev, void *data,
1166                          struct drm_file *file_priv)
1167 {
1168         drm_i915_private_t *dev_priv = dev->dev_private;
1169         drm_i915_irq_emit_t *emit = data;
1170         int result;
1171
1172         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1173                 DRM_ERROR("called with no initialization\n");
1174                 return -EINVAL;
1175         }
1176
1177         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1178
1179         mutex_lock(&dev->struct_mutex);
1180         result = i915_emit_irq(dev);
1181         mutex_unlock(&dev->struct_mutex);
1182
1183         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1184                 DRM_ERROR("copy_to_user\n");
1185                 return -EFAULT;
1186         }
1187
1188         return 0;
1189 }
1190
1191 /* Doesn't need the hardware lock.
1192  */
1193 int i915_irq_wait(struct drm_device *dev, void *data,
1194                          struct drm_file *file_priv)
1195 {
1196         drm_i915_private_t *dev_priv = dev->dev_private;
1197         drm_i915_irq_wait_t *irqwait = data;
1198
1199         if (!dev_priv) {
1200                 DRM_ERROR("called with no initialization\n");
1201                 return -EINVAL;
1202         }
1203
1204         return i915_wait_irq(dev, irqwait->irq_seq);
1205 }
1206
1207 /* Called from drm generic code, passed 'crtc' which
1208  * we use as a pipe index
1209  */
1210 int i915_enable_vblank(struct drm_device *dev, int pipe)
1211 {
1212         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1213         unsigned long irqflags;
1214         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1215         u32 pipeconf;
1216
1217         pipeconf = I915_READ(pipeconf_reg);
1218         if (!(pipeconf & PIPEACONF_ENABLE))
1219                 return -EINVAL;
1220
1221         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1222         if (HAS_PCH_SPLIT(dev))
1223                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1224                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1225         else if (IS_I965G(dev))
1226                 i915_enable_pipestat(dev_priv, pipe,
1227                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1228         else
1229                 i915_enable_pipestat(dev_priv, pipe,
1230                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1231         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1232         return 0;
1233 }
1234
1235 /* Called from drm generic code, passed 'crtc' which
1236  * we use as a pipe index
1237  */
1238 void i915_disable_vblank(struct drm_device *dev, int pipe)
1239 {
1240         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1241         unsigned long irqflags;
1242
1243         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1244         if (HAS_PCH_SPLIT(dev))
1245                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1246                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1247         else
1248                 i915_disable_pipestat(dev_priv, pipe,
1249                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1250                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1251         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1252 }
1253
1254 void i915_enable_interrupt (struct drm_device *dev)
1255 {
1256         struct drm_i915_private *dev_priv = dev->dev_private;
1257
1258         if (!HAS_PCH_SPLIT(dev))
1259                 intel_opregion_enable_asle(dev);
1260         dev_priv->irq_enabled = 1;
1261 }
1262
1263
1264 /* Set the vblank monitor pipe
1265  */
1266 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1267                          struct drm_file *file_priv)
1268 {
1269         drm_i915_private_t *dev_priv = dev->dev_private;
1270
1271         if (!dev_priv) {
1272                 DRM_ERROR("called with no initialization\n");
1273                 return -EINVAL;
1274         }
1275
1276         return 0;
1277 }
1278
1279 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1280                          struct drm_file *file_priv)
1281 {
1282         drm_i915_private_t *dev_priv = dev->dev_private;
1283         drm_i915_vblank_pipe_t *pipe = data;
1284
1285         if (!dev_priv) {
1286                 DRM_ERROR("called with no initialization\n");
1287                 return -EINVAL;
1288         }
1289
1290         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1291
1292         return 0;
1293 }
1294
1295 /**
1296  * Schedule buffer swap at given vertical blank.
1297  */
1298 int i915_vblank_swap(struct drm_device *dev, void *data,
1299                      struct drm_file *file_priv)
1300 {
1301         /* The delayed swap mechanism was fundamentally racy, and has been
1302          * removed.  The model was that the client requested a delayed flip/swap
1303          * from the kernel, then waited for vblank before continuing to perform
1304          * rendering.  The problem was that the kernel might wake the client
1305          * up before it dispatched the vblank swap (since the lock has to be
1306          * held while touching the ringbuffer), in which case the client would
1307          * clear and start the next frame before the swap occurred, and
1308          * flicker would occur in addition to likely missing the vblank.
1309          *
1310          * In the absence of this ioctl, userland falls back to a correct path
1311          * of waiting for a vblank, then dispatching the swap on its own.
1312          * Context switching to userland and back is plenty fast enough for
1313          * meeting the requirements of vblank swapping.
1314          */
1315         return -EINVAL;
1316 }
1317
1318 static struct drm_i915_gem_request *
1319 i915_get_tail_request(struct drm_device *dev)
1320 {
1321         drm_i915_private_t *dev_priv = dev->dev_private;
1322         return list_entry(dev_priv->render_ring.request_list.prev,
1323                         struct drm_i915_gem_request, list);
1324 }
1325
1326 /**
1327  * This is called when the chip hasn't reported back with completed
1328  * batchbuffers in a long time. The first time this is called we simply record
1329  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1330  * again, we assume the chip is wedged and try to fix it.
1331  */
1332 void i915_hangcheck_elapsed(unsigned long data)
1333 {
1334         struct drm_device *dev = (struct drm_device *)data;
1335         drm_i915_private_t *dev_priv = dev->dev_private;
1336         uint32_t acthd, instdone, instdone1;
1337
1338         /* No reset support on this chip yet. */
1339         if (IS_GEN6(dev))
1340                 return;
1341
1342         if (!IS_I965G(dev)) {
1343                 acthd = I915_READ(ACTHD);
1344                 instdone = I915_READ(INSTDONE);
1345                 instdone1 = 0;
1346         } else {
1347                 acthd = I915_READ(ACTHD_I965);
1348                 instdone = I915_READ(INSTDONE_I965);
1349                 instdone1 = I915_READ(INSTDONE1);
1350         }
1351
1352         /* If all work is done then ACTHD clearly hasn't advanced. */
1353         if (list_empty(&dev_priv->render_ring.request_list) ||
1354                 i915_seqno_passed(i915_get_gem_seqno(dev,
1355                                 &dev_priv->render_ring),
1356                         i915_get_tail_request(dev)->seqno)) {
1357                 dev_priv->hangcheck_count = 0;
1358
1359                 /* Issue a wake-up to catch stuck h/w. */
1360                 if (dev_priv->render_ring.waiting_gem_seqno |
1361                     dev_priv->bsd_ring.waiting_gem_seqno) {
1362                         DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1363                         if (dev_priv->render_ring.waiting_gem_seqno)
1364                                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1365                         if (dev_priv->bsd_ring.waiting_gem_seqno)
1366                                 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1367                 }
1368                 return;
1369         }
1370
1371         if (dev_priv->last_acthd == acthd &&
1372             dev_priv->last_instdone == instdone &&
1373             dev_priv->last_instdone1 == instdone1) {
1374                 if (dev_priv->hangcheck_count++ > 1) {
1375                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1376
1377                         if (!IS_GEN2(dev)) {
1378                                 /* Is the chip hanging on a WAIT_FOR_EVENT?
1379                                  * If so we can simply poke the RB_WAIT bit
1380                                  * and break the hang. This should work on
1381                                  * all but the second generation chipsets.
1382                                  */
1383                                 u32 tmp = I915_READ(PRB0_CTL);
1384                                 if (tmp & RING_WAIT) {
1385                                         I915_WRITE(PRB0_CTL, tmp);
1386                                         POSTING_READ(PRB0_CTL);
1387                                         goto out;
1388                                 }
1389                         }
1390
1391                         i915_handle_error(dev, true);
1392                         return;
1393                 }
1394         } else {
1395                 dev_priv->hangcheck_count = 0;
1396
1397                 dev_priv->last_acthd = acthd;
1398                 dev_priv->last_instdone = instdone;
1399                 dev_priv->last_instdone1 = instdone1;
1400         }
1401
1402 out:
1403         /* Reset timer case chip hangs without another request being added */
1404         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1405 }
1406
1407 /* drm_dma.h hooks
1408 */
1409 static void ironlake_irq_preinstall(struct drm_device *dev)
1410 {
1411         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1412
1413         I915_WRITE(HWSTAM, 0xeffe);
1414
1415         /* XXX hotplug from PCH */
1416
1417         I915_WRITE(DEIMR, 0xffffffff);
1418         I915_WRITE(DEIER, 0x0);
1419         (void) I915_READ(DEIER);
1420
1421         /* and GT */
1422         I915_WRITE(GTIMR, 0xffffffff);
1423         I915_WRITE(GTIER, 0x0);
1424         (void) I915_READ(GTIER);
1425
1426         /* south display irq */
1427         I915_WRITE(SDEIMR, 0xffffffff);
1428         I915_WRITE(SDEIER, 0x0);
1429         (void) I915_READ(SDEIER);
1430 }
1431
1432 static int ironlake_irq_postinstall(struct drm_device *dev)
1433 {
1434         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1435         /* enable kind of interrupts always enabled */
1436         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1437                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1438         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1439         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1440                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1441
1442         dev_priv->irq_mask_reg = ~display_mask;
1443         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1444
1445         /* should always can generate irq */
1446         I915_WRITE(DEIIR, I915_READ(DEIIR));
1447         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1448         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1449         (void) I915_READ(DEIER);
1450
1451         /* Gen6 only needs render pipe_control now */
1452         if (IS_GEN6(dev))
1453                 render_mask = GT_PIPE_NOTIFY;
1454
1455         dev_priv->gt_irq_mask_reg = ~render_mask;
1456         dev_priv->gt_irq_enable_reg = render_mask;
1457
1458         I915_WRITE(GTIIR, I915_READ(GTIIR));
1459         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1460         if (IS_GEN6(dev))
1461                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1462         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1463         (void) I915_READ(GTIER);
1464
1465         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1466         dev_priv->pch_irq_enable_reg = hotplug_mask;
1467
1468         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1469         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1470         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1471         (void) I915_READ(SDEIER);
1472
1473         if (IS_IRONLAKE_M(dev)) {
1474                 /* Clear & enable PCU event interrupts */
1475                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1476                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1477                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1478         }
1479
1480         return 0;
1481 }
1482
1483 void i915_driver_irq_preinstall(struct drm_device * dev)
1484 {
1485         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1486
1487         atomic_set(&dev_priv->irq_received, 0);
1488
1489         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1490         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1491
1492         if (HAS_PCH_SPLIT(dev)) {
1493                 ironlake_irq_preinstall(dev);
1494                 return;
1495         }
1496
1497         if (I915_HAS_HOTPLUG(dev)) {
1498                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1499                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1500         }
1501
1502         I915_WRITE(HWSTAM, 0xeffe);
1503         I915_WRITE(PIPEASTAT, 0);
1504         I915_WRITE(PIPEBSTAT, 0);
1505         I915_WRITE(IMR, 0xffffffff);
1506         I915_WRITE(IER, 0x0);
1507         (void) I915_READ(IER);
1508 }
1509
1510 /*
1511  * Must be called after intel_modeset_init or hotplug interrupts won't be
1512  * enabled correctly.
1513  */
1514 int i915_driver_irq_postinstall(struct drm_device *dev)
1515 {
1516         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1517         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1518         u32 error_mask;
1519
1520         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1521
1522         if (HAS_BSD(dev))
1523                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1524
1525         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1526
1527         if (HAS_PCH_SPLIT(dev))
1528                 return ironlake_irq_postinstall(dev);
1529
1530         /* Unmask the interrupts that we always want on. */
1531         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1532
1533         dev_priv->pipestat[0] = 0;
1534         dev_priv->pipestat[1] = 0;
1535
1536         if (I915_HAS_HOTPLUG(dev)) {
1537                 /* Enable in IER... */
1538                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1539                 /* and unmask in IMR */
1540                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1541         }
1542
1543         /*
1544          * Enable some error detection, note the instruction error mask
1545          * bit is reserved, so we leave it masked.
1546          */
1547         if (IS_G4X(dev)) {
1548                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1549                                GM45_ERROR_MEM_PRIV |
1550                                GM45_ERROR_CP_PRIV |
1551                                I915_ERROR_MEMORY_REFRESH);
1552         } else {
1553                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1554                                I915_ERROR_MEMORY_REFRESH);
1555         }
1556         I915_WRITE(EMR, error_mask);
1557
1558         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1559         I915_WRITE(IER, enable_mask);
1560         (void) I915_READ(IER);
1561
1562         if (I915_HAS_HOTPLUG(dev)) {
1563                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1564
1565                 /* Note HDMI and DP share bits */
1566                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1567                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1568                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1569                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1570                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1571                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1572                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1573                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1574                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1575                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1576                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1577                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1578
1579                         /* Programming the CRT detection parameters tends
1580                            to generate a spurious hotplug event about three
1581                            seconds later.  So just do it once.
1582                         */
1583                         if (IS_G4X(dev))
1584                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1585                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1586                 }
1587
1588                 /* Ignore TV since it's buggy */
1589
1590                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1591         }
1592
1593         intel_opregion_enable_asle(dev);
1594
1595         return 0;
1596 }
1597
1598 static void ironlake_irq_uninstall(struct drm_device *dev)
1599 {
1600         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1601         I915_WRITE(HWSTAM, 0xffffffff);
1602
1603         I915_WRITE(DEIMR, 0xffffffff);
1604         I915_WRITE(DEIER, 0x0);
1605         I915_WRITE(DEIIR, I915_READ(DEIIR));
1606
1607         I915_WRITE(GTIMR, 0xffffffff);
1608         I915_WRITE(GTIER, 0x0);
1609         I915_WRITE(GTIIR, I915_READ(GTIIR));
1610 }
1611
1612 void i915_driver_irq_uninstall(struct drm_device * dev)
1613 {
1614         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1615
1616         if (!dev_priv)
1617                 return;
1618
1619         dev_priv->vblank_pipe = 0;
1620
1621         if (HAS_PCH_SPLIT(dev)) {
1622                 ironlake_irq_uninstall(dev);
1623                 return;
1624         }
1625
1626         if (I915_HAS_HOTPLUG(dev)) {
1627                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1628                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1629         }
1630
1631         I915_WRITE(HWSTAM, 0xffffffff);
1632         I915_WRITE(PIPEASTAT, 0);
1633         I915_WRITE(PIPEBSTAT, 0);
1634         I915_WRITE(IMR, 0xffffffff);
1635         I915_WRITE(IER, 0x0);
1636
1637         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1638         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1639         I915_WRITE(IIR, I915_READ(IIR));
1640 }