drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37
  38 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
  39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  42                                              int write);
  43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  44                                                      uint64_t offset,
  45                                                      uint64_t size);
  46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  47 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  49                                            unsigned alignment);
  50 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  51 static int i915_gem_evict_something(struct drm_device *dev, int min_size);
  52 static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
  53 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  54                                 struct drm_i915_gem_pwrite *args,
  55                                 struct drm_file *file_priv);
  56 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
  57
  58 static LIST_HEAD(shrink_list);
  59 static DEFINE_SPINLOCK(shrink_list_lock);
  60
  61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  62                      unsigned long end)
  63 {
  64         drm_i915_private_t *dev_priv = dev->dev_private;
  65
  66         if (start >= end ||
  67             (start & (PAGE_SIZE - 1)) != 0 ||
  68             (end & (PAGE_SIZE - 1)) != 0) {
  69                 return -EINVAL;
  70         }
  71
  72         drm_mm_init(&dev_priv->mm.gtt_space, start,
  73                     end - start);
  74
  75         dev->gtt_total = (uint32_t) (end - start);
  76
  77         return 0;
  78 }
  79
  80 int
  81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  82                     struct drm_file *file_priv)
  83 {
  84         struct drm_i915_gem_init *args = data;
  85         int ret;
  86
  87         mutex_lock(&dev->struct_mutex);
  88         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
  89         mutex_unlock(&dev->struct_mutex);
  90
  91         return ret;
  92 }
  93
  94 int
  95 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  96                             struct drm_file *file_priv)
  97 {
  98         struct drm_i915_gem_get_aperture *args = data;
  99
 100         if (!(dev->driver->driver_features & DRIVER_GEM))
 101                 return -ENODEV;
 102
 103         args->aper_size = dev->gtt_total;
 104         args->aper_available_size = (args->aper_size -
 105                                      atomic_read(&dev->pin_memory));
 106
 107         return 0;
 108 }
 109
 110
 111 /**
 112  * Creates a new mm object and returns a handle to it.
 113  */
 114 int
 115 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 116                       struct drm_file *file_priv)
 117 {
 118         struct drm_i915_gem_create *args = data;
 119         struct drm_gem_object *obj;
 120         int ret;
 121         u32 handle;
 122
 123         args->size = roundup(args->size, PAGE_SIZE);
 124
 125         /* Allocate the new object */
 126         obj = i915_gem_alloc_object(dev, args->size);
 127         if (obj == NULL)
 128                 return -ENOMEM;
 129
 130         ret = drm_gem_handle_create(file_priv, obj, &handle);
 131         drm_gem_object_handle_unreference_unlocked(obj);
 132
 133         if (ret)
 134                 return ret;
 135
 136         args->handle = handle;
 137
 138         return 0;
 139 }
 140
 141 static inline int
 142 fast_shmem_read(struct page **pages,
 143                 loff_t page_base, int page_offset,
 144                 char __user *data,
 145                 int length)
 146 {
 147         char __iomem *vaddr;
 148         int unwritten;
 149
 150         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 151         if (vaddr == NULL)
 152                 return -ENOMEM;
 153         unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 154         kunmap_atomic(vaddr, KM_USER0);
 155
 156         if (unwritten)
 157                 return -EFAULT;
 158
 159         return 0;
 160 }
 161
 162 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 163 {
 164         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 165         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 166
 167         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 168                 obj_priv->tiling_mode != I915_TILING_NONE;
 169 }
 170
 171 static inline void
 172 slow_shmem_copy(struct page *dst_page,
 173                 int dst_offset,
 174                 struct page *src_page,
 175                 int src_offset,
 176                 int length)
 177 {
 178         char *dst_vaddr, *src_vaddr;
 179
 180         dst_vaddr = kmap(dst_page);
 181         src_vaddr = kmap(src_page);
 182
 183         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 184
 185         kunmap(src_page);
 186         kunmap(dst_page);
 187 }
 188
 189 static inline void
 190 slow_shmem_bit17_copy(struct page *gpu_page,
 191                       int gpu_offset,
 192                       struct page *cpu_page,
 193                       int cpu_offset,
 194                       int length,
 195                       int is_read)
 196 {
 197         char *gpu_vaddr, *cpu_vaddr;
 198
 199         /* Use the unswizzled path if this page isn't affected. */
 200         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 201                 if (is_read)
 202                         return slow_shmem_copy(cpu_page, cpu_offset,
 203                                                gpu_page, gpu_offset, length);
 204                 else
 205                         return slow_shmem_copy(gpu_page, gpu_offset,
 206                                                cpu_page, cpu_offset, length);
 207         }
 208
 209         gpu_vaddr = kmap(gpu_page);
 210         cpu_vaddr = kmap(cpu_page);
 211
 212         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 213          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 214          */
 215         while (length > 0) {
 216                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 217                 int this_length = min(cacheline_end - gpu_offset, length);
 218                 int swizzled_gpu_offset = gpu_offset ^ 64;
 219
 220                 if (is_read) {
 221                         memcpy(cpu_vaddr + cpu_offset,
 222                                gpu_vaddr + swizzled_gpu_offset,
 223                                this_length);
 224                 } else {
 225                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 226                                cpu_vaddr + cpu_offset,
 227                                this_length);
 228                 }
 229                 cpu_offset += this_length;
 230                 gpu_offset += this_length;
 231                 length -= this_length;
 232         }
 233
 234         kunmap(cpu_page);
 235         kunmap(gpu_page);
 236 }
 237
 238 /**
 239  * This is the fast shmem pread path, which attempts to copy_from_user directly
 240  * from the backing pages of the object to the user's address space.  On a
 241  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 242  */
 243 static int
 244 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 245                           struct drm_i915_gem_pread *args,
 246                           struct drm_file *file_priv)
 247 {
 248         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 249         ssize_t remain;
 250         loff_t offset, page_base;
 251         char __user *user_data;
 252         int page_offset, page_length;
 253         int ret;
 254
 255         user_data = (char __user *) (uintptr_t) args->data_ptr;
 256         remain = args->size;
 257
 258         mutex_lock(&dev->struct_mutex);
 259
 260         ret = i915_gem_object_get_pages(obj, 0);
 261         if (ret != 0)
 262                 goto fail_unlock;
 263
 264         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 265                                                         args->size);
 266         if (ret != 0)
 267                 goto fail_put_pages;
 268
 269         obj_priv = to_intel_bo(obj);
 270         offset = args->offset;
 271
 272         while (remain > 0) {
 273                 /* Operation in this page
 274                  *
 275                  * page_base = page offset within aperture
 276                  * page_offset = offset within page
 277                  * page_length = bytes to copy for this page
 278                  */
 279                 page_base = (offset & ~(PAGE_SIZE-1));
 280                 page_offset = offset & (PAGE_SIZE-1);
 281                 page_length = remain;
 282                 if ((page_offset + remain) > PAGE_SIZE)
 283                         page_length = PAGE_SIZE - page_offset;
 284
 285                 ret = fast_shmem_read(obj_priv->pages,
 286                                       page_base, page_offset,
 287                                       user_data, page_length);
 288                 if (ret)
 289                         goto fail_put_pages;
 290
 291                 remain -= page_length;
 292                 user_data += page_length;
 293                 offset += page_length;
 294         }
 295
 296 fail_put_pages:
 297         i915_gem_object_put_pages(obj);
 298 fail_unlock:
 299         mutex_unlock(&dev->struct_mutex);
 300
 301         return ret;
 302 }
 303
 304 static int
 305 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 306 {
 307         int ret;
 308
 309         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 310
 311         /* If we've insufficient memory to map in the pages, attempt
 312          * to make some space by throwing out some old buffers.
 313          */
 314         if (ret == -ENOMEM) {
 315                 struct drm_device *dev = obj->dev;
 316
 317                 ret = i915_gem_evict_something(dev, obj->size);
 318                 if (ret)
 319                         return ret;
 320
 321                 ret = i915_gem_object_get_pages(obj, 0);
 322         }
 323
 324         return ret;
 325 }
 326
 327 /**
 328  * This is the fallback shmem pread path, which allocates temporary storage
 329  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 330  * can copy out of the object's backing pages while holding the struct mutex
 331  * and not take page faults.
 332  */
 333 static int
 334 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 335                           struct drm_i915_gem_pread *args,
 336                           struct drm_file *file_priv)
 337 {
 338         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 339         struct mm_struct *mm = current->mm;
 340         struct page **user_pages;
 341         ssize_t remain;
 342         loff_t offset, pinned_pages, i;
 343         loff_t first_data_page, last_data_page, num_pages;
 344         int shmem_page_index, shmem_page_offset;
 345         int data_page_index,  data_page_offset;
 346         int page_length;
 347         int ret;
 348         uint64_t data_ptr = args->data_ptr;
 349         int do_bit17_swizzling;
 350
 351         remain = args->size;
 352
 353         /* Pin the user pages containing the data.  We can't fault while
 354          * holding the struct mutex, yet we want to hold it while
 355          * dereferencing the user data.
 356          */
 357         first_data_page = data_ptr / PAGE_SIZE;
 358         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 359         num_pages = last_data_page - first_data_page + 1;
 360
 361         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 362         if (user_pages == NULL)
 363                 return -ENOMEM;
 364
 365         down_read(&mm->mmap_sem);
 366         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 367                                       num_pages, 1, 0, user_pages, NULL);
 368         up_read(&mm->mmap_sem);
 369         if (pinned_pages < num_pages) {
 370                 ret = -EFAULT;
 371                 goto fail_put_user_pages;
 372         }
 373
 374         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 375
 376         mutex_lock(&dev->struct_mutex);
 377
 378         ret = i915_gem_object_get_pages_or_evict(obj);
 379         if (ret)
 380                 goto fail_unlock;
 381
 382         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 383                                                         args->size);
 384         if (ret != 0)
 385                 goto fail_put_pages;
 386
 387         obj_priv = to_intel_bo(obj);
 388         offset = args->offset;
 389
 390         while (remain > 0) {
 391                 /* Operation in this page
 392                  *
 393                  * shmem_page_index = page number within shmem file
 394                  * shmem_page_offset = offset within page in shmem file
 395                  * data_page_index = page number in get_user_pages return
 396                  * data_page_offset = offset with data_page_index page.
 397                  * page_length = bytes to copy for this page
 398                  */
 399                 shmem_page_index = offset / PAGE_SIZE;
 400                 shmem_page_offset = offset & ~PAGE_MASK;
 401                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 402                 data_page_offset = data_ptr & ~PAGE_MASK;
 403
 404                 page_length = remain;
 405                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 406                         page_length = PAGE_SIZE - shmem_page_offset;
 407                 if ((data_page_offset + page_length) > PAGE_SIZE)
 408                         page_length = PAGE_SIZE - data_page_offset;
 409
 410                 if (do_bit17_swizzling) {
 411                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 412                                               shmem_page_offset,
 413                                               user_pages[data_page_index],
 414                                               data_page_offset,
 415                                               page_length,
 416                                               1);
 417                 } else {
 418                         slow_shmem_copy(user_pages[data_page_index],
 419                                         data_page_offset,
 420                                         obj_priv->pages[shmem_page_index],
 421                                         shmem_page_offset,
 422                                         page_length);
 423                 }
 424
 425                 remain -= page_length;
 426                 data_ptr += page_length;
 427                 offset += page_length;
 428         }
 429
 430 fail_put_pages:
 431         i915_gem_object_put_pages(obj);
 432 fail_unlock:
 433         mutex_unlock(&dev->struct_mutex);
 434 fail_put_user_pages:
 435         for (i = 0; i < pinned_pages; i++) {
 436                 SetPageDirty(user_pages[i]);
 437                 page_cache_release(user_pages[i]);
 438         }
 439         drm_free_large(user_pages);
 440
 441         return ret;
 442 }
 443
 444 /**
 445  * Reads data from the object referenced by handle.
 446  *
 447  * On error, the contents of *data are undefined.
 448  */
 449 int
 450 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 451                      struct drm_file *file_priv)
 452 {
 453         struct drm_i915_gem_pread *args = data;
 454         struct drm_gem_object *obj;
 455         struct drm_i915_gem_object *obj_priv;
 456         int ret;
 457
 458         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 459         if (obj == NULL)
 460                 return -EBADF;
 461         obj_priv = to_intel_bo(obj);
 462
 463         /* Bounds check source.
 464          *
 465          * XXX: This could use review for overflow issues...
 466          */
 467         if (args->offset > obj->size || args->size > obj->size ||
 468             args->offset + args->size > obj->size) {
 469                 drm_gem_object_unreference_unlocked(obj);
 470                 return -EINVAL;
 471         }
 472
 473         if (i915_gem_object_needs_bit17_swizzle(obj)) {
 474                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 475         } else {
 476                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 477                 if (ret != 0)
 478                         ret = i915_gem_shmem_pread_slow(dev, obj, args,
 479                                                         file_priv);
 480         }
 481
 482         drm_gem_object_unreference_unlocked(obj);
 483
 484         return ret;
 485 }
 486
 487 /* This is the fast write path which cannot handle
 488  * page faults in the source data
 489  */
 490
 491 static inline int
 492 fast_user_write(struct io_mapping *mapping,
 493                 loff_t page_base, int page_offset,
 494                 char __user *user_data,
 495                 int length)
 496 {
 497         char *vaddr_atomic;
 498         unsigned long unwritten;
 499
 500         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 501         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 502                                                       user_data, length);
 503         io_mapping_unmap_atomic(vaddr_atomic);
 504         if (unwritten)
 505                 return -EFAULT;
 506         return 0;
 507 }
 508
 509 /* Here's the write path which can sleep for
 510  * page faults
 511  */
 512
 513 static inline void
 514 slow_kernel_write(struct io_mapping *mapping,
 515                   loff_t gtt_base, int gtt_offset,
 516                   struct page *user_page, int user_offset,
 517                   int length)
 518 {
 519         char __iomem *dst_vaddr;
 520         char *src_vaddr;
 521
 522         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 523         src_vaddr = kmap(user_page);
 524
 525         memcpy_toio(dst_vaddr + gtt_offset,
 526                     src_vaddr + user_offset,
 527                     length);
 528
 529         kunmap(user_page);
 530         io_mapping_unmap(dst_vaddr);
 531 }
 532
 533 static inline int
 534 fast_shmem_write(struct page **pages,
 535                  loff_t page_base, int page_offset,
 536                  char __user *data,
 537                  int length)
 538 {
 539         char __iomem *vaddr;
 540         unsigned long unwritten;
 541
 542         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
 543         if (vaddr == NULL)
 544                 return -ENOMEM;
 545         unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 546         kunmap_atomic(vaddr, KM_USER0);
 547
 548         if (unwritten)
 549                 return -EFAULT;
 550         return 0;
 551 }
 552
 553 /**
 554  * This is the fast pwrite path, where we copy the data directly from the
 555  * user into the GTT, uncached.
 556  */
 557 static int
 558 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 559                          struct drm_i915_gem_pwrite *args,
 560                          struct drm_file *file_priv)
 561 {
 562         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 563         drm_i915_private_t *dev_priv = dev->dev_private;
 564         ssize_t remain;
 565         loff_t offset, page_base;
 566         char __user *user_data;
 567         int page_offset, page_length;
 568         int ret;
 569
 570         user_data = (char __user *) (uintptr_t) args->data_ptr;
 571         remain = args->size;
 572         if (!access_ok(VERIFY_READ, user_data, remain))
 573                 return -EFAULT;
 574
 575
 576         mutex_lock(&dev->struct_mutex);
 577         ret = i915_gem_object_pin(obj, 0);
 578         if (ret) {
 579                 mutex_unlock(&dev->struct_mutex);
 580                 return ret;
 581         }
 582         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 583         if (ret)
 584                 goto fail;
 585
 586         obj_priv = to_intel_bo(obj);
 587         offset = obj_priv->gtt_offset + args->offset;
 588
 589         while (remain > 0) {
 590                 /* Operation in this page
 591                  *
 592                  * page_base = page offset within aperture
 593                  * page_offset = offset within page
 594                  * page_length = bytes to copy for this page
 595                  */
 596                 page_base = (offset & ~(PAGE_SIZE-1));
 597                 page_offset = offset & (PAGE_SIZE-1);
 598                 page_length = remain;
 599                 if ((page_offset + remain) > PAGE_SIZE)
 600                         page_length = PAGE_SIZE - page_offset;
 601
 602                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 603                                        page_offset, user_data, page_length);
 604
 605                 /* If we get a fault while copying data, then (presumably) our
 606                  * source page isn't available.  Return the error and we'll
 607                  * retry in the slow path.
 608                  */
 609                 if (ret)
 610                         goto fail;
 611
 612                 remain -= page_length;
 613                 user_data += page_length;
 614                 offset += page_length;
 615         }
 616
 617 fail:
 618         i915_gem_object_unpin(obj);
 619         mutex_unlock(&dev->struct_mutex);
 620
 621         return ret;
 622 }
 623
 624 /**
 625  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 626  * the memory and maps it using kmap_atomic for copying.
 627  *
 628  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 629  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 630  */
 631 static int
 632 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 633                          struct drm_i915_gem_pwrite *args,
 634                          struct drm_file *file_priv)
 635 {
 636         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 637         drm_i915_private_t *dev_priv = dev->dev_private;
 638         ssize_t remain;
 639         loff_t gtt_page_base, offset;
 640         loff_t first_data_page, last_data_page, num_pages;
 641         loff_t pinned_pages, i;
 642         struct page **user_pages;
 643         struct mm_struct *mm = current->mm;
 644         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 645         int ret;
 646         uint64_t data_ptr = args->data_ptr;
 647
 648         remain = args->size;
 649
 650         /* Pin the user pages containing the data.  We can't fault while
 651          * holding the struct mutex, and all of the pwrite implementations
 652          * want to hold it while dereferencing the user data.
 653          */
 654         first_data_page = data_ptr / PAGE_SIZE;
 655         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 656         num_pages = last_data_page - first_data_page + 1;
 657
 658         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 659         if (user_pages == NULL)
 660                 return -ENOMEM;
 661
 662         down_read(&mm->mmap_sem);
 663         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 664                                       num_pages, 0, 0, user_pages, NULL);
 665         up_read(&mm->mmap_sem);
 666         if (pinned_pages < num_pages) {
 667                 ret = -EFAULT;
 668                 goto out_unpin_pages;
 669         }
 670
 671         mutex_lock(&dev->struct_mutex);
 672         ret = i915_gem_object_pin(obj, 0);
 673         if (ret)
 674                 goto out_unlock;
 675
 676         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 677         if (ret)
 678                 goto out_unpin_object;
 679
 680         obj_priv = to_intel_bo(obj);
 681         offset = obj_priv->gtt_offset + args->offset;
 682
 683         while (remain > 0) {
 684                 /* Operation in this page
 685                  *
 686                  * gtt_page_base = page offset within aperture
 687                  * gtt_page_offset = offset within page in aperture
 688                  * data_page_index = page number in get_user_pages return
 689                  * data_page_offset = offset with data_page_index page.
 690                  * page_length = bytes to copy for this page
 691                  */
 692                 gtt_page_base = offset & PAGE_MASK;
 693                 gtt_page_offset = offset & ~PAGE_MASK;
 694                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 695                 data_page_offset = data_ptr & ~PAGE_MASK;
 696
 697                 page_length = remain;
 698                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 699                         page_length = PAGE_SIZE - gtt_page_offset;
 700                 if ((data_page_offset + page_length) > PAGE_SIZE)
 701                         page_length = PAGE_SIZE - data_page_offset;
 702
 703                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 704                                   gtt_page_base, gtt_page_offset,
 705                                   user_pages[data_page_index],
 706                                   data_page_offset,
 707                                   page_length);
 708
 709                 remain -= page_length;
 710                 offset += page_length;
 711                 data_ptr += page_length;
 712         }
 713
 714 out_unpin_object:
 715         i915_gem_object_unpin(obj);
 716 out_unlock:
 717         mutex_unlock(&dev->struct_mutex);
 718 out_unpin_pages:
 719         for (i = 0; i < pinned_pages; i++)
 720                 page_cache_release(user_pages[i]);
 721         drm_free_large(user_pages);
 722
 723         return ret;
 724 }
 725
 726 /**
 727  * This is the fast shmem pwrite path, which attempts to directly
 728  * copy_from_user into the kmapped pages backing the object.
 729  */
 730 static int
 731 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 732                            struct drm_i915_gem_pwrite *args,
 733                            struct drm_file *file_priv)
 734 {
 735         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 736         ssize_t remain;
 737         loff_t offset, page_base;
 738         char __user *user_data;
 739         int page_offset, page_length;
 740         int ret;
 741
 742         user_data = (char __user *) (uintptr_t) args->data_ptr;
 743         remain = args->size;
 744
 745         mutex_lock(&dev->struct_mutex);
 746
 747         ret = i915_gem_object_get_pages(obj, 0);
 748         if (ret != 0)
 749                 goto fail_unlock;
 750
 751         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 752         if (ret != 0)
 753                 goto fail_put_pages;
 754
 755         obj_priv = to_intel_bo(obj);
 756         offset = args->offset;
 757         obj_priv->dirty = 1;
 758
 759         while (remain > 0) {
 760                 /* Operation in this page
 761                  *
 762                  * page_base = page offset within aperture
 763                  * page_offset = offset within page
 764                  * page_length = bytes to copy for this page
 765                  */
 766                 page_base = (offset & ~(PAGE_SIZE-1));
 767                 page_offset = offset & (PAGE_SIZE-1);
 768                 page_length = remain;
 769                 if ((page_offset + remain) > PAGE_SIZE)
 770                         page_length = PAGE_SIZE - page_offset;
 771
 772                 ret = fast_shmem_write(obj_priv->pages,
 773                                        page_base, page_offset,
 774                                        user_data, page_length);
 775                 if (ret)
 776                         goto fail_put_pages;
 777
 778                 remain -= page_length;
 779                 user_data += page_length;
 780                 offset += page_length;
 781         }
 782
 783 fail_put_pages:
 784         i915_gem_object_put_pages(obj);
 785 fail_unlock:
 786         mutex_unlock(&dev->struct_mutex);
 787
 788         return ret;
 789 }
 790
 791 /**
 792  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 793  * the memory and maps it using kmap_atomic for copying.
 794  *
 795  * This avoids taking mmap_sem for faulting on the user's address while the
 796  * struct_mutex is held.
 797  */
 798 static int
 799 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 800                            struct drm_i915_gem_pwrite *args,
 801                            struct drm_file *file_priv)
 802 {
 803         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 804         struct mm_struct *mm = current->mm;
 805         struct page **user_pages;
 806         ssize_t remain;
 807         loff_t offset, pinned_pages, i;
 808         loff_t first_data_page, last_data_page, num_pages;
 809         int shmem_page_index, shmem_page_offset;
 810         int data_page_index,  data_page_offset;
 811         int page_length;
 812         int ret;
 813         uint64_t data_ptr = args->data_ptr;
 814         int do_bit17_swizzling;
 815
 816         remain = args->size;
 817
 818         /* Pin the user pages containing the data.  We can't fault while
 819          * holding the struct mutex, and all of the pwrite implementations
 820          * want to hold it while dereferencing the user data.
 821          */
 822         first_data_page = data_ptr / PAGE_SIZE;
 823         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 824         num_pages = last_data_page - first_data_page + 1;
 825
 826         user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
 827         if (user_pages == NULL)
 828                 return -ENOMEM;
 829
 830         down_read(&mm->mmap_sem);
 831         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 832                                       num_pages, 0, 0, user_pages, NULL);
 833         up_read(&mm->mmap_sem);
 834         if (pinned_pages < num_pages) {
 835                 ret = -EFAULT;
 836                 goto fail_put_user_pages;
 837         }
 838
 839         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 840
 841         mutex_lock(&dev->struct_mutex);
 842
 843         ret = i915_gem_object_get_pages_or_evict(obj);
 844         if (ret)
 845                 goto fail_unlock;
 846
 847         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 848         if (ret != 0)
 849                 goto fail_put_pages;
 850
 851         obj_priv = to_intel_bo(obj);
 852         offset = args->offset;
 853         obj_priv->dirty = 1;
 854
 855         while (remain > 0) {
 856                 /* Operation in this page
 857                  *
 858                  * shmem_page_index = page number within shmem file
 859                  * shmem_page_offset = offset within page in shmem file
 860                  * data_page_index = page number in get_user_pages return
 861                  * data_page_offset = offset with data_page_index page.
 862                  * page_length = bytes to copy for this page
 863                  */
 864                 shmem_page_index = offset / PAGE_SIZE;
 865                 shmem_page_offset = offset & ~PAGE_MASK;
 866                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 867                 data_page_offset = data_ptr & ~PAGE_MASK;
 868
 869                 page_length = remain;
 870                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 871                         page_length = PAGE_SIZE - shmem_page_offset;
 872                 if ((data_page_offset + page_length) > PAGE_SIZE)
 873                         page_length = PAGE_SIZE - data_page_offset;
 874
 875                 if (do_bit17_swizzling) {
 876                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 877                                               shmem_page_offset,
 878                                               user_pages[data_page_index],
 879                                               data_page_offset,
 880                                               page_length,
 881                                               0);
 882                 } else {
 883                         slow_shmem_copy(obj_priv->pages[shmem_page_index],
 884                                         shmem_page_offset,
 885                                         user_pages[data_page_index],
 886                                         data_page_offset,
 887                                         page_length);
 888                 }
 889
 890                 remain -= page_length;
 891                 data_ptr += page_length;
 892                 offset += page_length;
 893         }
 894
 895 fail_put_pages:
 896         i915_gem_object_put_pages(obj);
 897 fail_unlock:
 898         mutex_unlock(&dev->struct_mutex);
 899 fail_put_user_pages:
 900         for (i = 0; i < pinned_pages; i++)
 901                 page_cache_release(user_pages[i]);
 902         drm_free_large(user_pages);
 903
 904         return ret;
 905 }
 906
 907 /**
 908  * Writes data to the object referenced by handle.
 909  *
 910  * On error, the contents of the buffer that were to be modified are undefined.
 911  */
 912 int
 913 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 914                       struct drm_file *file_priv)
 915 {
 916         struct drm_i915_gem_pwrite *args = data;
 917         struct drm_gem_object *obj;
 918         struct drm_i915_gem_object *obj_priv;
 919         int ret = 0;
 920
 921         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 922         if (obj == NULL)
 923                 return -EBADF;
 924         obj_priv = to_intel_bo(obj);
 925
 926         /* Bounds check destination.
 927          *
 928          * XXX: This could use review for overflow issues...
 929          */
 930         if (args->offset > obj->size || args->size > obj->size ||
 931             args->offset + args->size > obj->size) {
 932                 drm_gem_object_unreference_unlocked(obj);
 933                 return -EINVAL;
 934         }
 935
 936         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 937          * it would end up going through the fenced access, and we'll get
 938          * different detiling behavior between reading and writing.
 939          * pread/pwrite currently are reading and writing from the CPU
 940          * perspective, requiring manual detiling by the client.
 941          */
 942         if (obj_priv->phys_obj)
 943                 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
 944         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
 945                  dev->gtt_total != 0 &&
 946                  obj->write_domain != I915_GEM_DOMAIN_CPU) {
 947                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
 948                 if (ret == -EFAULT) {
 949                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
 950                                                        file_priv);
 951                 }
 952         } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
 953                 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
 954         } else {
 955                 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
 956                 if (ret == -EFAULT) {
 957                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
 958                                                          file_priv);
 959                 }
 960         }
 961
 962 #if WATCH_PWRITE
 963         if (ret)
 964                 DRM_INFO("pwrite failed %d\n", ret);
 965 #endif
 966
 967         drm_gem_object_unreference_unlocked(obj);
 968
 969         return ret;
 970 }
 971
 972 /**
 973  * Called when user space prepares to use an object with the CPU, either
 974  * through the mmap ioctl's mapping or a GTT mapping.
 975  */
 976 int
 977 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 978                           struct drm_file *file_priv)
 979 {
 980         struct drm_i915_private *dev_priv = dev->dev_private;
 981         struct drm_i915_gem_set_domain *args = data;
 982         struct drm_gem_object *obj;
 983         struct drm_i915_gem_object *obj_priv;
 984         uint32_t read_domains = args->read_domains;
 985         uint32_t write_domain = args->write_domain;
 986         int ret;
 987
 988         if (!(dev->driver->driver_features & DRIVER_GEM))
 989                 return -ENODEV;
 990
 991         /* Only handle setting domains to types used by the CPU. */
 992         if (write_domain & I915_GEM_GPU_DOMAINS)
 993                 return -EINVAL;
 994
 995         if (read_domains & I915_GEM_GPU_DOMAINS)
 996                 return -EINVAL;
 997
 998         /* Having something in the write domain implies it's in the read
 999          * domain, and only that read domain.  Enforce that in the request.
1000          */
1001         if (write_domain != 0 && read_domains != write_domain)
1002                 return -EINVAL;
1003
1004         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1005         if (obj == NULL)
1006                 return -EBADF;
1007         obj_priv = to_intel_bo(obj);
1008
1009         mutex_lock(&dev->struct_mutex);
1010
1011         intel_mark_busy(dev, obj);
1012
1013 #if WATCH_BUF
1014         DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1015                  obj, obj->size, read_domains, write_domain);
1016 #endif
1017         if (read_domains & I915_GEM_DOMAIN_GTT) {
1018                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1019
1020                 /* Update the LRU on the fence for the CPU access that's
1021                  * about to occur.
1022                  */
1023                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1024                         struct drm_i915_fence_reg *reg =
1025                                 &dev_priv->fence_regs[obj_priv->fence_reg];
1026                         list_move_tail(&reg->lru_list,
1027                                        &dev_priv->mm.fence_list);
1028                 }
1029
1030                 /* Silently promote "you're not bound, there was nothing to do"
1031                  * to success, since the client was just asking us to
1032                  * make sure everything was done.
1033                  */
1034                 if (ret == -EINVAL)
1035                         ret = 0;
1036         } else {
1037                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1038         }
1039
1040         drm_gem_object_unreference(obj);
1041         mutex_unlock(&dev->struct_mutex);
1042         return ret;
1043 }
1044
1045 /**
1046  * Called when user space has done writes to this buffer
1047  */
1048 int
1049 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1050                       struct drm_file *file_priv)
1051 {
1052         struct drm_i915_gem_sw_finish *args = data;
1053         struct drm_gem_object *obj;
1054         struct drm_i915_gem_object *obj_priv;
1055         int ret = 0;
1056
1057         if (!(dev->driver->driver_features & DRIVER_GEM))
1058                 return -ENODEV;
1059
1060         mutex_lock(&dev->struct_mutex);
1061         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1062         if (obj == NULL) {
1063                 mutex_unlock(&dev->struct_mutex);
1064                 return -EBADF;
1065         }
1066
1067 #if WATCH_BUF
1068         DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1069                  __func__, args->handle, obj, obj->size);
1070 #endif
1071         obj_priv = to_intel_bo(obj);
1072
1073         /* Pinned buffers may be scanout, so flush the cache */
1074         if (obj_priv->pin_count)
1075                 i915_gem_object_flush_cpu_write_domain(obj);
1076
1077         drm_gem_object_unreference(obj);
1078         mutex_unlock(&dev->struct_mutex);
1079         return ret;
1080 }
1081
1082 /**
1083  * Maps the contents of an object, returning the address it is mapped
1084  * into.
1085  *
1086  * While the mapping holds a reference on the contents of the object, it doesn't
1087  * imply a ref on the object itself.
1088  */
1089 int
1090 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1091                    struct drm_file *file_priv)
1092 {
1093         struct drm_i915_gem_mmap *args = data;
1094         struct drm_gem_object *obj;
1095         loff_t offset;
1096         unsigned long addr;
1097
1098         if (!(dev->driver->driver_features & DRIVER_GEM))
1099                 return -ENODEV;
1100
1101         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1102         if (obj == NULL)
1103                 return -EBADF;
1104
1105         offset = args->offset;
1106
1107         down_write(&current->mm->mmap_sem);
1108         addr = do_mmap(obj->filp, 0, args->size,
1109                        PROT_READ | PROT_WRITE, MAP_SHARED,
1110                        args->offset);
1111         up_write(&current->mm->mmap_sem);
1112         drm_gem_object_unreference_unlocked(obj);
1113         if (IS_ERR((void *)addr))
1114                 return addr;
1115
1116         args->addr_ptr = (uint64_t) addr;
1117
1118         return 0;
1119 }
1120
1121 /**
1122  * i915_gem_fault - fault a page into the GTT
1123  * vma: VMA in question
1124  * vmf: fault info
1125  *
1126  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1127  * from userspace.  The fault handler takes care of binding the object to
1128  * the GTT (if needed), allocating and programming a fence register (again,
1129  * only if needed based on whether the old reg is still valid or the object
1130  * is tiled) and inserting a new PTE into the faulting process.
1131  *
1132  * Note that the faulting process may involve evicting existing objects
1133  * from the GTT and/or fence registers to make room.  So performance may
1134  * suffer if the GTT working set is large or there are few fence registers
1135  * left.
1136  */
1137 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1138 {
1139         struct drm_gem_object *obj = vma->vm_private_data;
1140         struct drm_device *dev = obj->dev;
1141         struct drm_i915_private *dev_priv = dev->dev_private;
1142         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1143         pgoff_t page_offset;
1144         unsigned long pfn;
1145         int ret = 0;
1146         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1147
1148         /* We don't use vmf->pgoff since that has the fake offset */
1149         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1150                 PAGE_SHIFT;
1151
1152         /* Now bind it into the GTT if needed */
1153         mutex_lock(&dev->struct_mutex);
1154         if (!obj_priv->gtt_space) {
1155                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1156                 if (ret)
1157                         goto unlock;
1158
1159                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1160
1161                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1162                 if (ret)
1163                         goto unlock;
1164         }
1165
1166         /* Need a new fence register? */
1167         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1168                 ret = i915_gem_object_get_fence_reg(obj);
1169                 if (ret)
1170                         goto unlock;
1171         }
1172
1173         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1174                 page_offset;
1175
1176         /* Finally, remap it using the new GTT offset */
1177         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1178 unlock:
1179         mutex_unlock(&dev->struct_mutex);
1180
1181         switch (ret) {
1182         case 0:
1183         case -ERESTARTSYS:
1184                 return VM_FAULT_NOPAGE;
1185         case -ENOMEM:
1186         case -EAGAIN:
1187                 return VM_FAULT_OOM;
1188         default:
1189                 return VM_FAULT_SIGBUS;
1190         }
1191 }
1192
1193 /**
1194  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1195  * @obj: obj in question
1196  *
1197  * GEM memory mapping works by handing back to userspace a fake mmap offset
1198  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1199  * up the object based on the offset and sets up the various memory mapping
1200  * structures.
1201  *
1202  * This routine allocates and attaches a fake offset for @obj.
1203  */
1204 static int
1205 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1206 {
1207         struct drm_device *dev = obj->dev;
1208         struct drm_gem_mm *mm = dev->mm_private;
1209         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1210         struct drm_map_list *list;
1211         struct drm_local_map *map;
1212         int ret = 0;
1213
1214         /* Set the object up for mmap'ing */
1215         list = &obj->map_list;
1216         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1217         if (!list->map)
1218                 return -ENOMEM;
1219
1220         map = list->map;
1221         map->type = _DRM_GEM;
1222         map->size = obj->size;
1223         map->handle = obj;
1224
1225         /* Get a DRM GEM mmap offset allocated... */
1226         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1227                                                     obj->size / PAGE_SIZE, 0, 0);
1228         if (!list->file_offset_node) {
1229                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1230                 ret = -ENOMEM;
1231                 goto out_free_list;
1232         }
1233
1234         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1235                                                   obj->size / PAGE_SIZE, 0);
1236         if (!list->file_offset_node) {
1237                 ret = -ENOMEM;
1238                 goto out_free_list;
1239         }
1240
1241         list->hash.key = list->file_offset_node->start;
1242         if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1243                 DRM_ERROR("failed to add to map hash\n");
1244                 ret = -ENOMEM;
1245                 goto out_free_mm;
1246         }
1247
1248         /* By now we should be all set, any drm_mmap request on the offset
1249          * below will get to our mmap & fault handler */
1250         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1251
1252         return 0;
1253
1254 out_free_mm:
1255         drm_mm_put_block(list->file_offset_node);
1256 out_free_list:
1257         kfree(list->map);
1258
1259         return ret;
1260 }
1261
1262 /**
1263  * i915_gem_release_mmap - remove physical page mappings
1264  * @obj: obj in question
1265  *
1266  * Preserve the reservation of the mmapping with the DRM core code, but
1267  * relinquish ownership of the pages back to the system.
1268  *
1269  * It is vital that we remove the page mapping if we have mapped a tiled
1270  * object through the GTT and then lose the fence register due to
1271  * resource pressure. Similarly if the object has been moved out of the
1272  * aperture, than pages mapped into userspace must be revoked. Removing the
1273  * mapping will then trigger a page fault on the next user access, allowing
1274  * fixup by i915_gem_fault().
1275  */
1276 void
1277 i915_gem_release_mmap(struct drm_gem_object *obj)
1278 {
1279         struct drm_device *dev = obj->dev;
1280         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1281
1282         if (dev->dev_mapping)
1283                 unmap_mapping_range(dev->dev_mapping,
1284                                     obj_priv->mmap_offset, obj->size, 1);
1285 }
1286
1287 static void
1288 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1289 {
1290         struct drm_device *dev = obj->dev;
1291         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1292         struct drm_gem_mm *mm = dev->mm_private;
1293         struct drm_map_list *list;
1294
1295         list = &obj->map_list;
1296         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1297
1298         if (list->file_offset_node) {
1299                 drm_mm_put_block(list->file_offset_node);
1300                 list->file_offset_node = NULL;
1301         }
1302
1303         if (list->map) {
1304                 kfree(list->map);
1305                 list->map = NULL;
1306         }
1307
1308         obj_priv->mmap_offset = 0;
1309 }
1310
1311 /**
1312  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1313  * @obj: object to check
1314  *
1315  * Return the required GTT alignment for an object, taking into account
1316  * potential fence register mapping if needed.
1317  */
1318 static uint32_t
1319 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1320 {
1321         struct drm_device *dev = obj->dev;
1322         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1323         int start, i;
1324
1325         /*
1326          * Minimum alignment is 4k (GTT page size), but might be greater
1327          * if a fence register is needed for the object.
1328          */
1329         if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1330                 return 4096;
1331
1332         /*
1333          * Previous chips need to be aligned to the size of the smallest
1334          * fence register that can contain the object.
1335          */
1336         if (IS_I9XX(dev))
1337                 start = 1024*1024;
1338         else
1339                 start = 512*1024;
1340
1341         for (i = start; i < obj->size; i <<= 1)
1342                 ;
1343
1344         return i;
1345 }
1346
1347 /**
1348  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1349  * @dev: DRM device
1350  * @data: GTT mapping ioctl data
1351  * @file_priv: GEM object info
1352  *
1353  * Simply returns the fake offset to userspace so it can mmap it.
1354  * The mmap call will end up in drm_gem_mmap(), which will set things
1355  * up so we can get faults in the handler above.
1356  *
1357  * The fault handler will take care of binding the object into the GTT
1358  * (since it may have been evicted to make room for something), allocating
1359  * a fence register, and mapping the appropriate aperture address into
1360  * userspace.
1361  */
1362 int
1363 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1364                         struct drm_file *file_priv)
1365 {
1366         struct drm_i915_gem_mmap_gtt *args = data;
1367         struct drm_i915_private *dev_priv = dev->dev_private;
1368         struct drm_gem_object *obj;
1369         struct drm_i915_gem_object *obj_priv;
1370         int ret;
1371
1372         if (!(dev->driver->driver_features & DRIVER_GEM))
1373                 return -ENODEV;
1374
1375         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1376         if (obj == NULL)
1377                 return -EBADF;
1378
1379         mutex_lock(&dev->struct_mutex);
1380
1381         obj_priv = to_intel_bo(obj);
1382
1383         if (obj_priv->madv != I915_MADV_WILLNEED) {
1384                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1385                 drm_gem_object_unreference(obj);
1386                 mutex_unlock(&dev->struct_mutex);
1387                 return -EINVAL;
1388         }
1389
1390
1391         if (!obj_priv->mmap_offset) {
1392                 ret = i915_gem_create_mmap_offset(obj);
1393                 if (ret) {
1394                         drm_gem_object_unreference(obj);
1395                         mutex_unlock(&dev->struct_mutex);
1396                         return ret;
1397                 }
1398         }
1399
1400         args->offset = obj_priv->mmap_offset;
1401
1402         /*
1403          * Pull it into the GTT so that we have a page list (makes the
1404          * initial fault faster and any subsequent flushing possible).
1405          */
1406         if (!obj_priv->agp_mem) {
1407                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1408                 if (ret) {
1409                         drm_gem_object_unreference(obj);
1410                         mutex_unlock(&dev->struct_mutex);
1411                         return ret;
1412                 }
1413                 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1414         }
1415
1416         drm_gem_object_unreference(obj);
1417         mutex_unlock(&dev->struct_mutex);
1418
1419         return 0;
1420 }
1421
1422 void
1423 i915_gem_object_put_pages(struct drm_gem_object *obj)
1424 {
1425         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1426         int page_count = obj->size / PAGE_SIZE;
1427         int i;
1428
1429         BUG_ON(obj_priv->pages_refcount == 0);
1430         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1431
1432         if (--obj_priv->pages_refcount != 0)
1433                 return;
1434
1435         if (obj_priv->tiling_mode != I915_TILING_NONE)
1436                 i915_gem_object_save_bit_17_swizzle(obj);
1437
1438         if (obj_priv->madv == I915_MADV_DONTNEED)
1439                 obj_priv->dirty = 0;
1440
1441         for (i = 0; i < page_count; i++) {
1442                 if (obj_priv->dirty)
1443                         set_page_dirty(obj_priv->pages[i]);
1444
1445                 if (obj_priv->madv == I915_MADV_WILLNEED)
1446                         mark_page_accessed(obj_priv->pages[i]);
1447
1448                 page_cache_release(obj_priv->pages[i]);
1449         }
1450         obj_priv->dirty = 0;
1451
1452         drm_free_large(obj_priv->pages);
1453         obj_priv->pages = NULL;
1454 }
1455
1456 static void
1457 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1458                                struct intel_ring_buffer *ring)
1459 {
1460         struct drm_device *dev = obj->dev;
1461         drm_i915_private_t *dev_priv = dev->dev_private;
1462         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1463         BUG_ON(ring == NULL);
1464         obj_priv->ring = ring;
1465
1466         /* Add a reference if we're newly entering the active list. */
1467         if (!obj_priv->active) {
1468                 drm_gem_object_reference(obj);
1469                 obj_priv->active = 1;
1470         }
1471         /* Move from whatever list we were on to the tail of execution. */
1472         spin_lock(&dev_priv->mm.active_list_lock);
1473         list_move_tail(&obj_priv->list, &ring->active_list);
1474         spin_unlock(&dev_priv->mm.active_list_lock);
1475         obj_priv->last_rendering_seqno = seqno;
1476 }
1477
1478 static void
1479 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1480 {
1481         struct drm_device *dev = obj->dev;
1482         drm_i915_private_t *dev_priv = dev->dev_private;
1483         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1484
1485         BUG_ON(!obj_priv->active);
1486         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1487         obj_priv->last_rendering_seqno = 0;
1488 }
1489
1490 /* Immediately discard the backing storage */
1491 static void
1492 i915_gem_object_truncate(struct drm_gem_object *obj)
1493 {
1494         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1495         struct inode *inode;
1496
1497         inode = obj->filp->f_path.dentry->d_inode;
1498         if (inode->i_op->truncate)
1499                 inode->i_op->truncate (inode);
1500
1501         obj_priv->madv = __I915_MADV_PURGED;
1502 }
1503
1504 static inline int
1505 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1506 {
1507         return obj_priv->madv == I915_MADV_DONTNEED;
1508 }
1509
1510 static void
1511 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1512 {
1513         struct drm_device *dev = obj->dev;
1514         drm_i915_private_t *dev_priv = dev->dev_private;
1515         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1516
1517         i915_verify_inactive(dev, __FILE__, __LINE__);
1518         if (obj_priv->pin_count != 0)
1519                 list_del_init(&obj_priv->list);
1520         else
1521                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1522
1523         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1524
1525         obj_priv->last_rendering_seqno = 0;
1526         obj_priv->ring = NULL;
1527         if (obj_priv->active) {
1528                 obj_priv->active = 0;
1529                 drm_gem_object_unreference(obj);
1530         }
1531         i915_verify_inactive(dev, __FILE__, __LINE__);
1532 }
1533
1534 static void
1535 i915_gem_process_flushing_list(struct drm_device *dev,
1536                                uint32_t flush_domains, uint32_t seqno,
1537                                struct intel_ring_buffer *ring)
1538 {
1539         drm_i915_private_t *dev_priv = dev->dev_private;
1540         struct drm_i915_gem_object *obj_priv, *next;
1541
1542         list_for_each_entry_safe(obj_priv, next,
1543                                  &dev_priv->mm.gpu_write_list,
1544                                  gpu_write_list) {
1545                 struct drm_gem_object *obj = &obj_priv->base;
1546
1547                 if ((obj->write_domain & flush_domains) ==
1548                     obj->write_domain &&
1549                     obj_priv->ring->ring_flag == ring->ring_flag) {
1550                         uint32_t old_write_domain = obj->write_domain;
1551
1552                         obj->write_domain = 0;
1553                         list_del_init(&obj_priv->gpu_write_list);
1554                         i915_gem_object_move_to_active(obj, seqno, ring);
1555
1556                         /* update the fence lru list */
1557                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1558                                 struct drm_i915_fence_reg *reg =
1559                                         &dev_priv->fence_regs[obj_priv->fence_reg];
1560                                 list_move_tail(&reg->lru_list,
1561                                                 &dev_priv->mm.fence_list);
1562                         }
1563
1564                         trace_i915_gem_object_change_domain(obj,
1565                                                             obj->read_domains,
1566                                                             old_write_domain);
1567                 }
1568         }
1569 }
1570
1571 uint32_t
1572 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1573                  uint32_t flush_domains, struct intel_ring_buffer *ring)
1574 {
1575         drm_i915_private_t *dev_priv = dev->dev_private;
1576         struct drm_i915_file_private *i915_file_priv = NULL;
1577         struct drm_i915_gem_request *request;
1578         uint32_t seqno;
1579         int was_empty;
1580
1581         if (file_priv != NULL)
1582                 i915_file_priv = file_priv->driver_priv;
1583
1584         request = kzalloc(sizeof(*request), GFP_KERNEL);
1585         if (request == NULL)
1586                 return 0;
1587
1588         seqno = ring->add_request(dev, ring, file_priv, flush_domains);
1589
1590         request->seqno = seqno;
1591         request->ring = ring;
1592         request->emitted_jiffies = jiffies;
1593         was_empty = list_empty(&ring->request_list);
1594         list_add_tail(&request->list, &ring->request_list);
1595
1596         if (i915_file_priv) {
1597                 list_add_tail(&request->client_list,
1598                               &i915_file_priv->mm.request_list);
1599         } else {
1600                 INIT_LIST_HEAD(&request->client_list);
1601         }
1602
1603         /* Associate any objects on the flushing list matching the write
1604          * domain we're flushing with our flush.
1605          */
1606         if (flush_domains != 0)
1607                 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
1608
1609         if (!dev_priv->mm.suspended) {
1610                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1611                 if (was_empty)
1612                         queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1613         }
1614         return seqno;
1615 }
1616
1617 /**
1618  * Command execution barrier
1619  *
1620  * Ensures that all commands in the ring are finished
1621  * before signalling the CPU
1622  */
1623 static uint32_t
1624 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1625 {
1626         uint32_t flush_domains = 0;
1627
1628         /* The sampler always gets flushed on i965 (sigh) */
1629         if (IS_I965G(dev))
1630                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1631
1632         ring->flush(dev, ring,
1633                         I915_GEM_DOMAIN_COMMAND, flush_domains);
1634         return flush_domains;
1635 }
1636
1637 /**
1638  * Moves buffers associated only with the given active seqno from the active
1639  * to inactive list, potentially freeing them.
1640  */
1641 static void
1642 i915_gem_retire_request(struct drm_device *dev,
1643                         struct drm_i915_gem_request *request)
1644 {
1645         drm_i915_private_t *dev_priv = dev->dev_private;
1646
1647         trace_i915_gem_request_retire(dev, request->seqno);
1648
1649         /* Move any buffers on the active list that are no longer referenced
1650          * by the ringbuffer to the flushing/inactive lists as appropriate.
1651          */
1652         spin_lock(&dev_priv->mm.active_list_lock);
1653         while (!list_empty(&request->ring->active_list)) {
1654                 struct drm_gem_object *obj;
1655                 struct drm_i915_gem_object *obj_priv;
1656
1657                 obj_priv = list_first_entry(&request->ring->active_list,
1658                                             struct drm_i915_gem_object,
1659                                             list);
1660                 obj = &obj_priv->base;
1661
1662                 /* If the seqno being retired doesn't match the oldest in the
1663                  * list, then the oldest in the list must still be newer than
1664                  * this seqno.
1665                  */
1666                 if (obj_priv->last_rendering_seqno != request->seqno)
1667                         goto out;
1668
1669 #if WATCH_LRU
1670                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1671                          __func__, request->seqno, obj);
1672 #endif
1673
1674                 if (obj->write_domain != 0)
1675                         i915_gem_object_move_to_flushing(obj);
1676                 else {
1677                         /* Take a reference on the object so it won't be
1678                          * freed while the spinlock is held.  The list
1679                          * protection for this spinlock is safe when breaking
1680                          * the lock like this since the next thing we do
1681                          * is just get the head of the list again.
1682                          */
1683                         drm_gem_object_reference(obj);
1684                         i915_gem_object_move_to_inactive(obj);
1685                         spin_unlock(&dev_priv->mm.active_list_lock);
1686                         drm_gem_object_unreference(obj);
1687                         spin_lock(&dev_priv->mm.active_list_lock);
1688                 }
1689         }
1690 out:
1691         spin_unlock(&dev_priv->mm.active_list_lock);
1692 }
1693
1694 /**
1695  * Returns true if seq1 is later than seq2.
1696  */
1697 bool
1698 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1699 {
1700         return (int32_t)(seq1 - seq2) >= 0;
1701 }
1702
1703 uint32_t
1704 i915_get_gem_seqno(struct drm_device *dev,
1705                    struct intel_ring_buffer *ring)
1706 {
1707         return ring->get_gem_seqno(dev, ring);
1708 }
1709
1710 /**
1711  * This function clears the request list as sequence numbers are passed.
1712  */
1713 static void
1714 i915_gem_retire_requests_ring(struct drm_device *dev,
1715                               struct intel_ring_buffer *ring)
1716 {
1717         drm_i915_private_t *dev_priv = dev->dev_private;
1718         uint32_t seqno;
1719
1720         if (!ring->status_page.page_addr
1721                         || list_empty(&ring->request_list))
1722                 return;
1723
1724         seqno = i915_get_gem_seqno(dev, ring);
1725
1726         while (!list_empty(&ring->request_list)) {
1727                 struct drm_i915_gem_request *request;
1728                 uint32_t retiring_seqno;
1729
1730                 request = list_first_entry(&ring->request_list,
1731                                            struct drm_i915_gem_request,
1732                                            list);
1733                 retiring_seqno = request->seqno;
1734
1735                 if (i915_seqno_passed(seqno, retiring_seqno) ||
1736                     atomic_read(&dev_priv->mm.wedged)) {
1737                         i915_gem_retire_request(dev, request);
1738
1739                         list_del(&request->list);
1740                         list_del(&request->client_list);
1741                         kfree(request);
1742                 } else
1743                         break;
1744         }
1745
1746         if (unlikely (dev_priv->trace_irq_seqno &&
1747                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1748
1749                 ring->user_irq_put(dev, ring);
1750                 dev_priv->trace_irq_seqno = 0;
1751         }
1752 }
1753
1754 void
1755 i915_gem_retire_requests(struct drm_device *dev)
1756 {
1757         drm_i915_private_t *dev_priv = dev->dev_private;
1758
1759         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1760             struct drm_i915_gem_object *obj_priv, *tmp;
1761
1762             /* We must be careful that during unbind() we do not
1763              * accidentally infinitely recurse into retire requests.
1764              * Currently:
1765              *   retire -> free -> unbind -> wait -> retire_ring
1766              */
1767             list_for_each_entry_safe(obj_priv, tmp,
1768                                      &dev_priv->mm.deferred_free_list,
1769                                      list)
1770                     i915_gem_free_object_tail(&obj_priv->base);
1771         }
1772
1773         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1774         if (HAS_BSD(dev))
1775                 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1776 }
1777
1778 void
1779 i915_gem_retire_work_handler(struct work_struct *work)
1780 {
1781         drm_i915_private_t *dev_priv;
1782         struct drm_device *dev;
1783
1784         dev_priv = container_of(work, drm_i915_private_t,
1785                                 mm.retire_work.work);
1786         dev = dev_priv->dev;
1787
1788         mutex_lock(&dev->struct_mutex);
1789         i915_gem_retire_requests(dev);
1790
1791         if (!dev_priv->mm.suspended &&
1792                 (!list_empty(&dev_priv->render_ring.request_list) ||
1793                         (HAS_BSD(dev) &&
1794                          !list_empty(&dev_priv->bsd_ring.request_list))))
1795                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1796         mutex_unlock(&dev->struct_mutex);
1797 }
1798
1799 int
1800 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1801                 int interruptible, struct intel_ring_buffer *ring)
1802 {
1803         drm_i915_private_t *dev_priv = dev->dev_private;
1804         u32 ier;
1805         int ret = 0;
1806
1807         BUG_ON(seqno == 0);
1808
1809         if (atomic_read(&dev_priv->mm.wedged))
1810                 return -EIO;
1811
1812         if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1813                 if (HAS_PCH_SPLIT(dev))
1814                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1815                 else
1816                         ier = I915_READ(IER);
1817                 if (!ier) {
1818                         DRM_ERROR("something (likely vbetool) disabled "
1819                                   "interrupts, re-enabling\n");
1820                         i915_driver_irq_preinstall(dev);
1821                         i915_driver_irq_postinstall(dev);
1822                 }
1823
1824                 trace_i915_gem_request_wait_begin(dev, seqno);
1825
1826                 ring->waiting_gem_seqno = seqno;
1827                 ring->user_irq_get(dev, ring);
1828                 if (interruptible)
1829                         ret = wait_event_interruptible(ring->irq_queue,
1830                                 i915_seqno_passed(
1831                                         ring->get_gem_seqno(dev, ring), seqno)
1832                                 || atomic_read(&dev_priv->mm.wedged));
1833                 else
1834                         wait_event(ring->irq_queue,
1835                                 i915_seqno_passed(
1836                                         ring->get_gem_seqno(dev, ring), seqno)
1837                                 || atomic_read(&dev_priv->mm.wedged));
1838
1839                 ring->user_irq_put(dev, ring);
1840                 ring->waiting_gem_seqno = 0;
1841
1842                 trace_i915_gem_request_wait_end(dev, seqno);
1843         }
1844         if (atomic_read(&dev_priv->mm.wedged))
1845                 ret = -EIO;
1846
1847         if (ret && ret != -ERESTARTSYS)
1848                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1849                           __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
1850
1851         /* Directly dispatch request retiring.  While we have the work queue
1852          * to handle this, the waiter on a request often wants an associated
1853          * buffer to have made it to the inactive list, and we would need
1854          * a separate wait queue to handle that.
1855          */
1856         if (ret == 0)
1857                 i915_gem_retire_requests_ring(dev, ring);
1858
1859         return ret;
1860 }
1861
1862 /**
1863  * Waits for a sequence number to be signaled, and cleans up the
1864  * request and object lists appropriately for that event.
1865  */
1866 static int
1867 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1868                 struct intel_ring_buffer *ring)
1869 {
1870         return i915_do_wait_request(dev, seqno, 1, ring);
1871 }
1872
1873 static void
1874 i915_gem_flush(struct drm_device *dev,
1875                uint32_t invalidate_domains,
1876                uint32_t flush_domains)
1877 {
1878         drm_i915_private_t *dev_priv = dev->dev_private;
1879         if (flush_domains & I915_GEM_DOMAIN_CPU)
1880                 drm_agp_chipset_flush(dev);
1881         dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1882                         invalidate_domains,
1883                         flush_domains);
1884
1885         if (HAS_BSD(dev))
1886                 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1887                                 invalidate_domains,
1888                                 flush_domains);
1889 }
1890
1891 static void
1892 i915_gem_flush_ring(struct drm_device *dev,
1893                uint32_t invalidate_domains,
1894                uint32_t flush_domains,
1895                struct intel_ring_buffer *ring)
1896 {
1897         if (flush_domains & I915_GEM_DOMAIN_CPU)
1898                 drm_agp_chipset_flush(dev);
1899         ring->flush(dev, ring,
1900                         invalidate_domains,
1901                         flush_domains);
1902 }
1903
1904 /**
1905  * Ensures that all rendering to the object has completed and the object is
1906  * safe to unbind from the GTT or access from the CPU.
1907  */
1908 static int
1909 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1910 {
1911         struct drm_device *dev = obj->dev;
1912         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1913         int ret;
1914
1915         /* This function only exists to support waiting for existing rendering,
1916          * not for emitting required flushes.
1917          */
1918         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1919
1920         /* If there is rendering queued on the buffer being evicted, wait for
1921          * it.
1922          */
1923         if (obj_priv->active) {
1924 #if WATCH_BUF
1925                 DRM_INFO("%s: object %p wait for seqno %08x\n",
1926                           __func__, obj, obj_priv->last_rendering_seqno);
1927 #endif
1928                 ret = i915_wait_request(dev,
1929                                 obj_priv->last_rendering_seqno, obj_priv->ring);
1930                 if (ret != 0)
1931                         return ret;
1932         }
1933
1934         return 0;
1935 }
1936
1937 /**
1938  * Unbinds an object from the GTT aperture.
1939  */
1940 int
1941 i915_gem_object_unbind(struct drm_gem_object *obj)
1942 {
1943         struct drm_device *dev = obj->dev;
1944         drm_i915_private_t *dev_priv = dev->dev_private;
1945         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1946         int ret = 0;
1947
1948 #if WATCH_BUF
1949         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1950         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1951 #endif
1952         if (obj_priv->gtt_space == NULL)
1953                 return 0;
1954
1955         if (obj_priv->pin_count != 0) {
1956                 DRM_ERROR("Attempting to unbind pinned buffer\n");
1957                 return -EINVAL;
1958         }
1959
1960         /* blow away mappings if mapped through GTT */
1961         i915_gem_release_mmap(obj);
1962
1963         /* Move the object to the CPU domain to ensure that
1964          * any possible CPU writes while it's not in the GTT
1965          * are flushed when we go to remap it. This will
1966          * also ensure that all pending GPU writes are finished
1967          * before we unbind.
1968          */
1969         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1970         if (ret) {
1971                 if (ret != -ERESTARTSYS)
1972                         DRM_ERROR("set_domain failed: %d\n", ret);
1973                 return ret;
1974         }
1975
1976         BUG_ON(obj_priv->active);
1977
1978         /* release the fence reg _after_ flushing */
1979         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1980                 i915_gem_clear_fence_reg(obj);
1981
1982         if (obj_priv->agp_mem != NULL) {
1983                 drm_unbind_agp(obj_priv->agp_mem);
1984                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1985                 obj_priv->agp_mem = NULL;
1986         }
1987
1988         i915_gem_object_put_pages(obj);
1989         BUG_ON(obj_priv->pages_refcount);
1990
1991         if (obj_priv->gtt_space) {
1992                 atomic_dec(&dev->gtt_count);
1993                 atomic_sub(obj->size, &dev->gtt_memory);
1994
1995                 drm_mm_put_block(obj_priv->gtt_space);
1996                 obj_priv->gtt_space = NULL;
1997         }
1998
1999         /* Remove ourselves from the LRU list if present. */
2000         spin_lock(&dev_priv->mm.active_list_lock);
2001         if (!list_empty(&obj_priv->list))
2002                 list_del_init(&obj_priv->list);
2003         spin_unlock(&dev_priv->mm.active_list_lock);
2004
2005         if (i915_gem_object_is_purgeable(obj_priv))
2006                 i915_gem_object_truncate(obj);
2007
2008         trace_i915_gem_object_unbind(obj);
2009
2010         return 0;
2011 }
2012
2013 static struct drm_gem_object *
2014 i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2015 {
2016         drm_i915_private_t *dev_priv = dev->dev_private;
2017         struct drm_i915_gem_object *obj_priv;
2018         struct drm_gem_object *best = NULL;
2019         struct drm_gem_object *first = NULL;
2020
2021         /* Try to find the smallest clean object */
2022         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2023                 struct drm_gem_object *obj = &obj_priv->base;
2024                 if (obj->size >= min_size) {
2025                         if ((!obj_priv->dirty ||
2026                              i915_gem_object_is_purgeable(obj_priv)) &&
2027                             (!best || obj->size < best->size)) {
2028                                 best = obj;
2029                                 if (best->size == min_size)
2030                                         return best;
2031                         }
2032                         if (!first)
2033                             first = obj;
2034                 }
2035         }
2036
2037         return best ? best : first;
2038 }
2039
2040 static int
2041 i915_gpu_idle(struct drm_device *dev)
2042 {
2043         drm_i915_private_t *dev_priv = dev->dev_private;
2044         bool lists_empty;
2045         uint32_t seqno1, seqno2;
2046         int ret;
2047
2048         spin_lock(&dev_priv->mm.active_list_lock);
2049         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2050                        list_empty(&dev_priv->render_ring.active_list) &&
2051                        (!HAS_BSD(dev) ||
2052                         list_empty(&dev_priv->bsd_ring.active_list)));
2053         spin_unlock(&dev_priv->mm.active_list_lock);
2054
2055         if (lists_empty)
2056                 return 0;
2057
2058         /* Flush everything onto the inactive list. */
2059         i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2060         seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2061                         &dev_priv->render_ring);
2062         if (seqno1 == 0)
2063                 return -ENOMEM;
2064         ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2065
2066         if (HAS_BSD(dev)) {
2067                 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2068                                 &dev_priv->bsd_ring);
2069                 if (seqno2 == 0)
2070                         return -ENOMEM;
2071
2072                 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2073                 if (ret)
2074                         return ret;
2075         }
2076
2077
2078         return ret;
2079 }
2080
2081 static int
2082 i915_gem_evict_everything(struct drm_device *dev)
2083 {
2084         drm_i915_private_t *dev_priv = dev->dev_private;
2085         int ret;
2086         bool lists_empty;
2087
2088         spin_lock(&dev_priv->mm.active_list_lock);
2089         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2090                        list_empty(&dev_priv->mm.flushing_list) &&
2091                        list_empty(&dev_priv->render_ring.active_list) &&
2092                        (!HAS_BSD(dev)
2093                         || list_empty(&dev_priv->bsd_ring.active_list)));
2094         spin_unlock(&dev_priv->mm.active_list_lock);
2095
2096         if (lists_empty)
2097                 return -ENOSPC;
2098
2099         /* Flush everything (on to the inactive lists) and evict */
2100         ret = i915_gpu_idle(dev);
2101         if (ret)
2102                 return ret;
2103
2104         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2105
2106         ret = i915_gem_evict_from_inactive_list(dev);
2107         if (ret)
2108                 return ret;
2109
2110         spin_lock(&dev_priv->mm.active_list_lock);
2111         lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2112                        list_empty(&dev_priv->mm.flushing_list) &&
2113                        list_empty(&dev_priv->render_ring.active_list) &&
2114                        (!HAS_BSD(dev)
2115                         || list_empty(&dev_priv->bsd_ring.active_list)));
2116         spin_unlock(&dev_priv->mm.active_list_lock);
2117         BUG_ON(!lists_empty);
2118
2119         return 0;
2120 }
2121
2122 static int
2123 i915_gem_evict_something(struct drm_device *dev, int min_size)
2124 {
2125         drm_i915_private_t *dev_priv = dev->dev_private;
2126         struct drm_gem_object *obj;
2127         int ret;
2128
2129         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
2130         struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
2131         for (;;) {
2132                 i915_gem_retire_requests(dev);
2133
2134                 /* If there's an inactive buffer available now, grab it
2135                  * and be done.
2136                  */
2137                 obj = i915_gem_find_inactive_object(dev, min_size);
2138                 if (obj) {
2139                         struct drm_i915_gem_object *obj_priv;
2140
2141 #if WATCH_LRU
2142                         DRM_INFO("%s: evicting %p\n", __func__, obj);
2143 #endif
2144                         obj_priv = to_intel_bo(obj);
2145                         BUG_ON(obj_priv->pin_count != 0);
2146                         BUG_ON(obj_priv->active);
2147
2148                         /* Wait on the rendering and unbind the buffer. */
2149                         return i915_gem_object_unbind(obj);
2150                 }
2151
2152                 /* If we didn't get anything, but the ring is still processing
2153                  * things, wait for the next to finish and hopefully leave us
2154                  * a buffer to evict.
2155                  */
2156                 if (!list_empty(&render_ring->request_list)) {
2157                         struct drm_i915_gem_request *request;
2158
2159                         request = list_first_entry(&render_ring->request_list,
2160                                                    struct drm_i915_gem_request,
2161                                                    list);
2162
2163                         ret = i915_wait_request(dev,
2164                                         request->seqno, request->ring);
2165                         if (ret)
2166                                 return ret;
2167
2168                         continue;
2169                 }
2170
2171                 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2172                         struct drm_i915_gem_request *request;
2173
2174                         request = list_first_entry(&bsd_ring->request_list,
2175                                                    struct drm_i915_gem_request,
2176                                                    list);
2177
2178                         ret = i915_wait_request(dev,
2179                                         request->seqno, request->ring);
2180                         if (ret)
2181                                 return ret;
2182
2183                         continue;
2184                 }
2185
2186                 /* If we didn't have anything on the request list but there
2187                  * are buffers awaiting a flush, emit one and try again.
2188                  * When we wait on it, those buffers waiting for that flush
2189                  * will get moved to inactive.
2190                  */
2191                 if (!list_empty(&dev_priv->mm.flushing_list)) {
2192                         struct drm_i915_gem_object *obj_priv;
2193
2194                         /* Find an object that we can immediately reuse */
2195                         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2196                                 obj = &obj_priv->base;
2197                                 if (obj->size >= min_size)
2198                                         break;
2199
2200                                 obj = NULL;
2201                         }
2202
2203                         if (obj != NULL) {
2204                                 uint32_t seqno;
2205
2206                                 i915_gem_flush_ring(dev,
2207                                                obj->write_domain,
2208                                                obj->write_domain,
2209                                                obj_priv->ring);
2210                                 seqno = i915_add_request(dev, NULL,
2211                                                 obj->write_domain,
2212                                                 obj_priv->ring);
2213                                 if (seqno == 0)
2214                                         return -ENOMEM;
2215                                 continue;
2216                         }
2217                 }
2218
2219                 /* If we didn't do any of the above, there's no single buffer
2220                  * large enough to swap out for the new one, so just evict
2221                  * everything and start again. (This should be rare.)
2222                  */
2223                 if (!list_empty (&dev_priv->mm.inactive_list))
2224                         return i915_gem_evict_from_inactive_list(dev);
2225                 else
2226                         return i915_gem_evict_everything(dev);
2227         }
2228 }
2229
2230 int
2231 i915_gem_object_get_pages(struct drm_gem_object *obj,
2232                           gfp_t gfpmask)
2233 {
2234         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2235         int page_count, i;
2236         struct address_space *mapping;
2237         struct inode *inode;
2238         struct page *page;
2239
2240         BUG_ON(obj_priv->pages_refcount
2241                         == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2242
2243         if (obj_priv->pages_refcount++ != 0)
2244                 return 0;
2245
2246         /* Get the list of pages out of our struct file.  They'll be pinned
2247          * at this point until we release them.
2248          */
2249         page_count = obj->size / PAGE_SIZE;
2250         BUG_ON(obj_priv->pages != NULL);
2251         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2252         if (obj_priv->pages == NULL) {
2253                 obj_priv->pages_refcount--;
2254                 return -ENOMEM;
2255         }
2256
2257         inode = obj->filp->f_path.dentry->d_inode;
2258         mapping = inode->i_mapping;
2259         for (i = 0; i < page_count; i++) {
2260                 page = read_cache_page_gfp(mapping, i,
2261                                            GFP_HIGHUSER |
2262                                            __GFP_COLD |
2263                                            __GFP_RECLAIMABLE |
2264                                            gfpmask);
2265                 if (IS_ERR(page))
2266                         goto err_pages;
2267
2268                 obj_priv->pages[i] = page;
2269         }
2270
2271         if (obj_priv->tiling_mode != I915_TILING_NONE)
2272                 i915_gem_object_do_bit_17_swizzle(obj);
2273
2274         return 0;
2275
2276 err_pages:
2277         while (i--)
2278                 page_cache_release(obj_priv->pages[i]);
2279
2280         drm_free_large(obj_priv->pages);
2281         obj_priv->pages = NULL;
2282         obj_priv->pages_refcount--;
2283         return PTR_ERR(page);
2284 }
2285
2286 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2287 {
2288         struct drm_gem_object *obj = reg->obj;
2289         struct drm_device *dev = obj->dev;
2290         drm_i915_private_t *dev_priv = dev->dev_private;
2291         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2292         int regnum = obj_priv->fence_reg;
2293         uint64_t val;
2294
2295         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2296                     0xfffff000) << 32;
2297         val |= obj_priv->gtt_offset & 0xfffff000;
2298         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2299                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2300
2301         if (obj_priv->tiling_mode == I915_TILING_Y)
2302                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2303         val |= I965_FENCE_REG_VALID;
2304
2305         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2306 }
2307
2308 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2309 {
2310         struct drm_gem_object *obj = reg->obj;
2311         struct drm_device *dev = obj->dev;
2312         drm_i915_private_t *dev_priv = dev->dev_private;
2313         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2314         int regnum = obj_priv->fence_reg;
2315         uint64_t val;
2316
2317         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2318                     0xfffff000) << 32;
2319         val |= obj_priv->gtt_offset & 0xfffff000;
2320         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2321         if (obj_priv->tiling_mode == I915_TILING_Y)
2322                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2323         val |= I965_FENCE_REG_VALID;
2324
2325         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2326 }
2327
2328 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2329 {
2330         struct drm_gem_object *obj = reg->obj;
2331         struct drm_device *dev = obj->dev;
2332         drm_i915_private_t *dev_priv = dev->dev_private;
2333         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2334         int regnum = obj_priv->fence_reg;
2335         int tile_width;
2336         uint32_t fence_reg, val;
2337         uint32_t pitch_val;
2338
2339         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2340             (obj_priv->gtt_offset & (obj->size - 1))) {
2341                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2342                      __func__, obj_priv->gtt_offset, obj->size);
2343                 return;
2344         }
2345
2346         if (obj_priv->tiling_mode == I915_TILING_Y &&
2347             HAS_128_BYTE_Y_TILING(dev))
2348                 tile_width = 128;
2349         else
2350                 tile_width = 512;
2351
2352         /* Note: pitch better be a power of two tile widths */
2353         pitch_val = obj_priv->stride / tile_width;
2354         pitch_val = ffs(pitch_val) - 1;
2355
2356         if (obj_priv->tiling_mode == I915_TILING_Y &&
2357             HAS_128_BYTE_Y_TILING(dev))
2358                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2359         else
2360                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2361
2362         val = obj_priv->gtt_offset;
2363         if (obj_priv->tiling_mode == I915_TILING_Y)
2364                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2365         val |= I915_FENCE_SIZE_BITS(obj->size);
2366         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2367         val |= I830_FENCE_REG_VALID;
2368
2369         if (regnum < 8)
2370                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2371         else
2372                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2373         I915_WRITE(fence_reg, val);
2374 }
2375
2376 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2377 {
2378         struct drm_gem_object *obj = reg->obj;
2379         struct drm_device *dev = obj->dev;
2380         drm_i915_private_t *dev_priv = dev->dev_private;
2381         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2382         int regnum = obj_priv->fence_reg;
2383         uint32_t val;
2384         uint32_t pitch_val;
2385         uint32_t fence_size_bits;
2386
2387         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2388             (obj_priv->gtt_offset & (obj->size - 1))) {
2389                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2390                      __func__, obj_priv->gtt_offset);
2391                 return;
2392         }
2393
2394         pitch_val = obj_priv->stride / 128;
2395         pitch_val = ffs(pitch_val) - 1;
2396         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2397
2398         val = obj_priv->gtt_offset;
2399         if (obj_priv->tiling_mode == I915_TILING_Y)
2400                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2401         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2402         WARN_ON(fence_size_bits & ~0x00000f00);
2403         val |= fence_size_bits;
2404         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2405         val |= I830_FENCE_REG_VALID;
2406
2407         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2408 }
2409
2410 static int i915_find_fence_reg(struct drm_device *dev)
2411 {
2412         struct drm_i915_fence_reg *reg = NULL;
2413         struct drm_i915_gem_object *obj_priv = NULL;
2414         struct drm_i915_private *dev_priv = dev->dev_private;
2415         struct drm_gem_object *obj = NULL;
2416         int i, avail, ret;
2417
2418         /* First try to find a free reg */
2419         avail = 0;
2420         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2421                 reg = &dev_priv->fence_regs[i];
2422                 if (!reg->obj)
2423                         return i;
2424
2425                 obj_priv = to_intel_bo(reg->obj);
2426                 if (!obj_priv->pin_count)
2427                     avail++;
2428         }
2429
2430         if (avail == 0)
2431                 return -ENOSPC;
2432
2433         /* None available, try to steal one or wait for a user to finish */
2434         i = I915_FENCE_REG_NONE;
2435         list_for_each_entry(reg, &dev_priv->mm.fence_list,
2436                             lru_list) {
2437                 obj = reg->obj;
2438                 obj_priv = to_intel_bo(obj);
2439
2440                 if (obj_priv->pin_count)
2441                         continue;
2442
2443                 /* found one! */
2444                 i = obj_priv->fence_reg;
2445                 break;
2446         }
2447
2448         BUG_ON(i == I915_FENCE_REG_NONE);
2449
2450         /* We only have a reference on obj from the active list. put_fence_reg
2451          * might drop that one, causing a use-after-free in it. So hold a
2452          * private reference to obj like the other callers of put_fence_reg
2453          * (set_tiling ioctl) do. */
2454         drm_gem_object_reference(obj);
2455         ret = i915_gem_object_put_fence_reg(obj);
2456         drm_gem_object_unreference(obj);
2457         if (ret != 0)
2458                 return ret;
2459
2460         return i;
2461 }
2462
2463 /**
2464  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2465  * @obj: object to map through a fence reg
2466  *
2467  * When mapping objects through the GTT, userspace wants to be able to write
2468  * to them without having to worry about swizzling if the object is tiled.
2469  *
2470  * This function walks the fence regs looking for a free one for @obj,
2471  * stealing one if it can't find any.
2472  *
2473  * It then sets up the reg based on the object's properties: address, pitch
2474  * and tiling format.
2475  */
2476 int
2477 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2478 {
2479         struct drm_device *dev = obj->dev;
2480         struct drm_i915_private *dev_priv = dev->dev_private;
2481         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2482         struct drm_i915_fence_reg *reg = NULL;
2483         int ret;
2484
2485         /* Just update our place in the LRU if our fence is getting used. */
2486         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2487                 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2488                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2489                 return 0;
2490         }
2491
2492         switch (obj_priv->tiling_mode) {
2493         case I915_TILING_NONE:
2494                 WARN(1, "allocating a fence for non-tiled object?\n");
2495                 break;
2496         case I915_TILING_X:
2497                 if (!obj_priv->stride)
2498                         return -EINVAL;
2499                 WARN((obj_priv->stride & (512 - 1)),
2500                      "object 0x%08x is X tiled but has non-512B pitch\n",
2501                      obj_priv->gtt_offset);
2502                 break;
2503         case I915_TILING_Y:
2504                 if (!obj_priv->stride)
2505                         return -EINVAL;
2506                 WARN((obj_priv->stride & (128 - 1)),
2507                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2508                      obj_priv->gtt_offset);
2509                 break;
2510         }
2511
2512         ret = i915_find_fence_reg(dev);
2513         if (ret < 0)
2514                 return ret;
2515
2516         obj_priv->fence_reg = ret;
2517         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2518         list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2519
2520         reg->obj = obj;
2521
2522         if (IS_GEN6(dev))
2523                 sandybridge_write_fence_reg(reg);
2524         else if (IS_I965G(dev))
2525                 i965_write_fence_reg(reg);
2526         else if (IS_I9XX(dev))
2527                 i915_write_fence_reg(reg);
2528         else
2529                 i830_write_fence_reg(reg);
2530
2531         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2532                         obj_priv->tiling_mode);
2533
2534         return 0;
2535 }
2536
2537 /**
2538  * i915_gem_clear_fence_reg - clear out fence register info
2539  * @obj: object to clear
2540  *
2541  * Zeroes out the fence register itself and clears out the associated
2542  * data structures in dev_priv and obj_priv.
2543  */
2544 static void
2545 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2546 {
2547         struct drm_device *dev = obj->dev;
2548         drm_i915_private_t *dev_priv = dev->dev_private;
2549         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2550         struct drm_i915_fence_reg *reg =
2551                 &dev_priv->fence_regs[obj_priv->fence_reg];
2552
2553         if (IS_GEN6(dev)) {
2554                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2555                              (obj_priv->fence_reg * 8), 0);
2556         } else if (IS_I965G(dev)) {
2557                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2558         } else {
2559                 uint32_t fence_reg;
2560
2561                 if (obj_priv->fence_reg < 8)
2562                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2563                 else
2564                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2565                                                        8) * 4;
2566
2567                 I915_WRITE(fence_reg, 0);
2568         }
2569
2570         reg->obj = NULL;
2571         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2572         list_del_init(&reg->lru_list);
2573 }
2574
2575 /**
2576  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2577  * to the buffer to finish, and then resets the fence register.
2578  * @obj: tiled object holding a fence register.
2579  *
2580  * Zeroes out the fence register itself and clears out the associated
2581  * data structures in dev_priv and obj_priv.
2582  */
2583 int
2584 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2585 {
2586         struct drm_device *dev = obj->dev;
2587         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2588
2589         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2590                 return 0;
2591
2592         /* If we've changed tiling, GTT-mappings of the object
2593          * need to re-fault to ensure that the correct fence register
2594          * setup is in place.
2595          */
2596         i915_gem_release_mmap(obj);
2597
2598         /* On the i915, GPU access to tiled buffers is via a fence,
2599          * therefore we must wait for any outstanding access to complete
2600          * before clearing the fence.
2601          */
2602         if (!IS_I965G(dev)) {
2603                 int ret;
2604
2605                 ret = i915_gem_object_flush_gpu_write_domain(obj);
2606                 if (ret != 0)
2607                         return ret;
2608
2609                 ret = i915_gem_object_wait_rendering(obj);
2610                 if (ret != 0)
2611                         return ret;
2612         }
2613
2614         i915_gem_object_flush_gtt_write_domain(obj);
2615         i915_gem_clear_fence_reg (obj);
2616
2617         return 0;
2618 }
2619
2620 /**
2621  * Finds free space in the GTT aperture and binds the object there.
2622  */
2623 static int
2624 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2625 {
2626         struct drm_device *dev = obj->dev;
2627         drm_i915_private_t *dev_priv = dev->dev_private;
2628         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2629         struct drm_mm_node *free_space;
2630         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2631         int ret;
2632
2633         if (obj_priv->madv != I915_MADV_WILLNEED) {
2634                 DRM_ERROR("Attempting to bind a purgeable object\n");
2635                 return -EINVAL;
2636         }
2637
2638         if (alignment == 0)
2639                 alignment = i915_gem_get_gtt_alignment(obj);
2640         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2641                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2642                 return -EINVAL;
2643         }
2644
2645         /* If the object is bigger than the entire aperture, reject it early
2646          * before evicting everything in a vain attempt to find space.
2647          */
2648         if (obj->size > dev->gtt_total) {
2649                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2650                 return -E2BIG;
2651         }
2652
2653  search_free:
2654         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2655                                         obj->size, alignment, 0);
2656         if (free_space != NULL) {
2657                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2658                                                        alignment);
2659                 if (obj_priv->gtt_space != NULL)
2660                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2661         }
2662         if (obj_priv->gtt_space == NULL) {
2663                 /* If the gtt is empty and we're still having trouble
2664                  * fitting our object in, we're out of memory.
2665                  */
2666 #if WATCH_LRU
2667                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2668 #endif
2669                 ret = i915_gem_evict_something(dev, obj->size);
2670                 if (ret)
2671                         return ret;
2672
2673                 goto search_free;
2674         }
2675
2676 #if WATCH_BUF
2677         DRM_INFO("Binding object of size %zd at 0x%08x\n",
2678                  obj->size, obj_priv->gtt_offset);
2679 #endif
2680         ret = i915_gem_object_get_pages(obj, gfpmask);
2681         if (ret) {
2682                 drm_mm_put_block(obj_priv->gtt_space);
2683                 obj_priv->gtt_space = NULL;
2684
2685                 if (ret == -ENOMEM) {
2686                         /* first try to clear up some space from the GTT */
2687                         ret = i915_gem_evict_something(dev, obj->size);
2688                         if (ret) {
2689                                 /* now try to shrink everyone else */
2690                                 if (gfpmask) {
2691                                         gfpmask = 0;
2692                                         goto search_free;
2693                                 }
2694
2695                                 return ret;
2696                         }
2697
2698                         goto search_free;
2699                 }
2700
2701                 return ret;
2702         }
2703
2704         /* Create an AGP memory structure pointing at our pages, and bind it
2705          * into the GTT.
2706          */
2707         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2708                                                obj_priv->pages,
2709                                                obj->size >> PAGE_SHIFT,
2710                                                obj_priv->gtt_offset,
2711                                                obj_priv->agp_type);
2712         if (obj_priv->agp_mem == NULL) {
2713                 i915_gem_object_put_pages(obj);
2714                 drm_mm_put_block(obj_priv->gtt_space);
2715                 obj_priv->gtt_space = NULL;
2716
2717                 ret = i915_gem_evict_something(dev, obj->size);
2718                 if (ret)
2719                         return ret;
2720
2721                 goto search_free;
2722         }
2723         atomic_inc(&dev->gtt_count);
2724         atomic_add(obj->size, &dev->gtt_memory);
2725
2726         /* Assert that the object is not currently in any GPU domain. As it
2727          * wasn't in the GTT, there shouldn't be any way it could have been in
2728          * a GPU cache
2729          */
2730         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2731         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2732
2733         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2734
2735         return 0;
2736 }
2737
2738 void
2739 i915_gem_clflush_object(struct drm_gem_object *obj)
2740 {
2741         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2742
2743         /* If we don't have a page list set up, then we're not pinned
2744          * to GPU, and we can ignore the cache flush because it'll happen
2745          * again at bind time.
2746          */
2747         if (obj_priv->pages == NULL)
2748                 return;
2749
2750         trace_i915_gem_object_clflush(obj);
2751
2752         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2753 }
2754
2755 /** Flushes any GPU write domain for the object if it's dirty. */
2756 static int
2757 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2758 {
2759         struct drm_device *dev = obj->dev;
2760         uint32_t old_write_domain;
2761         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2762
2763         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2764                 return 0;
2765
2766         /* Queue the GPU write cache flushing we need. */
2767         old_write_domain = obj->write_domain;
2768         i915_gem_flush(dev, 0, obj->write_domain);
2769         if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2770                 return -ENOMEM;
2771
2772         trace_i915_gem_object_change_domain(obj,
2773                                             obj->read_domains,
2774                                             old_write_domain);
2775         return 0;
2776 }
2777
2778 /** Flushes the GTT write domain for the object if it's dirty. */
2779 static void
2780 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2781 {
2782         uint32_t old_write_domain;
2783
2784         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2785                 return;
2786
2787         /* No actual flushing is required for the GTT write domain.   Writes
2788          * to it immediately go to main memory as far as we know, so there's
2789          * no chipset flush.  It also doesn't land in render cache.
2790          */
2791         old_write_domain = obj->write_domain;
2792         obj->write_domain = 0;
2793
2794         trace_i915_gem_object_change_domain(obj,
2795                                             obj->read_domains,
2796                                             old_write_domain);
2797 }
2798
2799 /** Flushes the CPU write domain for the object if it's dirty. */
2800 static void
2801 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2802 {
2803         struct drm_device *dev = obj->dev;
2804         uint32_t old_write_domain;
2805
2806         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2807                 return;
2808
2809         i915_gem_clflush_object(obj);
2810         drm_agp_chipset_flush(dev);
2811         old_write_domain = obj->write_domain;
2812         obj->write_domain = 0;
2813
2814         trace_i915_gem_object_change_domain(obj,
2815                                             obj->read_domains,
2816                                             old_write_domain);
2817 }
2818
2819 int
2820 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2821 {
2822         int ret = 0;
2823
2824         switch (obj->write_domain) {
2825         case I915_GEM_DOMAIN_GTT:
2826                 i915_gem_object_flush_gtt_write_domain(obj);
2827                 break;
2828         case I915_GEM_DOMAIN_CPU:
2829                 i915_gem_object_flush_cpu_write_domain(obj);
2830                 break;
2831         default:
2832                 ret = i915_gem_object_flush_gpu_write_domain(obj);
2833                 break;
2834         }
2835
2836         return ret;
2837 }
2838
2839 /**
2840  * Moves a single object to the GTT read, and possibly write domain.
2841  *
2842  * This function returns when the move is complete, including waiting on
2843  * flushes to occur.
2844  */
2845 int
2846 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2847 {
2848         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2849         uint32_t old_write_domain, old_read_domains;
2850         int ret;
2851
2852         /* Not valid to be called on unbound objects. */
2853         if (obj_priv->gtt_space == NULL)
2854                 return -EINVAL;
2855
2856         ret = i915_gem_object_flush_gpu_write_domain(obj);
2857         if (ret != 0)
2858                 return ret;
2859
2860         /* Wait on any GPU rendering and flushing to occur. */
2861         ret = i915_gem_object_wait_rendering(obj);
2862         if (ret != 0)
2863                 return ret;
2864
2865         old_write_domain = obj->write_domain;
2866         old_read_domains = obj->read_domains;
2867
2868         /* If we're writing through the GTT domain, then CPU and GPU caches
2869          * will need to be invalidated at next use.
2870          */
2871         if (write)
2872                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2873
2874         i915_gem_object_flush_cpu_write_domain(obj);
2875
2876         /* It should now be out of any other write domains, and we can update
2877          * the domain values for our changes.
2878          */
2879         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2880         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2881         if (write) {
2882                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2883                 obj_priv->dirty = 1;
2884         }
2885
2886         trace_i915_gem_object_change_domain(obj,
2887                                             old_read_domains,
2888                                             old_write_domain);
2889
2890         return 0;
2891 }
2892
2893 /*
2894  * Prepare buffer for display plane. Use uninterruptible for possible flush
2895  * wait, as in modesetting process we're not supposed to be interrupted.
2896  */
2897 int
2898 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2899 {
2900         struct drm_device *dev = obj->dev;
2901         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2902         uint32_t old_write_domain, old_read_domains;
2903         int ret;
2904
2905         /* Not valid to be called on unbound objects. */
2906         if (obj_priv->gtt_space == NULL)
2907                 return -EINVAL;
2908
2909         ret = i915_gem_object_flush_gpu_write_domain(obj);
2910         if (ret)
2911                 return ret;
2912
2913         /* Wait on any GPU rendering and flushing to occur. */
2914         if (obj_priv->active) {
2915 #if WATCH_BUF
2916                 DRM_INFO("%s: object %p wait for seqno %08x\n",
2917                           __func__, obj, obj_priv->last_rendering_seqno);
2918 #endif
2919                 ret = i915_do_wait_request(dev,
2920                                 obj_priv->last_rendering_seqno,
2921                                 0,
2922                                 obj_priv->ring);
2923                 if (ret != 0)
2924                         return ret;
2925         }
2926
2927         i915_gem_object_flush_cpu_write_domain(obj);
2928
2929         old_write_domain = obj->write_domain;
2930         old_read_domains = obj->read_domains;
2931
2932         /* It should now be out of any other write domains, and we can update
2933          * the domain values for our changes.
2934          */
2935         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2936         obj->read_domains = I915_GEM_DOMAIN_GTT;
2937         obj->write_domain = I915_GEM_DOMAIN_GTT;
2938         obj_priv->dirty = 1;
2939
2940         trace_i915_gem_object_change_domain(obj,
2941                                             old_read_domains,
2942                                             old_write_domain);
2943
2944         return 0;
2945 }
2946
2947 /**
2948  * Moves a single object to the CPU read, and possibly write domain.
2949  *
2950  * This function returns when the move is complete, including waiting on
2951  * flushes to occur.
2952  */
2953 static int
2954 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2955 {
2956         uint32_t old_write_domain, old_read_domains;
2957         int ret;
2958
2959         ret = i915_gem_object_flush_gpu_write_domain(obj);
2960         if (ret)
2961                 return ret;
2962
2963         /* Wait on any GPU rendering and flushing to occur. */
2964         ret = i915_gem_object_wait_rendering(obj);
2965         if (ret != 0)
2966                 return ret;
2967
2968         i915_gem_object_flush_gtt_write_domain(obj);
2969
2970         /* If we have a partially-valid cache of the object in the CPU,
2971          * finish invalidating it and free the per-page flags.
2972          */
2973         i915_gem_object_set_to_full_cpu_read_domain(obj);
2974
2975         old_write_domain = obj->write_domain;
2976         old_read_domains = obj->read_domains;
2977
2978         /* Flush the CPU cache if it's still invalid. */
2979         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2980                 i915_gem_clflush_object(obj);
2981
2982                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2983         }
2984
2985         /* It should now be out of any other write domains, and we can update
2986          * the domain values for our changes.
2987          */
2988         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2989
2990         /* If we're writing through the CPU, then the GPU read domains will
2991          * need to be invalidated at next use.
2992          */
2993         if (write) {
2994                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2995                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2996         }
2997
2998         trace_i915_gem_object_change_domain(obj,
2999                                             old_read_domains,
3000                                             old_write_domain);
3001
3002         return 0;
3003 }
3004
3005 /*
3006  * Set the next domain for the specified object. This
3007  * may not actually perform the necessary flushing/invaliding though,
3008  * as that may want to be batched with other set_domain operations
3009  *
3010  * This is (we hope) the only really tricky part of gem. The goal
3011  * is fairly simple -- track which caches hold bits of the object
3012  * and make sure they remain coherent. A few concrete examples may
3013  * help to explain how it works. For shorthand, we use the notation
3014  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3015  * a pair of read and write domain masks.
3016  *
3017  * Case 1: the batch buffer
3018  *
3019  *      1. Allocated
3020  *      2. Written by CPU
3021  *      3. Mapped to GTT
3022  *      4. Read by GPU
3023  *      5. Unmapped from GTT
3024  *      6. Freed
3025  *
3026  *      Let's take these a step at a time
3027  *
3028  *      1. Allocated
3029  *              Pages allocated from the kernel may still have
3030  *              cache contents, so we set them to (CPU, CPU) always.
3031  *      2. Written by CPU (using pwrite)
3032  *              The pwrite function calls set_domain (CPU, CPU) and
3033  *              this function does nothing (as nothing changes)
3034  *      3. Mapped by GTT
3035  *              This function asserts that the object is not
3036  *              currently in any GPU-based read or write domains
3037  *      4. Read by GPU
3038  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
3039  *              As write_domain is zero, this function adds in the
3040  *              current read domains (CPU+COMMAND, 0).
3041  *              flush_domains is set to CPU.
3042  *              invalidate_domains is set to COMMAND
3043  *              clflush is run to get data out of the CPU caches
3044  *              then i915_dev_set_domain calls i915_gem_flush to
3045  *              emit an MI_FLUSH and drm_agp_chipset_flush
3046  *      5. Unmapped from GTT
3047  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
3048  *              flush_domains and invalidate_domains end up both zero
3049  *              so no flushing/invalidating happens
3050  *      6. Freed
3051  *              yay, done
3052  *
3053  * Case 2: The shared render buffer
3054  *
3055  *      1. Allocated
3056  *      2. Mapped to GTT
3057  *      3. Read/written by GPU
3058  *      4. set_domain to (CPU,CPU)
3059  *      5. Read/written by CPU
3060  *      6. Read/written by GPU
3061  *
3062  *      1. Allocated
3063  *              Same as last example, (CPU, CPU)
3064  *      2. Mapped to GTT
3065  *              Nothing changes (assertions find that it is not in the GPU)
3066  *      3. Read/written by GPU
3067  *              execbuffer calls set_domain (RENDER, RENDER)
3068  *              flush_domains gets CPU
3069  *              invalidate_domains gets GPU
3070  *              clflush (obj)
3071  *              MI_FLUSH and drm_agp_chipset_flush
3072  *      4. set_domain (CPU, CPU)
3073  *              flush_domains gets GPU
3074  *              invalidate_domains gets CPU
3075  *              wait_rendering (obj) to make sure all drawing is complete.
3076  *              This will include an MI_FLUSH to get the data from GPU
3077  *              to memory
3078  *              clflush (obj) to invalidate the CPU cache
3079  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3080  *      5. Read/written by CPU
3081  *              cache lines are loaded and dirtied
3082  *      6. Read written by GPU
3083  *              Same as last GPU access
3084  *
3085  * Case 3: The constant buffer
3086  *
3087  *      1. Allocated
3088  *      2. Written by CPU
3089  *      3. Read by GPU
3090  *      4. Updated (written) by CPU again
3091  *      5. Read by GPU
3092  *
3093  *      1. Allocated
3094  *              (CPU, CPU)
3095  *      2. Written by CPU
3096  *              (CPU, CPU)
3097  *      3. Read by GPU
3098  *              (CPU+RENDER, 0)
3099  *              flush_domains = CPU
3100  *              invalidate_domains = RENDER
3101  *              clflush (obj)
3102  *              MI_FLUSH
3103  *              drm_agp_chipset_flush
3104  *      4. Updated (written) by CPU again
3105  *              (CPU, CPU)
3106  *              flush_domains = 0 (no previous write domain)
3107  *              invalidate_domains = 0 (no new read domains)
3108  *      5. Read by GPU
3109  *              (CPU+RENDER, 0)
3110  *              flush_domains = CPU
3111  *              invalidate_domains = RENDER
3112  *              clflush (obj)
3113  *              MI_FLUSH
3114  *              drm_agp_chipset_flush
3115  */
3116 static void
3117 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
3118 {
3119         struct drm_device               *dev = obj->dev;
3120         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
3121         uint32_t                        invalidate_domains = 0;
3122         uint32_t                        flush_domains = 0;
3123         uint32_t                        old_read_domains;
3124
3125         BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3126         BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
3127
3128         intel_mark_busy(dev, obj);
3129
3130 #if WATCH_BUF
3131         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3132                  __func__, obj,
3133                  obj->read_domains, obj->pending_read_domains,
3134                  obj->write_domain, obj->pending_write_domain);
3135 #endif
3136         /*
3137          * If the object isn't moving to a new write domain,
3138          * let the object stay in multiple read domains
3139          */
3140         if (obj->pending_write_domain == 0)
3141                 obj->pending_read_domains |= obj->read_domains;
3142         else
3143                 obj_priv->dirty = 1;
3144
3145         /*
3146          * Flush the current write domain if
3147          * the new read domains don't match. Invalidate
3148          * any read domains which differ from the old
3149          * write domain
3150          */
3151         if (obj->write_domain &&
3152             obj->write_domain != obj->pending_read_domains) {
3153                 flush_domains |= obj->write_domain;
3154                 invalidate_domains |=
3155                         obj->pending_read_domains & ~obj->write_domain;
3156         }
3157         /*
3158          * Invalidate any read caches which may have
3159          * stale data. That is, any new read domains.
3160          */
3161         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3162         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3163 #if WATCH_BUF
3164                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3165                          __func__, flush_domains, invalidate_domains);
3166 #endif
3167                 i915_gem_clflush_object(obj);
3168         }
3169
3170         old_read_domains = obj->read_domains;
3171
3172         /* The actual obj->write_domain will be updated with
3173          * pending_write_domain after we emit the accumulated flush for all
3174          * of our domain changes in execbuffers (which clears objects'
3175          * write_domains).  So if we have a current write domain that we
3176          * aren't changing, set pending_write_domain to that.
3177          */
3178         if (flush_domains == 0 && obj->pending_write_domain == 0)
3179                 obj->pending_write_domain = obj->write_domain;
3180         obj->read_domains = obj->pending_read_domains;
3181
3182         dev->invalidate_domains |= invalidate_domains;
3183         dev->flush_domains |= flush_domains;
3184 #if WATCH_BUF
3185         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3186                  __func__,
3187                  obj->read_domains, obj->write_domain,
3188                  dev->invalidate_domains, dev->flush_domains);
3189 #endif
3190
3191         trace_i915_gem_object_change_domain(obj,
3192                                             old_read_domains,
3193                                             obj->write_domain);
3194 }
3195
3196 /**
3197  * Moves the object from a partially CPU read to a full one.
3198  *
3199  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3200  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3201  */
3202 static void
3203 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3204 {
3205         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3206
3207         if (!obj_priv->page_cpu_valid)
3208                 return;
3209
3210         /* If we're partially in the CPU read domain, finish moving it in.
3211          */
3212         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3213                 int i;
3214
3215                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3216                         if (obj_priv->page_cpu_valid[i])
3217                                 continue;
3218                         drm_clflush_pages(obj_priv->pages + i, 1);
3219                 }
3220         }
3221
3222         /* Free the page_cpu_valid mappings which are now stale, whether
3223          * or not we've got I915_GEM_DOMAIN_CPU.
3224          */
3225         kfree(obj_priv->page_cpu_valid);
3226         obj_priv->page_cpu_valid = NULL;
3227 }
3228
3229 /**
3230  * Set the CPU read domain on a range of the object.
3231  *
3232  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3233  * not entirely valid.  The page_cpu_valid member of the object flags which
3234  * pages have been flushed, and will be respected by
3235  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3236  * of the whole object.
3237  *
3238  * This function returns when the move is complete, including waiting on
3239  * flushes to occur.
3240  */
3241 static int
3242 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3243                                           uint64_t offset, uint64_t size)
3244 {
3245         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3246         uint32_t old_read_domains;
3247         int i, ret;
3248
3249         if (offset == 0 && size == obj->size)
3250                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3251
3252         ret = i915_gem_object_flush_gpu_write_domain(obj);
3253         if (ret)
3254                 return ret;
3255
3256         /* Wait on any GPU rendering and flushing to occur. */
3257         ret = i915_gem_object_wait_rendering(obj);
3258         if (ret != 0)
3259                 return ret;
3260         i915_gem_object_flush_gtt_write_domain(obj);
3261
3262         /* If we're already fully in the CPU read domain, we're done. */
3263         if (obj_priv->page_cpu_valid == NULL &&
3264             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3265                 return 0;
3266
3267         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3268          * newly adding I915_GEM_DOMAIN_CPU
3269          */
3270         if (obj_priv->page_cpu_valid == NULL) {
3271                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3272                                                    GFP_KERNEL);
3273                 if (obj_priv->page_cpu_valid == NULL)
3274                         return -ENOMEM;
3275         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3276                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3277
3278         /* Flush the cache on any pages that are still invalid from the CPU's
3279          * perspective.
3280          */
3281         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3282              i++) {
3283                 if (obj_priv->page_cpu_valid[i])
3284                         continue;
3285
3286                 drm_clflush_pages(obj_priv->pages + i, 1);
3287
3288                 obj_priv->page_cpu_valid[i] = 1;
3289         }
3290
3291         /* It should now be out of any other write domains, and we can update
3292          * the domain values for our changes.
3293          */
3294         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3295
3296         old_read_domains = obj->read_domains;
3297         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3298
3299         trace_i915_gem_object_change_domain(obj,
3300                                             old_read_domains,
3301                                             obj->write_domain);
3302
3303         return 0;
3304 }
3305
3306 /**
3307  * Pin an object to the GTT and evaluate the relocations landing in it.
3308  */
3309 static int
3310 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3311                                  struct drm_file *file_priv,
3312                                  struct drm_i915_gem_exec_object2 *entry,
3313                                  struct drm_i915_gem_relocation_entry *relocs)
3314 {
3315         struct drm_device *dev = obj->dev;
3316         drm_i915_private_t *dev_priv = dev->dev_private;
3317         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3318         int i, ret;
3319         void __iomem *reloc_page;
3320         bool need_fence;
3321
3322         need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3323                      obj_priv->tiling_mode != I915_TILING_NONE;
3324
3325         /* Check fence reg constraints and rebind if necessary */
3326         if (need_fence &&
3327             !i915_gem_object_fence_offset_ok(obj,
3328                                              obj_priv->tiling_mode)) {
3329                 ret = i915_gem_object_unbind(obj);
3330                 if (ret)
3331                         return ret;
3332         }
3333
3334         /* Choose the GTT offset for our buffer and put it there. */
3335         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3336         if (ret)
3337                 return ret;
3338
3339         /*
3340          * Pre-965 chips need a fence register set up in order to
3341          * properly handle blits to/from tiled surfaces.
3342          */
3343         if (need_fence) {
3344                 ret = i915_gem_object_get_fence_reg(obj);
3345                 if (ret != 0) {
3346                         i915_gem_object_unpin(obj);
3347                         return ret;
3348                 }
3349         }
3350
3351         entry->offset = obj_priv->gtt_offset;
3352
3353         /* Apply the relocations, using the GTT aperture to avoid cache
3354          * flushing requirements.
3355          */
3356         for (i = 0; i < entry->relocation_count; i++) {
3357                 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3358                 struct drm_gem_object *target_obj;
3359                 struct drm_i915_gem_object *target_obj_priv;
3360                 uint32_t reloc_val, reloc_offset;
3361                 uint32_t __iomem *reloc_entry;
3362
3363                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3364                                                    reloc->target_handle);
3365                 if (target_obj == NULL) {
3366                         i915_gem_object_unpin(obj);
3367                         return -EBADF;
3368                 }
3369                 target_obj_priv = to_intel_bo(target_obj);
3370
3371 #if WATCH_RELOC
3372                 DRM_INFO("%s: obj %p offset %08x target %d "
3373                          "read %08x write %08x gtt %08x "
3374                          "presumed %08x delta %08x\n",
3375                          __func__,
3376                          obj,
3377                          (int) reloc->offset,
3378                          (int) reloc->target_handle,
3379                          (int) reloc->read_domains,
3380                          (int) reloc->write_domain,
3381                          (int) target_obj_priv->gtt_offset,
3382                          (int) reloc->presumed_offset,
3383                          reloc->delta);
3384 #endif
3385
3386                 /* The target buffer should have appeared before us in the
3387                  * exec_object list, so it should have a GTT space bound by now.
3388                  */
3389                 if (target_obj_priv->gtt_space == NULL) {
3390                         DRM_ERROR("No GTT space found for object %d\n",
3391                                   reloc->target_handle);
3392                         drm_gem_object_unreference(target_obj);
3393                         i915_gem_object_unpin(obj);
3394                         return -EINVAL;
3395                 }
3396
3397                 /* Validate that the target is in a valid r/w GPU domain */
3398                 if (reloc->write_domain & (reloc->write_domain - 1)) {
3399                         DRM_ERROR("reloc with multiple write domains: "
3400                                   "obj %p target %d offset %d "
3401                                   "read %08x write %08x",
3402                                   obj, reloc->target_handle,
3403                                   (int) reloc->offset,
3404                                   reloc->read_domains,
3405                                   reloc->write_domain);
3406                         return -EINVAL;
3407                 }
3408                 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3409                     reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3410                         DRM_ERROR("reloc with read/write CPU domains: "
3411                                   "obj %p target %d offset %d "
3412                                   "read %08x write %08x",
3413                                   obj, reloc->target_handle,
3414                                   (int) reloc->offset,
3415                                   reloc->read_domains,
3416                                   reloc->write_domain);
3417                         drm_gem_object_unreference(target_obj);
3418                         i915_gem_object_unpin(obj);
3419                         return -EINVAL;
3420                 }
3421                 if (reloc->write_domain && target_obj->pending_write_domain &&
3422                     reloc->write_domain != target_obj->pending_write_domain) {
3423                         DRM_ERROR("Write domain conflict: "
3424                                   "obj %p target %d offset %d "
3425                                   "new %08x old %08x\n",
3426                                   obj, reloc->target_handle,
3427                                   (int) reloc->offset,
3428                                   reloc->write_domain,
3429                                   target_obj->pending_write_domain);
3430                         drm_gem_object_unreference(target_obj);
3431                         i915_gem_object_unpin(obj);
3432                         return -EINVAL;
3433                 }
3434
3435                 target_obj->pending_read_domains |= reloc->read_domains;
3436                 target_obj->pending_write_domain |= reloc->write_domain;
3437
3438                 /* If the relocation already has the right value in it, no
3439                  * more work needs to be done.
3440                  */
3441                 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3442                         drm_gem_object_unreference(target_obj);
3443                         continue;
3444                 }
3445
3446                 /* Check that the relocation address is valid... */
3447                 if (reloc->offset > obj->size - 4) {
3448                         DRM_ERROR("Relocation beyond object bounds: "
3449                                   "obj %p target %d offset %d size %d.\n",
3450                                   obj, reloc->target_handle,
3451                                   (int) reloc->offset, (int) obj->size);
3452                         drm_gem_object_unreference(target_obj);
3453                         i915_gem_object_unpin(obj);
3454                         return -EINVAL;
3455                 }
3456                 if (reloc->offset & 3) {
3457                         DRM_ERROR("Relocation not 4-byte aligned: "
3458                                   "obj %p target %d offset %d.\n",
3459                                   obj, reloc->target_handle,
3460                                   (int) reloc->offset);
3461                         drm_gem_object_unreference(target_obj);
3462                         i915_gem_object_unpin(obj);
3463                         return -EINVAL;
3464                 }
3465
3466                 /* and points to somewhere within the target object. */
3467                 if (reloc->delta >= target_obj->size) {
3468                         DRM_ERROR("Relocation beyond target object bounds: "
3469                                   "obj %p target %d delta %d size %d.\n",
3470                                   obj, reloc->target_handle,
3471                                   (int) reloc->delta, (int) target_obj->size);
3472                         drm_gem_object_unreference(target_obj);
3473                         i915_gem_object_unpin(obj);
3474                         return -EINVAL;
3475                 }
3476
3477                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3478                 if (ret != 0) {
3479                         drm_gem_object_unreference(target_obj);
3480                         i915_gem_object_unpin(obj);
3481                         return -EINVAL;
3482                 }
3483
3484                 /* Map the page containing the relocation we're going to
3485                  * perform.
3486                  */
3487                 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3488                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3489                                                       (reloc_offset &
3490                                                        ~(PAGE_SIZE - 1)));
3491                 reloc_entry = (uint32_t __iomem *)(reloc_page +
3492                                                    (reloc_offset & (PAGE_SIZE - 1)));
3493                 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3494
3495 #if WATCH_BUF
3496                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3497                           obj, (unsigned int) reloc->offset,
3498                           readl(reloc_entry), reloc_val);
3499 #endif
3500                 writel(reloc_val, reloc_entry);
3501                 io_mapping_unmap_atomic(reloc_page);
3502
3503                 /* The updated presumed offset for this entry will be
3504                  * copied back out to the user.
3505                  */
3506                 reloc->presumed_offset = target_obj_priv->gtt_offset;
3507
3508                 drm_gem_object_unreference(target_obj);
3509         }
3510
3511 #if WATCH_BUF
3512         if (0)
3513                 i915_gem_dump_object(obj, 128, __func__, ~0);
3514 #endif
3515         return 0;
3516 }
3517
3518 /* Throttle our rendering by waiting until the ring has completed our requests
3519  * emitted over 20 msec ago.
3520  *
3521  * Note that if we were to use the current jiffies each time around the loop,
3522  * we wouldn't escape the function with any frames outstanding if the time to
3523  * render a frame was over 20ms.
3524  *
3525  * This should get us reasonable parallelism between CPU and GPU but also
3526  * relatively low latency when blocking on a particular request to finish.
3527  */
3528 static int
3529 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3530 {
3531         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3532         int ret = 0;
3533         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3534
3535         mutex_lock(&dev->struct_mutex);
3536         while (!list_empty(&i915_file_priv->mm.request_list)) {
3537                 struct drm_i915_gem_request *request;
3538
3539                 request = list_first_entry(&i915_file_priv->mm.request_list,
3540                                            struct drm_i915_gem_request,
3541                                            client_list);
3542
3543                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3544                         break;
3545
3546                 ret = i915_wait_request(dev, request->seqno, request->ring);
3547                 if (ret != 0)
3548                         break;
3549         }
3550         mutex_unlock(&dev->struct_mutex);
3551
3552         return ret;
3553 }
3554
3555 static int
3556 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3557                               uint32_t buffer_count,
3558                               struct drm_i915_gem_relocation_entry **relocs)
3559 {
3560         uint32_t reloc_count = 0, reloc_index = 0, i;
3561         int ret;
3562
3563         *relocs = NULL;
3564         for (i = 0; i < buffer_count; i++) {
3565                 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3566                         return -EINVAL;
3567                 reloc_count += exec_list[i].relocation_count;
3568         }
3569
3570         *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3571         if (*relocs == NULL) {
3572                 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3573                 return -ENOMEM;
3574         }
3575
3576         for (i = 0; i < buffer_count; i++) {
3577                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3578
3579                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3580
3581                 ret = copy_from_user(&(*relocs)[reloc_index],
3582                                      user_relocs,
3583                                      exec_list[i].relocation_count *
3584                                      sizeof(**relocs));
3585                 if (ret != 0) {
3586                         drm_free_large(*relocs);
3587                         *relocs = NULL;
3588                         return -EFAULT;
3589                 }
3590
3591                 reloc_index += exec_list[i].relocation_count;
3592         }
3593
3594         return 0;
3595 }
3596
3597 static int
3598 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3599                             uint32_t buffer_count,
3600                             struct drm_i915_gem_relocation_entry *relocs)
3601 {
3602         uint32_t reloc_count = 0, i;
3603         int ret = 0;
3604
3605         if (relocs == NULL)
3606             return 0;
3607
3608         for (i = 0; i < buffer_count; i++) {
3609                 struct drm_i915_gem_relocation_entry __user *user_relocs;
3610                 int unwritten;
3611
3612                 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3613
3614                 unwritten = copy_to_user(user_relocs,
3615                                          &relocs[reloc_count],
3616                                          exec_list[i].relocation_count *
3617                                          sizeof(*relocs));
3618
3619                 if (unwritten) {
3620                         ret = -EFAULT;
3621                         goto err;
3622                 }
3623
3624                 reloc_count += exec_list[i].relocation_count;
3625         }
3626
3627 err:
3628         drm_free_large(relocs);
3629
3630         return ret;
3631 }
3632
3633 static int
3634 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3635                            uint64_t exec_offset)
3636 {
3637         uint32_t exec_start, exec_len;
3638
3639         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3640         exec_len = (uint32_t) exec->batch_len;
3641
3642         if ((exec_start | exec_len) & 0x7)
3643                 return -EINVAL;
3644
3645         if (!exec_start)
3646                 return -EINVAL;
3647
3648         return 0;
3649 }
3650
3651 static int
3652 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3653                                struct drm_gem_object **object_list,
3654                                int count)
3655 {
3656         drm_i915_private_t *dev_priv = dev->dev_private;
3657         struct drm_i915_gem_object *obj_priv;
3658         DEFINE_WAIT(wait);
3659         int i, ret = 0;
3660
3661         for (;;) {
3662                 prepare_to_wait(&dev_priv->pending_flip_queue,
3663                                 &wait, TASK_INTERRUPTIBLE);
3664                 for (i = 0; i < count; i++) {
3665                         obj_priv = to_intel_bo(object_list[i]);
3666                         if (atomic_read(&obj_priv->pending_flip) > 0)
3667                                 break;
3668                 }
3669                 if (i == count)
3670                         break;
3671
3672                 if (!signal_pending(current)) {
3673                         mutex_unlock(&dev->struct_mutex);
3674                         schedule();
3675                         mutex_lock(&dev->struct_mutex);
3676                         continue;
3677                 }
3678                 ret = -ERESTARTSYS;
3679                 break;
3680         }
3681         finish_wait(&dev_priv->pending_flip_queue, &wait);
3682
3683         return ret;
3684 }
3685
3686
3687 int
3688 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3689                        struct drm_file *file_priv,
3690                        struct drm_i915_gem_execbuffer2 *args,
3691                        struct drm_i915_gem_exec_object2 *exec_list)
3692 {
3693         drm_i915_private_t *dev_priv = dev->dev_private;
3694         struct drm_gem_object **object_list = NULL;
3695         struct drm_gem_object *batch_obj;
3696         struct drm_i915_gem_object *obj_priv;
3697         struct drm_clip_rect *cliprects = NULL;
3698         struct drm_i915_gem_relocation_entry *relocs = NULL;
3699         int ret = 0, ret2, i, pinned = 0;
3700         uint64_t exec_offset;
3701         uint32_t seqno, flush_domains, reloc_index;
3702         int pin_tries, flips;
3703
3704         struct intel_ring_buffer *ring = NULL;
3705
3706 #if WATCH_EXEC
3707         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3708                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3709 #endif
3710         if (args->flags & I915_EXEC_BSD) {
3711                 if (!HAS_BSD(dev)) {
3712                         DRM_ERROR("execbuf with wrong flag\n");
3713                         return -EINVAL;
3714                 }
3715                 ring = &dev_priv->bsd_ring;
3716         } else {
3717                 ring = &dev_priv->render_ring;
3718         }
3719
3720
3721         if (args->buffer_count < 1) {
3722                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3723                 return -EINVAL;
3724         }
3725         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3726         if (object_list == NULL) {
3727                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3728                           args->buffer_count);
3729                 ret = -ENOMEM;
3730                 goto pre_mutex_err;
3731         }
3732
3733         if (args->num_cliprects != 0) {
3734                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3735                                     GFP_KERNEL);
3736                 if (cliprects == NULL) {
3737                         ret = -ENOMEM;
3738                         goto pre_mutex_err;
3739                 }
3740
3741                 ret = copy_from_user(cliprects,
3742                                      (struct drm_clip_rect __user *)
3743                                      (uintptr_t) args->cliprects_ptr,
3744                                      sizeof(*cliprects) * args->num_cliprects);
3745                 if (ret != 0) {
3746                         DRM_ERROR("copy %d cliprects failed: %d\n",
3747                                   args->num_cliprects, ret);
3748                         goto pre_mutex_err;
3749                 }
3750         }
3751
3752         ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3753                                             &relocs);
3754         if (ret != 0)
3755                 goto pre_mutex_err;
3756
3757         mutex_lock(&dev->struct_mutex);
3758
3759         i915_verify_inactive(dev, __FILE__, __LINE__);
3760
3761         if (atomic_read(&dev_priv->mm.wedged)) {
3762                 mutex_unlock(&dev->struct_mutex);
3763                 ret = -EIO;
3764                 goto pre_mutex_err;
3765         }
3766
3767         if (dev_priv->mm.suspended) {
3768                 mutex_unlock(&dev->struct_mutex);
3769                 ret = -EBUSY;
3770                 goto pre_mutex_err;
3771         }
3772
3773         /* Look up object handles */
3774         flips = 0;
3775         for (i = 0; i < args->buffer_count; i++) {
3776                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3777                                                        exec_list[i].handle);
3778                 if (object_list[i] == NULL) {
3779                         DRM_ERROR("Invalid object handle %d at index %d\n",
3780                                    exec_list[i].handle, i);
3781                         /* prevent error path from reading uninitialized data */
3782                         args->buffer_count = i + 1;
3783                         ret = -EBADF;
3784                         goto err;
3785                 }
3786
3787                 obj_priv = to_intel_bo(object_list[i]);
3788                 if (obj_priv->in_execbuffer) {
3789                         DRM_ERROR("Object %p appears more than once in object list\n",
3790                                    object_list[i]);
3791                         /* prevent error path from reading uninitialized data */
3792                         args->buffer_count = i + 1;
3793                         ret = -EBADF;
3794                         goto err;
3795                 }
3796                 obj_priv->in_execbuffer = true;
3797                 flips += atomic_read(&obj_priv->pending_flip);
3798         }
3799
3800         if (flips > 0) {
3801                 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3802                                                      args->buffer_count);
3803                 if (ret)
3804                         goto err;
3805         }
3806
3807         /* Pin and relocate */
3808         for (pin_tries = 0; ; pin_tries++) {
3809                 ret = 0;
3810                 reloc_index = 0;
3811
3812                 for (i = 0; i < args->buffer_count; i++) {
3813                         object_list[i]->pending_read_domains = 0;
3814                         object_list[i]->pending_write_domain = 0;
3815                         ret = i915_gem_object_pin_and_relocate(object_list[i],
3816                                                                file_priv,
3817                                                                &exec_list[i],
3818                                                                &relocs[reloc_index]);
3819                         if (ret)
3820                                 break;
3821                         pinned = i + 1;
3822                         reloc_index += exec_list[i].relocation_count;
3823                 }
3824                 /* success */
3825                 if (ret == 0)
3826                         break;
3827
3828                 /* error other than GTT full, or we've already tried again */
3829                 if (ret != -ENOSPC || pin_tries >= 1) {
3830                         if (ret != -ERESTARTSYS) {
3831                                 unsigned long long total_size = 0;
3832                                 int num_fences = 0;
3833                                 for (i = 0; i < args->buffer_count; i++) {
3834                                         obj_priv = to_intel_bo(object_list[i]);
3835
3836                                         total_size += object_list[i]->size;
3837                                         num_fences +=
3838                                                 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3839                                                 obj_priv->tiling_mode != I915_TILING_NONE;
3840                                 }
3841                                 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3842                                           pinned+1, args->buffer_count,
3843                                           total_size, num_fences,
3844                                           ret);
3845                                 DRM_ERROR("%d objects [%d pinned], "
3846                                           "%d object bytes [%d pinned], "
3847                                           "%d/%d gtt bytes\n",
3848                                           atomic_read(&dev->object_count),
3849                                           atomic_read(&dev->pin_count),
3850                                           atomic_read(&dev->object_memory),
3851                                           atomic_read(&dev->pin_memory),
3852                                           atomic_read(&dev->gtt_memory),
3853                                           dev->gtt_total);
3854                         }
3855                         goto err;
3856                 }
3857
3858                 /* unpin all of our buffers */
3859                 for (i = 0; i < pinned; i++)
3860                         i915_gem_object_unpin(object_list[i]);
3861                 pinned = 0;
3862
3863                 /* evict everyone we can from the aperture */
3864                 ret = i915_gem_evict_everything(dev);
3865                 if (ret && ret != -ENOSPC)
3866                         goto err;
3867         }
3868
3869         /* Set the pending read domains for the batch buffer to COMMAND */
3870         batch_obj = object_list[args->buffer_count-1];
3871         if (batch_obj->pending_write_domain) {
3872                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3873                 ret = -EINVAL;
3874                 goto err;
3875         }
3876         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3877
3878         /* Sanity check the batch buffer, prior to moving objects */
3879         exec_offset = exec_list[args->buffer_count - 1].offset;
3880         ret = i915_gem_check_execbuffer (args, exec_offset);
3881         if (ret != 0) {
3882                 DRM_ERROR("execbuf with invalid offset/length\n");
3883                 goto err;
3884         }
3885
3886         i915_verify_inactive(dev, __FILE__, __LINE__);
3887
3888         /* Zero the global flush/invalidate flags. These
3889          * will be modified as new domains are computed
3890          * for each object
3891          */
3892         dev->invalidate_domains = 0;
3893         dev->flush_domains = 0;
3894
3895         for (i = 0; i < args->buffer_count; i++) {
3896                 struct drm_gem_object *obj = object_list[i];
3897
3898                 /* Compute new gpu domains and update invalidate/flush */
3899                 i915_gem_object_set_to_gpu_domain(obj);
3900         }
3901
3902         i915_verify_inactive(dev, __FILE__, __LINE__);
3903
3904         if (dev->invalidate_domains | dev->flush_domains) {
3905 #if WATCH_EXEC
3906                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3907                           __func__,
3908                          dev->invalidate_domains,
3909                          dev->flush_domains);
3910 #endif
3911                 i915_gem_flush(dev,
3912                                dev->invalidate_domains,
3913                                dev->flush_domains);
3914                 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) {
3915                         (void)i915_add_request(dev, file_priv,
3916                                         dev->flush_domains,
3917                                         &dev_priv->render_ring);
3918
3919                         if (HAS_BSD(dev))
3920                                 (void)i915_add_request(dev, file_priv,
3921                                                 dev->flush_domains,
3922                                                 &dev_priv->bsd_ring);
3923                 }
3924         }
3925
3926         for (i = 0; i < args->buffer_count; i++) {
3927                 struct drm_gem_object *obj = object_list[i];
3928                 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3929                 uint32_t old_write_domain = obj->write_domain;
3930
3931                 obj->write_domain = obj->pending_write_domain;
3932                 if (obj->write_domain)
3933                         list_move_tail(&obj_priv->gpu_write_list,
3934                                        &dev_priv->mm.gpu_write_list);
3935                 else
3936                         list_del_init(&obj_priv->gpu_write_list);
3937
3938                 trace_i915_gem_object_change_domain(obj,
3939                                                     obj->read_domains,
3940                                                     old_write_domain);
3941         }
3942
3943         i915_verify_inactive(dev, __FILE__, __LINE__);
3944
3945 #if WATCH_COHERENCY
3946         for (i = 0; i < args->buffer_count; i++) {
3947                 i915_gem_object_check_coherency(object_list[i],
3948                                                 exec_list[i].handle);
3949         }
3950 #endif
3951
3952 #if WATCH_EXEC
3953         i915_gem_dump_object(batch_obj,
3954                               args->batch_len,
3955                               __func__,
3956                               ~0);
3957 #endif
3958
3959         /* Exec the batchbuffer */
3960         ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3961                         cliprects, exec_offset);
3962         if (ret) {
3963                 DRM_ERROR("dispatch failed %d\n", ret);
3964                 goto err;
3965         }
3966
3967         /*
3968          * Ensure that the commands in the batch buffer are
3969          * finished before the interrupt fires
3970          */
3971         flush_domains = i915_retire_commands(dev, ring);
3972
3973         i915_verify_inactive(dev, __FILE__, __LINE__);
3974
3975         /*
3976          * Get a seqno representing the execution of the current buffer,
3977          * which we can wait on.  We would like to mitigate these interrupts,
3978          * likely by only creating seqnos occasionally (so that we have
3979          * *some* interrupts representing completion of buffers that we can
3980          * wait on when trying to clear up gtt space).
3981          */
3982         seqno = i915_add_request(dev, file_priv, flush_domains, ring);
3983         BUG_ON(seqno == 0);
3984         for (i = 0; i < args->buffer_count; i++) {
3985                 struct drm_gem_object *obj = object_list[i];
3986                 obj_priv = to_intel_bo(obj);
3987
3988                 i915_gem_object_move_to_active(obj, seqno, ring);
3989 #if WATCH_LRU
3990                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3991 #endif
3992         }
3993 #if WATCH_LRU
3994         i915_dump_lru(dev, __func__);
3995 #endif
3996
3997         i915_verify_inactive(dev, __FILE__, __LINE__);
3998
3999 err:
4000         for (i = 0; i < pinned; i++)
4001                 i915_gem_object_unpin(object_list[i]);
4002
4003         for (i = 0; i < args->buffer_count; i++) {
4004                 if (object_list[i]) {
4005                         obj_priv = to_intel_bo(object_list[i]);
4006                         obj_priv->in_execbuffer = false;
4007                 }
4008                 drm_gem_object_unreference(object_list[i]);
4009         }
4010
4011         mutex_unlock(&dev->struct_mutex);
4012
4013 pre_mutex_err:
4014         /* Copy the updated relocations out regardless of current error
4015          * state.  Failure to update the relocs would mean that the next
4016          * time userland calls execbuf, it would do so with presumed offset
4017          * state that didn't match the actual object state.
4018          */
4019         ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
4020                                            relocs);
4021         if (ret2 != 0) {
4022                 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
4023
4024                 if (ret == 0)
4025                         ret = ret2;
4026         }
4027
4028         drm_free_large(object_list);
4029         kfree(cliprects);
4030
4031         return ret;
4032 }
4033
4034 /*
4035  * Legacy execbuffer just creates an exec2 list from the original exec object
4036  * list array and passes it to the real function.
4037  */
4038 int
4039 i915_gem_execbuffer(struct drm_device *dev, void *data,
4040                     struct drm_file *file_priv)
4041 {
4042         struct drm_i915_gem_execbuffer *args = data;
4043         struct drm_i915_gem_execbuffer2 exec2;
4044         struct drm_i915_gem_exec_object *exec_list = NULL;
4045         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4046         int ret, i;
4047
4048 #if WATCH_EXEC
4049         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4050                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4051 #endif
4052
4053         if (args->buffer_count < 1) {
4054                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4055                 return -EINVAL;
4056         }
4057
4058         /* Copy in the exec list from userland */
4059         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4060         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4061         if (exec_list == NULL || exec2_list == NULL) {
4062                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4063                           args->buffer_count);
4064                 drm_free_large(exec_list);
4065                 drm_free_large(exec2_list);
4066                 return -ENOMEM;
4067         }
4068         ret = copy_from_user(exec_list,
4069                              (struct drm_i915_relocation_entry __user *)
4070                              (uintptr_t) args->buffers_ptr,
4071                              sizeof(*exec_list) * args->buffer_count);
4072         if (ret != 0) {
4073                 DRM_ERROR("copy %d exec entries failed %d\n",
4074                           args->buffer_count, ret);
4075                 drm_free_large(exec_list);
4076                 drm_free_large(exec2_list);
4077                 return -EFAULT;
4078         }
4079
4080         for (i = 0; i < args->buffer_count; i++) {
4081                 exec2_list[i].handle = exec_list[i].handle;
4082                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4083                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4084                 exec2_list[i].alignment = exec_list[i].alignment;
4085                 exec2_list[i].offset = exec_list[i].offset;
4086                 if (!IS_I965G(dev))
4087                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4088                 else
4089                         exec2_list[i].flags = 0;
4090         }
4091
4092         exec2.buffers_ptr = args->buffers_ptr;
4093         exec2.buffer_count = args->buffer_count;
4094         exec2.batch_start_offset = args->batch_start_offset;
4095         exec2.batch_len = args->batch_len;
4096         exec2.DR1 = args->DR1;
4097         exec2.DR4 = args->DR4;
4098         exec2.num_cliprects = args->num_cliprects;
4099         exec2.cliprects_ptr = args->cliprects_ptr;
4100         exec2.flags = I915_EXEC_RENDER;
4101
4102         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4103         if (!ret) {
4104                 /* Copy the new buffer offsets back to the user's exec list. */
4105                 for (i = 0; i < args->buffer_count; i++)
4106                         exec_list[i].offset = exec2_list[i].offset;
4107                 /* ... and back out to userspace */
4108                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4109                                    (uintptr_t) args->buffers_ptr,
4110                                    exec_list,
4111                                    sizeof(*exec_list) * args->buffer_count);
4112                 if (ret) {
4113                         ret = -EFAULT;
4114                         DRM_ERROR("failed to copy %d exec entries "
4115                                   "back to user (%d)\n",
4116                                   args->buffer_count, ret);
4117                 }
4118         }
4119
4120         drm_free_large(exec_list);
4121         drm_free_large(exec2_list);
4122         return ret;
4123 }
4124
4125 int
4126 i915_gem_execbuffer2(struct drm_device *dev, void *data,
4127                      struct drm_file *file_priv)
4128 {
4129         struct drm_i915_gem_execbuffer2 *args = data;
4130         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4131         int ret;
4132
4133 #if WATCH_EXEC
4134         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4135                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4136 #endif
4137
4138         if (args->buffer_count < 1) {
4139                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4140                 return -EINVAL;
4141         }
4142
4143         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4144         if (exec2_list == NULL) {
4145                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4146                           args->buffer_count);
4147                 return -ENOMEM;
4148         }
4149         ret = copy_from_user(exec2_list,
4150                              (struct drm_i915_relocation_entry __user *)
4151                              (uintptr_t) args->buffers_ptr,
4152                              sizeof(*exec2_list) * args->buffer_count);
4153         if (ret != 0) {
4154                 DRM_ERROR("copy %d exec entries failed %d\n",
4155                           args->buffer_count, ret);
4156                 drm_free_large(exec2_list);
4157                 return -EFAULT;
4158         }
4159
4160         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4161         if (!ret) {
4162                 /* Copy the new buffer offsets back to the user's exec list. */
4163                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4164                                    (uintptr_t) args->buffers_ptr,
4165                                    exec2_list,
4166                                    sizeof(*exec2_list) * args->buffer_count);
4167                 if (ret) {
4168                         ret = -EFAULT;
4169                         DRM_ERROR("failed to copy %d exec entries "
4170                                   "back to user (%d)\n",
4171                                   args->buffer_count, ret);
4172                 }
4173         }
4174
4175         drm_free_large(exec2_list);
4176         return ret;
4177 }
4178
4179 int
4180 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4181 {
4182         struct drm_device *dev = obj->dev;
4183         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4184         int ret;
4185
4186         BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4187
4188         i915_verify_inactive(dev, __FILE__, __LINE__);
4189
4190         if (obj_priv->gtt_space != NULL) {
4191                 if (alignment == 0)
4192                         alignment = i915_gem_get_gtt_alignment(obj);
4193                 if (obj_priv->gtt_offset & (alignment - 1)) {
4194                         ret = i915_gem_object_unbind(obj);
4195                         if (ret)
4196                                 return ret;
4197                 }
4198         }
4199
4200         if (obj_priv->gtt_space == NULL) {
4201                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4202                 if (ret)
4203                         return ret;
4204         }
4205
4206         obj_priv->pin_count++;
4207
4208         /* If the object is not active and not pending a flush,
4209          * remove it from the inactive list
4210          */
4211         if (obj_priv->pin_count == 1) {
4212                 atomic_inc(&dev->pin_count);
4213                 atomic_add(obj->size, &dev->pin_memory);
4214                 if (!obj_priv->active &&
4215                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
4216                     !list_empty(&obj_priv->list))
4217                         list_del_init(&obj_priv->list);
4218         }
4219         i915_verify_inactive(dev, __FILE__, __LINE__);
4220
4221         return 0;
4222 }
4223
4224 void
4225 i915_gem_object_unpin(struct drm_gem_object *obj)
4226 {
4227         struct drm_device *dev = obj->dev;
4228         drm_i915_private_t *dev_priv = dev->dev_private;
4229         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4230
4231         i915_verify_inactive(dev, __FILE__, __LINE__);
4232         obj_priv->pin_count--;
4233         BUG_ON(obj_priv->pin_count < 0);
4234         BUG_ON(obj_priv->gtt_space == NULL);
4235
4236         /* If the object is no longer pinned, and is
4237          * neither active nor being flushed, then stick it on
4238          * the inactive list
4239          */
4240         if (obj_priv->pin_count == 0) {
4241                 if (!obj_priv->active &&
4242                     (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4243                         list_move_tail(&obj_priv->list,
4244                                        &dev_priv->mm.inactive_list);
4245                 atomic_dec(&dev->pin_count);
4246                 atomic_sub(obj->size, &dev->pin_memory);
4247         }
4248         i915_verify_inactive(dev, __FILE__, __LINE__);
4249 }
4250
4251 int
4252 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4253                    struct drm_file *file_priv)
4254 {
4255         struct drm_i915_gem_pin *args = data;
4256         struct drm_gem_object *obj;
4257         struct drm_i915_gem_object *obj_priv;
4258         int ret;
4259
4260         mutex_lock(&dev->struct_mutex);
4261
4262         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4263         if (obj == NULL) {
4264                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4265                           args->handle);
4266                 mutex_unlock(&dev->struct_mutex);
4267                 return -EBADF;
4268         }
4269         obj_priv = to_intel_bo(obj);
4270
4271         if (obj_priv->madv != I915_MADV_WILLNEED) {
4272                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4273                 drm_gem_object_unreference(obj);
4274                 mutex_unlock(&dev->struct_mutex);
4275                 return -EINVAL;
4276         }
4277
4278         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4279                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4280                           args->handle);
4281                 drm_gem_object_unreference(obj);
4282                 mutex_unlock(&dev->struct_mutex);
4283                 return -EINVAL;
4284         }
4285
4286         obj_priv->user_pin_count++;
4287         obj_priv->pin_filp = file_priv;
4288         if (obj_priv->user_pin_count == 1) {
4289                 ret = i915_gem_object_pin(obj, args->alignment);
4290                 if (ret != 0) {
4291                         drm_gem_object_unreference(obj);
4292                         mutex_unlock(&dev->struct_mutex);
4293                         return ret;
4294                 }
4295         }
4296
4297         /* XXX - flush the CPU caches for pinned objects
4298          * as the X server doesn't manage domains yet
4299          */
4300         i915_gem_object_flush_cpu_write_domain(obj);
4301         args->offset = obj_priv->gtt_offset;
4302         drm_gem_object_unreference(obj);
4303         mutex_unlock(&dev->struct_mutex);
4304
4305         return 0;
4306 }
4307
4308 int
4309 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4310                      struct drm_file *file_priv)
4311 {
4312         struct drm_i915_gem_pin *args = data;
4313         struct drm_gem_object *obj;
4314         struct drm_i915_gem_object *obj_priv;
4315
4316         mutex_lock(&dev->struct_mutex);
4317
4318         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4319         if (obj == NULL) {
4320                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4321                           args->handle);
4322                 mutex_unlock(&dev->struct_mutex);
4323                 return -EBADF;
4324         }
4325
4326         obj_priv = to_intel_bo(obj);
4327         if (obj_priv->pin_filp != file_priv) {
4328                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4329                           args->handle);
4330                 drm_gem_object_unreference(obj);
4331                 mutex_unlock(&dev->struct_mutex);
4332                 return -EINVAL;
4333         }
4334         obj_priv->user_pin_count--;
4335         if (obj_priv->user_pin_count == 0) {
4336                 obj_priv->pin_filp = NULL;
4337                 i915_gem_object_unpin(obj);
4338         }
4339
4340         drm_gem_object_unreference(obj);
4341         mutex_unlock(&dev->struct_mutex);
4342         return 0;
4343 }
4344
4345 int
4346 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4347                     struct drm_file *file_priv)
4348 {
4349         struct drm_i915_gem_busy *args = data;
4350         struct drm_gem_object *obj;
4351         struct drm_i915_gem_object *obj_priv;
4352
4353         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4354         if (obj == NULL) {
4355                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4356                           args->handle);
4357                 return -EBADF;
4358         }
4359
4360         mutex_lock(&dev->struct_mutex);
4361         /* Update the active list for the hardware's current position.
4362          * Otherwise this only updates on a delayed timer or when irqs are
4363          * actually unmasked, and our working set ends up being larger than
4364          * required.
4365          */
4366         i915_gem_retire_requests(dev);
4367
4368         obj_priv = to_intel_bo(obj);
4369         /* Don't count being on the flushing list against the object being
4370          * done.  Otherwise, a buffer left on the flushing list but not getting
4371          * flushed (because nobody's flushing that domain) won't ever return
4372          * unbusy and get reused by libdrm's bo cache.  The other expected
4373          * consumer of this interface, OpenGL's occlusion queries, also specs
4374          * that the objects get unbusy "eventually" without any interference.
4375          */
4376         args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
4377
4378         drm_gem_object_unreference(obj);
4379         mutex_unlock(&dev->struct_mutex);
4380         return 0;
4381 }
4382
4383 int
4384 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4385                         struct drm_file *file_priv)
4386 {
4387     return i915_gem_ring_throttle(dev, file_priv);
4388 }
4389
4390 int
4391 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4392                        struct drm_file *file_priv)
4393 {
4394         struct drm_i915_gem_madvise *args = data;
4395         struct drm_gem_object *obj;
4396         struct drm_i915_gem_object *obj_priv;
4397
4398         switch (args->madv) {
4399         case I915_MADV_DONTNEED:
4400         case I915_MADV_WILLNEED:
4401             break;
4402         default:
4403             return -EINVAL;
4404         }
4405
4406         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4407         if (obj == NULL) {
4408                 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4409                           args->handle);
4410                 return -EBADF;
4411         }
4412
4413         mutex_lock(&dev->struct_mutex);
4414         obj_priv = to_intel_bo(obj);
4415
4416         if (obj_priv->pin_count) {
4417                 drm_gem_object_unreference(obj);
4418                 mutex_unlock(&dev->struct_mutex);
4419
4420                 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4421                 return -EINVAL;
4422         }
4423
4424         if (obj_priv->madv != __I915_MADV_PURGED)
4425                 obj_priv->madv = args->madv;
4426
4427         /* if the object is no longer bound, discard its backing storage */
4428         if (i915_gem_object_is_purgeable(obj_priv) &&
4429             obj_priv->gtt_space == NULL)
4430                 i915_gem_object_truncate(obj);
4431
4432         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4433
4434         drm_gem_object_unreference(obj);
4435         mutex_unlock(&dev->struct_mutex);
4436
4437         return 0;
4438 }
4439
4440 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4441                                               size_t size)
4442 {
4443         struct drm_i915_gem_object *obj;
4444
4445         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4446         if (obj == NULL)
4447                 return NULL;
4448
4449         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4450                 kfree(obj);
4451                 return NULL;
4452         }
4453
4454         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4455         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4456
4457         obj->agp_type = AGP_USER_MEMORY;
4458         obj->base.driver_private = NULL;
4459         obj->fence_reg = I915_FENCE_REG_NONE;
4460         INIT_LIST_HEAD(&obj->list);
4461         INIT_LIST_HEAD(&obj->gpu_write_list);
4462         obj->madv = I915_MADV_WILLNEED;
4463
4464         trace_i915_gem_object_create(&obj->base);
4465
4466         return &obj->base;
4467 }
4468
4469 int i915_gem_init_object(struct drm_gem_object *obj)
4470 {
4471         BUG();
4472
4473         return 0;
4474 }
4475
4476 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4477 {
4478         struct drm_device *dev = obj->dev;
4479         drm_i915_private_t *dev_priv = dev->dev_private;
4480         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4481         int ret;
4482
4483         ret = i915_gem_object_unbind(obj);
4484         if (ret == -ERESTARTSYS) {
4485                 list_move(&obj_priv->list,
4486                           &dev_priv->mm.deferred_free_list);
4487                 return;
4488         }
4489
4490         if (obj_priv->mmap_offset)
4491                 i915_gem_free_mmap_offset(obj);
4492
4493         drm_gem_object_release(obj);
4494
4495         kfree(obj_priv->page_cpu_valid);
4496         kfree(obj_priv->bit_17);
4497         kfree(obj_priv);
4498 }
4499
4500 void i915_gem_free_object(struct drm_gem_object *obj)
4501 {
4502         struct drm_device *dev = obj->dev;
4503         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4504
4505         trace_i915_gem_object_destroy(obj);
4506
4507         while (obj_priv->pin_count > 0)
4508                 i915_gem_object_unpin(obj);
4509
4510         if (obj_priv->phys_obj)
4511                 i915_gem_detach_phys_object(dev, obj);
4512
4513         i915_gem_free_object_tail(obj);
4514 }
4515
4516 /** Unbinds all inactive objects. */
4517 static int
4518 i915_gem_evict_from_inactive_list(struct drm_device *dev)
4519 {
4520         drm_i915_private_t *dev_priv = dev->dev_private;
4521
4522         while (!list_empty(&dev_priv->mm.inactive_list)) {
4523                 struct drm_gem_object *obj;
4524                 int ret;
4525
4526                 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4527                                         struct drm_i915_gem_object,
4528                                         list)->base;
4529
4530                 ret = i915_gem_object_unbind(obj);
4531                 if (ret != 0) {
4532                         DRM_ERROR("Error unbinding object: %d\n", ret);
4533                         return ret;
4534                 }
4535         }
4536
4537         return 0;
4538 }
4539
4540 int
4541 i915_gem_idle(struct drm_device *dev)
4542 {
4543         drm_i915_private_t *dev_priv = dev->dev_private;
4544         int ret;
4545
4546         mutex_lock(&dev->struct_mutex);
4547
4548         if (dev_priv->mm.suspended ||
4549                         (dev_priv->render_ring.gem_object == NULL) ||
4550                         (HAS_BSD(dev) &&
4551                          dev_priv->bsd_ring.gem_object == NULL)) {
4552                 mutex_unlock(&dev->struct_mutex);
4553                 return 0;
4554         }
4555
4556         ret = i915_gpu_idle(dev);
4557         if (ret) {
4558                 mutex_unlock(&dev->struct_mutex);
4559                 return ret;
4560         }
4561
4562         /* Under UMS, be paranoid and evict. */
4563         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4564                 ret = i915_gem_evict_from_inactive_list(dev);
4565                 if (ret) {
4566                         mutex_unlock(&dev->struct_mutex);
4567                         return ret;
4568                 }
4569         }
4570
4571         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4572          * We need to replace this with a semaphore, or something.
4573          * And not confound mm.suspended!
4574          */
4575         dev_priv->mm.suspended = 1;
4576         del_timer(&dev_priv->hangcheck_timer);
4577
4578         i915_kernel_lost_context(dev);
4579         i915_gem_cleanup_ringbuffer(dev);
4580
4581         mutex_unlock(&dev->struct_mutex);
4582
4583         /* Cancel the retire work handler, which should be idle now. */
4584         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4585
4586         return 0;
4587 }
4588
4589 /*
4590  * 965+ support PIPE_CONTROL commands, which provide finer grained control
4591  * over cache flushing.
4592  */
4593 static int
4594 i915_gem_init_pipe_control(struct drm_device *dev)
4595 {
4596         drm_i915_private_t *dev_priv = dev->dev_private;
4597         struct drm_gem_object *obj;
4598         struct drm_i915_gem_object *obj_priv;
4599         int ret;
4600
4601         obj = i915_gem_alloc_object(dev, 4096);
4602         if (obj == NULL) {
4603                 DRM_ERROR("Failed to allocate seqno page\n");
4604                 ret = -ENOMEM;
4605                 goto err;
4606         }
4607         obj_priv = to_intel_bo(obj);
4608         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4609
4610         ret = i915_gem_object_pin(obj, 4096);
4611         if (ret)
4612                 goto err_unref;
4613
4614         dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4615         dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
4616         if (dev_priv->seqno_page == NULL)
4617                 goto err_unpin;
4618
4619         dev_priv->seqno_obj = obj;
4620         memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4621
4622         return 0;
4623
4624 err_unpin:
4625         i915_gem_object_unpin(obj);
4626 err_unref:
4627         drm_gem_object_unreference(obj);
4628 err:
4629         return ret;
4630 }
4631
4632
4633 static void
4634 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4635 {
4636         drm_i915_private_t *dev_priv = dev->dev_private;
4637         struct drm_gem_object *obj;
4638         struct drm_i915_gem_object *obj_priv;
4639
4640         obj = dev_priv->seqno_obj;
4641         obj_priv = to_intel_bo(obj);
4642         kunmap(obj_priv->pages[0]);
4643         i915_gem_object_unpin(obj);
4644         drm_gem_object_unreference(obj);
4645         dev_priv->seqno_obj = NULL;
4646
4647         dev_priv->seqno_page = NULL;
4648 }
4649
4650 int
4651 i915_gem_init_ringbuffer(struct drm_device *dev)
4652 {
4653         drm_i915_private_t *dev_priv = dev->dev_private;
4654         int ret;
4655
4656         dev_priv->render_ring = render_ring;
4657
4658         if (!I915_NEED_GFX_HWS(dev)) {
4659                 dev_priv->render_ring.status_page.page_addr
4660                         = dev_priv->status_page_dmah->vaddr;
4661                 memset(dev_priv->render_ring.status_page.page_addr,
4662                                 0, PAGE_SIZE);
4663         }
4664
4665         if (HAS_PIPE_CONTROL(dev)) {
4666                 ret = i915_gem_init_pipe_control(dev);
4667                 if (ret)
4668                         return ret;
4669         }
4670
4671         ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4672         if (ret)
4673                 goto cleanup_pipe_control;
4674
4675         if (HAS_BSD(dev)) {
4676                 dev_priv->bsd_ring = bsd_ring;
4677                 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4678                 if (ret)
4679                         goto cleanup_render_ring;
4680         }
4681
4682         return 0;
4683
4684 cleanup_render_ring:
4685         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4686 cleanup_pipe_control:
4687         if (HAS_PIPE_CONTROL(dev))
4688                 i915_gem_cleanup_pipe_control(dev);
4689         return ret;
4690 }
4691
4692 void
4693 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4694 {
4695         drm_i915_private_t *dev_priv = dev->dev_private;
4696
4697         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4698         if (HAS_BSD(dev))
4699                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4700         if (HAS_PIPE_CONTROL(dev))
4701                 i915_gem_cleanup_pipe_control(dev);
4702 }
4703
4704 int
4705 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4706                        struct drm_file *file_priv)
4707 {
4708         drm_i915_private_t *dev_priv = dev->dev_private;
4709         int ret;
4710
4711         if (drm_core_check_feature(dev, DRIVER_MODESET))
4712                 return 0;
4713
4714         if (atomic_read(&dev_priv->mm.wedged)) {
4715                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4716                 atomic_set(&dev_priv->mm.wedged, 0);
4717         }
4718
4719         mutex_lock(&dev->struct_mutex);
4720         dev_priv->mm.suspended = 0;
4721
4722         ret = i915_gem_init_ringbuffer(dev);
4723         if (ret != 0) {
4724                 mutex_unlock(&dev->struct_mutex);
4725                 return ret;
4726         }
4727
4728         spin_lock(&dev_priv->mm.active_list_lock);
4729         BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4730         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4731         spin_unlock(&dev_priv->mm.active_list_lock);
4732
4733         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4734         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4735         BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4736         BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4737         mutex_unlock(&dev->struct_mutex);
4738
4739         ret = drm_irq_install(dev);
4740         if (ret)
4741                 goto cleanup_ringbuffer;
4742
4743         return 0;
4744
4745 cleanup_ringbuffer:
4746         mutex_lock(&dev->struct_mutex);
4747         i915_gem_cleanup_ringbuffer(dev);
4748         dev_priv->mm.suspended = 1;
4749         mutex_unlock(&dev->struct_mutex);
4750
4751         return ret;
4752 }
4753
4754 int
4755 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4756                        struct drm_file *file_priv)
4757 {
4758         if (drm_core_check_feature(dev, DRIVER_MODESET))
4759                 return 0;
4760
4761         drm_irq_uninstall(dev);
4762         return i915_gem_idle(dev);
4763 }
4764
4765 void
4766 i915_gem_lastclose(struct drm_device *dev)
4767 {
4768         int ret;
4769
4770         if (drm_core_check_feature(dev, DRIVER_MODESET))
4771                 return;
4772
4773         ret = i915_gem_idle(dev);
4774         if (ret)
4775                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4776 }
4777
4778 void
4779 i915_gem_load(struct drm_device *dev)
4780 {
4781         int i;
4782         drm_i915_private_t *dev_priv = dev->dev_private;
4783
4784         spin_lock_init(&dev_priv->mm.active_list_lock);
4785         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4786         INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4787         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4788         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4789         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4790         INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4791         INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4792         if (HAS_BSD(dev)) {
4793                 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4794                 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4795         }
4796         for (i = 0; i < 16; i++)
4797                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4798         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4799                           i915_gem_retire_work_handler);
4800         spin_lock(&shrink_list_lock);
4801         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4802         spin_unlock(&shrink_list_lock);
4803
4804         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4805         if (IS_GEN3(dev)) {
4806                 u32 tmp = I915_READ(MI_ARB_STATE);
4807                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4808                         /* arb state is a masked write, so set bit + bit in mask */
4809                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4810                         I915_WRITE(MI_ARB_STATE, tmp);
4811                 }
4812         }
4813
4814         /* Old X drivers will take 0-2 for front, back, depth buffers */
4815         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4816                 dev_priv->fence_reg_start = 3;
4817
4818         if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4819                 dev_priv->num_fence_regs = 16;
4820         else
4821                 dev_priv->num_fence_regs = 8;
4822
4823         /* Initialize fence registers to zero */
4824         if (IS_I965G(dev)) {
4825                 for (i = 0; i < 16; i++)
4826                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4827         } else {
4828                 for (i = 0; i < 8; i++)
4829                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4830                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4831                         for (i = 0; i < 8; i++)
4832                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4833         }
4834         i915_gem_detect_bit_6_swizzle(dev);
4835         init_waitqueue_head(&dev_priv->pending_flip_queue);
4836 }
4837
4838 /*
4839  * Create a physically contiguous memory object for this object
4840  * e.g. for cursor + overlay regs
4841  */
4842 int i915_gem_init_phys_object(struct drm_device *dev,
4843                               int id, int size)
4844 {
4845         drm_i915_private_t *dev_priv = dev->dev_private;
4846         struct drm_i915_gem_phys_object *phys_obj;
4847         int ret;
4848
4849         if (dev_priv->mm.phys_objs[id - 1] || !size)
4850                 return 0;
4851
4852         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4853         if (!phys_obj)
4854                 return -ENOMEM;
4855
4856         phys_obj->id = id;
4857
4858         phys_obj->handle = drm_pci_alloc(dev, size, 0);
4859         if (!phys_obj->handle) {
4860                 ret = -ENOMEM;
4861                 goto kfree_obj;
4862         }
4863 #ifdef CONFIG_X86
4864         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4865 #endif
4866
4867         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4868
4869         return 0;
4870 kfree_obj:
4871         kfree(phys_obj);
4872         return ret;
4873 }
4874
4875 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4876 {
4877         drm_i915_private_t *dev_priv = dev->dev_private;
4878         struct drm_i915_gem_phys_object *phys_obj;
4879
4880         if (!dev_priv->mm.phys_objs[id - 1])
4881                 return;
4882
4883         phys_obj = dev_priv->mm.phys_objs[id - 1];
4884         if (phys_obj->cur_obj) {
4885                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4886         }
4887
4888 #ifdef CONFIG_X86
4889         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4890 #endif
4891         drm_pci_free(dev, phys_obj->handle);
4892         kfree(phys_obj);
4893         dev_priv->mm.phys_objs[id - 1] = NULL;
4894 }
4895
4896 void i915_gem_free_all_phys_object(struct drm_device *dev)
4897 {
4898         int i;
4899
4900         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4901                 i915_gem_free_phys_object(dev, i);
4902 }
4903
4904 void i915_gem_detach_phys_object(struct drm_device *dev,
4905                                  struct drm_gem_object *obj)
4906 {
4907         struct drm_i915_gem_object *obj_priv;
4908         int i;
4909         int ret;
4910         int page_count;
4911
4912         obj_priv = to_intel_bo(obj);
4913         if (!obj_priv->phys_obj)
4914                 return;
4915
4916         ret = i915_gem_object_get_pages(obj, 0);
4917         if (ret)
4918                 goto out;
4919
4920         page_count = obj->size / PAGE_SIZE;
4921
4922         for (i = 0; i < page_count; i++) {
4923                 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4924                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4925
4926                 memcpy(dst, src, PAGE_SIZE);
4927                 kunmap_atomic(dst, KM_USER0);
4928         }
4929         drm_clflush_pages(obj_priv->pages, page_count);
4930         drm_agp_chipset_flush(dev);
4931
4932         i915_gem_object_put_pages(obj);
4933 out:
4934         obj_priv->phys_obj->cur_obj = NULL;
4935         obj_priv->phys_obj = NULL;
4936 }
4937
4938 int
4939 i915_gem_attach_phys_object(struct drm_device *dev,
4940                             struct drm_gem_object *obj, int id)
4941 {
4942         drm_i915_private_t *dev_priv = dev->dev_private;
4943         struct drm_i915_gem_object *obj_priv;
4944         int ret = 0;
4945         int page_count;
4946         int i;
4947
4948         if (id > I915_MAX_PHYS_OBJECT)
4949                 return -EINVAL;
4950
4951         obj_priv = to_intel_bo(obj);
4952
4953         if (obj_priv->phys_obj) {
4954                 if (obj_priv->phys_obj->id == id)
4955                         return 0;
4956                 i915_gem_detach_phys_object(dev, obj);
4957         }
4958
4959
4960         /* create a new object */
4961         if (!dev_priv->mm.phys_objs[id - 1]) {
4962                 ret = i915_gem_init_phys_object(dev, id,
4963                                                 obj->size);
4964                 if (ret) {
4965                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4966                         goto out;
4967                 }
4968         }
4969
4970         /* bind to the object */
4971         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4972         obj_priv->phys_obj->cur_obj = obj;
4973
4974         ret = i915_gem_object_get_pages(obj, 0);
4975         if (ret) {
4976                 DRM_ERROR("failed to get page list\n");
4977                 goto out;
4978         }
4979
4980         page_count = obj->size / PAGE_SIZE;
4981
4982         for (i = 0; i < page_count; i++) {
4983                 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4984                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4985
4986                 memcpy(dst, src, PAGE_SIZE);
4987                 kunmap_atomic(src, KM_USER0);
4988         }
4989
4990         i915_gem_object_put_pages(obj);
4991
4992         return 0;
4993 out:
4994         return ret;
4995 }
4996
4997 static int
4998 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4999                      struct drm_i915_gem_pwrite *args,
5000                      struct drm_file *file_priv)
5001 {
5002         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5003         void *obj_addr;
5004         int ret;
5005         char __user *user_data;
5006
5007         user_data = (char __user *) (uintptr_t) args->data_ptr;
5008         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
5009
5010         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
5011         ret = copy_from_user(obj_addr, user_data, args->size);
5012         if (ret)
5013                 return -EFAULT;
5014
5015         drm_agp_chipset_flush(dev);
5016         return 0;
5017 }
5018
5019 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
5020 {
5021         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
5022
5023         /* Clean up our request list when the client is going away, so that
5024          * later retire_requests won't dereference our soon-to-be-gone
5025          * file_priv.
5026          */
5027         mutex_lock(&dev->struct_mutex);
5028         while (!list_empty(&i915_file_priv->mm.request_list))
5029                 list_del_init(i915_file_priv->mm.request_list.next);
5030         mutex_unlock(&dev->struct_mutex);
5031 }
5032
5033 static int
5034 i915_gpu_is_active(struct drm_device *dev)
5035 {
5036         drm_i915_private_t *dev_priv = dev->dev_private;
5037         int lists_empty;
5038
5039         spin_lock(&dev_priv->mm.active_list_lock);
5040         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
5041                       list_empty(&dev_priv->render_ring.active_list);
5042         if (HAS_BSD(dev))
5043                 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
5044         spin_unlock(&dev_priv->mm.active_list_lock);
5045
5046         return !lists_empty;
5047 }
5048
5049 static int
5050 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
5051 {
5052         drm_i915_private_t *dev_priv, *next_dev;
5053         struct drm_i915_gem_object *obj_priv, *next_obj;
5054         int cnt = 0;
5055         int would_deadlock = 1;
5056
5057         /* "fast-path" to count number of available objects */
5058         if (nr_to_scan == 0) {
5059                 spin_lock(&shrink_list_lock);
5060                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5061                         struct drm_device *dev = dev_priv->dev;
5062
5063                         if (mutex_trylock(&dev->struct_mutex)) {
5064                                 list_for_each_entry(obj_priv,
5065                                                     &dev_priv->mm.inactive_list,
5066                                                     list)
5067                                         cnt++;
5068                                 mutex_unlock(&dev->struct_mutex);
5069                         }
5070                 }
5071                 spin_unlock(&shrink_list_lock);
5072
5073                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5074         }
5075
5076         spin_lock(&shrink_list_lock);
5077
5078 rescan:
5079         /* first scan for clean buffers */
5080         list_for_each_entry_safe(dev_priv, next_dev,
5081                                  &shrink_list, mm.shrink_list) {
5082                 struct drm_device *dev = dev_priv->dev;
5083
5084                 if (! mutex_trylock(&dev->struct_mutex))
5085                         continue;
5086
5087                 spin_unlock(&shrink_list_lock);
5088                 i915_gem_retire_requests(dev);
5089
5090                 list_for_each_entry_safe(obj_priv, next_obj,
5091                                          &dev_priv->mm.inactive_list,
5092                                          list) {
5093                         if (i915_gem_object_is_purgeable(obj_priv)) {
5094                                 i915_gem_object_unbind(&obj_priv->base);
5095                                 if (--nr_to_scan <= 0)
5096                                         break;
5097                         }
5098                 }
5099
5100                 spin_lock(&shrink_list_lock);
5101                 mutex_unlock(&dev->struct_mutex);
5102
5103                 would_deadlock = 0;
5104
5105                 if (nr_to_scan <= 0)
5106                         break;
5107         }
5108
5109         /* second pass, evict/count anything still on the inactive list */
5110         list_for_each_entry_safe(dev_priv, next_dev,
5111                                  &shrink_list, mm.shrink_list) {
5112                 struct drm_device *dev = dev_priv->dev;
5113
5114                 if (! mutex_trylock(&dev->struct_mutex))
5115                         continue;
5116
5117                 spin_unlock(&shrink_list_lock);
5118
5119                 list_for_each_entry_safe(obj_priv, next_obj,
5120                                          &dev_priv->mm.inactive_list,
5121                                          list) {
5122                         if (nr_to_scan > 0) {
5123                                 i915_gem_object_unbind(&obj_priv->base);
5124                                 nr_to_scan--;
5125                         } else
5126                                 cnt++;
5127                 }
5128
5129                 spin_lock(&shrink_list_lock);
5130                 mutex_unlock(&dev->struct_mutex);
5131
5132                 would_deadlock = 0;
5133         }
5134
5135         if (nr_to_scan) {
5136                 int active = 0;
5137
5138                 /*
5139                  * We are desperate for pages, so as a last resort, wait
5140                  * for the GPU to finish and discard whatever we can.
5141                  * This has a dramatic impact to reduce the number of
5142                  * OOM-killer events whilst running the GPU aggressively.
5143                  */
5144                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5145                         struct drm_device *dev = dev_priv->dev;
5146
5147                         if (!mutex_trylock(&dev->struct_mutex))
5148                                 continue;
5149
5150                         spin_unlock(&shrink_list_lock);
5151
5152                         if (i915_gpu_is_active(dev)) {
5153                                 i915_gpu_idle(dev);
5154                                 active++;
5155                         }
5156
5157                         spin_lock(&shrink_list_lock);
5158                         mutex_unlock(&dev->struct_mutex);
5159                 }
5160
5161                 if (active)
5162                         goto rescan;
5163         }
5164
5165         spin_unlock(&shrink_list_lock);
5166
5167         if (would_deadlock)
5168                 return -1;
5169         else if (cnt > 0)
5170                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5171         else
5172                 return 0;
5173 }
5174
5175 static struct shrinker shrinker = {
5176         .shrink = i915_gem_shrink,
5177         .seeks = DEFAULT_SEEKS,
5178 };
5179
5180 __init void
5181 i915_gem_shrinker_init(void)
5182 {
5183     register_shrinker(&shrinker);
5184 }
5185
5186 __exit void
5187 i915_gem_shrinker_exit(void)
5188 {
5189     unregister_shrinker(&shrinker);
5190 }