drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/slab.h>
  35 #include <linux/swap.h>
  36 #include <linux/pci.h>
  37 #include <linux/intel-gtt.h>
  38
  39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
  40
  41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
  42                                                   bool pipelined);
  43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  46                                              int write);
  47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  48                                                      uint64_t offset,
  49                                                      uint64_t size);
  50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
  52                                           bool interruptible);
  53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
  54                                            unsigned alignment);
  55 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
  56 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
  57                                 struct drm_i915_gem_pwrite *args,
  58                                 struct drm_file *file_priv);
  59 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
  60
  61 static int
  62 i915_gem_object_get_pages(struct drm_gem_object *obj,
  63                           gfp_t gfpmask);
  64
  65 static void
  66 i915_gem_object_put_pages(struct drm_gem_object *obj);
  67
  68 static LIST_HEAD(shrink_list);
  69 static DEFINE_SPINLOCK(shrink_list_lock);
  70
  71 /* some bookkeeping */
  72 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  73                                   size_t size)
  74 {
  75         dev_priv->mm.object_count++;
  76         dev_priv->mm.object_memory += size;
  77 }
  78
  79 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  80                                      size_t size)
  81 {
  82         dev_priv->mm.object_count--;
  83         dev_priv->mm.object_memory -= size;
  84 }
  85
  86 static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv,
  87                                   size_t size)
  88 {
  89         dev_priv->mm.gtt_count++;
  90         dev_priv->mm.gtt_memory += size;
  91 }
  92
  93 static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv,
  94                                      size_t size)
  95 {
  96         dev_priv->mm.gtt_count--;
  97         dev_priv->mm.gtt_memory -= size;
  98 }
  99
 100 static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv,
 101                                   size_t size)
 102 {
 103         dev_priv->mm.pin_count++;
 104         dev_priv->mm.pin_memory += size;
 105 }
 106
 107 static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv,
 108                                      size_t size)
 109 {
 110         dev_priv->mm.pin_count--;
 111         dev_priv->mm.pin_memory -= size;
 112 }
 113
 114 int
 115 i915_gem_check_is_wedged(struct drm_device *dev)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118         struct completion *x = &dev_priv->error_completion;
 119         unsigned long flags;
 120         int ret;
 121
 122         if (!atomic_read(&dev_priv->mm.wedged))
 123                 return 0;
 124
 125         ret = wait_for_completion_interruptible(x);
 126         if (ret)
 127                 return ret;
 128
 129         /* Success, we reset the GPU! */
 130         if (!atomic_read(&dev_priv->mm.wedged))
 131                 return 0;
 132
 133         /* GPU is hung, bump the completion count to account for
 134          * the token we just consumed so that we never hit zero and
 135          * end up waiting upon a subsequent completion event that
 136          * will never happen.
 137          */
 138         spin_lock_irqsave(&x->wait.lock, flags);
 139         x->done++;
 140         spin_unlock_irqrestore(&x->wait.lock, flags);
 141         return -EIO;
 142 }
 143
 144 static int i915_mutex_lock_interruptible(struct drm_device *dev)
 145 {
 146         struct drm_i915_private *dev_priv = dev->dev_private;
 147         int ret;
 148
 149         ret = i915_gem_check_is_wedged(dev);
 150         if (ret)
 151                 return ret;
 152
 153         ret = mutex_lock_interruptible(&dev->struct_mutex);
 154         if (ret)
 155                 return ret;
 156
 157         if (atomic_read(&dev_priv->mm.wedged)) {
 158                 mutex_unlock(&dev->struct_mutex);
 159                 return -EAGAIN;
 160         }
 161
 162         WARN_ON(i915_verify_lists(dev));
 163         return 0;
 164 }
 165
 166 static inline bool
 167 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
 168 {
 169         return obj_priv->gtt_space &&
 170                 !obj_priv->active &&
 171                 obj_priv->pin_count == 0;
 172 }
 173
 174 int i915_gem_do_init(struct drm_device *dev,
 175                      unsigned long start,
 176                      unsigned long end)
 177 {
 178         drm_i915_private_t *dev_priv = dev->dev_private;
 179
 180         if (start >= end ||
 181             (start & (PAGE_SIZE - 1)) != 0 ||
 182             (end & (PAGE_SIZE - 1)) != 0) {
 183                 return -EINVAL;
 184         }
 185
 186         drm_mm_init(&dev_priv->mm.gtt_space, start,
 187                     end - start);
 188
 189         dev_priv->mm.gtt_total = end - start;
 190
 191         return 0;
 192 }
 193
 194 int
 195 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 196                     struct drm_file *file_priv)
 197 {
 198         struct drm_i915_gem_init *args = data;
 199         int ret;
 200
 201         mutex_lock(&dev->struct_mutex);
 202         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
 203         mutex_unlock(&dev->struct_mutex);
 204
 205         return ret;
 206 }
 207
 208 int
 209 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 210                             struct drm_file *file_priv)
 211 {
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct drm_i915_gem_get_aperture *args = data;
 214
 215         if (!(dev->driver->driver_features & DRIVER_GEM))
 216                 return -ENODEV;
 217
 218         mutex_lock(&dev->struct_mutex);
 219         args->aper_size = dev_priv->mm.gtt_total;
 220         args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory;
 221         mutex_unlock(&dev->struct_mutex);
 222
 223         return 0;
 224 }
 225
 226
 227 /**
 228  * Creates a new mm object and returns a handle to it.
 229  */
 230 int
 231 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 232                       struct drm_file *file_priv)
 233 {
 234         struct drm_i915_gem_create *args = data;
 235         struct drm_gem_object *obj;
 236         int ret;
 237         u32 handle;
 238
 239         args->size = roundup(args->size, PAGE_SIZE);
 240
 241         /* Allocate the new object */
 242         obj = i915_gem_alloc_object(dev, args->size);
 243         if (obj == NULL)
 244                 return -ENOMEM;
 245
 246         ret = drm_gem_handle_create(file_priv, obj, &handle);
 247         if (ret) {
 248                 drm_gem_object_release(obj);
 249                 i915_gem_info_remove_obj(dev->dev_private, obj->size);
 250                 kfree(obj);
 251                 return ret;
 252         }
 253
 254         /* drop reference from allocate - handle holds it now */
 255         drm_gem_object_unreference(obj);
 256         trace_i915_gem_object_create(obj);
 257
 258         args->handle = handle;
 259         return 0;
 260 }
 261
 262 static inline int
 263 fast_shmem_read(struct page **pages,
 264                 loff_t page_base, int page_offset,
 265                 char __user *data,
 266                 int length)
 267 {
 268         char *vaddr;
 269         int ret;
 270
 271         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]);
 272         ret = __copy_to_user_inatomic(data, vaddr + page_offset, length);
 273         kunmap_atomic(vaddr);
 274
 275         return ret;
 276 }
 277
 278 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
 279 {
 280         drm_i915_private_t *dev_priv = obj->dev->dev_private;
 281         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 282
 283         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
 284                 obj_priv->tiling_mode != I915_TILING_NONE;
 285 }
 286
 287 static inline void
 288 slow_shmem_copy(struct page *dst_page,
 289                 int dst_offset,
 290                 struct page *src_page,
 291                 int src_offset,
 292                 int length)
 293 {
 294         char *dst_vaddr, *src_vaddr;
 295
 296         dst_vaddr = kmap(dst_page);
 297         src_vaddr = kmap(src_page);
 298
 299         memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
 300
 301         kunmap(src_page);
 302         kunmap(dst_page);
 303 }
 304
 305 static inline void
 306 slow_shmem_bit17_copy(struct page *gpu_page,
 307                       int gpu_offset,
 308                       struct page *cpu_page,
 309                       int cpu_offset,
 310                       int length,
 311                       int is_read)
 312 {
 313         char *gpu_vaddr, *cpu_vaddr;
 314
 315         /* Use the unswizzled path if this page isn't affected. */
 316         if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
 317                 if (is_read)
 318                         return slow_shmem_copy(cpu_page, cpu_offset,
 319                                                gpu_page, gpu_offset, length);
 320                 else
 321                         return slow_shmem_copy(gpu_page, gpu_offset,
 322                                                cpu_page, cpu_offset, length);
 323         }
 324
 325         gpu_vaddr = kmap(gpu_page);
 326         cpu_vaddr = kmap(cpu_page);
 327
 328         /* Copy the data, XORing A6 with A17 (1). The user already knows he's
 329          * XORing with the other bits (A9 for Y, A9 and A10 for X)
 330          */
 331         while (length > 0) {
 332                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 333                 int this_length = min(cacheline_end - gpu_offset, length);
 334                 int swizzled_gpu_offset = gpu_offset ^ 64;
 335
 336                 if (is_read) {
 337                         memcpy(cpu_vaddr + cpu_offset,
 338                                gpu_vaddr + swizzled_gpu_offset,
 339                                this_length);
 340                 } else {
 341                         memcpy(gpu_vaddr + swizzled_gpu_offset,
 342                                cpu_vaddr + cpu_offset,
 343                                this_length);
 344                 }
 345                 cpu_offset += this_length;
 346                 gpu_offset += this_length;
 347                 length -= this_length;
 348         }
 349
 350         kunmap(cpu_page);
 351         kunmap(gpu_page);
 352 }
 353
 354 /**
 355  * This is the fast shmem pread path, which attempts to copy_from_user directly
 356  * from the backing pages of the object to the user's address space.  On a
 357  * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
 358  */
 359 static int
 360 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
 361                           struct drm_i915_gem_pread *args,
 362                           struct drm_file *file_priv)
 363 {
 364         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 365         ssize_t remain;
 366         loff_t offset, page_base;
 367         char __user *user_data;
 368         int page_offset, page_length;
 369
 370         user_data = (char __user *) (uintptr_t) args->data_ptr;
 371         remain = args->size;
 372
 373         obj_priv = to_intel_bo(obj);
 374         offset = args->offset;
 375
 376         while (remain > 0) {
 377                 /* Operation in this page
 378                  *
 379                  * page_base = page offset within aperture
 380                  * page_offset = offset within page
 381                  * page_length = bytes to copy for this page
 382                  */
 383                 page_base = (offset & ~(PAGE_SIZE-1));
 384                 page_offset = offset & (PAGE_SIZE-1);
 385                 page_length = remain;
 386                 if ((page_offset + remain) > PAGE_SIZE)
 387                         page_length = PAGE_SIZE - page_offset;
 388
 389                 if (fast_shmem_read(obj_priv->pages,
 390                                     page_base, page_offset,
 391                                     user_data, page_length))
 392                         return -EFAULT;
 393
 394                 remain -= page_length;
 395                 user_data += page_length;
 396                 offset += page_length;
 397         }
 398
 399         return 0;
 400 }
 401
 402 static int
 403 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
 404 {
 405         int ret;
 406
 407         ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
 408
 409         /* If we've insufficient memory to map in the pages, attempt
 410          * to make some space by throwing out some old buffers.
 411          */
 412         if (ret == -ENOMEM) {
 413                 struct drm_device *dev = obj->dev;
 414
 415                 ret = i915_gem_evict_something(dev, obj->size,
 416                                                i915_gem_get_gtt_alignment(obj));
 417                 if (ret)
 418                         return ret;
 419
 420                 ret = i915_gem_object_get_pages(obj, 0);
 421         }
 422
 423         return ret;
 424 }
 425
 426 /**
 427  * This is the fallback shmem pread path, which allocates temporary storage
 428  * in kernel space to copy_to_user into outside of the struct_mutex, so we
 429  * can copy out of the object's backing pages while holding the struct mutex
 430  * and not take page faults.
 431  */
 432 static int
 433 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
 434                           struct drm_i915_gem_pread *args,
 435                           struct drm_file *file_priv)
 436 {
 437         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 438         struct mm_struct *mm = current->mm;
 439         struct page **user_pages;
 440         ssize_t remain;
 441         loff_t offset, pinned_pages, i;
 442         loff_t first_data_page, last_data_page, num_pages;
 443         int shmem_page_index, shmem_page_offset;
 444         int data_page_index,  data_page_offset;
 445         int page_length;
 446         int ret;
 447         uint64_t data_ptr = args->data_ptr;
 448         int do_bit17_swizzling;
 449
 450         remain = args->size;
 451
 452         /* Pin the user pages containing the data.  We can't fault while
 453          * holding the struct mutex, yet we want to hold it while
 454          * dereferencing the user data.
 455          */
 456         first_data_page = data_ptr / PAGE_SIZE;
 457         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 458         num_pages = last_data_page - first_data_page + 1;
 459
 460         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 461         if (user_pages == NULL)
 462                 return -ENOMEM;
 463
 464         mutex_unlock(&dev->struct_mutex);
 465         down_read(&mm->mmap_sem);
 466         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 467                                       num_pages, 1, 0, user_pages, NULL);
 468         up_read(&mm->mmap_sem);
 469         mutex_lock(&dev->struct_mutex);
 470         if (pinned_pages < num_pages) {
 471                 ret = -EFAULT;
 472                 goto out;
 473         }
 474
 475         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 476                                                         args->offset,
 477                                                         args->size);
 478         if (ret)
 479                 goto out;
 480
 481         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 482
 483         obj_priv = to_intel_bo(obj);
 484         offset = args->offset;
 485
 486         while (remain > 0) {
 487                 /* Operation in this page
 488                  *
 489                  * shmem_page_index = page number within shmem file
 490                  * shmem_page_offset = offset within page in shmem file
 491                  * data_page_index = page number in get_user_pages return
 492                  * data_page_offset = offset with data_page_index page.
 493                  * page_length = bytes to copy for this page
 494                  */
 495                 shmem_page_index = offset / PAGE_SIZE;
 496                 shmem_page_offset = offset & ~PAGE_MASK;
 497                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 498                 data_page_offset = data_ptr & ~PAGE_MASK;
 499
 500                 page_length = remain;
 501                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 502                         page_length = PAGE_SIZE - shmem_page_offset;
 503                 if ((data_page_offset + page_length) > PAGE_SIZE)
 504                         page_length = PAGE_SIZE - data_page_offset;
 505
 506                 if (do_bit17_swizzling) {
 507                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 508                                               shmem_page_offset,
 509                                               user_pages[data_page_index],
 510                                               data_page_offset,
 511                                               page_length,
 512                                               1);
 513                 } else {
 514                         slow_shmem_copy(user_pages[data_page_index],
 515                                         data_page_offset,
 516                                         obj_priv->pages[shmem_page_index],
 517                                         shmem_page_offset,
 518                                         page_length);
 519                 }
 520
 521                 remain -= page_length;
 522                 data_ptr += page_length;
 523                 offset += page_length;
 524         }
 525
 526 out:
 527         for (i = 0; i < pinned_pages; i++) {
 528                 SetPageDirty(user_pages[i]);
 529                 page_cache_release(user_pages[i]);
 530         }
 531         drm_free_large(user_pages);
 532
 533         return ret;
 534 }
 535
 536 /**
 537  * Reads data from the object referenced by handle.
 538  *
 539  * On error, the contents of *data are undefined.
 540  */
 541 int
 542 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 543                      struct drm_file *file_priv)
 544 {
 545         struct drm_i915_gem_pread *args = data;
 546         struct drm_gem_object *obj;
 547         struct drm_i915_gem_object *obj_priv;
 548         int ret = 0;
 549
 550         ret = i915_mutex_lock_interruptible(dev);
 551         if (ret)
 552                 return ret;
 553
 554         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 555         if (obj == NULL) {
 556                 ret = -ENOENT;
 557                 goto unlock;
 558         }
 559         obj_priv = to_intel_bo(obj);
 560
 561         /* Bounds check source.  */
 562         if (args->offset > obj->size || args->size > obj->size - args->offset) {
 563                 ret = -EINVAL;
 564                 goto out;
 565         }
 566
 567         if (args->size == 0)
 568                 goto out;
 569
 570         if (!access_ok(VERIFY_WRITE,
 571                        (char __user *)(uintptr_t)args->data_ptr,
 572                        args->size)) {
 573                 ret = -EFAULT;
 574                 goto out;
 575         }
 576
 577         ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
 578                                        args->size);
 579         if (ret) {
 580                 ret = -EFAULT;
 581                 goto out;
 582         }
 583
 584         ret = i915_gem_object_get_pages_or_evict(obj);
 585         if (ret)
 586                 goto out;
 587
 588         ret = i915_gem_object_set_cpu_read_domain_range(obj,
 589                                                         args->offset,
 590                                                         args->size);
 591         if (ret)
 592                 goto out_put;
 593
 594         ret = -EFAULT;
 595         if (!i915_gem_object_needs_bit17_swizzle(obj))
 596                 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
 597         if (ret == -EFAULT)
 598                 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
 599
 600 out_put:
 601         i915_gem_object_put_pages(obj);
 602 out:
 603         drm_gem_object_unreference(obj);
 604 unlock:
 605         mutex_unlock(&dev->struct_mutex);
 606         return ret;
 607 }
 608
 609 /* This is the fast write path which cannot handle
 610  * page faults in the source data
 611  */
 612
 613 static inline int
 614 fast_user_write(struct io_mapping *mapping,
 615                 loff_t page_base, int page_offset,
 616                 char __user *user_data,
 617                 int length)
 618 {
 619         char *vaddr_atomic;
 620         unsigned long unwritten;
 621
 622         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 623         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 624                                                       user_data, length);
 625         io_mapping_unmap_atomic(vaddr_atomic);
 626         return unwritten;
 627 }
 628
 629 /* Here's the write path which can sleep for
 630  * page faults
 631  */
 632
 633 static inline void
 634 slow_kernel_write(struct io_mapping *mapping,
 635                   loff_t gtt_base, int gtt_offset,
 636                   struct page *user_page, int user_offset,
 637                   int length)
 638 {
 639         char __iomem *dst_vaddr;
 640         char *src_vaddr;
 641
 642         dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
 643         src_vaddr = kmap(user_page);
 644
 645         memcpy_toio(dst_vaddr + gtt_offset,
 646                     src_vaddr + user_offset,
 647                     length);
 648
 649         kunmap(user_page);
 650         io_mapping_unmap(dst_vaddr);
 651 }
 652
 653 static inline int
 654 fast_shmem_write(struct page **pages,
 655                  loff_t page_base, int page_offset,
 656                  char __user *data,
 657                  int length)
 658 {
 659         char *vaddr;
 660         int ret;
 661
 662         vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]);
 663         ret = __copy_from_user_inatomic(vaddr + page_offset, data, length);
 664         kunmap_atomic(vaddr);
 665
 666         return ret;
 667 }
 668
 669 /**
 670  * This is the fast pwrite path, where we copy the data directly from the
 671  * user into the GTT, uncached.
 672  */
 673 static int
 674 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 675                          struct drm_i915_gem_pwrite *args,
 676                          struct drm_file *file_priv)
 677 {
 678         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 679         drm_i915_private_t *dev_priv = dev->dev_private;
 680         ssize_t remain;
 681         loff_t offset, page_base;
 682         char __user *user_data;
 683         int page_offset, page_length;
 684
 685         user_data = (char __user *) (uintptr_t) args->data_ptr;
 686         remain = args->size;
 687
 688         obj_priv = to_intel_bo(obj);
 689         offset = obj_priv->gtt_offset + args->offset;
 690
 691         while (remain > 0) {
 692                 /* Operation in this page
 693                  *
 694                  * page_base = page offset within aperture
 695                  * page_offset = offset within page
 696                  * page_length = bytes to copy for this page
 697                  */
 698                 page_base = (offset & ~(PAGE_SIZE-1));
 699                 page_offset = offset & (PAGE_SIZE-1);
 700                 page_length = remain;
 701                 if ((page_offset + remain) > PAGE_SIZE)
 702                         page_length = PAGE_SIZE - page_offset;
 703
 704                 /* If we get a fault while copying data, then (presumably) our
 705                  * source page isn't available.  Return the error and we'll
 706                  * retry in the slow path.
 707                  */
 708                 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
 709                                     page_offset, user_data, page_length))
 710
 711                         return -EFAULT;
 712
 713                 remain -= page_length;
 714                 user_data += page_length;
 715                 offset += page_length;
 716         }
 717
 718         return 0;
 719 }
 720
 721 /**
 722  * This is the fallback GTT pwrite path, which uses get_user_pages to pin
 723  * the memory and maps it using kmap_atomic for copying.
 724  *
 725  * This code resulted in x11perf -rgb10text consuming about 10% more CPU
 726  * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
 727  */
 728 static int
 729 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 730                          struct drm_i915_gem_pwrite *args,
 731                          struct drm_file *file_priv)
 732 {
 733         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 734         drm_i915_private_t *dev_priv = dev->dev_private;
 735         ssize_t remain;
 736         loff_t gtt_page_base, offset;
 737         loff_t first_data_page, last_data_page, num_pages;
 738         loff_t pinned_pages, i;
 739         struct page **user_pages;
 740         struct mm_struct *mm = current->mm;
 741         int gtt_page_offset, data_page_offset, data_page_index, page_length;
 742         int ret;
 743         uint64_t data_ptr = args->data_ptr;
 744
 745         remain = args->size;
 746
 747         /* Pin the user pages containing the data.  We can't fault while
 748          * holding the struct mutex, and all of the pwrite implementations
 749          * want to hold it while dereferencing the user data.
 750          */
 751         first_data_page = data_ptr / PAGE_SIZE;
 752         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 753         num_pages = last_data_page - first_data_page + 1;
 754
 755         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 756         if (user_pages == NULL)
 757                 return -ENOMEM;
 758
 759         mutex_unlock(&dev->struct_mutex);
 760         down_read(&mm->mmap_sem);
 761         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 762                                       num_pages, 0, 0, user_pages, NULL);
 763         up_read(&mm->mmap_sem);
 764         mutex_lock(&dev->struct_mutex);
 765         if (pinned_pages < num_pages) {
 766                 ret = -EFAULT;
 767                 goto out_unpin_pages;
 768         }
 769
 770         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 771         if (ret)
 772                 goto out_unpin_pages;
 773
 774         obj_priv = to_intel_bo(obj);
 775         offset = obj_priv->gtt_offset + args->offset;
 776
 777         while (remain > 0) {
 778                 /* Operation in this page
 779                  *
 780                  * gtt_page_base = page offset within aperture
 781                  * gtt_page_offset = offset within page in aperture
 782                  * data_page_index = page number in get_user_pages return
 783                  * data_page_offset = offset with data_page_index page.
 784                  * page_length = bytes to copy for this page
 785                  */
 786                 gtt_page_base = offset & PAGE_MASK;
 787                 gtt_page_offset = offset & ~PAGE_MASK;
 788                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 789                 data_page_offset = data_ptr & ~PAGE_MASK;
 790
 791                 page_length = remain;
 792                 if ((gtt_page_offset + page_length) > PAGE_SIZE)
 793                         page_length = PAGE_SIZE - gtt_page_offset;
 794                 if ((data_page_offset + page_length) > PAGE_SIZE)
 795                         page_length = PAGE_SIZE - data_page_offset;
 796
 797                 slow_kernel_write(dev_priv->mm.gtt_mapping,
 798                                   gtt_page_base, gtt_page_offset,
 799                                   user_pages[data_page_index],
 800                                   data_page_offset,
 801                                   page_length);
 802
 803                 remain -= page_length;
 804                 offset += page_length;
 805                 data_ptr += page_length;
 806         }
 807
 808 out_unpin_pages:
 809         for (i = 0; i < pinned_pages; i++)
 810                 page_cache_release(user_pages[i]);
 811         drm_free_large(user_pages);
 812
 813         return ret;
 814 }
 815
 816 /**
 817  * This is the fast shmem pwrite path, which attempts to directly
 818  * copy_from_user into the kmapped pages backing the object.
 819  */
 820 static int
 821 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
 822                            struct drm_i915_gem_pwrite *args,
 823                            struct drm_file *file_priv)
 824 {
 825         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 826         ssize_t remain;
 827         loff_t offset, page_base;
 828         char __user *user_data;
 829         int page_offset, page_length;
 830
 831         user_data = (char __user *) (uintptr_t) args->data_ptr;
 832         remain = args->size;
 833
 834         obj_priv = to_intel_bo(obj);
 835         offset = args->offset;
 836         obj_priv->dirty = 1;
 837
 838         while (remain > 0) {
 839                 /* Operation in this page
 840                  *
 841                  * page_base = page offset within aperture
 842                  * page_offset = offset within page
 843                  * page_length = bytes to copy for this page
 844                  */
 845                 page_base = (offset & ~(PAGE_SIZE-1));
 846                 page_offset = offset & (PAGE_SIZE-1);
 847                 page_length = remain;
 848                 if ((page_offset + remain) > PAGE_SIZE)
 849                         page_length = PAGE_SIZE - page_offset;
 850
 851                 if (fast_shmem_write(obj_priv->pages,
 852                                        page_base, page_offset,
 853                                        user_data, page_length))
 854                         return -EFAULT;
 855
 856                 remain -= page_length;
 857                 user_data += page_length;
 858                 offset += page_length;
 859         }
 860
 861         return 0;
 862 }
 863
 864 /**
 865  * This is the fallback shmem pwrite path, which uses get_user_pages to pin
 866  * the memory and maps it using kmap_atomic for copying.
 867  *
 868  * This avoids taking mmap_sem for faulting on the user's address while the
 869  * struct_mutex is held.
 870  */
 871 static int
 872 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
 873                            struct drm_i915_gem_pwrite *args,
 874                            struct drm_file *file_priv)
 875 {
 876         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
 877         struct mm_struct *mm = current->mm;
 878         struct page **user_pages;
 879         ssize_t remain;
 880         loff_t offset, pinned_pages, i;
 881         loff_t first_data_page, last_data_page, num_pages;
 882         int shmem_page_index, shmem_page_offset;
 883         int data_page_index,  data_page_offset;
 884         int page_length;
 885         int ret;
 886         uint64_t data_ptr = args->data_ptr;
 887         int do_bit17_swizzling;
 888
 889         remain = args->size;
 890
 891         /* Pin the user pages containing the data.  We can't fault while
 892          * holding the struct mutex, and all of the pwrite implementations
 893          * want to hold it while dereferencing the user data.
 894          */
 895         first_data_page = data_ptr / PAGE_SIZE;
 896         last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
 897         num_pages = last_data_page - first_data_page + 1;
 898
 899         user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
 900         if (user_pages == NULL)
 901                 return -ENOMEM;
 902
 903         mutex_unlock(&dev->struct_mutex);
 904         down_read(&mm->mmap_sem);
 905         pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
 906                                       num_pages, 0, 0, user_pages, NULL);
 907         up_read(&mm->mmap_sem);
 908         mutex_lock(&dev->struct_mutex);
 909         if (pinned_pages < num_pages) {
 910                 ret = -EFAULT;
 911                 goto out;
 912         }
 913
 914         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 915         if (ret)
 916                 goto out;
 917
 918         do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 919
 920         obj_priv = to_intel_bo(obj);
 921         offset = args->offset;
 922         obj_priv->dirty = 1;
 923
 924         while (remain > 0) {
 925                 /* Operation in this page
 926                  *
 927                  * shmem_page_index = page number within shmem file
 928                  * shmem_page_offset = offset within page in shmem file
 929                  * data_page_index = page number in get_user_pages return
 930                  * data_page_offset = offset with data_page_index page.
 931                  * page_length = bytes to copy for this page
 932                  */
 933                 shmem_page_index = offset / PAGE_SIZE;
 934                 shmem_page_offset = offset & ~PAGE_MASK;
 935                 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
 936                 data_page_offset = data_ptr & ~PAGE_MASK;
 937
 938                 page_length = remain;
 939                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 940                         page_length = PAGE_SIZE - shmem_page_offset;
 941                 if ((data_page_offset + page_length) > PAGE_SIZE)
 942                         page_length = PAGE_SIZE - data_page_offset;
 943
 944                 if (do_bit17_swizzling) {
 945                         slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
 946                                               shmem_page_offset,
 947                                               user_pages[data_page_index],
 948                                               data_page_offset,
 949                                               page_length,
 950                                               0);
 951                 } else {
 952                         slow_shmem_copy(obj_priv->pages[shmem_page_index],
 953                                         shmem_page_offset,
 954                                         user_pages[data_page_index],
 955                                         data_page_offset,
 956                                         page_length);
 957                 }
 958
 959                 remain -= page_length;
 960                 data_ptr += page_length;
 961                 offset += page_length;
 962         }
 963
 964 out:
 965         for (i = 0; i < pinned_pages; i++)
 966                 page_cache_release(user_pages[i]);
 967         drm_free_large(user_pages);
 968
 969         return ret;
 970 }
 971
 972 /**
 973  * Writes data to the object referenced by handle.
 974  *
 975  * On error, the contents of the buffer that were to be modified are undefined.
 976  */
 977 int
 978 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 979                       struct drm_file *file)
 980 {
 981         struct drm_i915_gem_pwrite *args = data;
 982         struct drm_gem_object *obj;
 983         struct drm_i915_gem_object *obj_priv;
 984         int ret = 0;
 985
 986         ret = i915_mutex_lock_interruptible(dev);
 987         if (ret)
 988                 return ret;
 989
 990         obj = drm_gem_object_lookup(dev, file, args->handle);
 991         if (obj == NULL) {
 992                 ret = -ENOENT;
 993                 goto unlock;
 994         }
 995         obj_priv = to_intel_bo(obj);
 996
 997
 998         /* Bounds check destination. */
 999         if (args->offset > obj->size || args->size > obj->size - args->offset) {
1000                 ret = -EINVAL;
1001                 goto out;
1002         }
1003
1004         if (args->size == 0)
1005                 goto out;
1006
1007         if (!access_ok(VERIFY_READ,
1008                        (char __user *)(uintptr_t)args->data_ptr,
1009                        args->size)) {
1010                 ret = -EFAULT;
1011                 goto out;
1012         }
1013
1014         ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
1015                                       args->size);
1016         if (ret) {
1017                 ret = -EFAULT;
1018                 goto out;
1019         }
1020
1021         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1022          * it would end up going through the fenced access, and we'll get
1023          * different detiling behavior between reading and writing.
1024          * pread/pwrite currently are reading and writing from the CPU
1025          * perspective, requiring manual detiling by the client.
1026          */
1027         if (obj_priv->phys_obj)
1028                 ret = i915_gem_phys_pwrite(dev, obj, args, file);
1029         else if (obj_priv->tiling_mode == I915_TILING_NONE &&
1030                  obj_priv->gtt_space &&
1031                  obj->write_domain != I915_GEM_DOMAIN_CPU) {
1032                 ret = i915_gem_object_pin(obj, 0);
1033                 if (ret)
1034                         goto out;
1035
1036                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1037                 if (ret)
1038                         goto out_unpin;
1039
1040                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1041                 if (ret == -EFAULT)
1042                         ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1043
1044 out_unpin:
1045                 i915_gem_object_unpin(obj);
1046         } else {
1047                 ret = i915_gem_object_get_pages_or_evict(obj);
1048                 if (ret)
1049                         goto out;
1050
1051                 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1052                 if (ret)
1053                         goto out_put;
1054
1055                 ret = -EFAULT;
1056                 if (!i915_gem_object_needs_bit17_swizzle(obj))
1057                         ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1058                 if (ret == -EFAULT)
1059                         ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
1060
1061 out_put:
1062                 i915_gem_object_put_pages(obj);
1063         }
1064
1065 out:
1066         drm_gem_object_unreference(obj);
1067 unlock:
1068         mutex_unlock(&dev->struct_mutex);
1069         return ret;
1070 }
1071
1072 /**
1073  * Called when user space prepares to use an object with the CPU, either
1074  * through the mmap ioctl's mapping or a GTT mapping.
1075  */
1076 int
1077 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1078                           struct drm_file *file_priv)
1079 {
1080         struct drm_i915_private *dev_priv = dev->dev_private;
1081         struct drm_i915_gem_set_domain *args = data;
1082         struct drm_gem_object *obj;
1083         struct drm_i915_gem_object *obj_priv;
1084         uint32_t read_domains = args->read_domains;
1085         uint32_t write_domain = args->write_domain;
1086         int ret;
1087
1088         if (!(dev->driver->driver_features & DRIVER_GEM))
1089                 return -ENODEV;
1090
1091         /* Only handle setting domains to types used by the CPU. */
1092         if (write_domain & I915_GEM_GPU_DOMAINS)
1093                 return -EINVAL;
1094
1095         if (read_domains & I915_GEM_GPU_DOMAINS)
1096                 return -EINVAL;
1097
1098         /* Having something in the write domain implies it's in the read
1099          * domain, and only that read domain.  Enforce that in the request.
1100          */
1101         if (write_domain != 0 && read_domains != write_domain)
1102                 return -EINVAL;
1103
1104         ret = i915_mutex_lock_interruptible(dev);
1105         if (ret)
1106                 return ret;
1107
1108         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1109         if (obj == NULL) {
1110                 ret = -ENOENT;
1111                 goto unlock;
1112         }
1113         obj_priv = to_intel_bo(obj);
1114
1115         intel_mark_busy(dev, obj);
1116
1117         if (read_domains & I915_GEM_DOMAIN_GTT) {
1118                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1119
1120                 /* Update the LRU on the fence for the CPU access that's
1121                  * about to occur.
1122                  */
1123                 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1124                         struct drm_i915_fence_reg *reg =
1125                                 &dev_priv->fence_regs[obj_priv->fence_reg];
1126                         list_move_tail(&reg->lru_list,
1127                                        &dev_priv->mm.fence_list);
1128                 }
1129
1130                 /* Silently promote "you're not bound, there was nothing to do"
1131                  * to success, since the client was just asking us to
1132                  * make sure everything was done.
1133                  */
1134                 if (ret == -EINVAL)
1135                         ret = 0;
1136         } else {
1137                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1138         }
1139
1140         /* Maintain LRU order of "inactive" objects */
1141         if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1142                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1143
1144         drm_gem_object_unreference(obj);
1145 unlock:
1146         mutex_unlock(&dev->struct_mutex);
1147         return ret;
1148 }
1149
1150 /**
1151  * Called when user space has done writes to this buffer
1152  */
1153 int
1154 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1155                       struct drm_file *file_priv)
1156 {
1157         struct drm_i915_gem_sw_finish *args = data;
1158         struct drm_gem_object *obj;
1159         int ret = 0;
1160
1161         if (!(dev->driver->driver_features & DRIVER_GEM))
1162                 return -ENODEV;
1163
1164         ret = i915_mutex_lock_interruptible(dev);
1165         if (ret)
1166                 return ret;
1167
1168         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1169         if (obj == NULL) {
1170                 ret = -ENOENT;
1171                 goto unlock;
1172         }
1173
1174         /* Pinned buffers may be scanout, so flush the cache */
1175         if (to_intel_bo(obj)->pin_count)
1176                 i915_gem_object_flush_cpu_write_domain(obj);
1177
1178         drm_gem_object_unreference(obj);
1179 unlock:
1180         mutex_unlock(&dev->struct_mutex);
1181         return ret;
1182 }
1183
1184 /**
1185  * Maps the contents of an object, returning the address it is mapped
1186  * into.
1187  *
1188  * While the mapping holds a reference on the contents of the object, it doesn't
1189  * imply a ref on the object itself.
1190  */
1191 int
1192 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1193                    struct drm_file *file_priv)
1194 {
1195         struct drm_i915_gem_mmap *args = data;
1196         struct drm_gem_object *obj;
1197         loff_t offset;
1198         unsigned long addr;
1199
1200         if (!(dev->driver->driver_features & DRIVER_GEM))
1201                 return -ENODEV;
1202
1203         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1204         if (obj == NULL)
1205                 return -ENOENT;
1206
1207         offset = args->offset;
1208
1209         down_write(&current->mm->mmap_sem);
1210         addr = do_mmap(obj->filp, 0, args->size,
1211                        PROT_READ | PROT_WRITE, MAP_SHARED,
1212                        args->offset);
1213         up_write(&current->mm->mmap_sem);
1214         drm_gem_object_unreference_unlocked(obj);
1215         if (IS_ERR((void *)addr))
1216                 return addr;
1217
1218         args->addr_ptr = (uint64_t) addr;
1219
1220         return 0;
1221 }
1222
1223 /**
1224  * i915_gem_fault - fault a page into the GTT
1225  * vma: VMA in question
1226  * vmf: fault info
1227  *
1228  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1229  * from userspace.  The fault handler takes care of binding the object to
1230  * the GTT (if needed), allocating and programming a fence register (again,
1231  * only if needed based on whether the old reg is still valid or the object
1232  * is tiled) and inserting a new PTE into the faulting process.
1233  *
1234  * Note that the faulting process may involve evicting existing objects
1235  * from the GTT and/or fence registers to make room.  So performance may
1236  * suffer if the GTT working set is large or there are few fence registers
1237  * left.
1238  */
1239 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1240 {
1241         struct drm_gem_object *obj = vma->vm_private_data;
1242         struct drm_device *dev = obj->dev;
1243         drm_i915_private_t *dev_priv = dev->dev_private;
1244         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1245         pgoff_t page_offset;
1246         unsigned long pfn;
1247         int ret = 0;
1248         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1249
1250         /* We don't use vmf->pgoff since that has the fake offset */
1251         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1252                 PAGE_SHIFT;
1253
1254         /* Now bind it into the GTT if needed */
1255         mutex_lock(&dev->struct_mutex);
1256         if (!obj_priv->gtt_space) {
1257                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1258                 if (ret)
1259                         goto unlock;
1260
1261                 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1262                 if (ret)
1263                         goto unlock;
1264         }
1265
1266         /* Need a new fence register? */
1267         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1268                 ret = i915_gem_object_get_fence_reg(obj, true);
1269                 if (ret)
1270                         goto unlock;
1271         }
1272
1273         if (i915_gem_object_is_inactive(obj_priv))
1274                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1275
1276         pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1277                 page_offset;
1278
1279         /* Finally, remap it using the new GTT offset */
1280         ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1281 unlock:
1282         mutex_unlock(&dev->struct_mutex);
1283
1284         switch (ret) {
1285         case 0:
1286         case -ERESTARTSYS:
1287                 return VM_FAULT_NOPAGE;
1288         case -ENOMEM:
1289         case -EAGAIN:
1290                 return VM_FAULT_OOM;
1291         default:
1292                 return VM_FAULT_SIGBUS;
1293         }
1294 }
1295
1296 /**
1297  * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1298  * @obj: obj in question
1299  *
1300  * GEM memory mapping works by handing back to userspace a fake mmap offset
1301  * it can use in a subsequent mmap(2) call.  The DRM core code then looks
1302  * up the object based on the offset and sets up the various memory mapping
1303  * structures.
1304  *
1305  * This routine allocates and attaches a fake offset for @obj.
1306  */
1307 static int
1308 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1309 {
1310         struct drm_device *dev = obj->dev;
1311         struct drm_gem_mm *mm = dev->mm_private;
1312         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1313         struct drm_map_list *list;
1314         struct drm_local_map *map;
1315         int ret = 0;
1316
1317         /* Set the object up for mmap'ing */
1318         list = &obj->map_list;
1319         list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1320         if (!list->map)
1321                 return -ENOMEM;
1322
1323         map = list->map;
1324         map->type = _DRM_GEM;
1325         map->size = obj->size;
1326         map->handle = obj;
1327
1328         /* Get a DRM GEM mmap offset allocated... */
1329         list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1330                                                     obj->size / PAGE_SIZE, 0, 0);
1331         if (!list->file_offset_node) {
1332                 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1333                 ret = -ENOSPC;
1334                 goto out_free_list;
1335         }
1336
1337         list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1338                                                   obj->size / PAGE_SIZE, 0);
1339         if (!list->file_offset_node) {
1340                 ret = -ENOMEM;
1341                 goto out_free_list;
1342         }
1343
1344         list->hash.key = list->file_offset_node->start;
1345         ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1346         if (ret) {
1347                 DRM_ERROR("failed to add to map hash\n");
1348                 goto out_free_mm;
1349         }
1350
1351         /* By now we should be all set, any drm_mmap request on the offset
1352          * below will get to our mmap & fault handler */
1353         obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1354
1355         return 0;
1356
1357 out_free_mm:
1358         drm_mm_put_block(list->file_offset_node);
1359 out_free_list:
1360         kfree(list->map);
1361
1362         return ret;
1363 }
1364
1365 /**
1366  * i915_gem_release_mmap - remove physical page mappings
1367  * @obj: obj in question
1368  *
1369  * Preserve the reservation of the mmapping with the DRM core code, but
1370  * relinquish ownership of the pages back to the system.
1371  *
1372  * It is vital that we remove the page mapping if we have mapped a tiled
1373  * object through the GTT and then lose the fence register due to
1374  * resource pressure. Similarly if the object has been moved out of the
1375  * aperture, than pages mapped into userspace must be revoked. Removing the
1376  * mapping will then trigger a page fault on the next user access, allowing
1377  * fixup by i915_gem_fault().
1378  */
1379 void
1380 i915_gem_release_mmap(struct drm_gem_object *obj)
1381 {
1382         struct drm_device *dev = obj->dev;
1383         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1384
1385         if (dev->dev_mapping)
1386                 unmap_mapping_range(dev->dev_mapping,
1387                                     obj_priv->mmap_offset, obj->size, 1);
1388 }
1389
1390 static void
1391 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1392 {
1393         struct drm_device *dev = obj->dev;
1394         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1395         struct drm_gem_mm *mm = dev->mm_private;
1396         struct drm_map_list *list;
1397
1398         list = &obj->map_list;
1399         drm_ht_remove_item(&mm->offset_hash, &list->hash);
1400
1401         if (list->file_offset_node) {
1402                 drm_mm_put_block(list->file_offset_node);
1403                 list->file_offset_node = NULL;
1404         }
1405
1406         if (list->map) {
1407                 kfree(list->map);
1408                 list->map = NULL;
1409         }
1410
1411         obj_priv->mmap_offset = 0;
1412 }
1413
1414 /**
1415  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1416  * @obj: object to check
1417  *
1418  * Return the required GTT alignment for an object, taking into account
1419  * potential fence register mapping if needed.
1420  */
1421 static uint32_t
1422 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1423 {
1424         struct drm_device *dev = obj->dev;
1425         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1426         int start, i;
1427
1428         /*
1429          * Minimum alignment is 4k (GTT page size), but might be greater
1430          * if a fence register is needed for the object.
1431          */
1432         if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)
1433                 return 4096;
1434
1435         /*
1436          * Previous chips need to be aligned to the size of the smallest
1437          * fence register that can contain the object.
1438          */
1439         if (INTEL_INFO(dev)->gen == 3)
1440                 start = 1024*1024;
1441         else
1442                 start = 512*1024;
1443
1444         for (i = start; i < obj->size; i <<= 1)
1445                 ;
1446
1447         return i;
1448 }
1449
1450 /**
1451  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1452  * @dev: DRM device
1453  * @data: GTT mapping ioctl data
1454  * @file_priv: GEM object info
1455  *
1456  * Simply returns the fake offset to userspace so it can mmap it.
1457  * The mmap call will end up in drm_gem_mmap(), which will set things
1458  * up so we can get faults in the handler above.
1459  *
1460  * The fault handler will take care of binding the object into the GTT
1461  * (since it may have been evicted to make room for something), allocating
1462  * a fence register, and mapping the appropriate aperture address into
1463  * userspace.
1464  */
1465 int
1466 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1467                         struct drm_file *file_priv)
1468 {
1469         struct drm_i915_gem_mmap_gtt *args = data;
1470         struct drm_gem_object *obj;
1471         struct drm_i915_gem_object *obj_priv;
1472         int ret;
1473
1474         if (!(dev->driver->driver_features & DRIVER_GEM))
1475                 return -ENODEV;
1476
1477         ret = i915_mutex_lock_interruptible(dev);
1478         if (ret)
1479                 return ret;
1480
1481         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1482         if (obj == NULL) {
1483                 ret = -ENOENT;
1484                 goto unlock;
1485         }
1486         obj_priv = to_intel_bo(obj);
1487
1488         if (obj_priv->madv != I915_MADV_WILLNEED) {
1489                 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1490                 ret = -EINVAL;
1491                 goto out;
1492         }
1493
1494         if (!obj_priv->mmap_offset) {
1495                 ret = i915_gem_create_mmap_offset(obj);
1496                 if (ret)
1497                         goto out;
1498         }
1499
1500         args->offset = obj_priv->mmap_offset;
1501
1502         /*
1503          * Pull it into the GTT so that we have a page list (makes the
1504          * initial fault faster and any subsequent flushing possible).
1505          */
1506         if (!obj_priv->agp_mem) {
1507                 ret = i915_gem_object_bind_to_gtt(obj, 0);
1508                 if (ret)
1509                         goto out;
1510         }
1511
1512 out:
1513         drm_gem_object_unreference(obj);
1514 unlock:
1515         mutex_unlock(&dev->struct_mutex);
1516         return ret;
1517 }
1518
1519 static void
1520 i915_gem_object_put_pages(struct drm_gem_object *obj)
1521 {
1522         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1523         int page_count = obj->size / PAGE_SIZE;
1524         int i;
1525
1526         BUG_ON(obj_priv->pages_refcount == 0);
1527         BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1528
1529         if (--obj_priv->pages_refcount != 0)
1530                 return;
1531
1532         if (obj_priv->tiling_mode != I915_TILING_NONE)
1533                 i915_gem_object_save_bit_17_swizzle(obj);
1534
1535         if (obj_priv->madv == I915_MADV_DONTNEED)
1536                 obj_priv->dirty = 0;
1537
1538         for (i = 0; i < page_count; i++) {
1539                 if (obj_priv->dirty)
1540                         set_page_dirty(obj_priv->pages[i]);
1541
1542                 if (obj_priv->madv == I915_MADV_WILLNEED)
1543                         mark_page_accessed(obj_priv->pages[i]);
1544
1545                 page_cache_release(obj_priv->pages[i]);
1546         }
1547         obj_priv->dirty = 0;
1548
1549         drm_free_large(obj_priv->pages);
1550         obj_priv->pages = NULL;
1551 }
1552
1553 static uint32_t
1554 i915_gem_next_request_seqno(struct drm_device *dev,
1555                             struct intel_ring_buffer *ring)
1556 {
1557         drm_i915_private_t *dev_priv = dev->dev_private;
1558
1559         ring->outstanding_lazy_request = true;
1560         return dev_priv->next_seqno;
1561 }
1562
1563 static void
1564 i915_gem_object_move_to_active(struct drm_gem_object *obj,
1565                                struct intel_ring_buffer *ring)
1566 {
1567         struct drm_device *dev = obj->dev;
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1570         uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
1571
1572         BUG_ON(ring == NULL);
1573         obj_priv->ring = ring;
1574
1575         /* Add a reference if we're newly entering the active list. */
1576         if (!obj_priv->active) {
1577                 drm_gem_object_reference(obj);
1578                 obj_priv->active = 1;
1579         }
1580
1581         /* Move from whatever list we were on to the tail of execution. */
1582         list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list);
1583         list_move_tail(&obj_priv->ring_list, &ring->active_list);
1584         obj_priv->last_rendering_seqno = seqno;
1585 }
1586
1587 static void
1588 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1589 {
1590         struct drm_device *dev = obj->dev;
1591         drm_i915_private_t *dev_priv = dev->dev_private;
1592         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1593
1594         BUG_ON(!obj_priv->active);
1595         list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list);
1596         list_del_init(&obj_priv->ring_list);
1597         obj_priv->last_rendering_seqno = 0;
1598 }
1599
1600 /* Immediately discard the backing storage */
1601 static void
1602 i915_gem_object_truncate(struct drm_gem_object *obj)
1603 {
1604         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1605         struct inode *inode;
1606
1607         /* Our goal here is to return as much of the memory as
1608          * is possible back to the system as we are called from OOM.
1609          * To do this we must instruct the shmfs to drop all of its
1610          * backing pages, *now*. Here we mirror the actions taken
1611          * when by shmem_delete_inode() to release the backing store.
1612          */
1613         inode = obj->filp->f_path.dentry->d_inode;
1614         truncate_inode_pages(inode->i_mapping, 0);
1615         if (inode->i_op->truncate_range)
1616                 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1617
1618         obj_priv->madv = __I915_MADV_PURGED;
1619 }
1620
1621 static inline int
1622 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1623 {
1624         return obj_priv->madv == I915_MADV_DONTNEED;
1625 }
1626
1627 static void
1628 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1629 {
1630         struct drm_device *dev = obj->dev;
1631         drm_i915_private_t *dev_priv = dev->dev_private;
1632         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1633
1634         if (obj_priv->pin_count != 0)
1635                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list);
1636         else
1637                 list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
1638         list_del_init(&obj_priv->ring_list);
1639
1640         BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1641
1642         obj_priv->last_rendering_seqno = 0;
1643         obj_priv->ring = NULL;
1644         if (obj_priv->active) {
1645                 obj_priv->active = 0;
1646                 drm_gem_object_unreference(obj);
1647         }
1648         WARN_ON(i915_verify_lists(dev));
1649 }
1650
1651 static void
1652 i915_gem_process_flushing_list(struct drm_device *dev,
1653                                uint32_t flush_domains,
1654                                struct intel_ring_buffer *ring)
1655 {
1656         drm_i915_private_t *dev_priv = dev->dev_private;
1657         struct drm_i915_gem_object *obj_priv, *next;
1658
1659         list_for_each_entry_safe(obj_priv, next,
1660                                  &ring->gpu_write_list,
1661                                  gpu_write_list) {
1662                 struct drm_gem_object *obj = &obj_priv->base;
1663
1664                 if (obj->write_domain & flush_domains) {
1665                         uint32_t old_write_domain = obj->write_domain;
1666
1667                         obj->write_domain = 0;
1668                         list_del_init(&obj_priv->gpu_write_list);
1669                         i915_gem_object_move_to_active(obj, ring);
1670
1671                         /* update the fence lru list */
1672                         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1673                                 struct drm_i915_fence_reg *reg =
1674                                         &dev_priv->fence_regs[obj_priv->fence_reg];
1675                                 list_move_tail(&reg->lru_list,
1676                                                 &dev_priv->mm.fence_list);
1677                         }
1678
1679                         trace_i915_gem_object_change_domain(obj,
1680                                                             obj->read_domains,
1681                                                             old_write_domain);
1682                 }
1683         }
1684 }
1685
1686 int
1687 i915_add_request(struct drm_device *dev,
1688                  struct drm_file *file,
1689                  struct drm_i915_gem_request *request,
1690                  struct intel_ring_buffer *ring)
1691 {
1692         drm_i915_private_t *dev_priv = dev->dev_private;
1693         struct drm_i915_file_private *file_priv = NULL;
1694         uint32_t seqno;
1695         int was_empty;
1696         int ret;
1697
1698         BUG_ON(request == NULL);
1699
1700         if (file != NULL)
1701                 file_priv = file->driver_priv;
1702
1703         ret = ring->add_request(ring, &seqno);
1704         if (ret)
1705             return ret;
1706
1707         ring->outstanding_lazy_request = false;
1708
1709         request->seqno = seqno;
1710         request->ring = ring;
1711         request->emitted_jiffies = jiffies;
1712         was_empty = list_empty(&ring->request_list);
1713         list_add_tail(&request->list, &ring->request_list);
1714
1715         if (file_priv) {
1716                 spin_lock(&file_priv->mm.lock);
1717                 request->file_priv = file_priv;
1718                 list_add_tail(&request->client_list,
1719                               &file_priv->mm.request_list);
1720                 spin_unlock(&file_priv->mm.lock);
1721         }
1722
1723         if (!dev_priv->mm.suspended) {
1724                 mod_timer(&dev_priv->hangcheck_timer,
1725                           jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1726                 if (was_empty)
1727                         queue_delayed_work(dev_priv->wq,
1728                                            &dev_priv->mm.retire_work, HZ);
1729         }
1730         return 0;
1731 }
1732
1733 /**
1734  * Command execution barrier
1735  *
1736  * Ensures that all commands in the ring are finished
1737  * before signalling the CPU
1738  */
1739 static void
1740 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1741 {
1742         uint32_t flush_domains = 0;
1743
1744         /* The sampler always gets flushed on i965 (sigh) */
1745         if (INTEL_INFO(dev)->gen >= 4)
1746                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1747
1748         ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains);
1749 }
1750
1751 static inline void
1752 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1753 {
1754         struct drm_i915_file_private *file_priv = request->file_priv;
1755
1756         if (!file_priv)
1757                 return;
1758
1759         spin_lock(&file_priv->mm.lock);
1760         list_del(&request->client_list);
1761         request->file_priv = NULL;
1762         spin_unlock(&file_priv->mm.lock);
1763 }
1764
1765 static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1766                                       struct intel_ring_buffer *ring)
1767 {
1768         while (!list_empty(&ring->request_list)) {
1769                 struct drm_i915_gem_request *request;
1770
1771                 request = list_first_entry(&ring->request_list,
1772                                            struct drm_i915_gem_request,
1773                                            list);
1774
1775                 list_del(&request->list);
1776                 i915_gem_request_remove_from_client(request);
1777                 kfree(request);
1778         }
1779
1780         while (!list_empty(&ring->active_list)) {
1781                 struct drm_i915_gem_object *obj_priv;
1782
1783                 obj_priv = list_first_entry(&ring->active_list,
1784                                             struct drm_i915_gem_object,
1785                                             ring_list);
1786
1787                 obj_priv->base.write_domain = 0;
1788                 list_del_init(&obj_priv->gpu_write_list);
1789                 i915_gem_object_move_to_inactive(&obj_priv->base);
1790         }
1791 }
1792
1793 void i915_gem_reset(struct drm_device *dev)
1794 {
1795         struct drm_i915_private *dev_priv = dev->dev_private;
1796         struct drm_i915_gem_object *obj_priv;
1797         int i;
1798
1799         i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1800         i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
1801         i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring);
1802
1803         /* Remove anything from the flushing lists. The GPU cache is likely
1804          * to be lost on reset along with the data, so simply move the
1805          * lost bo to the inactive list.
1806          */
1807         while (!list_empty(&dev_priv->mm.flushing_list)) {
1808                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1809                                             struct drm_i915_gem_object,
1810                                             mm_list);
1811
1812                 obj_priv->base.write_domain = 0;
1813                 list_del_init(&obj_priv->gpu_write_list);
1814                 i915_gem_object_move_to_inactive(&obj_priv->base);
1815         }
1816
1817         /* Move everything out of the GPU domains to ensure we do any
1818          * necessary invalidation upon reuse.
1819          */
1820         list_for_each_entry(obj_priv,
1821                             &dev_priv->mm.inactive_list,
1822                             mm_list)
1823         {
1824                 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1825         }
1826
1827         /* The fence registers are invalidated so clear them out */
1828         for (i = 0; i < 16; i++) {
1829                 struct drm_i915_fence_reg *reg;
1830
1831                 reg = &dev_priv->fence_regs[i];
1832                 if (!reg->obj)
1833                         continue;
1834
1835                 i915_gem_clear_fence_reg(reg->obj);
1836         }
1837 }
1838
1839 /**
1840  * This function clears the request list as sequence numbers are passed.
1841  */
1842 static void
1843 i915_gem_retire_requests_ring(struct drm_device *dev,
1844                               struct intel_ring_buffer *ring)
1845 {
1846         drm_i915_private_t *dev_priv = dev->dev_private;
1847         uint32_t seqno;
1848
1849         if (!ring->status_page.page_addr ||
1850             list_empty(&ring->request_list))
1851                 return;
1852
1853         WARN_ON(i915_verify_lists(dev));
1854
1855         seqno = ring->get_seqno(ring);
1856         while (!list_empty(&ring->request_list)) {
1857                 struct drm_i915_gem_request *request;
1858
1859                 request = list_first_entry(&ring->request_list,
1860                                            struct drm_i915_gem_request,
1861                                            list);
1862
1863                 if (!i915_seqno_passed(seqno, request->seqno))
1864                         break;
1865
1866                 trace_i915_gem_request_retire(dev, request->seqno);
1867
1868                 list_del(&request->list);
1869                 i915_gem_request_remove_from_client(request);
1870                 kfree(request);
1871         }
1872
1873         /* Move any buffers on the active list that are no longer referenced
1874          * by the ringbuffer to the flushing/inactive lists as appropriate.
1875          */
1876         while (!list_empty(&ring->active_list)) {
1877                 struct drm_gem_object *obj;
1878                 struct drm_i915_gem_object *obj_priv;
1879
1880                 obj_priv = list_first_entry(&ring->active_list,
1881                                             struct drm_i915_gem_object,
1882                                             ring_list);
1883
1884                 if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
1885                         break;
1886
1887                 obj = &obj_priv->base;
1888                 if (obj->write_domain != 0)
1889                         i915_gem_object_move_to_flushing(obj);
1890                 else
1891                         i915_gem_object_move_to_inactive(obj);
1892         }
1893
1894         if (unlikely (dev_priv->trace_irq_seqno &&
1895                       i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1896                 ring->user_irq_put(ring);
1897                 dev_priv->trace_irq_seqno = 0;
1898         }
1899
1900         WARN_ON(i915_verify_lists(dev));
1901 }
1902
1903 void
1904 i915_gem_retire_requests(struct drm_device *dev)
1905 {
1906         drm_i915_private_t *dev_priv = dev->dev_private;
1907
1908         if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1909             struct drm_i915_gem_object *obj_priv, *tmp;
1910
1911             /* We must be careful that during unbind() we do not
1912              * accidentally infinitely recurse into retire requests.
1913              * Currently:
1914              *   retire -> free -> unbind -> wait -> retire_ring
1915              */
1916             list_for_each_entry_safe(obj_priv, tmp,
1917                                      &dev_priv->mm.deferred_free_list,
1918                                      mm_list)
1919                     i915_gem_free_object_tail(&obj_priv->base);
1920         }
1921
1922         i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1923         i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1924         i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring);
1925 }
1926
1927 static void
1928 i915_gem_retire_work_handler(struct work_struct *work)
1929 {
1930         drm_i915_private_t *dev_priv;
1931         struct drm_device *dev;
1932
1933         dev_priv = container_of(work, drm_i915_private_t,
1934                                 mm.retire_work.work);
1935         dev = dev_priv->dev;
1936
1937         /* Come back later if the device is busy... */
1938         if (!mutex_trylock(&dev->struct_mutex)) {
1939                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1940                 return;
1941         }
1942
1943         i915_gem_retire_requests(dev);
1944
1945         if (!dev_priv->mm.suspended &&
1946                 (!list_empty(&dev_priv->render_ring.request_list) ||
1947                  !list_empty(&dev_priv->bsd_ring.request_list) ||
1948                  !list_empty(&dev_priv->blt_ring.request_list)))
1949                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1950         mutex_unlock(&dev->struct_mutex);
1951 }
1952
1953 int
1954 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1955                      bool interruptible, struct intel_ring_buffer *ring)
1956 {
1957         drm_i915_private_t *dev_priv = dev->dev_private;
1958         u32 ier;
1959         int ret = 0;
1960
1961         BUG_ON(seqno == 0);
1962
1963         if (atomic_read(&dev_priv->mm.wedged))
1964                 return -EAGAIN;
1965
1966         if (ring->outstanding_lazy_request) {
1967                 struct drm_i915_gem_request *request;
1968
1969                 request = kzalloc(sizeof(*request), GFP_KERNEL);
1970                 if (request == NULL)
1971                         return -ENOMEM;
1972
1973                 ret = i915_add_request(dev, NULL, request, ring);
1974                 if (ret) {
1975                         kfree(request);
1976                         return ret;
1977                 }
1978
1979                 seqno = request->seqno;
1980         }
1981         BUG_ON(seqno == dev_priv->next_seqno);
1982
1983         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
1984                 if (HAS_PCH_SPLIT(dev))
1985                         ier = I915_READ(DEIER) | I915_READ(GTIER);
1986                 else
1987                         ier = I915_READ(IER);
1988                 if (!ier) {
1989                         DRM_ERROR("something (likely vbetool) disabled "
1990                                   "interrupts, re-enabling\n");
1991                         i915_driver_irq_preinstall(dev);
1992                         i915_driver_irq_postinstall(dev);
1993                 }
1994
1995                 trace_i915_gem_request_wait_begin(dev, seqno);
1996
1997                 ring->waiting_seqno = seqno;
1998                 ring->user_irq_get(ring);
1999                 if (interruptible)
2000                         ret = wait_event_interruptible(ring->irq_queue,
2001                                 i915_seqno_passed(ring->get_seqno(ring), seqno)
2002                                 || atomic_read(&dev_priv->mm.wedged));
2003                 else
2004                         wait_event(ring->irq_queue,
2005                                 i915_seqno_passed(ring->get_seqno(ring), seqno)
2006                                 || atomic_read(&dev_priv->mm.wedged));
2007
2008                 ring->user_irq_put(ring);
2009                 ring->waiting_seqno = 0;
2010
2011                 trace_i915_gem_request_wait_end(dev, seqno);
2012         }
2013         if (atomic_read(&dev_priv->mm.wedged))
2014                 ret = -EAGAIN;
2015
2016         if (ret && ret != -ERESTARTSYS)
2017                 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2018                           __func__, ret, seqno, ring->get_seqno(ring),
2019                           dev_priv->next_seqno);
2020
2021         /* Directly dispatch request retiring.  While we have the work queue
2022          * to handle this, the waiter on a request often wants an associated
2023          * buffer to have made it to the inactive list, and we would need
2024          * a separate wait queue to handle that.
2025          */
2026         if (ret == 0)
2027                 i915_gem_retire_requests_ring(dev, ring);
2028
2029         return ret;
2030 }
2031
2032 /**
2033  * Waits for a sequence number to be signaled, and cleans up the
2034  * request and object lists appropriately for that event.
2035  */
2036 static int
2037 i915_wait_request(struct drm_device *dev, uint32_t seqno,
2038                   struct intel_ring_buffer *ring)
2039 {
2040         return i915_do_wait_request(dev, seqno, 1, ring);
2041 }
2042
2043 static void
2044 i915_gem_flush_ring(struct drm_device *dev,
2045                     struct drm_file *file_priv,
2046                     struct intel_ring_buffer *ring,
2047                     uint32_t invalidate_domains,
2048                     uint32_t flush_domains)
2049 {
2050         ring->flush(ring, invalidate_domains, flush_domains);
2051         i915_gem_process_flushing_list(dev, flush_domains, ring);
2052 }
2053
2054 static void
2055 i915_gem_flush(struct drm_device *dev,
2056                struct drm_file *file_priv,
2057                uint32_t invalidate_domains,
2058                uint32_t flush_domains,
2059                uint32_t flush_rings)
2060 {
2061         drm_i915_private_t *dev_priv = dev->dev_private;
2062
2063         if (flush_domains & I915_GEM_DOMAIN_CPU)
2064                 drm_agp_chipset_flush(dev);
2065
2066         if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
2067                 if (flush_rings & RING_RENDER)
2068                         i915_gem_flush_ring(dev, file_priv,
2069                                             &dev_priv->render_ring,
2070                                             invalidate_domains, flush_domains);
2071                 if (flush_rings & RING_BSD)
2072                         i915_gem_flush_ring(dev, file_priv,
2073                                             &dev_priv->bsd_ring,
2074                                             invalidate_domains, flush_domains);
2075                 if (flush_rings & RING_BLT)
2076                         i915_gem_flush_ring(dev, file_priv,
2077                                             &dev_priv->blt_ring,
2078                                             invalidate_domains, flush_domains);
2079         }
2080 }
2081
2082 /**
2083  * Ensures that all rendering to the object has completed and the object is
2084  * safe to unbind from the GTT or access from the CPU.
2085  */
2086 static int
2087 i915_gem_object_wait_rendering(struct drm_gem_object *obj,
2088                                bool interruptible)
2089 {
2090         struct drm_device *dev = obj->dev;
2091         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2092         int ret;
2093
2094         /* This function only exists to support waiting for existing rendering,
2095          * not for emitting required flushes.
2096          */
2097         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
2098
2099         /* If there is rendering queued on the buffer being evicted, wait for
2100          * it.
2101          */
2102         if (obj_priv->active) {
2103                 ret = i915_do_wait_request(dev,
2104                                            obj_priv->last_rendering_seqno,
2105                                            interruptible,
2106                                            obj_priv->ring);
2107                 if (ret)
2108                         return ret;
2109         }
2110
2111         return 0;
2112 }
2113
2114 /**
2115  * Unbinds an object from the GTT aperture.
2116  */
2117 int
2118 i915_gem_object_unbind(struct drm_gem_object *obj)
2119 {
2120         struct drm_device *dev = obj->dev;
2121         struct drm_i915_private *dev_priv = dev->dev_private;
2122         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2123         int ret = 0;
2124
2125         if (obj_priv->gtt_space == NULL)
2126                 return 0;
2127
2128         if (obj_priv->pin_count != 0) {
2129                 DRM_ERROR("Attempting to unbind pinned buffer\n");
2130                 return -EINVAL;
2131         }
2132
2133         /* blow away mappings if mapped through GTT */
2134         i915_gem_release_mmap(obj);
2135
2136         /* Move the object to the CPU domain to ensure that
2137          * any possible CPU writes while it's not in the GTT
2138          * are flushed when we go to remap it. This will
2139          * also ensure that all pending GPU writes are finished
2140          * before we unbind.
2141          */
2142         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2143         if (ret == -ERESTARTSYS)
2144                 return ret;
2145         /* Continue on if we fail due to EIO, the GPU is hung so we
2146          * should be safe and we need to cleanup or else we might
2147          * cause memory corruption through use-after-free.
2148          */
2149         if (ret) {
2150                 i915_gem_clflush_object(obj);
2151                 obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU;
2152         }
2153
2154         /* release the fence reg _after_ flushing */
2155         if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2156                 i915_gem_clear_fence_reg(obj);
2157
2158         drm_unbind_agp(obj_priv->agp_mem);
2159         drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2160
2161         i915_gem_object_put_pages(obj);
2162         BUG_ON(obj_priv->pages_refcount);
2163
2164         i915_gem_info_remove_gtt(dev_priv, obj->size);
2165         list_del_init(&obj_priv->mm_list);
2166
2167         drm_mm_put_block(obj_priv->gtt_space);
2168         obj_priv->gtt_space = NULL;
2169         obj_priv->gtt_offset = 0;
2170
2171         if (i915_gem_object_is_purgeable(obj_priv))
2172                 i915_gem_object_truncate(obj);
2173
2174         trace_i915_gem_object_unbind(obj);
2175
2176         return ret;
2177 }
2178
2179 static int i915_ring_idle(struct drm_device *dev,
2180                           struct intel_ring_buffer *ring)
2181 {
2182         if (list_empty(&ring->gpu_write_list))
2183                 return 0;
2184
2185         i915_gem_flush_ring(dev, NULL, ring,
2186                             I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2187         return i915_wait_request(dev,
2188                                  i915_gem_next_request_seqno(dev, ring),
2189                                  ring);
2190 }
2191
2192 int
2193 i915_gpu_idle(struct drm_device *dev)
2194 {
2195         drm_i915_private_t *dev_priv = dev->dev_private;
2196         bool lists_empty;
2197         int ret;
2198
2199         lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2200                        list_empty(&dev_priv->render_ring.active_list) &&
2201                        list_empty(&dev_priv->bsd_ring.active_list) &&
2202                        list_empty(&dev_priv->blt_ring.active_list));
2203         if (lists_empty)
2204                 return 0;
2205
2206         /* Flush everything onto the inactive list. */
2207         ret = i915_ring_idle(dev, &dev_priv->render_ring);
2208         if (ret)
2209                 return ret;
2210
2211         ret = i915_ring_idle(dev, &dev_priv->bsd_ring);
2212         if (ret)
2213                 return ret;
2214
2215         ret = i915_ring_idle(dev, &dev_priv->blt_ring);
2216         if (ret)
2217                 return ret;
2218
2219         return 0;
2220 }
2221
2222 static int
2223 i915_gem_object_get_pages(struct drm_gem_object *obj,
2224                           gfp_t gfpmask)
2225 {
2226         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2227         int page_count, i;
2228         struct address_space *mapping;
2229         struct inode *inode;
2230         struct page *page;
2231
2232         BUG_ON(obj_priv->pages_refcount
2233                         == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2234
2235         if (obj_priv->pages_refcount++ != 0)
2236                 return 0;
2237
2238         /* Get the list of pages out of our struct file.  They'll be pinned
2239          * at this point until we release them.
2240          */
2241         page_count = obj->size / PAGE_SIZE;
2242         BUG_ON(obj_priv->pages != NULL);
2243         obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2244         if (obj_priv->pages == NULL) {
2245                 obj_priv->pages_refcount--;
2246                 return -ENOMEM;
2247         }
2248
2249         inode = obj->filp->f_path.dentry->d_inode;
2250         mapping = inode->i_mapping;
2251         for (i = 0; i < page_count; i++) {
2252                 page = read_cache_page_gfp(mapping, i,
2253                                            GFP_HIGHUSER |
2254                                            __GFP_COLD |
2255                                            __GFP_RECLAIMABLE |
2256                                            gfpmask);
2257                 if (IS_ERR(page))
2258                         goto err_pages;
2259
2260                 obj_priv->pages[i] = page;
2261         }
2262
2263         if (obj_priv->tiling_mode != I915_TILING_NONE)
2264                 i915_gem_object_do_bit_17_swizzle(obj);
2265
2266         return 0;
2267
2268 err_pages:
2269         while (i--)
2270                 page_cache_release(obj_priv->pages[i]);
2271
2272         drm_free_large(obj_priv->pages);
2273         obj_priv->pages = NULL;
2274         obj_priv->pages_refcount--;
2275         return PTR_ERR(page);
2276 }
2277
2278 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2279 {
2280         struct drm_gem_object *obj = reg->obj;
2281         struct drm_device *dev = obj->dev;
2282         drm_i915_private_t *dev_priv = dev->dev_private;
2283         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2284         int regnum = obj_priv->fence_reg;
2285         uint64_t val;
2286
2287         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2288                     0xfffff000) << 32;
2289         val |= obj_priv->gtt_offset & 0xfffff000;
2290         val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2291                 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2292
2293         if (obj_priv->tiling_mode == I915_TILING_Y)
2294                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2295         val |= I965_FENCE_REG_VALID;
2296
2297         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2298 }
2299
2300 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2301 {
2302         struct drm_gem_object *obj = reg->obj;
2303         struct drm_device *dev = obj->dev;
2304         drm_i915_private_t *dev_priv = dev->dev_private;
2305         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2306         int regnum = obj_priv->fence_reg;
2307         uint64_t val;
2308
2309         val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2310                     0xfffff000) << 32;
2311         val |= obj_priv->gtt_offset & 0xfffff000;
2312         val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2313         if (obj_priv->tiling_mode == I915_TILING_Y)
2314                 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2315         val |= I965_FENCE_REG_VALID;
2316
2317         I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2318 }
2319
2320 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2321 {
2322         struct drm_gem_object *obj = reg->obj;
2323         struct drm_device *dev = obj->dev;
2324         drm_i915_private_t *dev_priv = dev->dev_private;
2325         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2326         int regnum = obj_priv->fence_reg;
2327         int tile_width;
2328         uint32_t fence_reg, val;
2329         uint32_t pitch_val;
2330
2331         if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2332             (obj_priv->gtt_offset & (obj->size - 1))) {
2333                 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2334                      __func__, obj_priv->gtt_offset, obj->size);
2335                 return;
2336         }
2337
2338         if (obj_priv->tiling_mode == I915_TILING_Y &&
2339             HAS_128_BYTE_Y_TILING(dev))
2340                 tile_width = 128;
2341         else
2342                 tile_width = 512;
2343
2344         /* Note: pitch better be a power of two tile widths */
2345         pitch_val = obj_priv->stride / tile_width;
2346         pitch_val = ffs(pitch_val) - 1;
2347
2348         if (obj_priv->tiling_mode == I915_TILING_Y &&
2349             HAS_128_BYTE_Y_TILING(dev))
2350                 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2351         else
2352                 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2353
2354         val = obj_priv->gtt_offset;
2355         if (obj_priv->tiling_mode == I915_TILING_Y)
2356                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2357         val |= I915_FENCE_SIZE_BITS(obj->size);
2358         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2359         val |= I830_FENCE_REG_VALID;
2360
2361         if (regnum < 8)
2362                 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2363         else
2364                 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2365         I915_WRITE(fence_reg, val);
2366 }
2367
2368 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2369 {
2370         struct drm_gem_object *obj = reg->obj;
2371         struct drm_device *dev = obj->dev;
2372         drm_i915_private_t *dev_priv = dev->dev_private;
2373         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2374         int regnum = obj_priv->fence_reg;
2375         uint32_t val;
2376         uint32_t pitch_val;
2377         uint32_t fence_size_bits;
2378
2379         if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2380             (obj_priv->gtt_offset & (obj->size - 1))) {
2381                 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2382                      __func__, obj_priv->gtt_offset);
2383                 return;
2384         }
2385
2386         pitch_val = obj_priv->stride / 128;
2387         pitch_val = ffs(pitch_val) - 1;
2388         WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2389
2390         val = obj_priv->gtt_offset;
2391         if (obj_priv->tiling_mode == I915_TILING_Y)
2392                 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2393         fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2394         WARN_ON(fence_size_bits & ~0x00000f00);
2395         val |= fence_size_bits;
2396         val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2397         val |= I830_FENCE_REG_VALID;
2398
2399         I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2400 }
2401
2402 static int i915_find_fence_reg(struct drm_device *dev,
2403                                bool interruptible)
2404 {
2405         struct drm_i915_fence_reg *reg = NULL;
2406         struct drm_i915_gem_object *obj_priv = NULL;
2407         struct drm_i915_private *dev_priv = dev->dev_private;
2408         struct drm_gem_object *obj = NULL;
2409         int i, avail, ret;
2410
2411         /* First try to find a free reg */
2412         avail = 0;
2413         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2414                 reg = &dev_priv->fence_regs[i];
2415                 if (!reg->obj)
2416                         return i;
2417
2418                 obj_priv = to_intel_bo(reg->obj);
2419                 if (!obj_priv->pin_count)
2420                     avail++;
2421         }
2422
2423         if (avail == 0)
2424                 return -ENOSPC;
2425
2426         /* None available, try to steal one or wait for a user to finish */
2427         i = I915_FENCE_REG_NONE;
2428         list_for_each_entry(reg, &dev_priv->mm.fence_list,
2429                             lru_list) {
2430                 obj = reg->obj;
2431                 obj_priv = to_intel_bo(obj);
2432
2433                 if (obj_priv->pin_count)
2434                         continue;
2435
2436                 /* found one! */
2437                 i = obj_priv->fence_reg;
2438                 break;
2439         }
2440
2441         BUG_ON(i == I915_FENCE_REG_NONE);
2442
2443         /* We only have a reference on obj from the active list. put_fence_reg
2444          * might drop that one, causing a use-after-free in it. So hold a
2445          * private reference to obj like the other callers of put_fence_reg
2446          * (set_tiling ioctl) do. */
2447         drm_gem_object_reference(obj);
2448         ret = i915_gem_object_put_fence_reg(obj, interruptible);
2449         drm_gem_object_unreference(obj);
2450         if (ret != 0)
2451                 return ret;
2452
2453         return i;
2454 }
2455
2456 /**
2457  * i915_gem_object_get_fence_reg - set up a fence reg for an object
2458  * @obj: object to map through a fence reg
2459  *
2460  * When mapping objects through the GTT, userspace wants to be able to write
2461  * to them without having to worry about swizzling if the object is tiled.
2462  *
2463  * This function walks the fence regs looking for a free one for @obj,
2464  * stealing one if it can't find any.
2465  *
2466  * It then sets up the reg based on the object's properties: address, pitch
2467  * and tiling format.
2468  */
2469 int
2470 i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2471                               bool interruptible)
2472 {
2473         struct drm_device *dev = obj->dev;
2474         struct drm_i915_private *dev_priv = dev->dev_private;
2475         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2476         struct drm_i915_fence_reg *reg = NULL;
2477         int ret;
2478
2479         /* Just update our place in the LRU if our fence is getting used. */
2480         if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2481                 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2482                 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2483                 return 0;
2484         }
2485
2486         switch (obj_priv->tiling_mode) {
2487         case I915_TILING_NONE:
2488                 WARN(1, "allocating a fence for non-tiled object?\n");
2489                 break;
2490         case I915_TILING_X:
2491                 if (!obj_priv->stride)
2492                         return -EINVAL;
2493                 WARN((obj_priv->stride & (512 - 1)),
2494                      "object 0x%08x is X tiled but has non-512B pitch\n",
2495                      obj_priv->gtt_offset);
2496                 break;
2497         case I915_TILING_Y:
2498                 if (!obj_priv->stride)
2499                         return -EINVAL;
2500                 WARN((obj_priv->stride & (128 - 1)),
2501                      "object 0x%08x is Y tiled but has non-128B pitch\n",
2502                      obj_priv->gtt_offset);
2503                 break;
2504         }
2505
2506         ret = i915_find_fence_reg(dev, interruptible);
2507         if (ret < 0)
2508                 return ret;
2509
2510         obj_priv->fence_reg = ret;
2511         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2512         list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2513
2514         reg->obj = obj;
2515
2516         switch (INTEL_INFO(dev)->gen) {
2517         case 6:
2518                 sandybridge_write_fence_reg(reg);
2519                 break;
2520         case 5:
2521         case 4:
2522                 i965_write_fence_reg(reg);
2523                 break;
2524         case 3:
2525                 i915_write_fence_reg(reg);
2526                 break;
2527         case 2:
2528                 i830_write_fence_reg(reg);
2529                 break;
2530         }
2531
2532         trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2533                         obj_priv->tiling_mode);
2534
2535         return 0;
2536 }
2537
2538 /**
2539  * i915_gem_clear_fence_reg - clear out fence register info
2540  * @obj: object to clear
2541  *
2542  * Zeroes out the fence register itself and clears out the associated
2543  * data structures in dev_priv and obj_priv.
2544  */
2545 static void
2546 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2547 {
2548         struct drm_device *dev = obj->dev;
2549         drm_i915_private_t *dev_priv = dev->dev_private;
2550         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2551         struct drm_i915_fence_reg *reg =
2552                 &dev_priv->fence_regs[obj_priv->fence_reg];
2553         uint32_t fence_reg;
2554
2555         switch (INTEL_INFO(dev)->gen) {
2556         case 6:
2557                 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2558                              (obj_priv->fence_reg * 8), 0);
2559                 break;
2560         case 5:
2561         case 4:
2562                 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2563                 break;
2564         case 3:
2565                 if (obj_priv->fence_reg >= 8)
2566                         fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2567                 else
2568         case 2:
2569                         fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2570
2571                 I915_WRITE(fence_reg, 0);
2572                 break;
2573         }
2574
2575         reg->obj = NULL;
2576         obj_priv->fence_reg = I915_FENCE_REG_NONE;
2577         list_del_init(&reg->lru_list);
2578 }
2579
2580 /**
2581  * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2582  * to the buffer to finish, and then resets the fence register.
2583  * @obj: tiled object holding a fence register.
2584  * @bool: whether the wait upon the fence is interruptible
2585  *
2586  * Zeroes out the fence register itself and clears out the associated
2587  * data structures in dev_priv and obj_priv.
2588  */
2589 int
2590 i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2591                               bool interruptible)
2592 {
2593         struct drm_device *dev = obj->dev;
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2596         struct drm_i915_fence_reg *reg;
2597
2598         if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2599                 return 0;
2600
2601         /* If we've changed tiling, GTT-mappings of the object
2602          * need to re-fault to ensure that the correct fence register
2603          * setup is in place.
2604          */
2605         i915_gem_release_mmap(obj);
2606
2607         /* On the i915, GPU access to tiled buffers is via a fence,
2608          * therefore we must wait for any outstanding access to complete
2609          * before clearing the fence.
2610          */
2611         reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2612         if (reg->gpu) {
2613                 int ret;
2614
2615                 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2616                 if (ret)
2617                         return ret;
2618
2619                 ret = i915_gem_object_wait_rendering(obj, interruptible);
2620                 if (ret)
2621                         return ret;
2622
2623                 reg->gpu = false;
2624         }
2625
2626         i915_gem_object_flush_gtt_write_domain(obj);
2627         i915_gem_clear_fence_reg(obj);
2628
2629         return 0;
2630 }
2631
2632 /**
2633  * Finds free space in the GTT aperture and binds the object there.
2634  */
2635 static int
2636 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2637 {
2638         struct drm_device *dev = obj->dev;
2639         drm_i915_private_t *dev_priv = dev->dev_private;
2640         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2641         struct drm_mm_node *free_space;
2642         gfp_t gfpmask =  __GFP_NORETRY | __GFP_NOWARN;
2643         int ret;
2644
2645         if (obj_priv->madv != I915_MADV_WILLNEED) {
2646                 DRM_ERROR("Attempting to bind a purgeable object\n");
2647                 return -EINVAL;
2648         }
2649
2650         if (alignment == 0)
2651                 alignment = i915_gem_get_gtt_alignment(obj);
2652         if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2653                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2654                 return -EINVAL;
2655         }
2656
2657         /* If the object is bigger than the entire aperture, reject it early
2658          * before evicting everything in a vain attempt to find space.
2659          */
2660         if (obj->size > dev_priv->mm.gtt_total) {
2661                 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2662                 return -E2BIG;
2663         }
2664
2665  search_free:
2666         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2667                                         obj->size, alignment, 0);
2668         if (free_space != NULL)
2669                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2670                                                        alignment);
2671         if (obj_priv->gtt_space == NULL) {
2672                 /* If the gtt is empty and we're still having trouble
2673                  * fitting our object in, we're out of memory.
2674                  */
2675                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2676                 if (ret)
2677                         return ret;
2678
2679                 goto search_free;
2680         }
2681
2682         ret = i915_gem_object_get_pages(obj, gfpmask);
2683         if (ret) {
2684                 drm_mm_put_block(obj_priv->gtt_space);
2685                 obj_priv->gtt_space = NULL;
2686
2687                 if (ret == -ENOMEM) {
2688                         /* first try to clear up some space from the GTT */
2689                         ret = i915_gem_evict_something(dev, obj->size,
2690                                                        alignment);
2691                         if (ret) {
2692                                 /* now try to shrink everyone else */
2693                                 if (gfpmask) {
2694                                         gfpmask = 0;
2695                                         goto search_free;
2696                                 }
2697
2698                                 return ret;
2699                         }
2700
2701                         goto search_free;
2702                 }
2703
2704                 return ret;
2705         }
2706
2707         /* Create an AGP memory structure pointing at our pages, and bind it
2708          * into the GTT.
2709          */
2710         obj_priv->agp_mem = drm_agp_bind_pages(dev,
2711                                                obj_priv->pages,
2712                                                obj->size >> PAGE_SHIFT,
2713                                                obj_priv->gtt_space->start,
2714                                                obj_priv->agp_type);
2715         if (obj_priv->agp_mem == NULL) {
2716                 i915_gem_object_put_pages(obj);
2717                 drm_mm_put_block(obj_priv->gtt_space);
2718                 obj_priv->gtt_space = NULL;
2719
2720                 ret = i915_gem_evict_something(dev, obj->size, alignment);
2721                 if (ret)
2722                         return ret;
2723
2724                 goto search_free;
2725         }
2726
2727         /* keep track of bounds object by adding it to the inactive list */
2728         list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list);
2729         i915_gem_info_add_gtt(dev_priv, obj->size);
2730
2731         /* Assert that the object is not currently in any GPU domain. As it
2732          * wasn't in the GTT, there shouldn't be any way it could have been in
2733          * a GPU cache
2734          */
2735         BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2736         BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2737
2738         obj_priv->gtt_offset = obj_priv->gtt_space->start;
2739         trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2740
2741         return 0;
2742 }
2743
2744 void
2745 i915_gem_clflush_object(struct drm_gem_object *obj)
2746 {
2747         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
2748
2749         /* If we don't have a page list set up, then we're not pinned
2750          * to GPU, and we can ignore the cache flush because it'll happen
2751          * again at bind time.
2752          */
2753         if (obj_priv->pages == NULL)
2754                 return;
2755
2756         trace_i915_gem_object_clflush(obj);
2757
2758         drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2759 }
2760
2761 /** Flushes any GPU write domain for the object if it's dirty. */
2762 static int
2763 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2764                                        bool pipelined)
2765 {
2766         struct drm_device *dev = obj->dev;
2767         uint32_t old_write_domain;
2768
2769         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2770                 return 0;
2771
2772         /* Queue the GPU write cache flushing we need. */
2773         old_write_domain = obj->write_domain;
2774         i915_gem_flush_ring(dev, NULL,
2775                             to_intel_bo(obj)->ring,
2776                             0, obj->write_domain);
2777         BUG_ON(obj->write_domain);
2778
2779         trace_i915_gem_object_change_domain(obj,
2780                                             obj->read_domains,
2781                                             old_write_domain);
2782
2783         if (pipelined)
2784                 return 0;
2785
2786         return i915_gem_object_wait_rendering(obj, true);
2787 }
2788
2789 /** Flushes the GTT write domain for the object if it's dirty. */
2790 static void
2791 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2792 {
2793         uint32_t old_write_domain;
2794
2795         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2796                 return;
2797
2798         /* No actual flushing is required for the GTT write domain.   Writes
2799          * to it immediately go to main memory as far as we know, so there's
2800          * no chipset flush.  It also doesn't land in render cache.
2801          */
2802         old_write_domain = obj->write_domain;
2803         obj->write_domain = 0;
2804
2805         trace_i915_gem_object_change_domain(obj,
2806                                             obj->read_domains,
2807                                             old_write_domain);
2808 }
2809
2810 /** Flushes the CPU write domain for the object if it's dirty. */
2811 static void
2812 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2813 {
2814         struct drm_device *dev = obj->dev;
2815         uint32_t old_write_domain;
2816
2817         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2818                 return;
2819
2820         i915_gem_clflush_object(obj);
2821         drm_agp_chipset_flush(dev);
2822         old_write_domain = obj->write_domain;
2823         obj->write_domain = 0;
2824
2825         trace_i915_gem_object_change_domain(obj,
2826                                             obj->read_domains,
2827                                             old_write_domain);
2828 }
2829
2830 /**
2831  * Moves a single object to the GTT read, and possibly write domain.
2832  *
2833  * This function returns when the move is complete, including waiting on
2834  * flushes to occur.
2835  */
2836 int
2837 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2838 {
2839         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2840         uint32_t old_write_domain, old_read_domains;
2841         int ret;
2842
2843         /* Not valid to be called on unbound objects. */
2844         if (obj_priv->gtt_space == NULL)
2845                 return -EINVAL;
2846
2847         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2848         if (ret != 0)
2849                 return ret;
2850
2851         i915_gem_object_flush_cpu_write_domain(obj);
2852
2853         if (write) {
2854                 ret = i915_gem_object_wait_rendering(obj, true);
2855                 if (ret)
2856                         return ret;
2857         }
2858
2859         old_write_domain = obj->write_domain;
2860         old_read_domains = obj->read_domains;
2861
2862         /* It should now be out of any other write domains, and we can update
2863          * the domain values for our changes.
2864          */
2865         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2866         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2867         if (write) {
2868                 obj->read_domains = I915_GEM_DOMAIN_GTT;
2869                 obj->write_domain = I915_GEM_DOMAIN_GTT;
2870                 obj_priv->dirty = 1;
2871         }
2872
2873         trace_i915_gem_object_change_domain(obj,
2874                                             old_read_domains,
2875                                             old_write_domain);
2876
2877         return 0;
2878 }
2879
2880 /*
2881  * Prepare buffer for display plane. Use uninterruptible for possible flush
2882  * wait, as in modesetting process we're not supposed to be interrupted.
2883  */
2884 int
2885 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2886                                      bool pipelined)
2887 {
2888         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2889         uint32_t old_read_domains;
2890         int ret;
2891
2892         /* Not valid to be called on unbound objects. */
2893         if (obj_priv->gtt_space == NULL)
2894                 return -EINVAL;
2895
2896         ret = i915_gem_object_flush_gpu_write_domain(obj, true);
2897         if (ret)
2898                 return ret;
2899
2900         /* Currently, we are always called from an non-interruptible context. */
2901         if (!pipelined) {
2902                 ret = i915_gem_object_wait_rendering(obj, false);
2903                 if (ret)
2904                         return ret;
2905         }
2906
2907         i915_gem_object_flush_cpu_write_domain(obj);
2908
2909         old_read_domains = obj->read_domains;
2910         obj->read_domains |= I915_GEM_DOMAIN_GTT;
2911
2912         trace_i915_gem_object_change_domain(obj,
2913                                             old_read_domains,
2914                                             obj->write_domain);
2915
2916         return 0;
2917 }
2918
2919 /**
2920  * Moves a single object to the CPU read, and possibly write domain.
2921  *
2922  * This function returns when the move is complete, including waiting on
2923  * flushes to occur.
2924  */
2925 static int
2926 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2927 {
2928         uint32_t old_write_domain, old_read_domains;
2929         int ret;
2930
2931         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
2932         if (ret != 0)
2933                 return ret;
2934
2935         i915_gem_object_flush_gtt_write_domain(obj);
2936
2937         /* If we have a partially-valid cache of the object in the CPU,
2938          * finish invalidating it and free the per-page flags.
2939          */
2940         i915_gem_object_set_to_full_cpu_read_domain(obj);
2941
2942         if (write) {
2943                 ret = i915_gem_object_wait_rendering(obj, true);
2944                 if (ret)
2945                         return ret;
2946         }
2947
2948         old_write_domain = obj->write_domain;
2949         old_read_domains = obj->read_domains;
2950
2951         /* Flush the CPU cache if it's still invalid. */
2952         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2953                 i915_gem_clflush_object(obj);
2954
2955                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2956         }
2957
2958         /* It should now be out of any other write domains, and we can update
2959          * the domain values for our changes.
2960          */
2961         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2962
2963         /* If we're writing through the CPU, then the GPU read domains will
2964          * need to be invalidated at next use.
2965          */
2966         if (write) {
2967                 obj->read_domains = I915_GEM_DOMAIN_CPU;
2968                 obj->write_domain = I915_GEM_DOMAIN_CPU;
2969         }
2970
2971         trace_i915_gem_object_change_domain(obj,
2972                                             old_read_domains,
2973                                             old_write_domain);
2974
2975         return 0;
2976 }
2977
2978 /*
2979  * Set the next domain for the specified object. This
2980  * may not actually perform the necessary flushing/invaliding though,
2981  * as that may want to be batched with other set_domain operations
2982  *
2983  * This is (we hope) the only really tricky part of gem. The goal
2984  * is fairly simple -- track which caches hold bits of the object
2985  * and make sure they remain coherent. A few concrete examples may
2986  * help to explain how it works. For shorthand, we use the notation
2987  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2988  * a pair of read and write domain masks.
2989  *
2990  * Case 1: the batch buffer
2991  *
2992  *      1. Allocated
2993  *      2. Written by CPU
2994  *      3. Mapped to GTT
2995  *      4. Read by GPU
2996  *      5. Unmapped from GTT
2997  *      6. Freed
2998  *
2999  *      Let's take these a step at a time
3000  *
3001  *      1. Allocated
3002  *              Pages allocated from the kernel may still have
3003  *              cache contents, so we set them to (CPU, CPU) always.
3004  *      2. Written by CPU (using pwrite)
3005  *              The pwrite function calls set_domain (CPU, CPU) and
3006  *              this function does nothing (as nothing changes)
3007  *      3. Mapped by GTT
3008  *              This function asserts that the object is not
3009  *              currently in any GPU-based read or write domains
3010  *      4. Read by GPU
3011  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
3012  *              As write_domain is zero, this function adds in the
3013  *              current read domains (CPU+COMMAND, 0).
3014  *              flush_domains is set to CPU.
3015  *              invalidate_domains is set to COMMAND
3016  *              clflush is run to get data out of the CPU caches
3017  *              then i915_dev_set_domain calls i915_gem_flush to
3018  *              emit an MI_FLUSH and drm_agp_chipset_flush
3019  *      5. Unmapped from GTT
3020  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
3021  *              flush_domains and invalidate_domains end up both zero
3022  *              so no flushing/invalidating happens
3023  *      6. Freed
3024  *              yay, done
3025  *
3026  * Case 2: The shared render buffer
3027  *
3028  *      1. Allocated
3029  *      2. Mapped to GTT
3030  *      3. Read/written by GPU
3031  *      4. set_domain to (CPU,CPU)
3032  *      5. Read/written by CPU
3033  *      6. Read/written by GPU
3034  *
3035  *      1. Allocated
3036  *              Same as last example, (CPU, CPU)
3037  *      2. Mapped to GTT
3038  *              Nothing changes (assertions find that it is not in the GPU)
3039  *      3. Read/written by GPU
3040  *              execbuffer calls set_domain (RENDER, RENDER)
3041  *              flush_domains gets CPU
3042  *              invalidate_domains gets GPU
3043  *              clflush (obj)
3044  *              MI_FLUSH and drm_agp_chipset_flush
3045  *      4. set_domain (CPU, CPU)
3046  *              flush_domains gets GPU
3047  *              invalidate_domains gets CPU
3048  *              wait_rendering (obj) to make sure all drawing is complete.
3049  *              This will include an MI_FLUSH to get the data from GPU
3050  *              to memory
3051  *              clflush (obj) to invalidate the CPU cache
3052  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3053  *      5. Read/written by CPU
3054  *              cache lines are loaded and dirtied
3055  *      6. Read written by GPU
3056  *              Same as last GPU access
3057  *
3058  * Case 3: The constant buffer
3059  *
3060  *      1. Allocated
3061  *      2. Written by CPU
3062  *      3. Read by GPU
3063  *      4. Updated (written) by CPU again
3064  *      5. Read by GPU
3065  *
3066  *      1. Allocated
3067  *              (CPU, CPU)
3068  *      2. Written by CPU
3069  *              (CPU, CPU)
3070  *      3. Read by GPU
3071  *              (CPU+RENDER, 0)
3072  *              flush_domains = CPU
3073  *              invalidate_domains = RENDER
3074  *              clflush (obj)
3075  *              MI_FLUSH
3076  *              drm_agp_chipset_flush
3077  *      4. Updated (written) by CPU again
3078  *              (CPU, CPU)
3079  *              flush_domains = 0 (no previous write domain)
3080  *              invalidate_domains = 0 (no new read domains)
3081  *      5. Read by GPU
3082  *              (CPU+RENDER, 0)
3083  *              flush_domains = CPU
3084  *              invalidate_domains = RENDER
3085  *              clflush (obj)
3086  *              MI_FLUSH
3087  *              drm_agp_chipset_flush
3088  */
3089 static void
3090 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
3091                                   struct intel_ring_buffer *ring)
3092 {
3093         struct drm_device               *dev = obj->dev;
3094         struct drm_i915_private         *dev_priv = dev->dev_private;
3095         struct drm_i915_gem_object      *obj_priv = to_intel_bo(obj);
3096         uint32_t                        invalidate_domains = 0;
3097         uint32_t                        flush_domains = 0;
3098
3099         /*
3100          * If the object isn't moving to a new write domain,
3101          * let the object stay in multiple read domains
3102          */
3103         if (obj->pending_write_domain == 0)
3104                 obj->pending_read_domains |= obj->read_domains;
3105
3106         /*
3107          * Flush the current write domain if
3108          * the new read domains don't match. Invalidate
3109          * any read domains which differ from the old
3110          * write domain
3111          */
3112         if (obj->write_domain &&
3113             obj->write_domain != obj->pending_read_domains) {
3114                 flush_domains |= obj->write_domain;
3115                 invalidate_domains |=
3116                         obj->pending_read_domains & ~obj->write_domain;
3117         }
3118         /*
3119          * Invalidate any read caches which may have
3120          * stale data. That is, any new read domains.
3121          */
3122         invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3123         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
3124                 i915_gem_clflush_object(obj);
3125
3126         /* The actual obj->write_domain will be updated with
3127          * pending_write_domain after we emit the accumulated flush for all
3128          * of our domain changes in execbuffers (which clears objects'
3129          * write_domains).  So if we have a current write domain that we
3130          * aren't changing, set pending_write_domain to that.
3131          */
3132         if (flush_domains == 0 && obj->pending_write_domain == 0)
3133                 obj->pending_write_domain = obj->write_domain;
3134
3135         dev->invalidate_domains |= invalidate_domains;
3136         dev->flush_domains |= flush_domains;
3137         if (flush_domains & I915_GEM_GPU_DOMAINS)
3138                 dev_priv->mm.flush_rings |= obj_priv->ring->id;
3139         if (invalidate_domains & I915_GEM_GPU_DOMAINS)
3140                 dev_priv->mm.flush_rings |= ring->id;
3141 }
3142
3143 /**
3144  * Moves the object from a partially CPU read to a full one.
3145  *
3146  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3147  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3148  */
3149 static void
3150 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3151 {
3152         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3153
3154         if (!obj_priv->page_cpu_valid)
3155                 return;
3156
3157         /* If we're partially in the CPU read domain, finish moving it in.
3158          */
3159         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3160                 int i;
3161
3162                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3163                         if (obj_priv->page_cpu_valid[i])
3164                                 continue;
3165                         drm_clflush_pages(obj_priv->pages + i, 1);
3166                 }
3167         }
3168
3169         /* Free the page_cpu_valid mappings which are now stale, whether
3170          * or not we've got I915_GEM_DOMAIN_CPU.
3171          */
3172         kfree(obj_priv->page_cpu_valid);
3173         obj_priv->page_cpu_valid = NULL;
3174 }
3175
3176 /**
3177  * Set the CPU read domain on a range of the object.
3178  *
3179  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3180  * not entirely valid.  The page_cpu_valid member of the object flags which
3181  * pages have been flushed, and will be respected by
3182  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3183  * of the whole object.
3184  *
3185  * This function returns when the move is complete, including waiting on
3186  * flushes to occur.
3187  */
3188 static int
3189 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3190                                           uint64_t offset, uint64_t size)
3191 {
3192         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3193         uint32_t old_read_domains;
3194         int i, ret;
3195
3196         if (offset == 0 && size == obj->size)
3197                 return i915_gem_object_set_to_cpu_domain(obj, 0);
3198
3199         ret = i915_gem_object_flush_gpu_write_domain(obj, false);
3200         if (ret != 0)
3201                 return ret;
3202         i915_gem_object_flush_gtt_write_domain(obj);
3203
3204         /* If we're already fully in the CPU read domain, we're done. */
3205         if (obj_priv->page_cpu_valid == NULL &&
3206             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3207                 return 0;
3208
3209         /* Otherwise, create/clear the per-page CPU read domain flag if we're
3210          * newly adding I915_GEM_DOMAIN_CPU
3211          */
3212         if (obj_priv->page_cpu_valid == NULL) {
3213                 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3214                                                    GFP_KERNEL);
3215                 if (obj_priv->page_cpu_valid == NULL)
3216                         return -ENOMEM;
3217         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3218                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3219
3220         /* Flush the cache on any pages that are still invalid from the CPU's
3221          * perspective.
3222          */
3223         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3224              i++) {
3225                 if (obj_priv->page_cpu_valid[i])
3226                         continue;
3227
3228                 drm_clflush_pages(obj_priv->pages + i, 1);
3229
3230                 obj_priv->page_cpu_valid[i] = 1;
3231         }
3232
3233         /* It should now be out of any other write domains, and we can update
3234          * the domain values for our changes.
3235          */
3236         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3237
3238         old_read_domains = obj->read_domains;
3239         obj->read_domains |= I915_GEM_DOMAIN_CPU;
3240
3241         trace_i915_gem_object_change_domain(obj,
3242                                             old_read_domains,
3243                                             obj->write_domain);
3244
3245         return 0;
3246 }
3247
3248 /**
3249  * Pin an object to the GTT and evaluate the relocations landing in it.
3250  */
3251 static int
3252 i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj,
3253                              struct drm_file *file_priv,
3254                              struct drm_i915_gem_exec_object2 *entry)
3255 {
3256         struct drm_device *dev = obj->base.dev;
3257         drm_i915_private_t *dev_priv = dev->dev_private;
3258         struct drm_i915_gem_relocation_entry __user *user_relocs;
3259         struct drm_gem_object *target_obj = NULL;
3260         uint32_t target_handle = 0;
3261         int i, ret = 0;
3262
3263         user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
3264         for (i = 0; i < entry->relocation_count; i++) {
3265                 struct drm_i915_gem_relocation_entry reloc;
3266                 uint32_t target_offset;
3267
3268                 if (__copy_from_user_inatomic(&reloc,
3269                                               user_relocs+i,
3270                                               sizeof(reloc))) {
3271                         ret = -EFAULT;
3272                         break;
3273                 }
3274
3275                 if (reloc.target_handle != target_handle) {
3276                         drm_gem_object_unreference(target_obj);
3277
3278                         target_obj = drm_gem_object_lookup(dev, file_priv,
3279                                                            reloc.target_handle);
3280                         if (target_obj == NULL) {
3281                                 ret = -ENOENT;
3282                                 break;
3283                         }
3284
3285                         target_handle = reloc.target_handle;
3286                 }
3287                 target_offset = to_intel_bo(target_obj)->gtt_offset;
3288
3289 #if WATCH_RELOC
3290                 DRM_INFO("%s: obj %p offset %08x target %d "
3291                          "read %08x write %08x gtt %08x "
3292                          "presumed %08x delta %08x\n",
3293                          __func__,
3294                          obj,
3295                          (int) reloc.offset,
3296                          (int) reloc.target_handle,
3297                          (int) reloc.read_domains,
3298                          (int) reloc.write_domain,
3299                          (int) target_offset,
3300                          (int) reloc.presumed_offset,
3301                          reloc.delta);
3302 #endif
3303
3304                 /* The target buffer should have appeared before us in the
3305                  * exec_object list, so it should have a GTT space bound by now.
3306                  */
3307                 if (target_offset == 0) {
3308                         DRM_ERROR("No GTT space found for object %d\n",
3309                                   reloc.target_handle);
3310                         ret = -EINVAL;
3311                         break;
3312                 }
3313
3314                 /* Validate that the target is in a valid r/w GPU domain */
3315                 if (reloc.write_domain & (reloc.write_domain - 1)) {
3316                         DRM_ERROR("reloc with multiple write domains: "
3317                                   "obj %p target %d offset %d "
3318                                   "read %08x write %08x",
3319                                   obj, reloc.target_handle,
3320                                   (int) reloc.offset,
3321                                   reloc.read_domains,
3322                                   reloc.write_domain);
3323                         ret = -EINVAL;
3324                         break;
3325                 }
3326                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
3327                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
3328                         DRM_ERROR("reloc with read/write CPU domains: "
3329                                   "obj %p target %d offset %d "
3330                                   "read %08x write %08x",
3331                                   obj, reloc.target_handle,
3332                                   (int) reloc.offset,
3333                                   reloc.read_domains,
3334                                   reloc.write_domain);
3335                         ret = -EINVAL;
3336                         break;
3337                 }
3338                 if (reloc.write_domain && target_obj->pending_write_domain &&
3339                     reloc.write_domain != target_obj->pending_write_domain) {
3340                         DRM_ERROR("Write domain conflict: "
3341                                   "obj %p target %d offset %d "
3342                                   "new %08x old %08x\n",
3343                                   obj, reloc.target_handle,
3344                                   (int) reloc.offset,
3345                                   reloc.write_domain,
3346                                   target_obj->pending_write_domain);
3347                         ret = -EINVAL;
3348                         break;
3349                 }
3350
3351                 target_obj->pending_read_domains |= reloc.read_domains;
3352                 target_obj->pending_write_domain |= reloc.write_domain;
3353
3354                 /* If the relocation already has the right value in it, no
3355                  * more work needs to be done.
3356                  */
3357                 if (target_offset == reloc.presumed_offset)
3358                         continue;
3359
3360                 /* Check that the relocation address is valid... */
3361                 if (reloc.offset > obj->base.size - 4) {
3362                         DRM_ERROR("Relocation beyond object bounds: "
3363                                   "obj %p target %d offset %d size %d.\n",
3364                                   obj, reloc.target_handle,
3365                                   (int) reloc.offset, (int) obj->base.size);
3366                         ret = -EINVAL;
3367                         break;
3368                 }
3369                 if (reloc.offset & 3) {
3370                         DRM_ERROR("Relocation not 4-byte aligned: "
3371                                   "obj %p target %d offset %d.\n",
3372                                   obj, reloc.target_handle,
3373                                   (int) reloc.offset);
3374                         ret = -EINVAL;
3375                         break;
3376                 }
3377
3378                 /* and points to somewhere within the target object. */
3379                 if (reloc.delta >= target_obj->size) {
3380                         DRM_ERROR("Relocation beyond target object bounds: "
3381                                   "obj %p target %d delta %d size %d.\n",
3382                                   obj, reloc.target_handle,
3383                                   (int) reloc.delta, (int) target_obj->size);
3384                         ret = -EINVAL;
3385                         break;
3386                 }
3387
3388                 reloc.delta += target_offset;
3389                 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
3390                         uint32_t page_offset = reloc.offset & ~PAGE_MASK;
3391                         char *vaddr;
3392
3393                         vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]);
3394                         *(uint32_t *)(vaddr + page_offset) = reloc.delta;
3395                         kunmap_atomic(vaddr);
3396                 } else {
3397                         uint32_t __iomem *reloc_entry;
3398                         void __iomem *reloc_page;
3399
3400                         ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1);
3401                         if (ret)
3402                                 break;
3403
3404                         /* Map the page containing the relocation we're going to perform.  */
3405                         reloc.offset += obj->gtt_offset;
3406                         reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3407                                                               reloc.offset & PAGE_MASK);
3408                         reloc_entry = (uint32_t __iomem *)
3409                                 (reloc_page + (reloc.offset & ~PAGE_MASK));
3410                         iowrite32(reloc.delta, reloc_entry);
3411                         io_mapping_unmap_atomic(reloc_page);
3412                 }
3413
3414                 /* and update the user's relocation entry */
3415                 reloc.presumed_offset = target_offset;
3416                 if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset,
3417                                               &reloc.presumed_offset,
3418                                               sizeof(reloc.presumed_offset))) {
3419                     ret = -EFAULT;
3420                     break;
3421                 }
3422         }
3423
3424         drm_gem_object_unreference(target_obj);
3425         return ret;
3426 }
3427
3428 static int
3429 i915_gem_execbuffer_pin(struct drm_device *dev,
3430                         struct drm_file *file,
3431                         struct drm_gem_object **object_list,
3432                         struct drm_i915_gem_exec_object2 *exec_list,
3433                         int count)
3434 {
3435         struct drm_i915_private *dev_priv = dev->dev_private;
3436         int ret, i, retry;
3437
3438         /* attempt to pin all of the buffers into the GTT */
3439         for (retry = 0; retry < 2; retry++) {
3440                 ret = 0;
3441                 for (i = 0; i < count; i++) {
3442                         struct drm_i915_gem_exec_object2 *entry = &exec_list[i];
3443                         struct drm_i915_gem_object *obj= to_intel_bo(object_list[i]);
3444                         bool need_fence =
3445                                 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3446                                 obj->tiling_mode != I915_TILING_NONE;
3447
3448                         /* Check fence reg constraints and rebind if necessary */
3449                         if (need_fence &&
3450                             !i915_gem_object_fence_offset_ok(&obj->base,
3451                                                              obj->tiling_mode)) {
3452                                 ret = i915_gem_object_unbind(&obj->base);
3453                                 if (ret)
3454                                         break;
3455                         }
3456
3457                         ret = i915_gem_object_pin(&obj->base, entry->alignment);
3458                         if (ret)
3459                                 break;
3460
3461                         /*
3462                          * Pre-965 chips need a fence register set up in order
3463                          * to properly handle blits to/from tiled surfaces.
3464                          */
3465                         if (need_fence) {
3466                                 ret = i915_gem_object_get_fence_reg(&obj->base, true);
3467                                 if (ret) {
3468                                         i915_gem_object_unpin(&obj->base);
3469                                         break;
3470                                 }
3471
3472                                 dev_priv->fence_regs[obj->fence_reg].gpu = true;
3473                         }
3474
3475                         entry->offset = obj->gtt_offset;
3476                 }
3477
3478                 while (i--)
3479                         i915_gem_object_unpin(object_list[i]);
3480
3481                 if (ret == 0)
3482                         break;
3483
3484                 if (ret != -ENOSPC || retry)
3485                         return ret;
3486
3487                 ret = i915_gem_evict_everything(dev);
3488                 if (ret)
3489                         return ret;
3490         }
3491
3492         return 0;
3493 }
3494
3495 /* Throttle our rendering by waiting until the ring has completed our requests
3496  * emitted over 20 msec ago.
3497  *
3498  * Note that if we were to use the current jiffies each time around the loop,
3499  * we wouldn't escape the function with any frames outstanding if the time to
3500  * render a frame was over 20ms.
3501  *
3502  * This should get us reasonable parallelism between CPU and GPU but also
3503  * relatively low latency when blocking on a particular request to finish.
3504  */
3505 static int
3506 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3507 {
3508         struct drm_i915_private *dev_priv = dev->dev_private;
3509         struct drm_i915_file_private *file_priv = file->driver_priv;
3510         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3511         struct drm_i915_gem_request *request;
3512         struct intel_ring_buffer *ring = NULL;
3513         u32 seqno = 0;
3514         int ret;
3515
3516         spin_lock(&file_priv->mm.lock);
3517         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3518                 if (time_after_eq(request->emitted_jiffies, recent_enough))
3519                         break;
3520
3521                 ring = request->ring;
3522                 seqno = request->seqno;
3523         }
3524         spin_unlock(&file_priv->mm.lock);
3525
3526         if (seqno == 0)
3527                 return 0;
3528
3529         ret = 0;
3530         if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
3531                 /* And wait for the seqno passing without holding any locks and
3532                  * causing extra latency for others. This is safe as the irq
3533                  * generation is designed to be run atomically and so is
3534                  * lockless.
3535                  */
3536                 ring->user_irq_get(ring);
3537                 ret = wait_event_interruptible(ring->irq_queue,
3538                                                i915_seqno_passed(ring->get_seqno(ring), seqno)
3539                                                || atomic_read(&dev_priv->mm.wedged));
3540                 ring->user_irq_put(ring);
3541
3542                 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3543                         ret = -EIO;
3544         }
3545
3546         if (ret == 0)
3547                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3548
3549         return ret;
3550 }
3551
3552 static int
3553 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec,
3554                           uint64_t exec_offset)
3555 {
3556         uint32_t exec_start, exec_len;
3557
3558         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3559         exec_len = (uint32_t) exec->batch_len;
3560
3561         if ((exec_start | exec_len) & 0x7)
3562                 return -EINVAL;
3563
3564         if (!exec_start)
3565                 return -EINVAL;
3566
3567         return 0;
3568 }
3569
3570 static int
3571 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
3572                    int count)
3573 {
3574         int i;
3575
3576         for (i = 0; i < count; i++) {
3577                 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
3578                 size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry);
3579
3580                 if (!access_ok(VERIFY_READ, ptr, length))
3581                         return -EFAULT;
3582
3583                 /* we may also need to update the presumed offsets */
3584                 if (!access_ok(VERIFY_WRITE, ptr, length))
3585                         return -EFAULT;
3586
3587                 if (fault_in_pages_readable(ptr, length))
3588                         return -EFAULT;
3589         }
3590
3591         return 0;
3592 }
3593
3594 static int
3595 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3596                        struct drm_file *file,
3597                        struct drm_i915_gem_execbuffer2 *args,
3598                        struct drm_i915_gem_exec_object2 *exec_list)
3599 {
3600         drm_i915_private_t *dev_priv = dev->dev_private;
3601         struct drm_gem_object **object_list = NULL;
3602         struct drm_gem_object *batch_obj;
3603         struct drm_clip_rect *cliprects = NULL;
3604         struct drm_i915_gem_request *request = NULL;
3605         int ret, i, flips;
3606         uint64_t exec_offset;
3607
3608         struct intel_ring_buffer *ring = NULL;
3609
3610         ret = i915_gem_check_is_wedged(dev);
3611         if (ret)
3612                 return ret;
3613
3614         ret = validate_exec_list(exec_list, args->buffer_count);
3615         if (ret)
3616                 return ret;
3617
3618 #if WATCH_EXEC
3619         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3620                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3621 #endif
3622         switch (args->flags & I915_EXEC_RING_MASK) {
3623         case I915_EXEC_DEFAULT:
3624         case I915_EXEC_RENDER:
3625                 ring = &dev_priv->render_ring;
3626                 break;
3627         case I915_EXEC_BSD:
3628                 if (!HAS_BSD(dev)) {
3629                         DRM_ERROR("execbuf with invalid ring (BSD)\n");
3630                         return -EINVAL;
3631                 }
3632                 ring = &dev_priv->bsd_ring;
3633                 break;
3634         case I915_EXEC_BLT:
3635                 if (!HAS_BLT(dev)) {
3636                         DRM_ERROR("execbuf with invalid ring (BLT)\n");
3637                         return -EINVAL;
3638                 }
3639                 ring = &dev_priv->blt_ring;
3640                 break;
3641         default:
3642                 DRM_ERROR("execbuf with unknown ring: %d\n",
3643                           (int)(args->flags & I915_EXEC_RING_MASK));
3644                 return -EINVAL;
3645         }
3646
3647         if (args->buffer_count < 1) {
3648                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3649                 return -EINVAL;
3650         }
3651         object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3652         if (object_list == NULL) {
3653                 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3654                           args->buffer_count);
3655                 ret = -ENOMEM;
3656                 goto pre_mutex_err;
3657         }
3658
3659         if (args->num_cliprects != 0) {
3660                 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3661                                     GFP_KERNEL);
3662                 if (cliprects == NULL) {
3663                         ret = -ENOMEM;
3664                         goto pre_mutex_err;
3665                 }
3666
3667                 ret = copy_from_user(cliprects,
3668                                      (struct drm_clip_rect __user *)
3669                                      (uintptr_t) args->cliprects_ptr,
3670                                      sizeof(*cliprects) * args->num_cliprects);
3671                 if (ret != 0) {
3672                         DRM_ERROR("copy %d cliprects failed: %d\n",
3673                                   args->num_cliprects, ret);
3674                         ret = -EFAULT;
3675                         goto pre_mutex_err;
3676                 }
3677         }
3678
3679         request = kzalloc(sizeof(*request), GFP_KERNEL);
3680         if (request == NULL) {
3681                 ret = -ENOMEM;
3682                 goto pre_mutex_err;
3683         }
3684
3685         ret = i915_mutex_lock_interruptible(dev);
3686         if (ret)
3687                 goto pre_mutex_err;
3688
3689         if (dev_priv->mm.suspended) {
3690                 mutex_unlock(&dev->struct_mutex);
3691                 ret = -EBUSY;
3692                 goto pre_mutex_err;
3693         }
3694
3695         /* Look up object handles */
3696         for (i = 0; i < args->buffer_count; i++) {
3697                 struct drm_i915_gem_object *obj_priv;
3698
3699                 object_list[i] = drm_gem_object_lookup(dev, file,
3700                                                        exec_list[i].handle);
3701                 if (object_list[i] == NULL) {
3702                         DRM_ERROR("Invalid object handle %d at index %d\n",
3703                                    exec_list[i].handle, i);
3704                         /* prevent error path from reading uninitialized data */
3705                         args->buffer_count = i + 1;
3706                         ret = -ENOENT;
3707                         goto err;
3708                 }
3709
3710                 obj_priv = to_intel_bo(object_list[i]);
3711                 if (obj_priv->in_execbuffer) {
3712                         DRM_ERROR("Object %p appears more than once in object list\n",
3713                                    object_list[i]);
3714                         /* prevent error path from reading uninitialized data */
3715                         args->buffer_count = i + 1;
3716                         ret = -EINVAL;
3717                         goto err;
3718                 }
3719                 obj_priv->in_execbuffer = true;
3720         }
3721
3722         /* Move the objects en-masse into the GTT, evicting if necessary. */
3723         ret = i915_gem_execbuffer_pin(dev, file,
3724                                       object_list, exec_list,
3725                                       args->buffer_count);
3726         if (ret)
3727                 goto err;
3728
3729         /* The objects are in their final locations, apply the relocations. */
3730         for (i = 0; i < args->buffer_count; i++) {
3731                 struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]);
3732                 obj->base.pending_read_domains = 0;
3733                 obj->base.pending_write_domain = 0;
3734                 ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]);
3735                 if (ret)
3736                         goto err;
3737         }
3738
3739         /* Set the pending read domains for the batch buffer to COMMAND */
3740         batch_obj = object_list[args->buffer_count-1];
3741         if (batch_obj->pending_write_domain) {
3742                 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3743                 ret = -EINVAL;
3744                 goto err;
3745         }
3746         batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3747
3748         /* Sanity check the batch buffer */
3749         exec_offset = to_intel_bo(batch_obj)->gtt_offset;
3750         ret = i915_gem_check_execbuffer(args, exec_offset);
3751         if (ret != 0) {
3752                 DRM_ERROR("execbuf with invalid offset/length\n");
3753                 goto err;
3754         }
3755
3756         /* Zero the global flush/invalidate flags. These
3757          * will be modified as new domains are computed
3758          * for each object
3759          */
3760         dev->invalidate_domains = 0;
3761         dev->flush_domains = 0;
3762         dev_priv->mm.flush_rings = 0;
3763         for (i = 0; i < args->buffer_count; i++)
3764                 i915_gem_object_set_to_gpu_domain(object_list[i], ring);
3765
3766         if (dev->invalidate_domains | dev->flush_domains) {
3767 #if WATCH_EXEC
3768                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3769                           __func__,
3770                          dev->invalidate_domains,
3771                          dev->flush_domains);
3772 #endif
3773                 i915_gem_flush(dev, file,
3774                                dev->invalidate_domains,
3775                                dev->flush_domains,
3776                                dev_priv->mm.flush_rings);
3777         }
3778
3779 #if WATCH_COHERENCY
3780         for (i = 0; i < args->buffer_count; i++) {
3781                 i915_gem_object_check_coherency(object_list[i],
3782                                                 exec_list[i].handle);
3783         }
3784 #endif
3785
3786 #if WATCH_EXEC
3787         i915_gem_dump_object(batch_obj,
3788                               args->batch_len,
3789                               __func__,
3790                               ~0);
3791 #endif
3792
3793         /* Check for any pending flips. As we only maintain a flip queue depth
3794          * of 1, we can simply insert a WAIT for the next display flip prior
3795          * to executing the batch and avoid stalling the CPU.
3796          */
3797         flips = 0;
3798         for (i = 0; i < args->buffer_count; i++) {
3799                 if (object_list[i]->write_domain)
3800                         flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip);
3801         }
3802         if (flips) {
3803                 int plane, flip_mask;
3804
3805                 for (plane = 0; flips >> plane; plane++) {
3806                         if (((flips >> plane) & 1) == 0)
3807                                 continue;
3808
3809                         if (plane)
3810                                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
3811                         else
3812                                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
3813
3814                         ret = intel_ring_begin(ring, 2);
3815                         if (ret)
3816                                 goto err;
3817
3818                         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
3819                         intel_ring_emit(ring, MI_NOOP);
3820                         intel_ring_advance(ring);
3821                 }
3822         }
3823
3824         /* Exec the batchbuffer */
3825         ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset);
3826         if (ret) {
3827                 DRM_ERROR("dispatch failed %d\n", ret);
3828                 goto err;
3829         }
3830
3831         for (i = 0; i < args->buffer_count; i++) {
3832                 struct drm_gem_object *obj = object_list[i];
3833
3834                 obj->read_domains = obj->pending_read_domains;
3835                 obj->write_domain = obj->pending_write_domain;
3836
3837                 i915_gem_object_move_to_active(obj, ring);
3838                 if (obj->write_domain) {
3839                         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3840                         obj_priv->dirty = 1;
3841                         list_move_tail(&obj_priv->gpu_write_list,
3842                                        &ring->gpu_write_list);
3843                         intel_mark_busy(dev, obj);
3844                 }
3845
3846                 trace_i915_gem_object_change_domain(obj,
3847                                                     obj->read_domains,
3848                                                     obj->write_domain);
3849         }
3850
3851         /*
3852          * Ensure that the commands in the batch buffer are
3853          * finished before the interrupt fires
3854          */
3855         i915_retire_commands(dev, ring);
3856
3857         if (i915_add_request(dev, file, request, ring))
3858                 ring->outstanding_lazy_request = true;
3859         else
3860                 request = NULL;
3861
3862 err:
3863         for (i = 0; i < args->buffer_count; i++) {
3864                 if (object_list[i] == NULL)
3865                     break;
3866
3867                 to_intel_bo(object_list[i])->in_execbuffer = false;
3868                 drm_gem_object_unreference(object_list[i]);
3869         }
3870
3871         mutex_unlock(&dev->struct_mutex);
3872
3873 pre_mutex_err:
3874         drm_free_large(object_list);
3875         kfree(cliprects);
3876         kfree(request);
3877
3878         return ret;
3879 }
3880
3881 /*
3882  * Legacy execbuffer just creates an exec2 list from the original exec object
3883  * list array and passes it to the real function.
3884  */
3885 int
3886 i915_gem_execbuffer(struct drm_device *dev, void *data,
3887                     struct drm_file *file_priv)
3888 {
3889         struct drm_i915_gem_execbuffer *args = data;
3890         struct drm_i915_gem_execbuffer2 exec2;
3891         struct drm_i915_gem_exec_object *exec_list = NULL;
3892         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3893         int ret, i;
3894
3895 #if WATCH_EXEC
3896         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3897                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3898 #endif
3899
3900         if (args->buffer_count < 1) {
3901                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3902                 return -EINVAL;
3903         }
3904
3905         /* Copy in the exec list from userland */
3906         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3907         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3908         if (exec_list == NULL || exec2_list == NULL) {
3909                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3910                           args->buffer_count);
3911                 drm_free_large(exec_list);
3912                 drm_free_large(exec2_list);
3913                 return -ENOMEM;
3914         }
3915         ret = copy_from_user(exec_list,
3916                              (struct drm_i915_relocation_entry __user *)
3917                              (uintptr_t) args->buffers_ptr,
3918                              sizeof(*exec_list) * args->buffer_count);
3919         if (ret != 0) {
3920                 DRM_ERROR("copy %d exec entries failed %d\n",
3921                           args->buffer_count, ret);
3922                 drm_free_large(exec_list);
3923                 drm_free_large(exec2_list);
3924                 return -EFAULT;
3925         }
3926
3927         for (i = 0; i < args->buffer_count; i++) {
3928                 exec2_list[i].handle = exec_list[i].handle;
3929                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3930                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3931                 exec2_list[i].alignment = exec_list[i].alignment;
3932                 exec2_list[i].offset = exec_list[i].offset;
3933                 if (INTEL_INFO(dev)->gen < 4)
3934                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3935                 else
3936                         exec2_list[i].flags = 0;
3937         }
3938
3939         exec2.buffers_ptr = args->buffers_ptr;
3940         exec2.buffer_count = args->buffer_count;
3941         exec2.batch_start_offset = args->batch_start_offset;
3942         exec2.batch_len = args->batch_len;
3943         exec2.DR1 = args->DR1;
3944         exec2.DR4 = args->DR4;
3945         exec2.num_cliprects = args->num_cliprects;
3946         exec2.cliprects_ptr = args->cliprects_ptr;
3947         exec2.flags = I915_EXEC_RENDER;
3948
3949         ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3950         if (!ret) {
3951                 /* Copy the new buffer offsets back to the user's exec list. */
3952                 for (i = 0; i < args->buffer_count; i++)
3953                         exec_list[i].offset = exec2_list[i].offset;
3954                 /* ... and back out to userspace */
3955                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3956                                    (uintptr_t) args->buffers_ptr,
3957                                    exec_list,
3958                                    sizeof(*exec_list) * args->buffer_count);
3959                 if (ret) {
3960                         ret = -EFAULT;
3961                         DRM_ERROR("failed to copy %d exec entries "
3962                                   "back to user (%d)\n",
3963                                   args->buffer_count, ret);
3964                 }
3965         }
3966
3967         drm_free_large(exec_list);
3968         drm_free_large(exec2_list);
3969         return ret;
3970 }
3971
3972 int
3973 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3974                      struct drm_file *file_priv)
3975 {
3976         struct drm_i915_gem_execbuffer2 *args = data;
3977         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3978         int ret;
3979
3980 #if WATCH_EXEC
3981         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3982                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3983 #endif
3984
3985         if (args->buffer_count < 1) {
3986                 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3987                 return -EINVAL;
3988         }
3989
3990         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3991         if (exec2_list == NULL) {
3992                 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3993                           args->buffer_count);
3994                 return -ENOMEM;
3995         }
3996         ret = copy_from_user(exec2_list,
3997                              (struct drm_i915_relocation_entry __user *)
3998                              (uintptr_t) args->buffers_ptr,
3999                              sizeof(*exec2_list) * args->buffer_count);
4000         if (ret != 0) {
4001                 DRM_ERROR("copy %d exec entries failed %d\n",
4002                           args->buffer_count, ret);
4003                 drm_free_large(exec2_list);
4004                 return -EFAULT;
4005         }
4006
4007         ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4008         if (!ret) {
4009                 /* Copy the new buffer offsets back to the user's exec list. */
4010                 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4011                                    (uintptr_t) args->buffers_ptr,
4012                                    exec2_list,
4013                                    sizeof(*exec2_list) * args->buffer_count);
4014                 if (ret) {
4015                         ret = -EFAULT;
4016                         DRM_ERROR("failed to copy %d exec entries "
4017                                   "back to user (%d)\n",
4018                                   args->buffer_count, ret);
4019                 }
4020         }
4021
4022         drm_free_large(exec2_list);
4023         return ret;
4024 }
4025
4026 int
4027 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4028 {
4029         struct drm_device *dev = obj->dev;
4030         struct drm_i915_private *dev_priv = dev->dev_private;
4031         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4032         int ret;
4033
4034         BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4035         WARN_ON(i915_verify_lists(dev));
4036
4037         if (obj_priv->gtt_space != NULL) {
4038                 if (alignment == 0)
4039                         alignment = i915_gem_get_gtt_alignment(obj);
4040                 if (obj_priv->gtt_offset & (alignment - 1)) {
4041                         WARN(obj_priv->pin_count,
4042                              "bo is already pinned with incorrect alignment:"
4043                              " offset=%x, req.alignment=%x\n",
4044                              obj_priv->gtt_offset, alignment);
4045                         ret = i915_gem_object_unbind(obj);
4046                         if (ret)
4047                                 return ret;
4048                 }
4049         }
4050
4051         if (obj_priv->gtt_space == NULL) {
4052                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4053                 if (ret)
4054                         return ret;
4055         }
4056
4057         obj_priv->pin_count++;
4058
4059         /* If the object is not active and not pending a flush,
4060          * remove it from the inactive list
4061          */
4062         if (obj_priv->pin_count == 1) {
4063                 i915_gem_info_add_pin(dev_priv, obj->size);
4064                 if (!obj_priv->active)
4065                         list_move_tail(&obj_priv->mm_list,
4066                                        &dev_priv->mm.pinned_list);
4067         }
4068
4069         WARN_ON(i915_verify_lists(dev));
4070         return 0;
4071 }
4072
4073 void
4074 i915_gem_object_unpin(struct drm_gem_object *obj)
4075 {
4076         struct drm_device *dev = obj->dev;
4077         drm_i915_private_t *dev_priv = dev->dev_private;
4078         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4079
4080         WARN_ON(i915_verify_lists(dev));
4081         obj_priv->pin_count--;
4082         BUG_ON(obj_priv->pin_count < 0);
4083         BUG_ON(obj_priv->gtt_space == NULL);
4084
4085         /* If the object is no longer pinned, and is
4086          * neither active nor being flushed, then stick it on
4087          * the inactive list
4088          */
4089         if (obj_priv->pin_count == 0) {
4090                 if (!obj_priv->active)
4091                         list_move_tail(&obj_priv->mm_list,
4092                                        &dev_priv->mm.inactive_list);
4093                 i915_gem_info_remove_pin(dev_priv, obj->size);
4094         }
4095         WARN_ON(i915_verify_lists(dev));
4096 }
4097
4098 int
4099 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4100                    struct drm_file *file_priv)
4101 {
4102         struct drm_i915_gem_pin *args = data;
4103         struct drm_gem_object *obj;
4104         struct drm_i915_gem_object *obj_priv;
4105         int ret;
4106
4107         ret = i915_mutex_lock_interruptible(dev);
4108         if (ret)
4109                 return ret;
4110
4111         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4112         if (obj == NULL) {
4113                 ret = -ENOENT;
4114                 goto unlock;
4115         }
4116         obj_priv = to_intel_bo(obj);
4117
4118         if (obj_priv->madv != I915_MADV_WILLNEED) {
4119                 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4120                 ret = -EINVAL;
4121                 goto out;
4122         }
4123
4124         if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4125                 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4126                           args->handle);
4127                 ret = -EINVAL;
4128                 goto out;
4129         }
4130
4131         obj_priv->user_pin_count++;
4132         obj_priv->pin_filp = file_priv;
4133         if (obj_priv->user_pin_count == 1) {
4134                 ret = i915_gem_object_pin(obj, args->alignment);
4135                 if (ret)
4136                         goto out;
4137         }
4138
4139         /* XXX - flush the CPU caches for pinned objects
4140          * as the X server doesn't manage domains yet
4141          */
4142         i915_gem_object_flush_cpu_write_domain(obj);
4143         args->offset = obj_priv->gtt_offset;
4144 out:
4145         drm_gem_object_unreference(obj);
4146 unlock:
4147         mutex_unlock(&dev->struct_mutex);
4148         return ret;
4149 }
4150
4151 int
4152 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4153                      struct drm_file *file_priv)
4154 {
4155         struct drm_i915_gem_pin *args = data;
4156         struct drm_gem_object *obj;
4157         struct drm_i915_gem_object *obj_priv;
4158         int ret;
4159
4160         ret = i915_mutex_lock_interruptible(dev);
4161         if (ret)
4162                 return ret;
4163
4164         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4165         if (obj == NULL) {
4166                 ret = -ENOENT;
4167                 goto unlock;
4168         }
4169         obj_priv = to_intel_bo(obj);
4170
4171         if (obj_priv->pin_filp != file_priv) {
4172                 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4173                           args->handle);
4174                 ret = -EINVAL;
4175                 goto out;
4176         }
4177         obj_priv->user_pin_count--;
4178         if (obj_priv->user_pin_count == 0) {
4179                 obj_priv->pin_filp = NULL;
4180                 i915_gem_object_unpin(obj);
4181         }
4182
4183 out:
4184         drm_gem_object_unreference(obj);
4185 unlock:
4186         mutex_unlock(&dev->struct_mutex);
4187         return ret;
4188 }
4189
4190 int
4191 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4192                     struct drm_file *file_priv)
4193 {
4194         struct drm_i915_gem_busy *args = data;
4195         struct drm_gem_object *obj;
4196         struct drm_i915_gem_object *obj_priv;
4197         int ret;
4198
4199         ret = i915_mutex_lock_interruptible(dev);
4200         if (ret)
4201                 return ret;
4202
4203         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4204         if (obj == NULL) {
4205                 ret = -ENOENT;
4206                 goto unlock;
4207         }
4208         obj_priv = to_intel_bo(obj);
4209
4210         /* Count all active objects as busy, even if they are currently not used
4211          * by the gpu. Users of this interface expect objects to eventually
4212          * become non-busy without any further actions, therefore emit any
4213          * necessary flushes here.
4214          */
4215         args->busy = obj_priv->active;
4216         if (args->busy) {
4217                 /* Unconditionally flush objects, even when the gpu still uses this
4218                  * object. Userspace calling this function indicates that it wants to
4219                  * use this buffer rather sooner than later, so issuing the required
4220                  * flush earlier is beneficial.
4221                  */
4222                 if (obj->write_domain & I915_GEM_GPU_DOMAINS)
4223                         i915_gem_flush_ring(dev, file_priv,
4224                                             obj_priv->ring,
4225                                             0, obj->write_domain);
4226
4227                 /* Update the active list for the hardware's current position.
4228                  * Otherwise this only updates on a delayed timer or when irqs
4229                  * are actually unmasked, and our working set ends up being
4230                  * larger than required.
4231                  */
4232                 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4233
4234                 args->busy = obj_priv->active;
4235         }
4236
4237         drm_gem_object_unreference(obj);
4238 unlock:
4239         mutex_unlock(&dev->struct_mutex);
4240         return ret;
4241 }
4242
4243 int
4244 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4245                         struct drm_file *file_priv)
4246 {
4247     return i915_gem_ring_throttle(dev, file_priv);
4248 }
4249
4250 int
4251 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4252                        struct drm_file *file_priv)
4253 {
4254         struct drm_i915_gem_madvise *args = data;
4255         struct drm_gem_object *obj;
4256         struct drm_i915_gem_object *obj_priv;
4257         int ret;
4258
4259         switch (args->madv) {
4260         case I915_MADV_DONTNEED:
4261         case I915_MADV_WILLNEED:
4262             break;
4263         default:
4264             return -EINVAL;
4265         }
4266
4267         ret = i915_mutex_lock_interruptible(dev);
4268         if (ret)
4269                 return ret;
4270
4271         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4272         if (obj == NULL) {
4273                 ret = -ENOENT;
4274                 goto unlock;
4275         }
4276         obj_priv = to_intel_bo(obj);
4277
4278         if (obj_priv->pin_count) {
4279                 ret = -EINVAL;
4280                 goto out;
4281         }
4282
4283         if (obj_priv->madv != __I915_MADV_PURGED)
4284                 obj_priv->madv = args->madv;
4285
4286         /* if the object is no longer bound, discard its backing storage */
4287         if (i915_gem_object_is_purgeable(obj_priv) &&
4288             obj_priv->gtt_space == NULL)
4289                 i915_gem_object_truncate(obj);
4290
4291         args->retained = obj_priv->madv != __I915_MADV_PURGED;
4292
4293 out:
4294         drm_gem_object_unreference(obj);
4295 unlock:
4296         mutex_unlock(&dev->struct_mutex);
4297         return ret;
4298 }
4299
4300 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4301                                               size_t size)
4302 {
4303         struct drm_i915_private *dev_priv = dev->dev_private;
4304         struct drm_i915_gem_object *obj;
4305
4306         obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4307         if (obj == NULL)
4308                 return NULL;
4309
4310         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4311                 kfree(obj);
4312                 return NULL;
4313         }
4314
4315         i915_gem_info_add_obj(dev_priv, size);
4316
4317         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4318         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4319
4320         obj->agp_type = AGP_USER_MEMORY;
4321         obj->base.driver_private = NULL;
4322         obj->fence_reg = I915_FENCE_REG_NONE;
4323         INIT_LIST_HEAD(&obj->mm_list);
4324         INIT_LIST_HEAD(&obj->ring_list);
4325         INIT_LIST_HEAD(&obj->gpu_write_list);
4326         obj->madv = I915_MADV_WILLNEED;
4327
4328         return &obj->base;
4329 }
4330
4331 int i915_gem_init_object(struct drm_gem_object *obj)
4332 {
4333         BUG();
4334
4335         return 0;
4336 }
4337
4338 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4339 {
4340         struct drm_device *dev = obj->dev;
4341         drm_i915_private_t *dev_priv = dev->dev_private;
4342         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4343         int ret;
4344
4345         ret = i915_gem_object_unbind(obj);
4346         if (ret == -ERESTARTSYS) {
4347                 list_move(&obj_priv->mm_list,
4348                           &dev_priv->mm.deferred_free_list);
4349                 return;
4350         }
4351
4352         if (obj_priv->mmap_offset)
4353                 i915_gem_free_mmap_offset(obj);
4354
4355         drm_gem_object_release(obj);
4356         i915_gem_info_remove_obj(dev_priv, obj->size);
4357
4358         kfree(obj_priv->page_cpu_valid);
4359         kfree(obj_priv->bit_17);
4360         kfree(obj_priv);
4361 }
4362
4363 void i915_gem_free_object(struct drm_gem_object *obj)
4364 {
4365         struct drm_device *dev = obj->dev;
4366         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4367
4368         trace_i915_gem_object_destroy(obj);
4369
4370         while (obj_priv->pin_count > 0)
4371                 i915_gem_object_unpin(obj);
4372
4373         if (obj_priv->phys_obj)
4374                 i915_gem_detach_phys_object(dev, obj);
4375
4376         i915_gem_free_object_tail(obj);
4377 }
4378
4379 int
4380 i915_gem_idle(struct drm_device *dev)
4381 {
4382         drm_i915_private_t *dev_priv = dev->dev_private;
4383         int ret;
4384
4385         mutex_lock(&dev->struct_mutex);
4386
4387         if (dev_priv->mm.suspended) {
4388                 mutex_unlock(&dev->struct_mutex);
4389                 return 0;
4390         }
4391
4392         ret = i915_gpu_idle(dev);
4393         if (ret) {
4394                 mutex_unlock(&dev->struct_mutex);
4395                 return ret;
4396         }
4397
4398         /* Under UMS, be paranoid and evict. */
4399         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4400                 ret = i915_gem_evict_inactive(dev);
4401                 if (ret) {
4402                         mutex_unlock(&dev->struct_mutex);
4403                         return ret;
4404                 }
4405         }
4406
4407         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4408          * We need to replace this with a semaphore, or something.
4409          * And not confound mm.suspended!
4410          */
4411         dev_priv->mm.suspended = 1;
4412         del_timer_sync(&dev_priv->hangcheck_timer);
4413
4414         i915_kernel_lost_context(dev);
4415         i915_gem_cleanup_ringbuffer(dev);
4416
4417         mutex_unlock(&dev->struct_mutex);
4418
4419         /* Cancel the retire work handler, which should be idle now. */
4420         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4421
4422         return 0;
4423 }
4424
4425 /*
4426  * 965+ support PIPE_CONTROL commands, which provide finer grained control
4427  * over cache flushing.
4428  */
4429 static int
4430 i915_gem_init_pipe_control(struct drm_device *dev)
4431 {
4432         drm_i915_private_t *dev_priv = dev->dev_private;
4433         struct drm_gem_object *obj;
4434         struct drm_i915_gem_object *obj_priv;
4435         int ret;
4436
4437         obj = i915_gem_alloc_object(dev, 4096);
4438         if (obj == NULL) {
4439                 DRM_ERROR("Failed to allocate seqno page\n");
4440                 ret = -ENOMEM;
4441                 goto err;
4442         }
4443         obj_priv = to_intel_bo(obj);
4444         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4445
4446         ret = i915_gem_object_pin(obj, 4096);
4447         if (ret)
4448                 goto err_unref;
4449
4450         dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4451         dev_priv->seqno_page =  kmap(obj_priv->pages[0]);
4452         if (dev_priv->seqno_page == NULL)
4453                 goto err_unpin;
4454
4455         dev_priv->seqno_obj = obj;
4456         memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4457
4458         return 0;
4459
4460 err_unpin:
4461         i915_gem_object_unpin(obj);
4462 err_unref:
4463         drm_gem_object_unreference(obj);
4464 err:
4465         return ret;
4466 }
4467
4468
4469 static void
4470 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4471 {
4472         drm_i915_private_t *dev_priv = dev->dev_private;
4473         struct drm_gem_object *obj;
4474         struct drm_i915_gem_object *obj_priv;
4475
4476         obj = dev_priv->seqno_obj;
4477         obj_priv = to_intel_bo(obj);
4478         kunmap(obj_priv->pages[0]);
4479         i915_gem_object_unpin(obj);
4480         drm_gem_object_unreference(obj);
4481         dev_priv->seqno_obj = NULL;
4482
4483         dev_priv->seqno_page = NULL;
4484 }
4485
4486 int
4487 i915_gem_init_ringbuffer(struct drm_device *dev)
4488 {
4489         drm_i915_private_t *dev_priv = dev->dev_private;
4490         int ret;
4491
4492         if (HAS_PIPE_CONTROL(dev)) {
4493                 ret = i915_gem_init_pipe_control(dev);
4494                 if (ret)
4495                         return ret;
4496         }
4497
4498         ret = intel_init_render_ring_buffer(dev);
4499         if (ret)
4500                 goto cleanup_pipe_control;
4501
4502         if (HAS_BSD(dev)) {
4503                 ret = intel_init_bsd_ring_buffer(dev);
4504                 if (ret)
4505                         goto cleanup_render_ring;
4506         }
4507
4508         if (HAS_BLT(dev)) {
4509                 ret = intel_init_blt_ring_buffer(dev);
4510                 if (ret)
4511                         goto cleanup_bsd_ring;
4512         }
4513
4514         dev_priv->next_seqno = 1;
4515
4516         return 0;
4517
4518 cleanup_bsd_ring:
4519         intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
4520 cleanup_render_ring:
4521         intel_cleanup_ring_buffer(&dev_priv->render_ring);
4522 cleanup_pipe_control:
4523         if (HAS_PIPE_CONTROL(dev))
4524                 i915_gem_cleanup_pipe_control(dev);
4525         return ret;
4526 }
4527
4528 void
4529 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4530 {
4531         drm_i915_private_t *dev_priv = dev->dev_private;
4532
4533         intel_cleanup_ring_buffer(&dev_priv->render_ring);
4534         intel_cleanup_ring_buffer(&dev_priv->bsd_ring);
4535         intel_cleanup_ring_buffer(&dev_priv->blt_ring);
4536         if (HAS_PIPE_CONTROL(dev))
4537                 i915_gem_cleanup_pipe_control(dev);
4538 }
4539
4540 int
4541 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4542                        struct drm_file *file_priv)
4543 {
4544         drm_i915_private_t *dev_priv = dev->dev_private;
4545         int ret;
4546
4547         if (drm_core_check_feature(dev, DRIVER_MODESET))
4548                 return 0;
4549
4550         if (atomic_read(&dev_priv->mm.wedged)) {
4551                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4552                 atomic_set(&dev_priv->mm.wedged, 0);
4553         }
4554
4555         mutex_lock(&dev->struct_mutex);
4556         dev_priv->mm.suspended = 0;
4557
4558         ret = i915_gem_init_ringbuffer(dev);
4559         if (ret != 0) {
4560                 mutex_unlock(&dev->struct_mutex);
4561                 return ret;
4562         }
4563
4564         BUG_ON(!list_empty(&dev_priv->mm.active_list));
4565         BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4566         BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list));
4567         BUG_ON(!list_empty(&dev_priv->blt_ring.active_list));
4568         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4569         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4570         BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4571         BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list));
4572         BUG_ON(!list_empty(&dev_priv->blt_ring.request_list));
4573         mutex_unlock(&dev->struct_mutex);
4574
4575         ret = drm_irq_install(dev);
4576         if (ret)
4577                 goto cleanup_ringbuffer;
4578
4579         return 0;
4580
4581 cleanup_ringbuffer:
4582         mutex_lock(&dev->struct_mutex);
4583         i915_gem_cleanup_ringbuffer(dev);
4584         dev_priv->mm.suspended = 1;
4585         mutex_unlock(&dev->struct_mutex);
4586
4587         return ret;
4588 }
4589
4590 int
4591 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4592                        struct drm_file *file_priv)
4593 {
4594         if (drm_core_check_feature(dev, DRIVER_MODESET))
4595                 return 0;
4596
4597         drm_irq_uninstall(dev);
4598         return i915_gem_idle(dev);
4599 }
4600
4601 void
4602 i915_gem_lastclose(struct drm_device *dev)
4603 {
4604         int ret;
4605
4606         if (drm_core_check_feature(dev, DRIVER_MODESET))
4607                 return;
4608
4609         ret = i915_gem_idle(dev);
4610         if (ret)
4611                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4612 }
4613
4614 static void
4615 init_ring_lists(struct intel_ring_buffer *ring)
4616 {
4617         INIT_LIST_HEAD(&ring->active_list);
4618         INIT_LIST_HEAD(&ring->request_list);
4619         INIT_LIST_HEAD(&ring->gpu_write_list);
4620 }
4621
4622 void
4623 i915_gem_load(struct drm_device *dev)
4624 {
4625         int i;
4626         drm_i915_private_t *dev_priv = dev->dev_private;
4627
4628         INIT_LIST_HEAD(&dev_priv->mm.active_list);
4629         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4630         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4631         INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
4632         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4633         INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4634         init_ring_lists(&dev_priv->render_ring);
4635         init_ring_lists(&dev_priv->bsd_ring);
4636         init_ring_lists(&dev_priv->blt_ring);
4637         for (i = 0; i < 16; i++)
4638                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4639         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4640                           i915_gem_retire_work_handler);
4641         init_completion(&dev_priv->error_completion);
4642         spin_lock(&shrink_list_lock);
4643         list_add(&dev_priv->mm.shrink_list, &shrink_list);
4644         spin_unlock(&shrink_list_lock);
4645
4646         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4647         if (IS_GEN3(dev)) {
4648                 u32 tmp = I915_READ(MI_ARB_STATE);
4649                 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4650                         /* arb state is a masked write, so set bit + bit in mask */
4651                         tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4652                         I915_WRITE(MI_ARB_STATE, tmp);
4653                 }
4654         }
4655
4656         /* Old X drivers will take 0-2 for front, back, depth buffers */
4657         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4658                 dev_priv->fence_reg_start = 3;
4659
4660         if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4661                 dev_priv->num_fence_regs = 16;
4662         else
4663                 dev_priv->num_fence_regs = 8;
4664
4665         /* Initialize fence registers to zero */
4666         switch (INTEL_INFO(dev)->gen) {
4667         case 6:
4668                 for (i = 0; i < 16; i++)
4669                         I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
4670                 break;
4671         case 5:
4672         case 4:
4673                 for (i = 0; i < 16; i++)
4674                         I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4675                 break;
4676         case 3:
4677                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4678                         for (i = 0; i < 8; i++)
4679                                 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4680         case 2:
4681                 for (i = 0; i < 8; i++)
4682                         I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4683                 break;
4684         }
4685         i915_gem_detect_bit_6_swizzle(dev);
4686         init_waitqueue_head(&dev_priv->pending_flip_queue);
4687 }
4688
4689 /*
4690  * Create a physically contiguous memory object for this object
4691  * e.g. for cursor + overlay regs
4692  */
4693 static int i915_gem_init_phys_object(struct drm_device *dev,
4694                                      int id, int size, int align)
4695 {
4696         drm_i915_private_t *dev_priv = dev->dev_private;
4697         struct drm_i915_gem_phys_object *phys_obj;
4698         int ret;
4699
4700         if (dev_priv->mm.phys_objs[id - 1] || !size)
4701                 return 0;
4702
4703         phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4704         if (!phys_obj)
4705                 return -ENOMEM;
4706
4707         phys_obj->id = id;
4708
4709         phys_obj->handle = drm_pci_alloc(dev, size, align);
4710         if (!phys_obj->handle) {
4711                 ret = -ENOMEM;
4712                 goto kfree_obj;
4713         }
4714 #ifdef CONFIG_X86
4715         set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4716 #endif
4717
4718         dev_priv->mm.phys_objs[id - 1] = phys_obj;
4719
4720         return 0;
4721 kfree_obj:
4722         kfree(phys_obj);
4723         return ret;
4724 }
4725
4726 static void i915_gem_free_phys_object(struct drm_device *dev, int id)
4727 {
4728         drm_i915_private_t *dev_priv = dev->dev_private;
4729         struct drm_i915_gem_phys_object *phys_obj;
4730
4731         if (!dev_priv->mm.phys_objs[id - 1])
4732                 return;
4733
4734         phys_obj = dev_priv->mm.phys_objs[id - 1];
4735         if (phys_obj->cur_obj) {
4736                 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4737         }
4738
4739 #ifdef CONFIG_X86
4740         set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4741 #endif
4742         drm_pci_free(dev, phys_obj->handle);
4743         kfree(phys_obj);
4744         dev_priv->mm.phys_objs[id - 1] = NULL;
4745 }
4746
4747 void i915_gem_free_all_phys_object(struct drm_device *dev)
4748 {
4749         int i;
4750
4751         for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4752                 i915_gem_free_phys_object(dev, i);
4753 }
4754
4755 void i915_gem_detach_phys_object(struct drm_device *dev,
4756                                  struct drm_gem_object *obj)
4757 {
4758         struct drm_i915_gem_object *obj_priv;
4759         int i;
4760         int ret;
4761         int page_count;
4762
4763         obj_priv = to_intel_bo(obj);
4764         if (!obj_priv->phys_obj)
4765                 return;
4766
4767         ret = i915_gem_object_get_pages(obj, 0);
4768         if (ret)
4769                 goto out;
4770
4771         page_count = obj->size / PAGE_SIZE;
4772
4773         for (i = 0; i < page_count; i++) {
4774                 char *dst = kmap_atomic(obj_priv->pages[i]);
4775                 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4776
4777                 memcpy(dst, src, PAGE_SIZE);
4778                 kunmap_atomic(dst);
4779         }
4780         drm_clflush_pages(obj_priv->pages, page_count);
4781         drm_agp_chipset_flush(dev);
4782
4783         i915_gem_object_put_pages(obj);
4784 out:
4785         obj_priv->phys_obj->cur_obj = NULL;
4786         obj_priv->phys_obj = NULL;
4787 }
4788
4789 int
4790 i915_gem_attach_phys_object(struct drm_device *dev,
4791                             struct drm_gem_object *obj,
4792                             int id,
4793                             int align)
4794 {
4795         drm_i915_private_t *dev_priv = dev->dev_private;
4796         struct drm_i915_gem_object *obj_priv;
4797         int ret = 0;
4798         int page_count;
4799         int i;
4800
4801         if (id > I915_MAX_PHYS_OBJECT)
4802                 return -EINVAL;
4803
4804         obj_priv = to_intel_bo(obj);
4805
4806         if (obj_priv->phys_obj) {
4807                 if (obj_priv->phys_obj->id == id)
4808                         return 0;
4809                 i915_gem_detach_phys_object(dev, obj);
4810         }
4811
4812         /* create a new object */
4813         if (!dev_priv->mm.phys_objs[id - 1]) {
4814                 ret = i915_gem_init_phys_object(dev, id,
4815                                                 obj->size, align);
4816                 if (ret) {
4817                         DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4818                         goto out;
4819                 }
4820         }
4821
4822         /* bind to the object */
4823         obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4824         obj_priv->phys_obj->cur_obj = obj;
4825
4826         ret = i915_gem_object_get_pages(obj, 0);
4827         if (ret) {
4828                 DRM_ERROR("failed to get page list\n");
4829                 goto out;
4830         }
4831
4832         page_count = obj->size / PAGE_SIZE;
4833
4834         for (i = 0; i < page_count; i++) {
4835                 char *src = kmap_atomic(obj_priv->pages[i]);
4836                 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4837
4838                 memcpy(dst, src, PAGE_SIZE);
4839                 kunmap_atomic(src);
4840         }
4841
4842         i915_gem_object_put_pages(obj);
4843
4844         return 0;
4845 out:
4846         return ret;
4847 }
4848
4849 static int
4850 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4851                      struct drm_i915_gem_pwrite *args,
4852                      struct drm_file *file_priv)
4853 {
4854         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4855         void *obj_addr;
4856         int ret;
4857         char __user *user_data;
4858
4859         user_data = (char __user *) (uintptr_t) args->data_ptr;
4860         obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4861
4862         DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4863         ret = copy_from_user(obj_addr, user_data, args->size);
4864         if (ret)
4865                 return -EFAULT;
4866
4867         drm_agp_chipset_flush(dev);
4868         return 0;
4869 }
4870
4871 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
4872 {
4873         struct drm_i915_file_private *file_priv = file->driver_priv;
4874
4875         /* Clean up our request list when the client is going away, so that
4876          * later retire_requests won't dereference our soon-to-be-gone
4877          * file_priv.
4878          */
4879         spin_lock(&file_priv->mm.lock);
4880         while (!list_empty(&file_priv->mm.request_list)) {
4881                 struct drm_i915_gem_request *request;
4882
4883                 request = list_first_entry(&file_priv->mm.request_list,
4884                                            struct drm_i915_gem_request,
4885                                            client_list);
4886                 list_del(&request->client_list);
4887                 request->file_priv = NULL;
4888         }
4889         spin_unlock(&file_priv->mm.lock);
4890 }
4891
4892 static int
4893 i915_gpu_is_active(struct drm_device *dev)
4894 {
4895         drm_i915_private_t *dev_priv = dev->dev_private;
4896         int lists_empty;
4897
4898         lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4899                       list_empty(&dev_priv->render_ring.active_list) &&
4900                       list_empty(&dev_priv->bsd_ring.active_list) &&
4901                       list_empty(&dev_priv->blt_ring.active_list);
4902
4903         return !lists_empty;
4904 }
4905
4906 static int
4907 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4908 {
4909         drm_i915_private_t *dev_priv, *next_dev;
4910         struct drm_i915_gem_object *obj_priv, *next_obj;
4911         int cnt = 0;
4912         int would_deadlock = 1;
4913
4914         /* "fast-path" to count number of available objects */
4915         if (nr_to_scan == 0) {
4916                 spin_lock(&shrink_list_lock);
4917                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4918                         struct drm_device *dev = dev_priv->dev;
4919
4920                         if (mutex_trylock(&dev->struct_mutex)) {
4921                                 list_for_each_entry(obj_priv,
4922                                                     &dev_priv->mm.inactive_list,
4923                                                     mm_list)
4924                                         cnt++;
4925                                 mutex_unlock(&dev->struct_mutex);
4926                         }
4927                 }
4928                 spin_unlock(&shrink_list_lock);
4929
4930                 return (cnt / 100) * sysctl_vfs_cache_pressure;
4931         }
4932
4933         spin_lock(&shrink_list_lock);
4934
4935 rescan:
4936         /* first scan for clean buffers */
4937         list_for_each_entry_safe(dev_priv, next_dev,
4938                                  &shrink_list, mm.shrink_list) {
4939                 struct drm_device *dev = dev_priv->dev;
4940
4941                 if (! mutex_trylock(&dev->struct_mutex))
4942                         continue;
4943
4944                 spin_unlock(&shrink_list_lock);
4945                 i915_gem_retire_requests(dev);
4946
4947                 list_for_each_entry_safe(obj_priv, next_obj,
4948                                          &dev_priv->mm.inactive_list,
4949                                          mm_list) {
4950                         if (i915_gem_object_is_purgeable(obj_priv)) {
4951                                 i915_gem_object_unbind(&obj_priv->base);
4952                                 if (--nr_to_scan <= 0)
4953                                         break;
4954                         }
4955                 }
4956
4957                 spin_lock(&shrink_list_lock);
4958                 mutex_unlock(&dev->struct_mutex);
4959
4960                 would_deadlock = 0;
4961
4962                 if (nr_to_scan <= 0)
4963                         break;
4964         }
4965
4966         /* second pass, evict/count anything still on the inactive list */
4967         list_for_each_entry_safe(dev_priv, next_dev,
4968                                  &shrink_list, mm.shrink_list) {
4969                 struct drm_device *dev = dev_priv->dev;
4970
4971                 if (! mutex_trylock(&dev->struct_mutex))
4972                         continue;
4973
4974                 spin_unlock(&shrink_list_lock);
4975
4976                 list_for_each_entry_safe(obj_priv, next_obj,
4977                                          &dev_priv->mm.inactive_list,
4978                                          mm_list) {
4979                         if (nr_to_scan > 0) {
4980                                 i915_gem_object_unbind(&obj_priv->base);
4981                                 nr_to_scan--;
4982                         } else
4983                                 cnt++;
4984                 }
4985
4986                 spin_lock(&shrink_list_lock);
4987                 mutex_unlock(&dev->struct_mutex);
4988
4989                 would_deadlock = 0;
4990         }
4991
4992         if (nr_to_scan) {
4993                 int active = 0;
4994
4995                 /*
4996                  * We are desperate for pages, so as a last resort, wait
4997                  * for the GPU to finish and discard whatever we can.
4998                  * This has a dramatic impact to reduce the number of
4999                  * OOM-killer events whilst running the GPU aggressively.
5000                  */
5001                 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5002                         struct drm_device *dev = dev_priv->dev;
5003
5004                         if (!mutex_trylock(&dev->struct_mutex))
5005                                 continue;
5006
5007                         spin_unlock(&shrink_list_lock);
5008
5009                         if (i915_gpu_is_active(dev)) {
5010                                 i915_gpu_idle(dev);
5011                                 active++;
5012                         }
5013
5014                         spin_lock(&shrink_list_lock);
5015                         mutex_unlock(&dev->struct_mutex);
5016                 }
5017
5018                 if (active)
5019                         goto rescan;
5020         }
5021
5022         spin_unlock(&shrink_list_lock);
5023
5024         if (would_deadlock)
5025                 return -1;
5026         else if (cnt > 0)
5027                 return (cnt / 100) * sysctl_vfs_cache_pressure;
5028         else
5029                 return 0;
5030 }
5031
5032 static struct shrinker shrinker = {
5033         .shrink = i915_gem_shrink,
5034         .seeks = DEFAULT_SEEKS,
5035 };
5036
5037 __init void
5038 i915_gem_shrinker_init(void)
5039 {
5040     register_shrinker(&shrinker);
5041 }
5042
5043 __exit void
5044 i915_gem_shrinker_exit(void)
5045 {
5046     unregister_shrinker(&shrinker);
5047 }