drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (i915_gem_obj_is_pinned(obj))
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct i915_vma *vma;
 124         int pin_count = 0;
 125
 126         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
 127                    &obj->base,
 128                    get_pin_flag(obj),
 129                    get_tiling_flag(obj),
 130                    get_global_flag(obj),
 131                    obj->base.size / 1024,
 132                    obj->base.read_domains,
 133                    obj->base.write_domain,
 134                    i915_gem_request_get_seqno(obj->last_read_req),
 135                    i915_gem_request_get_seqno(obj->last_write_req),
 136                    i915_gem_request_get_seqno(obj->last_fenced_req),
 137                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 138                    obj->dirty ? " dirty" : "",
 139                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 140         if (obj->base.name)
 141                 seq_printf(m, " (name: %d)", obj->base.name);
 142         list_for_each_entry(vma, &obj->vma_list, vma_link)
 143                 if (vma->pin_count > 0)
 144                         pin_count++;
 145                 seq_printf(m, " (pinned x %d)", pin_count);
 146         if (obj->pin_display)
 147                 seq_printf(m, " (display)");
 148         if (obj->fence_reg != I915_FENCE_REG_NONE)
 149                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 150         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 151                 if (!i915_is_ggtt(vma->vm))
 152                         seq_puts(m, " (pp");
 153                 else
 154                         seq_puts(m, " (g");
 155                 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
 156                            vma->node.start, vma->node.size);
 157         }
 158         if (obj->stolen)
 159                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 160         if (obj->pin_mappable || obj->fault_mappable) {
 161                 char s[3], *t = s;
 162                 if (obj->pin_mappable)
 163                         *t++ = 'p';
 164                 if (obj->fault_mappable)
 165                         *t++ = 'f';
 166                 *t = '\0';
 167                 seq_printf(m, " (%s mappable)", s);
 168         }
 169         if (obj->last_read_req != NULL)
 170                 seq_printf(m, " (%s)",
 171                            i915_gem_request_get_ring(obj->last_read_req)->name);
 172         if (obj->frontbuffer_bits)
 173                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 174 }
 175
 176 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 177 {
 178         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 179         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 180         seq_putc(m, ' ');
 181 }
 182
 183 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 184 {
 185         struct drm_info_node *node = m->private;
 186         uintptr_t list = (uintptr_t) node->info_ent->data;
 187         struct list_head *head;
 188         struct drm_device *dev = node->minor->dev;
 189         struct drm_i915_private *dev_priv = dev->dev_private;
 190         struct i915_address_space *vm = &dev_priv->gtt.base;
 191         struct i915_vma *vma;
 192         size_t total_obj_size, total_gtt_size;
 193         int count, ret;
 194
 195         ret = mutex_lock_interruptible(&dev->struct_mutex);
 196         if (ret)
 197                 return ret;
 198
 199         /* FIXME: the user of this interface might want more than just GGTT */
 200         switch (list) {
 201         case ACTIVE_LIST:
 202                 seq_puts(m, "Active:\n");
 203                 head = &vm->active_list;
 204                 break;
 205         case INACTIVE_LIST:
 206                 seq_puts(m, "Inactive:\n");
 207                 head = &vm->inactive_list;
 208                 break;
 209         default:
 210                 mutex_unlock(&dev->struct_mutex);
 211                 return -EINVAL;
 212         }
 213
 214         total_obj_size = total_gtt_size = count = 0;
 215         list_for_each_entry(vma, head, mm_list) {
 216                 seq_printf(m, "   ");
 217                 describe_obj(m, vma->obj);
 218                 seq_printf(m, "\n");
 219                 total_obj_size += vma->obj->base.size;
 220                 total_gtt_size += vma->node.size;
 221                 count++;
 222         }
 223         mutex_unlock(&dev->struct_mutex);
 224
 225         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 226                    count, total_obj_size, total_gtt_size);
 227         return 0;
 228 }
 229
 230 static int obj_rank_by_stolen(void *priv,
 231                               struct list_head *A, struct list_head *B)
 232 {
 233         struct drm_i915_gem_object *a =
 234                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 235         struct drm_i915_gem_object *b =
 236                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 237
 238         return a->stolen->start - b->stolen->start;
 239 }
 240
 241 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 242 {
 243         struct drm_info_node *node = m->private;
 244         struct drm_device *dev = node->minor->dev;
 245         struct drm_i915_private *dev_priv = dev->dev_private;
 246         struct drm_i915_gem_object *obj;
 247         size_t total_obj_size, total_gtt_size;
 248         LIST_HEAD(stolen);
 249         int count, ret;
 250
 251         ret = mutex_lock_interruptible(&dev->struct_mutex);
 252         if (ret)
 253                 return ret;
 254
 255         total_obj_size = total_gtt_size = count = 0;
 256         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 257                 if (obj->stolen == NULL)
 258                         continue;
 259
 260                 list_add(&obj->obj_exec_link, &stolen);
 261
 262                 total_obj_size += obj->base.size;
 263                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 264                 count++;
 265         }
 266         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 267                 if (obj->stolen == NULL)
 268                         continue;
 269
 270                 list_add(&obj->obj_exec_link, &stolen);
 271
 272                 total_obj_size += obj->base.size;
 273                 count++;
 274         }
 275         list_sort(NULL, &stolen, obj_rank_by_stolen);
 276         seq_puts(m, "Stolen:\n");
 277         while (!list_empty(&stolen)) {
 278                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 279                 seq_puts(m, "   ");
 280                 describe_obj(m, obj);
 281                 seq_putc(m, '\n');
 282                 list_del_init(&obj->obj_exec_link);
 283         }
 284         mutex_unlock(&dev->struct_mutex);
 285
 286         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 287                    count, total_obj_size, total_gtt_size);
 288         return 0;
 289 }
 290
 291 #define count_objects(list, member) do { \
 292         list_for_each_entry(obj, list, member) { \
 293                 size += i915_gem_obj_ggtt_size(obj); \
 294                 ++count; \
 295                 if (obj->map_and_fenceable) { \
 296                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 297                         ++mappable_count; \
 298                 } \
 299         } \
 300 } while (0)
 301
 302 struct file_stats {
 303         struct drm_i915_file_private *file_priv;
 304         int count;
 305         size_t total, unbound;
 306         size_t global, shared;
 307         size_t active, inactive;
 308 };
 309
 310 static int per_file_stats(int id, void *ptr, void *data)
 311 {
 312         struct drm_i915_gem_object *obj = ptr;
 313         struct file_stats *stats = data;
 314         struct i915_vma *vma;
 315
 316         stats->count++;
 317         stats->total += obj->base.size;
 318
 319         if (obj->base.name || obj->base.dma_buf)
 320                 stats->shared += obj->base.size;
 321
 322         if (USES_FULL_PPGTT(obj->base.dev)) {
 323                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 324                         struct i915_hw_ppgtt *ppgtt;
 325
 326                         if (!drm_mm_node_allocated(&vma->node))
 327                                 continue;
 328
 329                         if (i915_is_ggtt(vma->vm)) {
 330                                 stats->global += obj->base.size;
 331                                 continue;
 332                         }
 333
 334                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 335                         if (ppgtt->file_priv != stats->file_priv)
 336                                 continue;
 337
 338                         if (obj->active) /* XXX per-vma statistic */
 339                                 stats->active += obj->base.size;
 340                         else
 341                                 stats->inactive += obj->base.size;
 342
 343                         return 0;
 344                 }
 345         } else {
 346                 if (i915_gem_obj_ggtt_bound(obj)) {
 347                         stats->global += obj->base.size;
 348                         if (obj->active)
 349                                 stats->active += obj->base.size;
 350                         else
 351                                 stats->inactive += obj->base.size;
 352                         return 0;
 353                 }
 354         }
 355
 356         if (!list_empty(&obj->global_list))
 357                 stats->unbound += obj->base.size;
 358
 359         return 0;
 360 }
 361
 362 #define count_vmas(list, member) do { \
 363         list_for_each_entry(vma, list, member) { \
 364                 size += i915_gem_obj_ggtt_size(vma->obj); \
 365                 ++count; \
 366                 if (vma->obj->map_and_fenceable) { \
 367                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 368                         ++mappable_count; \
 369                 } \
 370         } \
 371 } while (0)
 372
 373 static int i915_gem_object_info(struct seq_file *m, void* data)
 374 {
 375         struct drm_info_node *node = m->private;
 376         struct drm_device *dev = node->minor->dev;
 377         struct drm_i915_private *dev_priv = dev->dev_private;
 378         u32 count, mappable_count, purgeable_count;
 379         size_t size, mappable_size, purgeable_size;
 380         struct drm_i915_gem_object *obj;
 381         struct i915_address_space *vm = &dev_priv->gtt.base;
 382         struct drm_file *file;
 383         struct i915_vma *vma;
 384         int ret;
 385
 386         ret = mutex_lock_interruptible(&dev->struct_mutex);
 387         if (ret)
 388                 return ret;
 389
 390         seq_printf(m, "%u objects, %zu bytes\n",
 391                    dev_priv->mm.object_count,
 392                    dev_priv->mm.object_memory);
 393
 394         size = count = mappable_size = mappable_count = 0;
 395         count_objects(&dev_priv->mm.bound_list, global_list);
 396         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 397                    count, mappable_count, size, mappable_size);
 398
 399         size = count = mappable_size = mappable_count = 0;
 400         count_vmas(&vm->active_list, mm_list);
 401         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 402                    count, mappable_count, size, mappable_size);
 403
 404         size = count = mappable_size = mappable_count = 0;
 405         count_vmas(&vm->inactive_list, mm_list);
 406         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 407                    count, mappable_count, size, mappable_size);
 408
 409         size = count = purgeable_size = purgeable_count = 0;
 410         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 411                 size += obj->base.size, ++count;
 412                 if (obj->madv == I915_MADV_DONTNEED)
 413                         purgeable_size += obj->base.size, ++purgeable_count;
 414         }
 415         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 416
 417         size = count = mappable_size = mappable_count = 0;
 418         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 419                 if (obj->fault_mappable) {
 420                         size += i915_gem_obj_ggtt_size(obj);
 421                         ++count;
 422                 }
 423                 if (obj->pin_mappable) {
 424                         mappable_size += i915_gem_obj_ggtt_size(obj);
 425                         ++mappable_count;
 426                 }
 427                 if (obj->madv == I915_MADV_DONTNEED) {
 428                         purgeable_size += obj->base.size;
 429                         ++purgeable_count;
 430                 }
 431         }
 432         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 433                    purgeable_count, purgeable_size);
 434         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 435                    mappable_count, mappable_size);
 436         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 437                    count, size);
 438
 439         seq_printf(m, "%zu [%lu] gtt total\n",
 440                    dev_priv->gtt.base.total,
 441                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 442
 443         seq_putc(m, '\n');
 444         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 445                 struct file_stats stats;
 446                 struct task_struct *task;
 447
 448                 memset(&stats, 0, sizeof(stats));
 449                 stats.file_priv = file->driver_priv;
 450                 spin_lock(&file->table_lock);
 451                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 452                 spin_unlock(&file->table_lock);
 453                 /*
 454                  * Although we have a valid reference on file->pid, that does
 455                  * not guarantee that the task_struct who called get_pid() is
 456                  * still alive (e.g. get_pid(current) => fork() => exit()).
 457                  * Therefore, we need to protect this ->comm access using RCU.
 458                  */
 459                 rcu_read_lock();
 460                 task = pid_task(file->pid, PIDTYPE_PID);
 461                 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
 462                            task ? task->comm : "<unknown>",
 463                            stats.count,
 464                            stats.total,
 465                            stats.active,
 466                            stats.inactive,
 467                            stats.global,
 468                            stats.shared,
 469                            stats.unbound);
 470                 rcu_read_unlock();
 471         }
 472
 473         mutex_unlock(&dev->struct_mutex);
 474
 475         return 0;
 476 }
 477
 478 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 479 {
 480         struct drm_info_node *node = m->private;
 481         struct drm_device *dev = node->minor->dev;
 482         uintptr_t list = (uintptr_t) node->info_ent->data;
 483         struct drm_i915_private *dev_priv = dev->dev_private;
 484         struct drm_i915_gem_object *obj;
 485         size_t total_obj_size, total_gtt_size;
 486         int count, ret;
 487
 488         ret = mutex_lock_interruptible(&dev->struct_mutex);
 489         if (ret)
 490                 return ret;
 491
 492         total_obj_size = total_gtt_size = count = 0;
 493         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 494                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 495                         continue;
 496
 497                 seq_puts(m, "   ");
 498                 describe_obj(m, obj);
 499                 seq_putc(m, '\n');
 500                 total_obj_size += obj->base.size;
 501                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 502                 count++;
 503         }
 504
 505         mutex_unlock(&dev->struct_mutex);
 506
 507         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 508                    count, total_obj_size, total_gtt_size);
 509
 510         return 0;
 511 }
 512
 513 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 514 {
 515         struct drm_info_node *node = m->private;
 516         struct drm_device *dev = node->minor->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         struct intel_crtc *crtc;
 519         int ret;
 520
 521         ret = mutex_lock_interruptible(&dev->struct_mutex);
 522         if (ret)
 523                 return ret;
 524
 525         for_each_intel_crtc(dev, crtc) {
 526                 const char pipe = pipe_name(crtc->pipe);
 527                 const char plane = plane_name(crtc->plane);
 528                 struct intel_unpin_work *work;
 529
 530                 spin_lock_irq(&dev->event_lock);
 531                 work = crtc->unpin_work;
 532                 if (work == NULL) {
 533                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 534                                    pipe, plane);
 535                 } else {
 536                         u32 addr;
 537
 538                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 539                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 540                                            pipe, plane);
 541                         } else {
 542                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 543                                            pipe, plane);
 544                         }
 545                         if (work->flip_queued_req) {
 546                                 struct intel_engine_cs *ring =
 547                                         i915_gem_request_get_ring(work->flip_queued_req);
 548
 549                                 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
 550                                            ring->name,
 551                                            i915_gem_request_get_seqno(work->flip_queued_req),
 552                                            dev_priv->next_seqno,
 553                                            ring->get_seqno(ring, true),
 554                                            i915_gem_request_completed(work->flip_queued_req, true));
 555                         } else
 556                                 seq_printf(m, "Flip not associated with any ring\n");
 557                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 558                                    work->flip_queued_vblank,
 559                                    work->flip_ready_vblank,
 560                                    drm_vblank_count(dev, crtc->pipe));
 561                         if (work->enable_stall_check)
 562                                 seq_puts(m, "Stall check enabled, ");
 563                         else
 564                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 565                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 566
 567                         if (INTEL_INFO(dev)->gen >= 4)
 568                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 569                         else
 570                                 addr = I915_READ(DSPADDR(crtc->plane));
 571                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 572
 573                         if (work->pending_flip_obj) {
 574                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 575                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 576                         }
 577                 }
 578                 spin_unlock_irq(&dev->event_lock);
 579         }
 580
 581         mutex_unlock(&dev->struct_mutex);
 582
 583         return 0;
 584 }
 585
 586 static int i915_gem_request_info(struct seq_file *m, void *data)
 587 {
 588         struct drm_info_node *node = m->private;
 589         struct drm_device *dev = node->minor->dev;
 590         struct drm_i915_private *dev_priv = dev->dev_private;
 591         struct intel_engine_cs *ring;
 592         struct drm_i915_gem_request *gem_request;
 593         int ret, count, i;
 594
 595         ret = mutex_lock_interruptible(&dev->struct_mutex);
 596         if (ret)
 597                 return ret;
 598
 599         count = 0;
 600         for_each_ring(ring, dev_priv, i) {
 601                 if (list_empty(&ring->request_list))
 602                         continue;
 603
 604                 seq_printf(m, "%s requests:\n", ring->name);
 605                 list_for_each_entry(gem_request,
 606                                     &ring->request_list,
 607                                     list) {
 608                         seq_printf(m, "    %d @ %d\n",
 609                                    gem_request->seqno,
 610                                    (int) (jiffies - gem_request->emitted_jiffies));
 611                 }
 612                 count++;
 613         }
 614         mutex_unlock(&dev->struct_mutex);
 615
 616         if (count == 0)
 617                 seq_puts(m, "No requests\n");
 618
 619         return 0;
 620 }
 621
 622 static void i915_ring_seqno_info(struct seq_file *m,
 623                                  struct intel_engine_cs *ring)
 624 {
 625         if (ring->get_seqno) {
 626                 seq_printf(m, "Current sequence (%s): %u\n",
 627                            ring->name, ring->get_seqno(ring, false));
 628         }
 629 }
 630
 631 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 632 {
 633         struct drm_info_node *node = m->private;
 634         struct drm_device *dev = node->minor->dev;
 635         struct drm_i915_private *dev_priv = dev->dev_private;
 636         struct intel_engine_cs *ring;
 637         int ret, i;
 638
 639         ret = mutex_lock_interruptible(&dev->struct_mutex);
 640         if (ret)
 641                 return ret;
 642         intel_runtime_pm_get(dev_priv);
 643
 644         for_each_ring(ring, dev_priv, i)
 645                 i915_ring_seqno_info(m, ring);
 646
 647         intel_runtime_pm_put(dev_priv);
 648         mutex_unlock(&dev->struct_mutex);
 649
 650         return 0;
 651 }
 652
 653
 654 static int i915_interrupt_info(struct seq_file *m, void *data)
 655 {
 656         struct drm_info_node *node = m->private;
 657         struct drm_device *dev = node->minor->dev;
 658         struct drm_i915_private *dev_priv = dev->dev_private;
 659         struct intel_engine_cs *ring;
 660         int ret, i, pipe;
 661
 662         ret = mutex_lock_interruptible(&dev->struct_mutex);
 663         if (ret)
 664                 return ret;
 665         intel_runtime_pm_get(dev_priv);
 666
 667         if (IS_CHERRYVIEW(dev)) {
 668                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 669                            I915_READ(GEN8_MASTER_IRQ));
 670
 671                 seq_printf(m, "Display IER:\t%08x\n",
 672                            I915_READ(VLV_IER));
 673                 seq_printf(m, "Display IIR:\t%08x\n",
 674                            I915_READ(VLV_IIR));
 675                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 676                            I915_READ(VLV_IIR_RW));
 677                 seq_printf(m, "Display IMR:\t%08x\n",
 678                            I915_READ(VLV_IMR));
 679                 for_each_pipe(dev_priv, pipe)
 680                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 681                                    pipe_name(pipe),
 682                                    I915_READ(PIPESTAT(pipe)));
 683
 684                 seq_printf(m, "Port hotplug:\t%08x\n",
 685                            I915_READ(PORT_HOTPLUG_EN));
 686                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 687                            I915_READ(VLV_DPFLIPSTAT));
 688                 seq_printf(m, "DPINVGTT:\t%08x\n",
 689                            I915_READ(DPINVGTT));
 690
 691                 for (i = 0; i < 4; i++) {
 692                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 693                                    i, I915_READ(GEN8_GT_IMR(i)));
 694                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 695                                    i, I915_READ(GEN8_GT_IIR(i)));
 696                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 697                                    i, I915_READ(GEN8_GT_IER(i)));
 698                 }
 699
 700                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 701                            I915_READ(GEN8_PCU_IMR));
 702                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 703                            I915_READ(GEN8_PCU_IIR));
 704                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 705                            I915_READ(GEN8_PCU_IER));
 706         } else if (INTEL_INFO(dev)->gen >= 8) {
 707                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 708                            I915_READ(GEN8_MASTER_IRQ));
 709
 710                 for (i = 0; i < 4; i++) {
 711                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 712                                    i, I915_READ(GEN8_GT_IMR(i)));
 713                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 714                                    i, I915_READ(GEN8_GT_IIR(i)));
 715                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 716                                    i, I915_READ(GEN8_GT_IER(i)));
 717                 }
 718
 719                 for_each_pipe(dev_priv, pipe) {
 720                         if (!intel_display_power_is_enabled(dev_priv,
 721                                                 POWER_DOMAIN_PIPE(pipe))) {
 722                                 seq_printf(m, "Pipe %c power disabled\n",
 723                                            pipe_name(pipe));
 724                                 continue;
 725                         }
 726                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 727                                    pipe_name(pipe),
 728                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 729                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 730                                    pipe_name(pipe),
 731                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 732                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 733                                    pipe_name(pipe),
 734                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 735                 }
 736
 737                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 738                            I915_READ(GEN8_DE_PORT_IMR));
 739                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 740                            I915_READ(GEN8_DE_PORT_IIR));
 741                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 742                            I915_READ(GEN8_DE_PORT_IER));
 743
 744                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 745                            I915_READ(GEN8_DE_MISC_IMR));
 746                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 747                            I915_READ(GEN8_DE_MISC_IIR));
 748                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 749                            I915_READ(GEN8_DE_MISC_IER));
 750
 751                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 752                            I915_READ(GEN8_PCU_IMR));
 753                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 754                            I915_READ(GEN8_PCU_IIR));
 755                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 756                            I915_READ(GEN8_PCU_IER));
 757         } else if (IS_VALLEYVIEW(dev)) {
 758                 seq_printf(m, "Display IER:\t%08x\n",
 759                            I915_READ(VLV_IER));
 760                 seq_printf(m, "Display IIR:\t%08x\n",
 761                            I915_READ(VLV_IIR));
 762                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 763                            I915_READ(VLV_IIR_RW));
 764                 seq_printf(m, "Display IMR:\t%08x\n",
 765                            I915_READ(VLV_IMR));
 766                 for_each_pipe(dev_priv, pipe)
 767                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 768                                    pipe_name(pipe),
 769                                    I915_READ(PIPESTAT(pipe)));
 770
 771                 seq_printf(m, "Master IER:\t%08x\n",
 772                            I915_READ(VLV_MASTER_IER));
 773
 774                 seq_printf(m, "Render IER:\t%08x\n",
 775                            I915_READ(GTIER));
 776                 seq_printf(m, "Render IIR:\t%08x\n",
 777                            I915_READ(GTIIR));
 778                 seq_printf(m, "Render IMR:\t%08x\n",
 779                            I915_READ(GTIMR));
 780
 781                 seq_printf(m, "PM IER:\t\t%08x\n",
 782                            I915_READ(GEN6_PMIER));
 783                 seq_printf(m, "PM IIR:\t\t%08x\n",
 784                            I915_READ(GEN6_PMIIR));
 785                 seq_printf(m, "PM IMR:\t\t%08x\n",
 786                            I915_READ(GEN6_PMIMR));
 787
 788                 seq_printf(m, "Port hotplug:\t%08x\n",
 789                            I915_READ(PORT_HOTPLUG_EN));
 790                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 791                            I915_READ(VLV_DPFLIPSTAT));
 792                 seq_printf(m, "DPINVGTT:\t%08x\n",
 793                            I915_READ(DPINVGTT));
 794
 795         } else if (!HAS_PCH_SPLIT(dev)) {
 796                 seq_printf(m, "Interrupt enable:    %08x\n",
 797                            I915_READ(IER));
 798                 seq_printf(m, "Interrupt identity:  %08x\n",
 799                            I915_READ(IIR));
 800                 seq_printf(m, "Interrupt mask:      %08x\n",
 801                            I915_READ(IMR));
 802                 for_each_pipe(dev_priv, pipe)
 803                         seq_printf(m, "Pipe %c stat:         %08x\n",
 804                                    pipe_name(pipe),
 805                                    I915_READ(PIPESTAT(pipe)));
 806         } else {
 807                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 808                            I915_READ(DEIER));
 809                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 810                            I915_READ(DEIIR));
 811                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 812                            I915_READ(DEIMR));
 813                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 814                            I915_READ(SDEIER));
 815                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 816                            I915_READ(SDEIIR));
 817                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 818                            I915_READ(SDEIMR));
 819                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 820                            I915_READ(GTIER));
 821                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 822                            I915_READ(GTIIR));
 823                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 824                            I915_READ(GTIMR));
 825         }
 826         for_each_ring(ring, dev_priv, i) {
 827                 if (INTEL_INFO(dev)->gen >= 6) {
 828                         seq_printf(m,
 829                                    "Graphics Interrupt mask (%s):       %08x\n",
 830                                    ring->name, I915_READ_IMR(ring));
 831                 }
 832                 i915_ring_seqno_info(m, ring);
 833         }
 834         intel_runtime_pm_put(dev_priv);
 835         mutex_unlock(&dev->struct_mutex);
 836
 837         return 0;
 838 }
 839
 840 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 841 {
 842         struct drm_info_node *node = m->private;
 843         struct drm_device *dev = node->minor->dev;
 844         struct drm_i915_private *dev_priv = dev->dev_private;
 845         int i, ret;
 846
 847         ret = mutex_lock_interruptible(&dev->struct_mutex);
 848         if (ret)
 849                 return ret;
 850
 851         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 852         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 853         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 854                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 855
 856                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 857                            i, dev_priv->fence_regs[i].pin_count);
 858                 if (obj == NULL)
 859                         seq_puts(m, "unused");
 860                 else
 861                         describe_obj(m, obj);
 862                 seq_putc(m, '\n');
 863         }
 864
 865         mutex_unlock(&dev->struct_mutex);
 866         return 0;
 867 }
 868
 869 static int i915_hws_info(struct seq_file *m, void *data)
 870 {
 871         struct drm_info_node *node = m->private;
 872         struct drm_device *dev = node->minor->dev;
 873         struct drm_i915_private *dev_priv = dev->dev_private;
 874         struct intel_engine_cs *ring;
 875         const u32 *hws;
 876         int i;
 877
 878         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 879         hws = ring->status_page.page_addr;
 880         if (hws == NULL)
 881                 return 0;
 882
 883         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 884                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 885                            i * 4,
 886                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 887         }
 888         return 0;
 889 }
 890
 891 static ssize_t
 892 i915_error_state_write(struct file *filp,
 893                        const char __user *ubuf,
 894                        size_t cnt,
 895                        loff_t *ppos)
 896 {
 897         struct i915_error_state_file_priv *error_priv = filp->private_data;
 898         struct drm_device *dev = error_priv->dev;
 899         int ret;
 900
 901         DRM_DEBUG_DRIVER("Resetting error state\n");
 902
 903         ret = mutex_lock_interruptible(&dev->struct_mutex);
 904         if (ret)
 905                 return ret;
 906
 907         i915_destroy_error_state(dev);
 908         mutex_unlock(&dev->struct_mutex);
 909
 910         return cnt;
 911 }
 912
 913 static int i915_error_state_open(struct inode *inode, struct file *file)
 914 {
 915         struct drm_device *dev = inode->i_private;
 916         struct i915_error_state_file_priv *error_priv;
 917
 918         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 919         if (!error_priv)
 920                 return -ENOMEM;
 921
 922         error_priv->dev = dev;
 923
 924         i915_error_state_get(dev, error_priv);
 925
 926         file->private_data = error_priv;
 927
 928         return 0;
 929 }
 930
 931 static int i915_error_state_release(struct inode *inode, struct file *file)
 932 {
 933         struct i915_error_state_file_priv *error_priv = file->private_data;
 934
 935         i915_error_state_put(error_priv);
 936         kfree(error_priv);
 937
 938         return 0;
 939 }
 940
 941 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 942                                      size_t count, loff_t *pos)
 943 {
 944         struct i915_error_state_file_priv *error_priv = file->private_data;
 945         struct drm_i915_error_state_buf error_str;
 946         loff_t tmp_pos = 0;
 947         ssize_t ret_count = 0;
 948         int ret;
 949
 950         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
 951         if (ret)
 952                 return ret;
 953
 954         ret = i915_error_state_to_str(&error_str, error_priv);
 955         if (ret)
 956                 goto out;
 957
 958         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
 959                                             error_str.buf,
 960                                             error_str.bytes);
 961
 962         if (ret_count < 0)
 963                 ret = ret_count;
 964         else
 965                 *pos = error_str.start + ret_count;
 966 out:
 967         i915_error_state_buf_release(&error_str);
 968         return ret ?: ret_count;
 969 }
 970
 971 static const struct file_operations i915_error_state_fops = {
 972         .owner = THIS_MODULE,
 973         .open = i915_error_state_open,
 974         .read = i915_error_state_read,
 975         .write = i915_error_state_write,
 976         .llseek = default_llseek,
 977         .release = i915_error_state_release,
 978 };
 979
 980 static int
 981 i915_next_seqno_get(void *data, u64 *val)
 982 {
 983         struct drm_device *dev = data;
 984         struct drm_i915_private *dev_priv = dev->dev_private;
 985         int ret;
 986
 987         ret = mutex_lock_interruptible(&dev->struct_mutex);
 988         if (ret)
 989                 return ret;
 990
 991         *val = dev_priv->next_seqno;
 992         mutex_unlock(&dev->struct_mutex);
 993
 994         return 0;
 995 }
 996
 997 static int
 998 i915_next_seqno_set(void *data, u64 val)
 999 {
1000         struct drm_device *dev = data;
1001         int ret;
1002
1003         ret = mutex_lock_interruptible(&dev->struct_mutex);
1004         if (ret)
1005                 return ret;
1006
1007         ret = i915_gem_set_seqno(dev, val);
1008         mutex_unlock(&dev->struct_mutex);
1009
1010         return ret;
1011 }
1012
1013 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1014                         i915_next_seqno_get, i915_next_seqno_set,
1015                         "0x%llx\n");
1016
1017 static int i915_frequency_info(struct seq_file *m, void *unused)
1018 {
1019         struct drm_info_node *node = m->private;
1020         struct drm_device *dev = node->minor->dev;
1021         struct drm_i915_private *dev_priv = dev->dev_private;
1022         int ret = 0;
1023
1024         intel_runtime_pm_get(dev_priv);
1025
1026         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1027
1028         if (IS_GEN5(dev)) {
1029                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1030                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1031
1032                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1033                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1034                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1035                            MEMSTAT_VID_SHIFT);
1036                 seq_printf(m, "Current P-state: %d\n",
1037                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1038         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1039                    IS_BROADWELL(dev)) {
1040                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1041                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1042                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1043                 u32 rpmodectl, rpinclimit, rpdeclimit;
1044                 u32 rpstat, cagf, reqf;
1045                 u32 rpupei, rpcurup, rpprevup;
1046                 u32 rpdownei, rpcurdown, rpprevdown;
1047                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1048                 int max_freq;
1049
1050                 /* RPSTAT1 is in the GT power well */
1051                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1052                 if (ret)
1053                         goto out;
1054
1055                 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
1056
1057                 reqf = I915_READ(GEN6_RPNSWREQ);
1058                 reqf &= ~GEN6_TURBO_DISABLE;
1059                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1060                         reqf >>= 24;
1061                 else
1062                         reqf >>= 25;
1063                 reqf *= GT_FREQUENCY_MULTIPLIER;
1064
1065                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1066                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1067                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1068
1069                 rpstat = I915_READ(GEN6_RPSTAT1);
1070                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1071                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1072                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1073                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1074                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1075                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1076                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1077                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1078                 else
1079                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1080                 cagf *= GT_FREQUENCY_MULTIPLIER;
1081
1082                 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
1083                 mutex_unlock(&dev->struct_mutex);
1084
1085                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1086                         pm_ier = I915_READ(GEN6_PMIER);
1087                         pm_imr = I915_READ(GEN6_PMIMR);
1088                         pm_isr = I915_READ(GEN6_PMISR);
1089                         pm_iir = I915_READ(GEN6_PMIIR);
1090                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1091                 } else {
1092                         pm_ier = I915_READ(GEN8_GT_IER(2));
1093                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1094                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1095                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1096                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1097                 }
1098                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1099                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1100                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1101                 seq_printf(m, "Render p-state ratio: %d\n",
1102                            (gt_perf_status & 0xff00) >> 8);
1103                 seq_printf(m, "Render p-state VID: %d\n",
1104                            gt_perf_status & 0xff);
1105                 seq_printf(m, "Render p-state limit: %d\n",
1106                            rp_state_limits & 0xff);
1107                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1108                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1109                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1110                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1111                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1112                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1113                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1114                            GEN6_CURICONT_MASK);
1115                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1116                            GEN6_CURBSYTAVG_MASK);
1117                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1118                            GEN6_CURBSYTAVG_MASK);
1119                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1120                            GEN6_CURIAVG_MASK);
1121                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1122                            GEN6_CURBSYTAVG_MASK);
1123                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1124                            GEN6_CURBSYTAVG_MASK);
1125
1126                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1127                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1128                            max_freq * GT_FREQUENCY_MULTIPLIER);
1129
1130                 max_freq = (rp_state_cap & 0xff00) >> 8;
1131                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1132                            max_freq * GT_FREQUENCY_MULTIPLIER);
1133
1134                 max_freq = rp_state_cap & 0xff;
1135                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1136                            max_freq * GT_FREQUENCY_MULTIPLIER);
1137
1138                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1139                            dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
1140         } else if (IS_VALLEYVIEW(dev)) {
1141                 u32 freq_sts;
1142
1143                 mutex_lock(&dev_priv->rps.hw_lock);
1144                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1145                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1146                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1147
1148                 seq_printf(m, "max GPU freq: %d MHz\n",
1149                            vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1150
1151                 seq_printf(m, "min GPU freq: %d MHz\n",
1152                            vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1153
1154                 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
1155                            vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1156
1157                 seq_printf(m, "current GPU freq: %d MHz\n",
1158                            vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1159                 mutex_unlock(&dev_priv->rps.hw_lock);
1160         } else {
1161                 seq_puts(m, "no P-state info available\n");
1162         }
1163
1164 out:
1165         intel_runtime_pm_put(dev_priv);
1166         return ret;
1167 }
1168
1169 static int ironlake_drpc_info(struct seq_file *m)
1170 {
1171         struct drm_info_node *node = m->private;
1172         struct drm_device *dev = node->minor->dev;
1173         struct drm_i915_private *dev_priv = dev->dev_private;
1174         u32 rgvmodectl, rstdbyctl;
1175         u16 crstandvid;
1176         int ret;
1177
1178         ret = mutex_lock_interruptible(&dev->struct_mutex);
1179         if (ret)
1180                 return ret;
1181         intel_runtime_pm_get(dev_priv);
1182
1183         rgvmodectl = I915_READ(MEMMODECTL);
1184         rstdbyctl = I915_READ(RSTDBYCTL);
1185         crstandvid = I915_READ16(CRSTANDVID);
1186
1187         intel_runtime_pm_put(dev_priv);
1188         mutex_unlock(&dev->struct_mutex);
1189
1190         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1191                    "yes" : "no");
1192         seq_printf(m, "Boost freq: %d\n",
1193                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1194                    MEMMODE_BOOST_FREQ_SHIFT);
1195         seq_printf(m, "HW control enabled: %s\n",
1196                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1197         seq_printf(m, "SW control enabled: %s\n",
1198                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1199         seq_printf(m, "Gated voltage change: %s\n",
1200                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1201         seq_printf(m, "Starting frequency: P%d\n",
1202                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1203         seq_printf(m, "Max P-state: P%d\n",
1204                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1205         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1206         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1207         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1208         seq_printf(m, "Render standby enabled: %s\n",
1209                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1210         seq_puts(m, "Current RS state: ");
1211         switch (rstdbyctl & RSX_STATUS_MASK) {
1212         case RSX_STATUS_ON:
1213                 seq_puts(m, "on\n");
1214                 break;
1215         case RSX_STATUS_RC1:
1216                 seq_puts(m, "RC1\n");
1217                 break;
1218         case RSX_STATUS_RC1E:
1219                 seq_puts(m, "RC1E\n");
1220                 break;
1221         case RSX_STATUS_RS1:
1222                 seq_puts(m, "RS1\n");
1223                 break;
1224         case RSX_STATUS_RS2:
1225                 seq_puts(m, "RS2 (RC6)\n");
1226                 break;
1227         case RSX_STATUS_RS3:
1228                 seq_puts(m, "RC3 (RC6+)\n");
1229                 break;
1230         default:
1231                 seq_puts(m, "unknown\n");
1232                 break;
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int vlv_drpc_info(struct seq_file *m)
1239 {
1240
1241         struct drm_info_node *node = m->private;
1242         struct drm_device *dev = node->minor->dev;
1243         struct drm_i915_private *dev_priv = dev->dev_private;
1244         u32 rpmodectl1, rcctl1, pw_status;
1245         unsigned fw_rendercount = 0, fw_mediacount = 0;
1246
1247         intel_runtime_pm_get(dev_priv);
1248
1249         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1250         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1251         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1252
1253         intel_runtime_pm_put(dev_priv);
1254
1255         seq_printf(m, "Video Turbo Mode: %s\n",
1256                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1257         seq_printf(m, "Turbo enabled: %s\n",
1258                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1259         seq_printf(m, "HW control enabled: %s\n",
1260                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1261         seq_printf(m, "SW control enabled: %s\n",
1262                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1263                           GEN6_RP_MEDIA_SW_MODE));
1264         seq_printf(m, "RC6 Enabled: %s\n",
1265                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1266                                         GEN6_RC_CTL_EI_MODE(1))));
1267         seq_printf(m, "Render Power Well: %s\n",
1268                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1269         seq_printf(m, "Media Power Well: %s\n",
1270                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1271
1272         seq_printf(m, "Render RC6 residency since boot: %u\n",
1273                    I915_READ(VLV_GT_RENDER_RC6));
1274         seq_printf(m, "Media RC6 residency since boot: %u\n",
1275                    I915_READ(VLV_GT_MEDIA_RC6));
1276
1277         spin_lock_irq(&dev_priv->uncore.lock);
1278         fw_rendercount = dev_priv->uncore.fw_rendercount;
1279         fw_mediacount = dev_priv->uncore.fw_mediacount;
1280         spin_unlock_irq(&dev_priv->uncore.lock);
1281
1282         seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1283         seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1284
1285
1286         return 0;
1287 }
1288
1289
1290 static int gen6_drpc_info(struct seq_file *m)
1291 {
1292
1293         struct drm_info_node *node = m->private;
1294         struct drm_device *dev = node->minor->dev;
1295         struct drm_i915_private *dev_priv = dev->dev_private;
1296         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1297         unsigned forcewake_count;
1298         int count = 0, ret;
1299
1300         ret = mutex_lock_interruptible(&dev->struct_mutex);
1301         if (ret)
1302                 return ret;
1303         intel_runtime_pm_get(dev_priv);
1304
1305         spin_lock_irq(&dev_priv->uncore.lock);
1306         forcewake_count = dev_priv->uncore.forcewake_count;
1307         spin_unlock_irq(&dev_priv->uncore.lock);
1308
1309         if (forcewake_count) {
1310                 seq_puts(m, "RC information inaccurate because somebody "
1311                             "holds a forcewake reference \n");
1312         } else {
1313                 /* NB: we cannot use forcewake, else we read the wrong values */
1314                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1315                         udelay(10);
1316                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1317         }
1318
1319         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1320         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1321
1322         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1323         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1324         mutex_unlock(&dev->struct_mutex);
1325         mutex_lock(&dev_priv->rps.hw_lock);
1326         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1327         mutex_unlock(&dev_priv->rps.hw_lock);
1328
1329         intel_runtime_pm_put(dev_priv);
1330
1331         seq_printf(m, "Video Turbo Mode: %s\n",
1332                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1333         seq_printf(m, "HW control enabled: %s\n",
1334                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1335         seq_printf(m, "SW control enabled: %s\n",
1336                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1337                           GEN6_RP_MEDIA_SW_MODE));
1338         seq_printf(m, "RC1e Enabled: %s\n",
1339                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1340         seq_printf(m, "RC6 Enabled: %s\n",
1341                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1342         seq_printf(m, "Deep RC6 Enabled: %s\n",
1343                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1344         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1345                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1346         seq_puts(m, "Current RC state: ");
1347         switch (gt_core_status & GEN6_RCn_MASK) {
1348         case GEN6_RC0:
1349                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1350                         seq_puts(m, "Core Power Down\n");
1351                 else
1352                         seq_puts(m, "on\n");
1353                 break;
1354         case GEN6_RC3:
1355                 seq_puts(m, "RC3\n");
1356                 break;
1357         case GEN6_RC6:
1358                 seq_puts(m, "RC6\n");
1359                 break;
1360         case GEN6_RC7:
1361                 seq_puts(m, "RC7\n");
1362                 break;
1363         default:
1364                 seq_puts(m, "Unknown\n");
1365                 break;
1366         }
1367
1368         seq_printf(m, "Core Power Down: %s\n",
1369                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1370
1371         /* Not exactly sure what this is */
1372         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1373                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1374         seq_printf(m, "RC6 residency since boot: %u\n",
1375                    I915_READ(GEN6_GT_GFX_RC6));
1376         seq_printf(m, "RC6+ residency since boot: %u\n",
1377                    I915_READ(GEN6_GT_GFX_RC6p));
1378         seq_printf(m, "RC6++ residency since boot: %u\n",
1379                    I915_READ(GEN6_GT_GFX_RC6pp));
1380
1381         seq_printf(m, "RC6   voltage: %dmV\n",
1382                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1383         seq_printf(m, "RC6+  voltage: %dmV\n",
1384                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1385         seq_printf(m, "RC6++ voltage: %dmV\n",
1386                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1387         return 0;
1388 }
1389
1390 static int i915_drpc_info(struct seq_file *m, void *unused)
1391 {
1392         struct drm_info_node *node = m->private;
1393         struct drm_device *dev = node->minor->dev;
1394
1395         if (IS_VALLEYVIEW(dev))
1396                 return vlv_drpc_info(m);
1397         else if (INTEL_INFO(dev)->gen >= 6)
1398                 return gen6_drpc_info(m);
1399         else
1400                 return ironlake_drpc_info(m);
1401 }
1402
1403 static int i915_fbc_status(struct seq_file *m, void *unused)
1404 {
1405         struct drm_info_node *node = m->private;
1406         struct drm_device *dev = node->minor->dev;
1407         struct drm_i915_private *dev_priv = dev->dev_private;
1408
1409         if (!HAS_FBC(dev)) {
1410                 seq_puts(m, "FBC unsupported on this chipset\n");
1411                 return 0;
1412         }
1413
1414         intel_runtime_pm_get(dev_priv);
1415
1416         if (intel_fbc_enabled(dev)) {
1417                 seq_puts(m, "FBC enabled\n");
1418         } else {
1419                 seq_puts(m, "FBC disabled: ");
1420                 switch (dev_priv->fbc.no_fbc_reason) {
1421                 case FBC_OK:
1422                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1423                         break;
1424                 case FBC_UNSUPPORTED:
1425                         seq_puts(m, "unsupported by this chipset");
1426                         break;
1427                 case FBC_NO_OUTPUT:
1428                         seq_puts(m, "no outputs");
1429                         break;
1430                 case FBC_STOLEN_TOO_SMALL:
1431                         seq_puts(m, "not enough stolen memory");
1432                         break;
1433                 case FBC_UNSUPPORTED_MODE:
1434                         seq_puts(m, "mode not supported");
1435                         break;
1436                 case FBC_MODE_TOO_LARGE:
1437                         seq_puts(m, "mode too large");
1438                         break;
1439                 case FBC_BAD_PLANE:
1440                         seq_puts(m, "FBC unsupported on plane");
1441                         break;
1442                 case FBC_NOT_TILED:
1443                         seq_puts(m, "scanout buffer not tiled");
1444                         break;
1445                 case FBC_MULTIPLE_PIPES:
1446                         seq_puts(m, "multiple pipes are enabled");
1447                         break;
1448                 case FBC_MODULE_PARAM:
1449                         seq_puts(m, "disabled per module param (default off)");
1450                         break;
1451                 case FBC_CHIP_DEFAULT:
1452                         seq_puts(m, "disabled per chip default");
1453                         break;
1454                 default:
1455                         seq_puts(m, "unknown reason");
1456                 }
1457                 seq_putc(m, '\n');
1458         }
1459
1460         intel_runtime_pm_put(dev_priv);
1461
1462         return 0;
1463 }
1464
1465 static int i915_fbc_fc_get(void *data, u64 *val)
1466 {
1467         struct drm_device *dev = data;
1468         struct drm_i915_private *dev_priv = dev->dev_private;
1469
1470         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1471                 return -ENODEV;
1472
1473         drm_modeset_lock_all(dev);
1474         *val = dev_priv->fbc.false_color;
1475         drm_modeset_unlock_all(dev);
1476
1477         return 0;
1478 }
1479
1480 static int i915_fbc_fc_set(void *data, u64 val)
1481 {
1482         struct drm_device *dev = data;
1483         struct drm_i915_private *dev_priv = dev->dev_private;
1484         u32 reg;
1485
1486         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1487                 return -ENODEV;
1488
1489         drm_modeset_lock_all(dev);
1490
1491         reg = I915_READ(ILK_DPFC_CONTROL);
1492         dev_priv->fbc.false_color = val;
1493
1494         I915_WRITE(ILK_DPFC_CONTROL, val ?
1495                    (reg | FBC_CTL_FALSE_COLOR) :
1496                    (reg & ~FBC_CTL_FALSE_COLOR));
1497
1498         drm_modeset_unlock_all(dev);
1499         return 0;
1500 }
1501
1502 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1503                         i915_fbc_fc_get, i915_fbc_fc_set,
1504                         "%llu\n");
1505
1506 static int i915_ips_status(struct seq_file *m, void *unused)
1507 {
1508         struct drm_info_node *node = m->private;
1509         struct drm_device *dev = node->minor->dev;
1510         struct drm_i915_private *dev_priv = dev->dev_private;
1511
1512         if (!HAS_IPS(dev)) {
1513                 seq_puts(m, "not supported\n");
1514                 return 0;
1515         }
1516
1517         intel_runtime_pm_get(dev_priv);
1518
1519         seq_printf(m, "Enabled by kernel parameter: %s\n",
1520                    yesno(i915.enable_ips));
1521
1522         if (INTEL_INFO(dev)->gen >= 8) {
1523                 seq_puts(m, "Currently: unknown\n");
1524         } else {
1525                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1526                         seq_puts(m, "Currently: enabled\n");
1527                 else
1528                         seq_puts(m, "Currently: disabled\n");
1529         }
1530
1531         intel_runtime_pm_put(dev_priv);
1532
1533         return 0;
1534 }
1535
1536 static int i915_sr_status(struct seq_file *m, void *unused)
1537 {
1538         struct drm_info_node *node = m->private;
1539         struct drm_device *dev = node->minor->dev;
1540         struct drm_i915_private *dev_priv = dev->dev_private;
1541         bool sr_enabled = false;
1542
1543         intel_runtime_pm_get(dev_priv);
1544
1545         if (HAS_PCH_SPLIT(dev))
1546                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1547         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1548                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1549         else if (IS_I915GM(dev))
1550                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1551         else if (IS_PINEVIEW(dev))
1552                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1553
1554         intel_runtime_pm_put(dev_priv);
1555
1556         seq_printf(m, "self-refresh: %s\n",
1557                    sr_enabled ? "enabled" : "disabled");
1558
1559         return 0;
1560 }
1561
1562 static int i915_emon_status(struct seq_file *m, void *unused)
1563 {
1564         struct drm_info_node *node = m->private;
1565         struct drm_device *dev = node->minor->dev;
1566         struct drm_i915_private *dev_priv = dev->dev_private;
1567         unsigned long temp, chipset, gfx;
1568         int ret;
1569
1570         if (!IS_GEN5(dev))
1571                 return -ENODEV;
1572
1573         ret = mutex_lock_interruptible(&dev->struct_mutex);
1574         if (ret)
1575                 return ret;
1576
1577         temp = i915_mch_val(dev_priv);
1578         chipset = i915_chipset_val(dev_priv);
1579         gfx = i915_gfx_val(dev_priv);
1580         mutex_unlock(&dev->struct_mutex);
1581
1582         seq_printf(m, "GMCH temp: %ld\n", temp);
1583         seq_printf(m, "Chipset power: %ld\n", chipset);
1584         seq_printf(m, "GFX power: %ld\n", gfx);
1585         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1586
1587         return 0;
1588 }
1589
1590 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1591 {
1592         struct drm_info_node *node = m->private;
1593         struct drm_device *dev = node->minor->dev;
1594         struct drm_i915_private *dev_priv = dev->dev_private;
1595         int ret = 0;
1596         int gpu_freq, ia_freq;
1597
1598         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1599                 seq_puts(m, "unsupported on this chipset\n");
1600                 return 0;
1601         }
1602
1603         intel_runtime_pm_get(dev_priv);
1604
1605         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1606
1607         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1608         if (ret)
1609                 goto out;
1610
1611         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1612
1613         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1614              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1615              gpu_freq++) {
1616                 ia_freq = gpu_freq;
1617                 sandybridge_pcode_read(dev_priv,
1618                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1619                                        &ia_freq);
1620                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1621                            gpu_freq * GT_FREQUENCY_MULTIPLIER,
1622                            ((ia_freq >> 0) & 0xff) * 100,
1623                            ((ia_freq >> 8) & 0xff) * 100);
1624         }
1625
1626         mutex_unlock(&dev_priv->rps.hw_lock);
1627
1628 out:
1629         intel_runtime_pm_put(dev_priv);
1630         return ret;
1631 }
1632
1633 static int i915_opregion(struct seq_file *m, void *unused)
1634 {
1635         struct drm_info_node *node = m->private;
1636         struct drm_device *dev = node->minor->dev;
1637         struct drm_i915_private *dev_priv = dev->dev_private;
1638         struct intel_opregion *opregion = &dev_priv->opregion;
1639         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1640         int ret;
1641
1642         if (data == NULL)
1643                 return -ENOMEM;
1644
1645         ret = mutex_lock_interruptible(&dev->struct_mutex);
1646         if (ret)
1647                 goto out;
1648
1649         if (opregion->header) {
1650                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1651                 seq_write(m, data, OPREGION_SIZE);
1652         }
1653
1654         mutex_unlock(&dev->struct_mutex);
1655
1656 out:
1657         kfree(data);
1658         return 0;
1659 }
1660
1661 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1662 {
1663         struct drm_info_node *node = m->private;
1664         struct drm_device *dev = node->minor->dev;
1665         struct intel_fbdev *ifbdev = NULL;
1666         struct intel_framebuffer *fb;
1667
1668 #ifdef CONFIG_DRM_I915_FBDEV
1669         struct drm_i915_private *dev_priv = dev->dev_private;
1670
1671         ifbdev = dev_priv->fbdev;
1672         fb = to_intel_framebuffer(ifbdev->helper.fb);
1673
1674         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1675                    fb->base.width,
1676                    fb->base.height,
1677                    fb->base.depth,
1678                    fb->base.bits_per_pixel,
1679                    atomic_read(&fb->base.refcount.refcount));
1680         describe_obj(m, fb->obj);
1681         seq_putc(m, '\n');
1682 #endif
1683
1684         mutex_lock(&dev->mode_config.fb_lock);
1685         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1686                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1687                         continue;
1688
1689                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1690                            fb->base.width,
1691                            fb->base.height,
1692                            fb->base.depth,
1693                            fb->base.bits_per_pixel,
1694                            atomic_read(&fb->base.refcount.refcount));
1695                 describe_obj(m, fb->obj);
1696                 seq_putc(m, '\n');
1697         }
1698         mutex_unlock(&dev->mode_config.fb_lock);
1699
1700         return 0;
1701 }
1702
1703 static void describe_ctx_ringbuf(struct seq_file *m,
1704                                  struct intel_ringbuffer *ringbuf)
1705 {
1706         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1707                    ringbuf->space, ringbuf->head, ringbuf->tail,
1708                    ringbuf->last_retired_head);
1709 }
1710
1711 static int i915_context_status(struct seq_file *m, void *unused)
1712 {
1713         struct drm_info_node *node = m->private;
1714         struct drm_device *dev = node->minor->dev;
1715         struct drm_i915_private *dev_priv = dev->dev_private;
1716         struct intel_engine_cs *ring;
1717         struct intel_context *ctx;
1718         int ret, i;
1719
1720         ret = mutex_lock_interruptible(&dev->struct_mutex);
1721         if (ret)
1722                 return ret;
1723
1724         if (dev_priv->ips.pwrctx) {
1725                 seq_puts(m, "power context ");
1726                 describe_obj(m, dev_priv->ips.pwrctx);
1727                 seq_putc(m, '\n');
1728         }
1729
1730         if (dev_priv->ips.renderctx) {
1731                 seq_puts(m, "render context ");
1732                 describe_obj(m, dev_priv->ips.renderctx);
1733                 seq_putc(m, '\n');
1734         }
1735
1736         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1737                 if (!i915.enable_execlists &&
1738                     ctx->legacy_hw_ctx.rcs_state == NULL)
1739                         continue;
1740
1741                 seq_puts(m, "HW context ");
1742                 describe_ctx(m, ctx);
1743                 for_each_ring(ring, dev_priv, i) {
1744                         if (ring->default_context == ctx)
1745                                 seq_printf(m, "(default context %s) ",
1746                                            ring->name);
1747                 }
1748
1749                 if (i915.enable_execlists) {
1750                         seq_putc(m, '\n');
1751                         for_each_ring(ring, dev_priv, i) {
1752                                 struct drm_i915_gem_object *ctx_obj =
1753                                         ctx->engine[i].state;
1754                                 struct intel_ringbuffer *ringbuf =
1755                                         ctx->engine[i].ringbuf;
1756
1757                                 seq_printf(m, "%s: ", ring->name);
1758                                 if (ctx_obj)
1759                                         describe_obj(m, ctx_obj);
1760                                 if (ringbuf)
1761                                         describe_ctx_ringbuf(m, ringbuf);
1762                                 seq_putc(m, '\n');
1763                         }
1764                 } else {
1765                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1766                 }
1767
1768                 seq_putc(m, '\n');
1769         }
1770
1771         mutex_unlock(&dev->struct_mutex);
1772
1773         return 0;
1774 }
1775
1776 static void i915_dump_lrc_obj(struct seq_file *m,
1777                               struct intel_engine_cs *ring,
1778                               struct drm_i915_gem_object *ctx_obj)
1779 {
1780         struct page *page;
1781         uint32_t *reg_state;
1782         int j;
1783         unsigned long ggtt_offset = 0;
1784
1785         if (ctx_obj == NULL) {
1786                 seq_printf(m, "Context on %s with no gem object\n",
1787                            ring->name);
1788                 return;
1789         }
1790
1791         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1792                    intel_execlists_ctx_id(ctx_obj));
1793
1794         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1795                 seq_puts(m, "\tNot bound in GGTT\n");
1796         else
1797                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1798
1799         if (i915_gem_object_get_pages(ctx_obj)) {
1800                 seq_puts(m, "\tFailed to get pages for context object\n");
1801                 return;
1802         }
1803
1804         page = i915_gem_object_get_page(ctx_obj, 1);
1805         if (!WARN_ON(page == NULL)) {
1806                 reg_state = kmap_atomic(page);
1807
1808                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1809                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1810                                    ggtt_offset + 4096 + (j * 4),
1811                                    reg_state[j], reg_state[j + 1],
1812                                    reg_state[j + 2], reg_state[j + 3]);
1813                 }
1814                 kunmap_atomic(reg_state);
1815         }
1816
1817         seq_putc(m, '\n');
1818 }
1819
1820 static int i915_dump_lrc(struct seq_file *m, void *unused)
1821 {
1822         struct drm_info_node *node = (struct drm_info_node *) m->private;
1823         struct drm_device *dev = node->minor->dev;
1824         struct drm_i915_private *dev_priv = dev->dev_private;
1825         struct intel_engine_cs *ring;
1826         struct intel_context *ctx;
1827         int ret, i;
1828
1829         if (!i915.enable_execlists) {
1830                 seq_printf(m, "Logical Ring Contexts are disabled\n");
1831                 return 0;
1832         }
1833
1834         ret = mutex_lock_interruptible(&dev->struct_mutex);
1835         if (ret)
1836                 return ret;
1837
1838         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1839                 for_each_ring(ring, dev_priv, i) {
1840                         if (ring->default_context != ctx)
1841                                 i915_dump_lrc_obj(m, ring,
1842                                                   ctx->engine[i].state);
1843                 }
1844         }
1845
1846         mutex_unlock(&dev->struct_mutex);
1847
1848         return 0;
1849 }
1850
1851 static int i915_execlists(struct seq_file *m, void *data)
1852 {
1853         struct drm_info_node *node = (struct drm_info_node *)m->private;
1854         struct drm_device *dev = node->minor->dev;
1855         struct drm_i915_private *dev_priv = dev->dev_private;
1856         struct intel_engine_cs *ring;
1857         u32 status_pointer;
1858         u8 read_pointer;
1859         u8 write_pointer;
1860         u32 status;
1861         u32 ctx_id;
1862         struct list_head *cursor;
1863         int ring_id, i;
1864         int ret;
1865
1866         if (!i915.enable_execlists) {
1867                 seq_puts(m, "Logical Ring Contexts are disabled\n");
1868                 return 0;
1869         }
1870
1871         ret = mutex_lock_interruptible(&dev->struct_mutex);
1872         if (ret)
1873                 return ret;
1874
1875         intel_runtime_pm_get(dev_priv);
1876
1877         for_each_ring(ring, dev_priv, ring_id) {
1878                 struct intel_ctx_submit_request *head_req = NULL;
1879                 int count = 0;
1880                 unsigned long flags;
1881
1882                 seq_printf(m, "%s\n", ring->name);
1883
1884                 status = I915_READ(RING_EXECLIST_STATUS(ring));
1885                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1886                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1887                            status, ctx_id);
1888
1889                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1890                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1891
1892                 read_pointer = ring->next_context_status_buffer;
1893                 write_pointer = status_pointer & 0x07;
1894                 if (read_pointer > write_pointer)
1895                         write_pointer += 6;
1896                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1897                            read_pointer, write_pointer);
1898
1899                 for (i = 0; i < 6; i++) {
1900                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1901                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1902
1903                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1904                                    i, status, ctx_id);
1905                 }
1906
1907                 spin_lock_irqsave(&ring->execlist_lock, flags);
1908                 list_for_each(cursor, &ring->execlist_queue)
1909                         count++;
1910                 head_req = list_first_entry_or_null(&ring->execlist_queue,
1911                                 struct intel_ctx_submit_request, execlist_link);
1912                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1913
1914                 seq_printf(m, "\t%d requests in queue\n", count);
1915                 if (head_req) {
1916                         struct drm_i915_gem_object *ctx_obj;
1917
1918                         ctx_obj = head_req->ctx->engine[ring_id].state;
1919                         seq_printf(m, "\tHead request id: %u\n",
1920                                    intel_execlists_ctx_id(ctx_obj));
1921                         seq_printf(m, "\tHead request tail: %u\n",
1922                                    head_req->tail);
1923                 }
1924
1925                 seq_putc(m, '\n');
1926         }
1927
1928         intel_runtime_pm_put(dev_priv);
1929         mutex_unlock(&dev->struct_mutex);
1930
1931         return 0;
1932 }
1933
1934 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1935 {
1936         struct drm_info_node *node = m->private;
1937         struct drm_device *dev = node->minor->dev;
1938         struct drm_i915_private *dev_priv = dev->dev_private;
1939         unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1940
1941         spin_lock_irq(&dev_priv->uncore.lock);
1942         if (IS_VALLEYVIEW(dev)) {
1943                 fw_rendercount = dev_priv->uncore.fw_rendercount;
1944                 fw_mediacount = dev_priv->uncore.fw_mediacount;
1945         } else
1946                 forcewake_count = dev_priv->uncore.forcewake_count;
1947         spin_unlock_irq(&dev_priv->uncore.lock);
1948
1949         if (IS_VALLEYVIEW(dev)) {
1950                 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1951                 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1952         } else
1953                 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1954
1955         return 0;
1956 }
1957
1958 static const char *swizzle_string(unsigned swizzle)
1959 {
1960         switch (swizzle) {
1961         case I915_BIT_6_SWIZZLE_NONE:
1962                 return "none";
1963         case I915_BIT_6_SWIZZLE_9:
1964                 return "bit9";
1965         case I915_BIT_6_SWIZZLE_9_10:
1966                 return "bit9/bit10";
1967         case I915_BIT_6_SWIZZLE_9_11:
1968                 return "bit9/bit11";
1969         case I915_BIT_6_SWIZZLE_9_10_11:
1970                 return "bit9/bit10/bit11";
1971         case I915_BIT_6_SWIZZLE_9_17:
1972                 return "bit9/bit17";
1973         case I915_BIT_6_SWIZZLE_9_10_17:
1974                 return "bit9/bit10/bit17";
1975         case I915_BIT_6_SWIZZLE_UNKNOWN:
1976                 return "unknown";
1977         }
1978
1979         return "bug";
1980 }
1981
1982 static int i915_swizzle_info(struct seq_file *m, void *data)
1983 {
1984         struct drm_info_node *node = m->private;
1985         struct drm_device *dev = node->minor->dev;
1986         struct drm_i915_private *dev_priv = dev->dev_private;
1987         int ret;
1988
1989         ret = mutex_lock_interruptible(&dev->struct_mutex);
1990         if (ret)
1991                 return ret;
1992         intel_runtime_pm_get(dev_priv);
1993
1994         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1995                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1996         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1997                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1998
1999         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2000                 seq_printf(m, "DDC = 0x%08x\n",
2001                            I915_READ(DCC));
2002                 seq_printf(m, "DDC2 = 0x%08x\n",
2003                            I915_READ(DCC2));
2004                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2005                            I915_READ16(C0DRB3));
2006                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2007                            I915_READ16(C1DRB3));
2008         } else if (INTEL_INFO(dev)->gen >= 6) {
2009                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2010                            I915_READ(MAD_DIMM_C0));
2011                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2012                            I915_READ(MAD_DIMM_C1));
2013                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2014                            I915_READ(MAD_DIMM_C2));
2015                 seq_printf(m, "TILECTL = 0x%08x\n",
2016                            I915_READ(TILECTL));
2017                 if (INTEL_INFO(dev)->gen >= 8)
2018                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2019                                    I915_READ(GAMTARBMODE));
2020                 else
2021                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2022                                    I915_READ(ARB_MODE));
2023                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2024                            I915_READ(DISP_ARB_CTL));
2025         }
2026
2027         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2028                 seq_puts(m, "L-shaped memory detected\n");
2029
2030         intel_runtime_pm_put(dev_priv);
2031         mutex_unlock(&dev->struct_mutex);
2032
2033         return 0;
2034 }
2035
2036 static int per_file_ctx(int id, void *ptr, void *data)
2037 {
2038         struct intel_context *ctx = ptr;
2039         struct seq_file *m = data;
2040         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2041
2042         if (!ppgtt) {
2043                 seq_printf(m, "  no ppgtt for context %d\n",
2044                            ctx->user_handle);
2045                 return 0;
2046         }
2047
2048         if (i915_gem_context_is_default(ctx))
2049                 seq_puts(m, "  default context:\n");
2050         else
2051                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2052         ppgtt->debug_dump(ppgtt, m);
2053
2054         return 0;
2055 }
2056
2057 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2058 {
2059         struct drm_i915_private *dev_priv = dev->dev_private;
2060         struct intel_engine_cs *ring;
2061         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2062         int unused, i;
2063
2064         if (!ppgtt)
2065                 return;
2066
2067         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
2068         seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
2069         for_each_ring(ring, dev_priv, unused) {
2070                 seq_printf(m, "%s\n", ring->name);
2071                 for (i = 0; i < 4; i++) {
2072                         u32 offset = 0x270 + i * 8;
2073                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2074                         pdp <<= 32;
2075                         pdp |= I915_READ(ring->mmio_base + offset);
2076                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2077                 }
2078         }
2079 }
2080
2081 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2082 {
2083         struct drm_i915_private *dev_priv = dev->dev_private;
2084         struct intel_engine_cs *ring;
2085         struct drm_file *file;
2086         int i;
2087
2088         if (INTEL_INFO(dev)->gen == 6)
2089                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2090
2091         for_each_ring(ring, dev_priv, i) {
2092                 seq_printf(m, "%s\n", ring->name);
2093                 if (INTEL_INFO(dev)->gen == 7)
2094                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2095                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2096                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2097                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2098         }
2099         if (dev_priv->mm.aliasing_ppgtt) {
2100                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2101
2102                 seq_puts(m, "aliasing PPGTT:\n");
2103                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
2104
2105                 ppgtt->debug_dump(ppgtt, m);
2106         }
2107
2108         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2109                 struct drm_i915_file_private *file_priv = file->driver_priv;
2110
2111                 seq_printf(m, "proc: %s\n",
2112                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2113                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2114         }
2115         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2116 }
2117
2118 static int i915_ppgtt_info(struct seq_file *m, void *data)
2119 {
2120         struct drm_info_node *node = m->private;
2121         struct drm_device *dev = node->minor->dev;
2122         struct drm_i915_private *dev_priv = dev->dev_private;
2123
2124         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2125         if (ret)
2126                 return ret;
2127         intel_runtime_pm_get(dev_priv);
2128
2129         if (INTEL_INFO(dev)->gen >= 8)
2130                 gen8_ppgtt_info(m, dev);
2131         else if (INTEL_INFO(dev)->gen >= 6)
2132                 gen6_ppgtt_info(m, dev);
2133
2134         intel_runtime_pm_put(dev_priv);
2135         mutex_unlock(&dev->struct_mutex);
2136
2137         return 0;
2138 }
2139
2140 static int i915_llc(struct seq_file *m, void *data)
2141 {
2142         struct drm_info_node *node = m->private;
2143         struct drm_device *dev = node->minor->dev;
2144         struct drm_i915_private *dev_priv = dev->dev_private;
2145
2146         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2147         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2148         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2149
2150         return 0;
2151 }
2152
2153 static int i915_edp_psr_status(struct seq_file *m, void *data)
2154 {
2155         struct drm_info_node *node = m->private;
2156         struct drm_device *dev = node->minor->dev;
2157         struct drm_i915_private *dev_priv = dev->dev_private;
2158         u32 psrperf = 0;
2159         u32 stat[3];
2160         enum pipe pipe;
2161         bool enabled = false;
2162
2163         intel_runtime_pm_get(dev_priv);
2164
2165         mutex_lock(&dev_priv->psr.lock);
2166         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2167         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2168         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2169         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2170         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2171                    dev_priv->psr.busy_frontbuffer_bits);
2172         seq_printf(m, "Re-enable work scheduled: %s\n",
2173                    yesno(work_busy(&dev_priv->psr.work.work)));
2174
2175         if (HAS_PSR(dev)) {
2176                 if (HAS_DDI(dev))
2177                         enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2178                 else {
2179                         for_each_pipe(dev_priv, pipe) {
2180                                 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2181                                         VLV_EDP_PSR_CURR_STATE_MASK;
2182                                 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2183                                     (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2184                                         enabled = true;
2185                         }
2186                 }
2187         }
2188         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2189
2190         if (!HAS_DDI(dev))
2191                 for_each_pipe(dev_priv, pipe) {
2192                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2193                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2194                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2195                 }
2196         seq_puts(m, "\n");
2197
2198         /* CHV PSR has no kind of performance counter */
2199         if (HAS_PSR(dev) && HAS_DDI(dev)) {
2200                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2201                         EDP_PSR_PERF_CNT_MASK;
2202
2203                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2204         }
2205         mutex_unlock(&dev_priv->psr.lock);
2206
2207         intel_runtime_pm_put(dev_priv);
2208         return 0;
2209 }
2210
2211 static int i915_sink_crc(struct seq_file *m, void *data)
2212 {
2213         struct drm_info_node *node = m->private;
2214         struct drm_device *dev = node->minor->dev;
2215         struct intel_encoder *encoder;
2216         struct intel_connector *connector;
2217         struct intel_dp *intel_dp = NULL;
2218         int ret;
2219         u8 crc[6];
2220
2221         drm_modeset_lock_all(dev);
2222         list_for_each_entry(connector, &dev->mode_config.connector_list,
2223                             base.head) {
2224
2225                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2226                         continue;
2227
2228                 if (!connector->base.encoder)
2229                         continue;
2230
2231                 encoder = to_intel_encoder(connector->base.encoder);
2232                 if (encoder->type != INTEL_OUTPUT_EDP)
2233                         continue;
2234
2235                 intel_dp = enc_to_intel_dp(&encoder->base);
2236
2237                 ret = intel_dp_sink_crc(intel_dp, crc);
2238                 if (ret)
2239                         goto out;
2240
2241                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2242                            crc[0], crc[1], crc[2],
2243                            crc[3], crc[4], crc[5]);
2244                 goto out;
2245         }
2246         ret = -ENODEV;
2247 out:
2248         drm_modeset_unlock_all(dev);
2249         return ret;
2250 }
2251
2252 static int i915_energy_uJ(struct seq_file *m, void *data)
2253 {
2254         struct drm_info_node *node = m->private;
2255         struct drm_device *dev = node->minor->dev;
2256         struct drm_i915_private *dev_priv = dev->dev_private;
2257         u64 power;
2258         u32 units;
2259
2260         if (INTEL_INFO(dev)->gen < 6)
2261                 return -ENODEV;
2262
2263         intel_runtime_pm_get(dev_priv);
2264
2265         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2266         power = (power & 0x1f00) >> 8;
2267         units = 1000000 / (1 << power); /* convert to uJ */
2268         power = I915_READ(MCH_SECP_NRG_STTS);
2269         power *= units;
2270
2271         intel_runtime_pm_put(dev_priv);
2272
2273         seq_printf(m, "%llu", (long long unsigned)power);
2274
2275         return 0;
2276 }
2277
2278 static int i915_pc8_status(struct seq_file *m, void *unused)
2279 {
2280         struct drm_info_node *node = m->private;
2281         struct drm_device *dev = node->minor->dev;
2282         struct drm_i915_private *dev_priv = dev->dev_private;
2283
2284         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2285                 seq_puts(m, "not supported\n");
2286                 return 0;
2287         }
2288
2289         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2290         seq_printf(m, "IRQs disabled: %s\n",
2291                    yesno(!intel_irqs_enabled(dev_priv)));
2292
2293         return 0;
2294 }
2295
2296 static const char *power_domain_str(enum intel_display_power_domain domain)
2297 {
2298         switch (domain) {
2299         case POWER_DOMAIN_PIPE_A:
2300                 return "PIPE_A";
2301         case POWER_DOMAIN_PIPE_B:
2302                 return "PIPE_B";
2303         case POWER_DOMAIN_PIPE_C:
2304                 return "PIPE_C";
2305         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2306                 return "PIPE_A_PANEL_FITTER";
2307         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2308                 return "PIPE_B_PANEL_FITTER";
2309         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2310                 return "PIPE_C_PANEL_FITTER";
2311         case POWER_DOMAIN_TRANSCODER_A:
2312                 return "TRANSCODER_A";
2313         case POWER_DOMAIN_TRANSCODER_B:
2314                 return "TRANSCODER_B";
2315         case POWER_DOMAIN_TRANSCODER_C:
2316                 return "TRANSCODER_C";
2317         case POWER_DOMAIN_TRANSCODER_EDP:
2318                 return "TRANSCODER_EDP";
2319         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2320                 return "PORT_DDI_A_2_LANES";
2321         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2322                 return "PORT_DDI_A_4_LANES";
2323         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2324                 return "PORT_DDI_B_2_LANES";
2325         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2326                 return "PORT_DDI_B_4_LANES";
2327         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2328                 return "PORT_DDI_C_2_LANES";
2329         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2330                 return "PORT_DDI_C_4_LANES";
2331         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2332                 return "PORT_DDI_D_2_LANES";
2333         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2334                 return "PORT_DDI_D_4_LANES";
2335         case POWER_DOMAIN_PORT_DSI:
2336                 return "PORT_DSI";
2337         case POWER_DOMAIN_PORT_CRT:
2338                 return "PORT_CRT";
2339         case POWER_DOMAIN_PORT_OTHER:
2340                 return "PORT_OTHER";
2341         case POWER_DOMAIN_VGA:
2342                 return "VGA";
2343         case POWER_DOMAIN_AUDIO:
2344                 return "AUDIO";
2345         case POWER_DOMAIN_PLLS:
2346                 return "PLLS";
2347         case POWER_DOMAIN_INIT:
2348                 return "INIT";
2349         default:
2350                 WARN_ON(1);
2351                 return "?";
2352         }
2353 }
2354
2355 static int i915_power_domain_info(struct seq_file *m, void *unused)
2356 {
2357         struct drm_info_node *node = m->private;
2358         struct drm_device *dev = node->minor->dev;
2359         struct drm_i915_private *dev_priv = dev->dev_private;
2360         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2361         int i;
2362
2363         mutex_lock(&power_domains->lock);
2364
2365         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2366         for (i = 0; i < power_domains->power_well_count; i++) {
2367                 struct i915_power_well *power_well;
2368                 enum intel_display_power_domain power_domain;
2369
2370                 power_well = &power_domains->power_wells[i];
2371                 seq_printf(m, "%-25s %d\n", power_well->name,
2372                            power_well->count);
2373
2374                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2375                      power_domain++) {
2376                         if (!(BIT(power_domain) & power_well->domains))
2377                                 continue;
2378
2379                         seq_printf(m, "  %-23s %d\n",
2380                                  power_domain_str(power_domain),
2381                                  power_domains->domain_use_count[power_domain]);
2382                 }
2383         }
2384
2385         mutex_unlock(&power_domains->lock);
2386
2387         return 0;
2388 }
2389
2390 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2391                                  struct drm_display_mode *mode)
2392 {
2393         int i;
2394
2395         for (i = 0; i < tabs; i++)
2396                 seq_putc(m, '\t');
2397
2398         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2399                    mode->base.id, mode->name,
2400                    mode->vrefresh, mode->clock,
2401                    mode->hdisplay, mode->hsync_start,
2402                    mode->hsync_end, mode->htotal,
2403                    mode->vdisplay, mode->vsync_start,
2404                    mode->vsync_end, mode->vtotal,
2405                    mode->type, mode->flags);
2406 }
2407
2408 static void intel_encoder_info(struct seq_file *m,
2409                                struct intel_crtc *intel_crtc,
2410                                struct intel_encoder *intel_encoder)
2411 {
2412         struct drm_info_node *node = m->private;
2413         struct drm_device *dev = node->minor->dev;
2414         struct drm_crtc *crtc = &intel_crtc->base;
2415         struct intel_connector *intel_connector;
2416         struct drm_encoder *encoder;
2417
2418         encoder = &intel_encoder->base;
2419         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2420                    encoder->base.id, encoder->name);
2421         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2422                 struct drm_connector *connector = &intel_connector->base;
2423                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2424                            connector->base.id,
2425                            connector->name,
2426                            drm_get_connector_status_name(connector->status));
2427                 if (connector->status == connector_status_connected) {
2428                         struct drm_display_mode *mode = &crtc->mode;
2429                         seq_printf(m, ", mode:\n");
2430                         intel_seq_print_mode(m, 2, mode);
2431                 } else {
2432                         seq_putc(m, '\n');
2433                 }
2434         }
2435 }
2436
2437 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2438 {
2439         struct drm_info_node *node = m->private;
2440         struct drm_device *dev = node->minor->dev;
2441         struct drm_crtc *crtc = &intel_crtc->base;
2442         struct intel_encoder *intel_encoder;
2443
2444         if (crtc->primary->fb)
2445                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2446                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2447                            crtc->primary->fb->width, crtc->primary->fb->height);
2448         else
2449                 seq_puts(m, "\tprimary plane disabled\n");
2450         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2451                 intel_encoder_info(m, intel_crtc, intel_encoder);
2452 }
2453
2454 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2455 {
2456         struct drm_display_mode *mode = panel->fixed_mode;
2457
2458         seq_printf(m, "\tfixed mode:\n");
2459         intel_seq_print_mode(m, 2, mode);
2460 }
2461
2462 static void intel_dp_info(struct seq_file *m,
2463                           struct intel_connector *intel_connector)
2464 {
2465         struct intel_encoder *intel_encoder = intel_connector->encoder;
2466         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2467
2468         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2469         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2470                    "no");
2471         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2472                 intel_panel_info(m, &intel_connector->panel);
2473 }
2474
2475 static void intel_hdmi_info(struct seq_file *m,
2476                             struct intel_connector *intel_connector)
2477 {
2478         struct intel_encoder *intel_encoder = intel_connector->encoder;
2479         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2480
2481         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2482                    "no");
2483 }
2484
2485 static void intel_lvds_info(struct seq_file *m,
2486                             struct intel_connector *intel_connector)
2487 {
2488         intel_panel_info(m, &intel_connector->panel);
2489 }
2490
2491 static void intel_connector_info(struct seq_file *m,
2492                                  struct drm_connector *connector)
2493 {
2494         struct intel_connector *intel_connector = to_intel_connector(connector);
2495         struct intel_encoder *intel_encoder = intel_connector->encoder;
2496         struct drm_display_mode *mode;
2497
2498         seq_printf(m, "connector %d: type %s, status: %s\n",
2499                    connector->base.id, connector->name,
2500                    drm_get_connector_status_name(connector->status));
2501         if (connector->status == connector_status_connected) {
2502                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2503                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2504                            connector->display_info.width_mm,
2505                            connector->display_info.height_mm);
2506                 seq_printf(m, "\tsubpixel order: %s\n",
2507                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2508                 seq_printf(m, "\tCEA rev: %d\n",
2509                            connector->display_info.cea_rev);
2510         }
2511         if (intel_encoder) {
2512                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2513                     intel_encoder->type == INTEL_OUTPUT_EDP)
2514                         intel_dp_info(m, intel_connector);
2515                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2516                         intel_hdmi_info(m, intel_connector);
2517                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2518                         intel_lvds_info(m, intel_connector);
2519         }
2520
2521         seq_printf(m, "\tmodes:\n");
2522         list_for_each_entry(mode, &connector->modes, head)
2523                 intel_seq_print_mode(m, 2, mode);
2524 }
2525
2526 static bool cursor_active(struct drm_device *dev, int pipe)
2527 {
2528         struct drm_i915_private *dev_priv = dev->dev_private;
2529         u32 state;
2530
2531         if (IS_845G(dev) || IS_I865G(dev))
2532                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2533         else
2534                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2535
2536         return state;
2537 }
2538
2539 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2540 {
2541         struct drm_i915_private *dev_priv = dev->dev_private;
2542         u32 pos;
2543
2544         pos = I915_READ(CURPOS(pipe));
2545
2546         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2547         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2548                 *x = -*x;
2549
2550         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2551         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2552                 *y = -*y;
2553
2554         return cursor_active(dev, pipe);
2555 }
2556
2557 static int i915_display_info(struct seq_file *m, void *unused)
2558 {
2559         struct drm_info_node *node = m->private;
2560         struct drm_device *dev = node->minor->dev;
2561         struct drm_i915_private *dev_priv = dev->dev_private;
2562         struct intel_crtc *crtc;
2563         struct drm_connector *connector;
2564
2565         intel_runtime_pm_get(dev_priv);
2566         drm_modeset_lock_all(dev);
2567         seq_printf(m, "CRTC info\n");
2568         seq_printf(m, "---------\n");
2569         for_each_intel_crtc(dev, crtc) {
2570                 bool active;
2571                 int x, y;
2572
2573                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2574                            crtc->base.base.id, pipe_name(crtc->pipe),
2575                            yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
2576                 if (crtc->active) {
2577                         intel_crtc_info(m, crtc);
2578
2579                         active = cursor_position(dev, crtc->pipe, &x, &y);
2580                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2581                                    yesno(crtc->cursor_base),
2582                                    x, y, crtc->cursor_width, crtc->cursor_height,
2583                                    crtc->cursor_addr, yesno(active));
2584                 }
2585
2586                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2587                            yesno(!crtc->cpu_fifo_underrun_disabled),
2588                            yesno(!crtc->pch_fifo_underrun_disabled));
2589         }
2590
2591         seq_printf(m, "\n");
2592         seq_printf(m, "Connector info\n");
2593         seq_printf(m, "--------------\n");
2594         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2595                 intel_connector_info(m, connector);
2596         }
2597         drm_modeset_unlock_all(dev);
2598         intel_runtime_pm_put(dev_priv);
2599
2600         return 0;
2601 }
2602
2603 static int i915_semaphore_status(struct seq_file *m, void *unused)
2604 {
2605         struct drm_info_node *node = (struct drm_info_node *) m->private;
2606         struct drm_device *dev = node->minor->dev;
2607         struct drm_i915_private *dev_priv = dev->dev_private;
2608         struct intel_engine_cs *ring;
2609         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2610         int i, j, ret;
2611
2612         if (!i915_semaphore_is_enabled(dev)) {
2613                 seq_puts(m, "Semaphores are disabled\n");
2614                 return 0;
2615         }
2616
2617         ret = mutex_lock_interruptible(&dev->struct_mutex);
2618         if (ret)
2619                 return ret;
2620         intel_runtime_pm_get(dev_priv);
2621
2622         if (IS_BROADWELL(dev)) {
2623                 struct page *page;
2624                 uint64_t *seqno;
2625
2626                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2627
2628                 seqno = (uint64_t *)kmap_atomic(page);
2629                 for_each_ring(ring, dev_priv, i) {
2630                         uint64_t offset;
2631
2632                         seq_printf(m, "%s\n", ring->name);
2633
2634                         seq_puts(m, "  Last signal:");
2635                         for (j = 0; j < num_rings; j++) {
2636                                 offset = i * I915_NUM_RINGS + j;
2637                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2638                                            seqno[offset], offset * 8);
2639                         }
2640                         seq_putc(m, '\n');
2641
2642                         seq_puts(m, "  Last wait:  ");
2643                         for (j = 0; j < num_rings; j++) {
2644                                 offset = i + (j * I915_NUM_RINGS);
2645                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2646                                            seqno[offset], offset * 8);
2647                         }
2648                         seq_putc(m, '\n');
2649
2650                 }
2651                 kunmap_atomic(seqno);
2652         } else {
2653                 seq_puts(m, "  Last signal:");
2654                 for_each_ring(ring, dev_priv, i)
2655                         for (j = 0; j < num_rings; j++)
2656                                 seq_printf(m, "0x%08x\n",
2657                                            I915_READ(ring->semaphore.mbox.signal[j]));
2658                 seq_putc(m, '\n');
2659         }
2660
2661         seq_puts(m, "\nSync seqno:\n");
2662         for_each_ring(ring, dev_priv, i) {
2663                 for (j = 0; j < num_rings; j++) {
2664                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2665                 }
2666                 seq_putc(m, '\n');
2667         }
2668         seq_putc(m, '\n');
2669
2670         intel_runtime_pm_put(dev_priv);
2671         mutex_unlock(&dev->struct_mutex);
2672         return 0;
2673 }
2674
2675 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2676 {
2677         struct drm_info_node *node = (struct drm_info_node *) m->private;
2678         struct drm_device *dev = node->minor->dev;
2679         struct drm_i915_private *dev_priv = dev->dev_private;
2680         int i;
2681
2682         drm_modeset_lock_all(dev);
2683         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2684                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2685
2686                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2687                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2688                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2689                 seq_printf(m, " tracked hardware state:\n");
2690                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2691                 seq_printf(m, " dpll_md: 0x%08x\n",
2692                            pll->config.hw_state.dpll_md);
2693                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2694                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2695                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2696         }
2697         drm_modeset_unlock_all(dev);
2698
2699         return 0;
2700 }
2701
2702 static int i915_wa_registers(struct seq_file *m, void *unused)
2703 {
2704         int i;
2705         int ret;
2706         struct drm_info_node *node = (struct drm_info_node *) m->private;
2707         struct drm_device *dev = node->minor->dev;
2708         struct drm_i915_private *dev_priv = dev->dev_private;
2709
2710         ret = mutex_lock_interruptible(&dev->struct_mutex);
2711         if (ret)
2712                 return ret;
2713
2714         intel_runtime_pm_get(dev_priv);
2715
2716         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2717         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2718                 u32 addr, mask, value, read;
2719                 bool ok;
2720
2721                 addr = dev_priv->workarounds.reg[i].addr;
2722                 mask = dev_priv->workarounds.reg[i].mask;
2723                 value = dev_priv->workarounds.reg[i].value;
2724                 read = I915_READ(addr);
2725                 ok = (value & mask) == (read & mask);
2726                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2727                            addr, value, mask, read, ok ? "OK" : "FAIL");
2728         }
2729
2730         intel_runtime_pm_put(dev_priv);
2731         mutex_unlock(&dev->struct_mutex);
2732
2733         return 0;
2734 }
2735
2736 static int i915_ddb_info(struct seq_file *m, void *unused)
2737 {
2738         struct drm_info_node *node = m->private;
2739         struct drm_device *dev = node->minor->dev;
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         struct skl_ddb_allocation *ddb;
2742         struct skl_ddb_entry *entry;
2743         enum pipe pipe;
2744         int plane;
2745
2746         if (INTEL_INFO(dev)->gen < 9)
2747                 return 0;
2748
2749         drm_modeset_lock_all(dev);
2750
2751         ddb = &dev_priv->wm.skl_hw.ddb;
2752
2753         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2754
2755         for_each_pipe(dev_priv, pipe) {
2756                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2757
2758                 for_each_plane(pipe, plane) {
2759                         entry = &ddb->plane[pipe][plane];
2760                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2761                                    entry->start, entry->end,
2762                                    skl_ddb_entry_size(entry));
2763                 }
2764
2765                 entry = &ddb->cursor[pipe];
2766                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2767                            entry->end, skl_ddb_entry_size(entry));
2768         }
2769
2770         drm_modeset_unlock_all(dev);
2771
2772         return 0;
2773 }
2774
2775 struct pipe_crc_info {
2776         const char *name;
2777         struct drm_device *dev;
2778         enum pipe pipe;
2779 };
2780
2781 static int i915_dp_mst_info(struct seq_file *m, void *unused)
2782 {
2783         struct drm_info_node *node = (struct drm_info_node *) m->private;
2784         struct drm_device *dev = node->minor->dev;
2785         struct drm_encoder *encoder;
2786         struct intel_encoder *intel_encoder;
2787         struct intel_digital_port *intel_dig_port;
2788         drm_modeset_lock_all(dev);
2789         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2790                 intel_encoder = to_intel_encoder(encoder);
2791                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2792                         continue;
2793                 intel_dig_port = enc_to_dig_port(encoder);
2794                 if (!intel_dig_port->dp.can_mst)
2795                         continue;
2796
2797                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2798         }
2799         drm_modeset_unlock_all(dev);
2800         return 0;
2801 }
2802
2803 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2804 {
2805         struct pipe_crc_info *info = inode->i_private;
2806         struct drm_i915_private *dev_priv = info->dev->dev_private;
2807         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2808
2809         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2810                 return -ENODEV;
2811
2812         spin_lock_irq(&pipe_crc->lock);
2813
2814         if (pipe_crc->opened) {
2815                 spin_unlock_irq(&pipe_crc->lock);
2816                 return -EBUSY; /* already open */
2817         }
2818
2819         pipe_crc->opened = true;
2820         filep->private_data = inode->i_private;
2821
2822         spin_unlock_irq(&pipe_crc->lock);
2823
2824         return 0;
2825 }
2826
2827 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2828 {
2829         struct pipe_crc_info *info = inode->i_private;
2830         struct drm_i915_private *dev_priv = info->dev->dev_private;
2831         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2832
2833         spin_lock_irq(&pipe_crc->lock);
2834         pipe_crc->opened = false;
2835         spin_unlock_irq(&pipe_crc->lock);
2836
2837         return 0;
2838 }
2839
2840 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2841 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2842 /* account for \'0' */
2843 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2844
2845 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2846 {
2847         assert_spin_locked(&pipe_crc->lock);
2848         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2849                         INTEL_PIPE_CRC_ENTRIES_NR);
2850 }
2851
2852 static ssize_t
2853 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2854                    loff_t *pos)
2855 {
2856         struct pipe_crc_info *info = filep->private_data;
2857         struct drm_device *dev = info->dev;
2858         struct drm_i915_private *dev_priv = dev->dev_private;
2859         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2860         char buf[PIPE_CRC_BUFFER_LEN];
2861         int n_entries;
2862         ssize_t bytes_read;
2863
2864         /*
2865          * Don't allow user space to provide buffers not big enough to hold
2866          * a line of data.
2867          */
2868         if (count < PIPE_CRC_LINE_LEN)
2869                 return -EINVAL;
2870
2871         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2872                 return 0;
2873
2874         /* nothing to read */
2875         spin_lock_irq(&pipe_crc->lock);
2876         while (pipe_crc_data_count(pipe_crc) == 0) {
2877                 int ret;
2878
2879                 if (filep->f_flags & O_NONBLOCK) {
2880                         spin_unlock_irq(&pipe_crc->lock);
2881                         return -EAGAIN;
2882                 }
2883
2884                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2885                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2886                 if (ret) {
2887                         spin_unlock_irq(&pipe_crc->lock);
2888                         return ret;
2889                 }
2890         }
2891
2892         /* We now have one or more entries to read */
2893         n_entries = count / PIPE_CRC_LINE_LEN;
2894
2895         bytes_read = 0;
2896         while (n_entries > 0) {
2897                 struct intel_pipe_crc_entry *entry =
2898                         &pipe_crc->entries[pipe_crc->tail];
2899                 int ret;
2900
2901                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2902                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2903                         break;
2904
2905                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2906                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2907
2908                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2909                                        "%8u %8x %8x %8x %8x %8x\n",
2910                                        entry->frame, entry->crc[0],
2911                                        entry->crc[1], entry->crc[2],
2912                                        entry->crc[3], entry->crc[4]);
2913
2914                 spin_unlock_irq(&pipe_crc->lock);
2915
2916                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
2917                 if (ret == PIPE_CRC_LINE_LEN)
2918                         return -EFAULT;
2919
2920                 user_buf += PIPE_CRC_LINE_LEN;
2921                 n_entries--;
2922
2923                 spin_lock_irq(&pipe_crc->lock);
2924         }
2925
2926         spin_unlock_irq(&pipe_crc->lock);
2927
2928         return bytes_read;
2929 }
2930
2931 static const struct file_operations i915_pipe_crc_fops = {
2932         .owner = THIS_MODULE,
2933         .open = i915_pipe_crc_open,
2934         .read = i915_pipe_crc_read,
2935         .release = i915_pipe_crc_release,
2936 };
2937
2938 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2939         {
2940                 .name = "i915_pipe_A_crc",
2941                 .pipe = PIPE_A,
2942         },
2943         {
2944                 .name = "i915_pipe_B_crc",
2945                 .pipe = PIPE_B,
2946         },
2947         {
2948                 .name = "i915_pipe_C_crc",
2949                 .pipe = PIPE_C,
2950         },
2951 };
2952
2953 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2954                                 enum pipe pipe)
2955 {
2956         struct drm_device *dev = minor->dev;
2957         struct dentry *ent;
2958         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2959
2960         info->dev = dev;
2961         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2962                                   &i915_pipe_crc_fops);
2963         if (!ent)
2964                 return -ENOMEM;
2965
2966         return drm_add_fake_info_node(minor, ent, info);
2967 }
2968
2969 static const char * const pipe_crc_sources[] = {
2970         "none",
2971         "plane1",
2972         "plane2",
2973         "pf",
2974         "pipe",
2975         "TV",
2976         "DP-B",
2977         "DP-C",
2978         "DP-D",
2979         "auto",
2980 };
2981
2982 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2983 {
2984         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2985         return pipe_crc_sources[source];
2986 }
2987
2988 static int display_crc_ctl_show(struct seq_file *m, void *data)
2989 {
2990         struct drm_device *dev = m->private;
2991         struct drm_i915_private *dev_priv = dev->dev_private;
2992         int i;
2993
2994         for (i = 0; i < I915_MAX_PIPES; i++)
2995                 seq_printf(m, "%c %s\n", pipe_name(i),
2996                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2997
2998         return 0;
2999 }
3000
3001 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3002 {
3003         struct drm_device *dev = inode->i_private;
3004
3005         return single_open(file, display_crc_ctl_show, dev);
3006 }
3007
3008 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3009                                  uint32_t *val)
3010 {
3011         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3012                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3013
3014         switch (*source) {
3015         case INTEL_PIPE_CRC_SOURCE_PIPE:
3016                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3017                 break;
3018         case INTEL_PIPE_CRC_SOURCE_NONE:
3019                 *val = 0;
3020                 break;
3021         default:
3022                 return -EINVAL;
3023         }
3024
3025         return 0;
3026 }
3027
3028 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3029                                      enum intel_pipe_crc_source *source)
3030 {
3031         struct intel_encoder *encoder;
3032         struct intel_crtc *crtc;
3033         struct intel_digital_port *dig_port;
3034         int ret = 0;
3035
3036         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3037
3038         drm_modeset_lock_all(dev);
3039         for_each_intel_encoder(dev, encoder) {
3040                 if (!encoder->base.crtc)
3041                         continue;
3042
3043                 crtc = to_intel_crtc(encoder->base.crtc);
3044
3045                 if (crtc->pipe != pipe)
3046                         continue;
3047
3048                 switch (encoder->type) {
3049                 case INTEL_OUTPUT_TVOUT:
3050                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3051                         break;
3052                 case INTEL_OUTPUT_DISPLAYPORT:
3053                 case INTEL_OUTPUT_EDP:
3054                         dig_port = enc_to_dig_port(&encoder->base);
3055                         switch (dig_port->port) {
3056                         case PORT_B:
3057                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3058                                 break;
3059                         case PORT_C:
3060                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3061                                 break;
3062                         case PORT_D:
3063                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3064                                 break;
3065                         default:
3066                                 WARN(1, "nonexisting DP port %c\n",
3067                                      port_name(dig_port->port));
3068                                 break;
3069                         }
3070                         break;
3071                 default:
3072                         break;
3073                 }
3074         }
3075         drm_modeset_unlock_all(dev);
3076
3077         return ret;
3078 }
3079
3080 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3081                                 enum pipe pipe,
3082                                 enum intel_pipe_crc_source *source,
3083                                 uint32_t *val)
3084 {
3085         struct drm_i915_private *dev_priv = dev->dev_private;
3086         bool need_stable_symbols = false;
3087
3088         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3089                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3090                 if (ret)
3091                         return ret;
3092         }
3093
3094         switch (*source) {
3095         case INTEL_PIPE_CRC_SOURCE_PIPE:
3096                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3097                 break;
3098         case INTEL_PIPE_CRC_SOURCE_DP_B:
3099                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3100                 need_stable_symbols = true;
3101                 break;
3102         case INTEL_PIPE_CRC_SOURCE_DP_C:
3103                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3104                 need_stable_symbols = true;
3105                 break;
3106         case INTEL_PIPE_CRC_SOURCE_DP_D:
3107                 if (!IS_CHERRYVIEW(dev))
3108                         return -EINVAL;
3109                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3110                 need_stable_symbols = true;
3111                 break;
3112         case INTEL_PIPE_CRC_SOURCE_NONE:
3113                 *val = 0;
3114                 break;
3115         default:
3116                 return -EINVAL;
3117         }
3118
3119         /*
3120          * When the pipe CRC tap point is after the transcoders we need
3121          * to tweak symbol-level features to produce a deterministic series of
3122          * symbols for a given frame. We need to reset those features only once
3123          * a frame (instead of every nth symbol):
3124          *   - DC-balance: used to ensure a better clock recovery from the data
3125          *     link (SDVO)
3126          *   - DisplayPort scrambling: used for EMI reduction
3127          */
3128         if (need_stable_symbols) {
3129                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3130
3131                 tmp |= DC_BALANCE_RESET_VLV;
3132                 switch (pipe) {
3133                 case PIPE_A:
3134                         tmp |= PIPE_A_SCRAMBLE_RESET;
3135                         break;
3136                 case PIPE_B:
3137                         tmp |= PIPE_B_SCRAMBLE_RESET;
3138                         break;
3139                 case PIPE_C:
3140                         tmp |= PIPE_C_SCRAMBLE_RESET;
3141                         break;
3142                 default:
3143                         return -EINVAL;
3144                 }
3145                 I915_WRITE(PORT_DFT2_G4X, tmp);
3146         }
3147
3148         return 0;
3149 }
3150
3151 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3152                                  enum pipe pipe,
3153                                  enum intel_pipe_crc_source *source,
3154                                  uint32_t *val)
3155 {
3156         struct drm_i915_private *dev_priv = dev->dev_private;
3157         bool need_stable_symbols = false;
3158
3159         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3160                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3161                 if (ret)
3162                         return ret;
3163         }
3164
3165         switch (*source) {
3166         case INTEL_PIPE_CRC_SOURCE_PIPE:
3167                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3168                 break;
3169         case INTEL_PIPE_CRC_SOURCE_TV:
3170                 if (!SUPPORTS_TV(dev))
3171                         return -EINVAL;
3172                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3173                 break;
3174         case INTEL_PIPE_CRC_SOURCE_DP_B:
3175                 if (!IS_G4X(dev))
3176                         return -EINVAL;
3177                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3178                 need_stable_symbols = true;
3179                 break;
3180         case INTEL_PIPE_CRC_SOURCE_DP_C:
3181                 if (!IS_G4X(dev))
3182                         return -EINVAL;
3183                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3184                 need_stable_symbols = true;
3185                 break;
3186         case INTEL_PIPE_CRC_SOURCE_DP_D:
3187                 if (!IS_G4X(dev))
3188                         return -EINVAL;
3189                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3190                 need_stable_symbols = true;
3191                 break;
3192         case INTEL_PIPE_CRC_SOURCE_NONE:
3193                 *val = 0;
3194                 break;
3195         default:
3196                 return -EINVAL;
3197         }
3198
3199         /*
3200          * When the pipe CRC tap point is after the transcoders we need
3201          * to tweak symbol-level features to produce a deterministic series of
3202          * symbols for a given frame. We need to reset those features only once
3203          * a frame (instead of every nth symbol):
3204          *   - DC-balance: used to ensure a better clock recovery from the data
3205          *     link (SDVO)
3206          *   - DisplayPort scrambling: used for EMI reduction
3207          */
3208         if (need_stable_symbols) {
3209                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3210
3211                 WARN_ON(!IS_G4X(dev));
3212
3213                 I915_WRITE(PORT_DFT_I9XX,
3214                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3215
3216                 if (pipe == PIPE_A)
3217                         tmp |= PIPE_A_SCRAMBLE_RESET;
3218                 else
3219                         tmp |= PIPE_B_SCRAMBLE_RESET;
3220
3221                 I915_WRITE(PORT_DFT2_G4X, tmp);
3222         }
3223
3224         return 0;
3225 }
3226
3227 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3228                                          enum pipe pipe)
3229 {
3230         struct drm_i915_private *dev_priv = dev->dev_private;
3231         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3232
3233         switch (pipe) {
3234         case PIPE_A:
3235                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3236                 break;
3237         case PIPE_B:
3238                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3239                 break;
3240         case PIPE_C:
3241                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3242                 break;
3243         default:
3244                 return;
3245         }
3246         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3247                 tmp &= ~DC_BALANCE_RESET_VLV;
3248         I915_WRITE(PORT_DFT2_G4X, tmp);
3249
3250 }
3251
3252 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3253                                          enum pipe pipe)
3254 {
3255         struct drm_i915_private *dev_priv = dev->dev_private;
3256         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3257
3258         if (pipe == PIPE_A)
3259                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3260         else
3261                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3262         I915_WRITE(PORT_DFT2_G4X, tmp);
3263
3264         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3265                 I915_WRITE(PORT_DFT_I9XX,
3266                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3267         }
3268 }
3269
3270 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3271                                 uint32_t *val)
3272 {
3273         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3274                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3275
3276         switch (*source) {
3277         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3278                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3279                 break;
3280         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3281                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3282                 break;
3283         case INTEL_PIPE_CRC_SOURCE_PIPE:
3284                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3285                 break;
3286         case INTEL_PIPE_CRC_SOURCE_NONE:
3287                 *val = 0;
3288                 break;
3289         default:
3290                 return -EINVAL;
3291         }
3292
3293         return 0;
3294 }
3295
3296 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3297 {
3298         struct drm_i915_private *dev_priv = dev->dev_private;
3299         struct intel_crtc *crtc =
3300                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3301
3302         drm_modeset_lock_all(dev);
3303         /*
3304          * If we use the eDP transcoder we need to make sure that we don't
3305          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3306          * relevant on hsw with pipe A when using the always-on power well
3307          * routing.
3308          */
3309         if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3310             !crtc->config.pch_pfit.enabled) {
3311                 crtc->config.pch_pfit.force_thru = true;
3312
3313                 intel_display_power_get(dev_priv,
3314                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3315
3316                 dev_priv->display.crtc_disable(&crtc->base);
3317                 dev_priv->display.crtc_enable(&crtc->base);
3318         }
3319         drm_modeset_unlock_all(dev);
3320 }
3321
3322 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3323 {
3324         struct drm_i915_private *dev_priv = dev->dev_private;
3325         struct intel_crtc *crtc =
3326                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3327
3328         drm_modeset_lock_all(dev);
3329         /*
3330          * If we use the eDP transcoder we need to make sure that we don't
3331          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3332          * relevant on hsw with pipe A when using the always-on power well
3333          * routing.
3334          */
3335         if (crtc->config.pch_pfit.force_thru) {
3336                 crtc->config.pch_pfit.force_thru = false;
3337
3338                 dev_priv->display.crtc_disable(&crtc->base);
3339                 dev_priv->display.crtc_enable(&crtc->base);
3340
3341                 intel_display_power_put(dev_priv,
3342                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3343         }
3344         drm_modeset_unlock_all(dev);
3345 }
3346
3347 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3348                                 enum pipe pipe,
3349                                 enum intel_pipe_crc_source *source,
3350                                 uint32_t *val)
3351 {
3352         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3353                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3354
3355         switch (*source) {
3356         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3357                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3358                 break;
3359         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3360                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3361                 break;
3362         case INTEL_PIPE_CRC_SOURCE_PF:
3363                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3364                         hsw_trans_edp_pipe_A_crc_wa(dev);
3365
3366                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3367                 break;
3368         case INTEL_PIPE_CRC_SOURCE_NONE:
3369                 *val = 0;
3370                 break;
3371         default:
3372                 return -EINVAL;
3373         }
3374
3375         return 0;
3376 }
3377
3378 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3379                                enum intel_pipe_crc_source source)
3380 {
3381         struct drm_i915_private *dev_priv = dev->dev_private;
3382         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3383         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3384                                                                         pipe));
3385         u32 val = 0; /* shut up gcc */
3386         int ret;
3387
3388         if (pipe_crc->source == source)
3389                 return 0;
3390
3391         /* forbid changing the source without going back to 'none' */
3392         if (pipe_crc->source && source)
3393                 return -EINVAL;
3394
3395         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3396                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3397                 return -EIO;
3398         }
3399
3400         if (IS_GEN2(dev))
3401                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3402         else if (INTEL_INFO(dev)->gen < 5)
3403                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3404         else if (IS_VALLEYVIEW(dev))
3405                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3406         else if (IS_GEN5(dev) || IS_GEN6(dev))
3407                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3408         else
3409                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3410
3411         if (ret != 0)
3412                 return ret;
3413
3414         /* none -> real source transition */
3415         if (source) {
3416                 struct intel_pipe_crc_entry *entries;
3417
3418                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3419                                  pipe_name(pipe), pipe_crc_source_name(source));
3420
3421                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3422                                   sizeof(pipe_crc->entries[0]),
3423                                   GFP_KERNEL);
3424                 if (!entries)
3425                         return -ENOMEM;
3426
3427                 /*
3428                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3429                  * enabled and disabled dynamically based on package C states,
3430                  * user space can't make reliable use of the CRCs, so let's just
3431                  * completely disable it.
3432                  */
3433                 hsw_disable_ips(crtc);
3434
3435                 spin_lock_irq(&pipe_crc->lock);
3436                 kfree(pipe_crc->entries);
3437                 pipe_crc->entries = entries;
3438                 pipe_crc->head = 0;
3439                 pipe_crc->tail = 0;
3440                 spin_unlock_irq(&pipe_crc->lock);
3441         }
3442
3443         pipe_crc->source = source;
3444
3445         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3446         POSTING_READ(PIPE_CRC_CTL(pipe));
3447
3448         /* real source -> none transition */
3449         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3450                 struct intel_pipe_crc_entry *entries;
3451                 struct intel_crtc *crtc =
3452                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3453
3454                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3455                                  pipe_name(pipe));
3456
3457                 drm_modeset_lock(&crtc->base.mutex, NULL);
3458                 if (crtc->active)
3459                         intel_wait_for_vblank(dev, pipe);
3460                 drm_modeset_unlock(&crtc->base.mutex);
3461
3462                 spin_lock_irq(&pipe_crc->lock);
3463                 entries = pipe_crc->entries;
3464                 pipe_crc->entries = NULL;
3465                 pipe_crc->head = 0;
3466                 pipe_crc->tail = 0;
3467                 spin_unlock_irq(&pipe_crc->lock);
3468
3469                 kfree(entries);
3470
3471                 if (IS_G4X(dev))
3472                         g4x_undo_pipe_scramble_reset(dev, pipe);
3473                 else if (IS_VALLEYVIEW(dev))
3474                         vlv_undo_pipe_scramble_reset(dev, pipe);
3475                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3476                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3477
3478                 hsw_enable_ips(crtc);
3479         }
3480
3481         return 0;
3482 }
3483
3484 /*
3485  * Parse pipe CRC command strings:
3486  *   command: wsp* object wsp+ name wsp+ source wsp*
3487  *   object: 'pipe'
3488  *   name: (A | B | C)
3489  *   source: (none | plane1 | plane2 | pf)
3490  *   wsp: (#0x20 | #0x9 | #0xA)+
3491  *
3492  * eg.:
3493  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3494  *  "pipe A none"    ->  Stop CRC
3495  */
3496 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3497 {
3498         int n_words = 0;
3499
3500         while (*buf) {
3501                 char *end;
3502
3503                 /* skip leading white space */
3504                 buf = skip_spaces(buf);
3505                 if (!*buf)
3506                         break;  /* end of buffer */
3507
3508                 /* find end of word */
3509                 for (end = buf; *end && !isspace(*end); end++)
3510                         ;
3511
3512                 if (n_words == max_words) {
3513                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3514                                          max_words);
3515                         return -EINVAL; /* ran out of words[] before bytes */
3516                 }
3517
3518                 if (*end)
3519                         *end++ = '\0';
3520                 words[n_words++] = buf;
3521                 buf = end;
3522         }
3523
3524         return n_words;
3525 }
3526
3527 enum intel_pipe_crc_object {
3528         PIPE_CRC_OBJECT_PIPE,
3529 };
3530
3531 static const char * const pipe_crc_objects[] = {
3532         "pipe",
3533 };
3534
3535 static int
3536 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3537 {
3538         int i;
3539
3540         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3541                 if (!strcmp(buf, pipe_crc_objects[i])) {
3542                         *o = i;
3543                         return 0;
3544                     }
3545
3546         return -EINVAL;
3547 }
3548
3549 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3550 {
3551         const char name = buf[0];
3552
3553         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3554                 return -EINVAL;
3555
3556         *pipe = name - 'A';
3557
3558         return 0;
3559 }
3560
3561 static int
3562 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3563 {
3564         int i;
3565
3566         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3567                 if (!strcmp(buf, pipe_crc_sources[i])) {
3568                         *s = i;
3569                         return 0;
3570                     }
3571
3572         return -EINVAL;
3573 }
3574
3575 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3576 {
3577 #define N_WORDS 3
3578         int n_words;
3579         char *words[N_WORDS];
3580         enum pipe pipe;
3581         enum intel_pipe_crc_object object;
3582         enum intel_pipe_crc_source source;
3583
3584         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3585         if (n_words != N_WORDS) {
3586                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3587                                  N_WORDS);
3588                 return -EINVAL;
3589         }
3590
3591         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3592                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3593                 return -EINVAL;
3594         }
3595
3596         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3597                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3598                 return -EINVAL;
3599         }
3600
3601         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3602                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3603                 return -EINVAL;
3604         }
3605
3606         return pipe_crc_set_source(dev, pipe, source);
3607 }
3608
3609 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3610                                      size_t len, loff_t *offp)
3611 {
3612         struct seq_file *m = file->private_data;
3613         struct drm_device *dev = m->private;
3614         char *tmpbuf;
3615         int ret;
3616
3617         if (len == 0)
3618                 return 0;
3619
3620         if (len > PAGE_SIZE - 1) {
3621                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3622                                  PAGE_SIZE);
3623                 return -E2BIG;
3624         }
3625
3626         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3627         if (!tmpbuf)
3628                 return -ENOMEM;
3629
3630         if (copy_from_user(tmpbuf, ubuf, len)) {
3631                 ret = -EFAULT;
3632                 goto out;
3633         }
3634         tmpbuf[len] = '\0';
3635
3636         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3637
3638 out:
3639         kfree(tmpbuf);
3640         if (ret < 0)
3641                 return ret;
3642
3643         *offp += len;
3644         return len;
3645 }
3646
3647 static const struct file_operations i915_display_crc_ctl_fops = {
3648         .owner = THIS_MODULE,
3649         .open = display_crc_ctl_open,
3650         .read = seq_read,
3651         .llseek = seq_lseek,
3652         .release = single_release,
3653         .write = display_crc_ctl_write
3654 };
3655
3656 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
3657 {
3658         struct drm_device *dev = m->private;
3659         int num_levels = ilk_wm_max_level(dev) + 1;
3660         int level;
3661
3662         drm_modeset_lock_all(dev);
3663
3664         for (level = 0; level < num_levels; level++) {
3665                 unsigned int latency = wm[level];
3666
3667                 /*
3668                  * - WM1+ latency values in 0.5us units
3669                  * - latencies are in us on gen9
3670                  */
3671                 if (INTEL_INFO(dev)->gen >= 9)
3672                         latency *= 10;
3673                 else if (level > 0)
3674                         latency *= 5;
3675
3676                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3677                            level, wm[level], latency / 10, latency % 10);
3678         }
3679
3680         drm_modeset_unlock_all(dev);
3681 }
3682
3683 static int pri_wm_latency_show(struct seq_file *m, void *data)
3684 {
3685         struct drm_device *dev = m->private;
3686         struct drm_i915_private *dev_priv = dev->dev_private;
3687         const uint16_t *latencies;
3688
3689         if (INTEL_INFO(dev)->gen >= 9)
3690                 latencies = dev_priv->wm.skl_latency;
3691         else
3692                 latencies = to_i915(dev)->wm.pri_latency;
3693
3694         wm_latency_show(m, latencies);
3695
3696         return 0;
3697 }
3698
3699 static int spr_wm_latency_show(struct seq_file *m, void *data)
3700 {
3701         struct drm_device *dev = m->private;
3702         struct drm_i915_private *dev_priv = dev->dev_private;
3703         const uint16_t *latencies;
3704
3705         if (INTEL_INFO(dev)->gen >= 9)
3706                 latencies = dev_priv->wm.skl_latency;
3707         else
3708                 latencies = to_i915(dev)->wm.spr_latency;
3709
3710         wm_latency_show(m, latencies);
3711
3712         return 0;
3713 }
3714
3715 static int cur_wm_latency_show(struct seq_file *m, void *data)
3716 {
3717         struct drm_device *dev = m->private;
3718         struct drm_i915_private *dev_priv = dev->dev_private;
3719         const uint16_t *latencies;
3720
3721         if (INTEL_INFO(dev)->gen >= 9)
3722                 latencies = dev_priv->wm.skl_latency;
3723         else
3724                 latencies = to_i915(dev)->wm.cur_latency;
3725
3726         wm_latency_show(m, latencies);
3727
3728         return 0;
3729 }
3730
3731 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3732 {
3733         struct drm_device *dev = inode->i_private;
3734
3735         if (HAS_GMCH_DISPLAY(dev))
3736                 return -ENODEV;
3737
3738         return single_open(file, pri_wm_latency_show, dev);
3739 }
3740
3741 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3742 {
3743         struct drm_device *dev = inode->i_private;
3744
3745         if (HAS_GMCH_DISPLAY(dev))
3746                 return -ENODEV;
3747
3748         return single_open(file, spr_wm_latency_show, dev);
3749 }
3750
3751 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3752 {
3753         struct drm_device *dev = inode->i_private;
3754
3755         if (HAS_GMCH_DISPLAY(dev))
3756                 return -ENODEV;
3757
3758         return single_open(file, cur_wm_latency_show, dev);
3759 }
3760
3761 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3762                                 size_t len, loff_t *offp, uint16_t wm[8])
3763 {
3764         struct seq_file *m = file->private_data;
3765         struct drm_device *dev = m->private;
3766         uint16_t new[8] = { 0 };
3767         int num_levels = ilk_wm_max_level(dev) + 1;
3768         int level;
3769         int ret;
3770         char tmp[32];
3771
3772         if (len >= sizeof(tmp))
3773                 return -EINVAL;
3774
3775         if (copy_from_user(tmp, ubuf, len))
3776                 return -EFAULT;
3777
3778         tmp[len] = '\0';
3779
3780         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3781                      &new[0], &new[1], &new[2], &new[3],
3782                      &new[4], &new[5], &new[6], &new[7]);
3783         if (ret != num_levels)
3784                 return -EINVAL;
3785
3786         drm_modeset_lock_all(dev);
3787
3788         for (level = 0; level < num_levels; level++)
3789                 wm[level] = new[level];
3790
3791         drm_modeset_unlock_all(dev);
3792
3793         return len;
3794 }
3795
3796
3797 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3798                                     size_t len, loff_t *offp)
3799 {
3800         struct seq_file *m = file->private_data;
3801         struct drm_device *dev = m->private;
3802         struct drm_i915_private *dev_priv = dev->dev_private;
3803         uint16_t *latencies;
3804
3805         if (INTEL_INFO(dev)->gen >= 9)
3806                 latencies = dev_priv->wm.skl_latency;
3807         else
3808                 latencies = to_i915(dev)->wm.pri_latency;
3809
3810         return wm_latency_write(file, ubuf, len, offp, latencies);
3811 }
3812
3813 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3814                                     size_t len, loff_t *offp)
3815 {
3816         struct seq_file *m = file->private_data;
3817         struct drm_device *dev = m->private;
3818         struct drm_i915_private *dev_priv = dev->dev_private;
3819         uint16_t *latencies;
3820
3821         if (INTEL_INFO(dev)->gen >= 9)
3822                 latencies = dev_priv->wm.skl_latency;
3823         else
3824                 latencies = to_i915(dev)->wm.spr_latency;
3825
3826         return wm_latency_write(file, ubuf, len, offp, latencies);
3827 }
3828
3829 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3830                                     size_t len, loff_t *offp)
3831 {
3832         struct seq_file *m = file->private_data;
3833         struct drm_device *dev = m->private;
3834         struct drm_i915_private *dev_priv = dev->dev_private;
3835         uint16_t *latencies;
3836
3837         if (INTEL_INFO(dev)->gen >= 9)
3838                 latencies = dev_priv->wm.skl_latency;
3839         else
3840                 latencies = to_i915(dev)->wm.cur_latency;
3841
3842         return wm_latency_write(file, ubuf, len, offp, latencies);
3843 }
3844
3845 static const struct file_operations i915_pri_wm_latency_fops = {
3846         .owner = THIS_MODULE,
3847         .open = pri_wm_latency_open,
3848         .read = seq_read,
3849         .llseek = seq_lseek,
3850         .release = single_release,
3851         .write = pri_wm_latency_write
3852 };
3853
3854 static const struct file_operations i915_spr_wm_latency_fops = {
3855         .owner = THIS_MODULE,
3856         .open = spr_wm_latency_open,
3857         .read = seq_read,
3858         .llseek = seq_lseek,
3859         .release = single_release,
3860         .write = spr_wm_latency_write
3861 };
3862
3863 static const struct file_operations i915_cur_wm_latency_fops = {
3864         .owner = THIS_MODULE,
3865         .open = cur_wm_latency_open,
3866         .read = seq_read,
3867         .llseek = seq_lseek,
3868         .release = single_release,
3869         .write = cur_wm_latency_write
3870 };
3871
3872 static int
3873 i915_wedged_get(void *data, u64 *val)
3874 {
3875         struct drm_device *dev = data;
3876         struct drm_i915_private *dev_priv = dev->dev_private;
3877
3878         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3879
3880         return 0;
3881 }
3882
3883 static int
3884 i915_wedged_set(void *data, u64 val)
3885 {
3886         struct drm_device *dev = data;
3887         struct drm_i915_private *dev_priv = dev->dev_private;
3888
3889         intel_runtime_pm_get(dev_priv);
3890
3891         i915_handle_error(dev, val,
3892                           "Manually setting wedged to %llu", val);
3893
3894         intel_runtime_pm_put(dev_priv);
3895
3896         return 0;
3897 }
3898
3899 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3900                         i915_wedged_get, i915_wedged_set,
3901                         "%llu\n");
3902
3903 static int
3904 i915_ring_stop_get(void *data, u64 *val)
3905 {
3906         struct drm_device *dev = data;
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908
3909         *val = dev_priv->gpu_error.stop_rings;
3910
3911         return 0;
3912 }
3913
3914 static int
3915 i915_ring_stop_set(void *data, u64 val)
3916 {
3917         struct drm_device *dev = data;
3918         struct drm_i915_private *dev_priv = dev->dev_private;
3919         int ret;
3920
3921         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3922
3923         ret = mutex_lock_interruptible(&dev->struct_mutex);
3924         if (ret)
3925                 return ret;
3926
3927         dev_priv->gpu_error.stop_rings = val;
3928         mutex_unlock(&dev->struct_mutex);
3929
3930         return 0;
3931 }
3932
3933 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3934                         i915_ring_stop_get, i915_ring_stop_set,
3935                         "0x%08llx\n");
3936
3937 static int
3938 i915_ring_missed_irq_get(void *data, u64 *val)
3939 {
3940         struct drm_device *dev = data;
3941         struct drm_i915_private *dev_priv = dev->dev_private;
3942
3943         *val = dev_priv->gpu_error.missed_irq_rings;
3944         return 0;
3945 }
3946
3947 static int
3948 i915_ring_missed_irq_set(void *data, u64 val)
3949 {
3950         struct drm_device *dev = data;
3951         struct drm_i915_private *dev_priv = dev->dev_private;
3952         int ret;
3953
3954         /* Lock against concurrent debugfs callers */
3955         ret = mutex_lock_interruptible(&dev->struct_mutex);
3956         if (ret)
3957                 return ret;
3958         dev_priv->gpu_error.missed_irq_rings = val;
3959         mutex_unlock(&dev->struct_mutex);
3960
3961         return 0;
3962 }
3963
3964 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3965                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3966                         "0x%08llx\n");
3967
3968 static int
3969 i915_ring_test_irq_get(void *data, u64 *val)
3970 {
3971         struct drm_device *dev = data;
3972         struct drm_i915_private *dev_priv = dev->dev_private;
3973
3974         *val = dev_priv->gpu_error.test_irq_rings;
3975
3976         return 0;
3977 }
3978
3979 static int
3980 i915_ring_test_irq_set(void *data, u64 val)
3981 {
3982         struct drm_device *dev = data;
3983         struct drm_i915_private *dev_priv = dev->dev_private;
3984         int ret;
3985
3986         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3987
3988         /* Lock against concurrent debugfs callers */
3989         ret = mutex_lock_interruptible(&dev->struct_mutex);
3990         if (ret)
3991                 return ret;
3992
3993         dev_priv->gpu_error.test_irq_rings = val;
3994         mutex_unlock(&dev->struct_mutex);
3995
3996         return 0;
3997 }
3998
3999 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4000                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4001                         "0x%08llx\n");
4002
4003 #define DROP_UNBOUND 0x1
4004 #define DROP_BOUND 0x2
4005 #define DROP_RETIRE 0x4
4006 #define DROP_ACTIVE 0x8
4007 #define DROP_ALL (DROP_UNBOUND | \
4008                   DROP_BOUND | \
4009                   DROP_RETIRE | \
4010                   DROP_ACTIVE)
4011 static int
4012 i915_drop_caches_get(void *data, u64 *val)
4013 {
4014         *val = DROP_ALL;
4015
4016         return 0;
4017 }
4018
4019 static int
4020 i915_drop_caches_set(void *data, u64 val)
4021 {
4022         struct drm_device *dev = data;
4023         struct drm_i915_private *dev_priv = dev->dev_private;
4024         int ret;
4025
4026         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4027
4028         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4029          * on ioctls on -EAGAIN. */
4030         ret = mutex_lock_interruptible(&dev->struct_mutex);
4031         if (ret)
4032                 return ret;
4033
4034         if (val & DROP_ACTIVE) {
4035                 ret = i915_gpu_idle(dev);
4036                 if (ret)
4037                         goto unlock;
4038         }
4039
4040         if (val & (DROP_RETIRE | DROP_ACTIVE))
4041                 i915_gem_retire_requests(dev);
4042
4043         if (val & DROP_BOUND)
4044                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4045
4046         if (val & DROP_UNBOUND)
4047                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4048
4049 unlock:
4050         mutex_unlock(&dev->struct_mutex);
4051
4052         return ret;
4053 }
4054
4055 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4056                         i915_drop_caches_get, i915_drop_caches_set,
4057                         "0x%08llx\n");
4058
4059 static int
4060 i915_max_freq_get(void *data, u64 *val)
4061 {
4062         struct drm_device *dev = data;
4063         struct drm_i915_private *dev_priv = dev->dev_private;
4064         int ret;
4065
4066         if (INTEL_INFO(dev)->gen < 6)
4067                 return -ENODEV;
4068
4069         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4070
4071         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4072         if (ret)
4073                 return ret;
4074
4075         if (IS_VALLEYVIEW(dev))
4076                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4077         else
4078                 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4079         mutex_unlock(&dev_priv->rps.hw_lock);
4080
4081         return 0;
4082 }
4083
4084 static int
4085 i915_max_freq_set(void *data, u64 val)
4086 {
4087         struct drm_device *dev = data;
4088         struct drm_i915_private *dev_priv = dev->dev_private;
4089         u32 rp_state_cap, hw_max, hw_min;
4090         int ret;
4091
4092         if (INTEL_INFO(dev)->gen < 6)
4093                 return -ENODEV;
4094
4095         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4096
4097         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4098
4099         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4100         if (ret)
4101                 return ret;
4102
4103         /*
4104          * Turbo will still be enabled, but won't go above the set value.
4105          */
4106         if (IS_VALLEYVIEW(dev)) {
4107                 val = vlv_freq_opcode(dev_priv, val);
4108
4109                 hw_max = dev_priv->rps.max_freq;
4110                 hw_min = dev_priv->rps.min_freq;
4111         } else {
4112                 do_div(val, GT_FREQUENCY_MULTIPLIER);
4113
4114                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4115                 hw_max = dev_priv->rps.max_freq;
4116                 hw_min = (rp_state_cap >> 16) & 0xff;
4117         }
4118
4119         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4120                 mutex_unlock(&dev_priv->rps.hw_lock);
4121                 return -EINVAL;
4122         }
4123
4124         dev_priv->rps.max_freq_softlimit = val;
4125
4126         if (IS_VALLEYVIEW(dev))
4127                 valleyview_set_rps(dev, val);
4128         else
4129                 gen6_set_rps(dev, val);
4130
4131         mutex_unlock(&dev_priv->rps.hw_lock);
4132
4133         return 0;
4134 }
4135
4136 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4137                         i915_max_freq_get, i915_max_freq_set,
4138                         "%llu\n");
4139
4140 static int
4141 i915_min_freq_get(void *data, u64 *val)
4142 {
4143         struct drm_device *dev = data;
4144         struct drm_i915_private *dev_priv = dev->dev_private;
4145         int ret;
4146
4147         if (INTEL_INFO(dev)->gen < 6)
4148                 return -ENODEV;
4149
4150         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4151
4152         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4153         if (ret)
4154                 return ret;
4155
4156         if (IS_VALLEYVIEW(dev))
4157                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4158         else
4159                 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4160         mutex_unlock(&dev_priv->rps.hw_lock);
4161
4162         return 0;
4163 }
4164
4165 static int
4166 i915_min_freq_set(void *data, u64 val)
4167 {
4168         struct drm_device *dev = data;
4169         struct drm_i915_private *dev_priv = dev->dev_private;
4170         u32 rp_state_cap, hw_max, hw_min;
4171         int ret;
4172
4173         if (INTEL_INFO(dev)->gen < 6)
4174                 return -ENODEV;
4175
4176         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4177
4178         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4179
4180         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4181         if (ret)
4182                 return ret;
4183
4184         /*
4185          * Turbo will still be enabled, but won't go below the set value.
4186          */
4187         if (IS_VALLEYVIEW(dev)) {
4188                 val = vlv_freq_opcode(dev_priv, val);
4189
4190                 hw_max = dev_priv->rps.max_freq;
4191                 hw_min = dev_priv->rps.min_freq;
4192         } else {
4193                 do_div(val, GT_FREQUENCY_MULTIPLIER);
4194
4195                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4196                 hw_max = dev_priv->rps.max_freq;
4197                 hw_min = (rp_state_cap >> 16) & 0xff;
4198         }
4199
4200         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4201                 mutex_unlock(&dev_priv->rps.hw_lock);
4202                 return -EINVAL;
4203         }
4204
4205         dev_priv->rps.min_freq_softlimit = val;
4206
4207         if (IS_VALLEYVIEW(dev))
4208                 valleyview_set_rps(dev, val);
4209         else
4210                 gen6_set_rps(dev, val);
4211
4212         mutex_unlock(&dev_priv->rps.hw_lock);
4213
4214         return 0;
4215 }
4216
4217 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4218                         i915_min_freq_get, i915_min_freq_set,
4219                         "%llu\n");
4220
4221 static int
4222 i915_cache_sharing_get(void *data, u64 *val)
4223 {
4224         struct drm_device *dev = data;
4225         struct drm_i915_private *dev_priv = dev->dev_private;
4226         u32 snpcr;
4227         int ret;
4228
4229         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4230                 return -ENODEV;
4231
4232         ret = mutex_lock_interruptible(&dev->struct_mutex);
4233         if (ret)
4234                 return ret;
4235         intel_runtime_pm_get(dev_priv);
4236
4237         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4238
4239         intel_runtime_pm_put(dev_priv);
4240         mutex_unlock(&dev_priv->dev->struct_mutex);
4241
4242         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4243
4244         return 0;
4245 }
4246
4247 static int
4248 i915_cache_sharing_set(void *data, u64 val)
4249 {
4250         struct drm_device *dev = data;
4251         struct drm_i915_private *dev_priv = dev->dev_private;
4252         u32 snpcr;
4253
4254         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4255                 return -ENODEV;
4256
4257         if (val > 3)
4258                 return -EINVAL;
4259
4260         intel_runtime_pm_get(dev_priv);
4261         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4262
4263         /* Update the cache sharing policy here as well */
4264         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4265         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4266         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4267         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4268
4269         intel_runtime_pm_put(dev_priv);
4270         return 0;
4271 }
4272
4273 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4274                         i915_cache_sharing_get, i915_cache_sharing_set,
4275                         "%llu\n");
4276
4277 static int i915_forcewake_open(struct inode *inode, struct file *file)
4278 {
4279         struct drm_device *dev = inode->i_private;
4280         struct drm_i915_private *dev_priv = dev->dev_private;
4281
4282         if (INTEL_INFO(dev)->gen < 6)
4283                 return 0;
4284
4285         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4286
4287         return 0;
4288 }
4289
4290 static int i915_forcewake_release(struct inode *inode, struct file *file)
4291 {
4292         struct drm_device *dev = inode->i_private;
4293         struct drm_i915_private *dev_priv = dev->dev_private;
4294
4295         if (INTEL_INFO(dev)->gen < 6)
4296                 return 0;
4297
4298         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4299
4300         return 0;
4301 }
4302
4303 static const struct file_operations i915_forcewake_fops = {
4304         .owner = THIS_MODULE,
4305         .open = i915_forcewake_open,
4306         .release = i915_forcewake_release,
4307 };
4308
4309 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4310 {
4311         struct drm_device *dev = minor->dev;
4312         struct dentry *ent;
4313
4314         ent = debugfs_create_file("i915_forcewake_user",
4315                                   S_IRUSR,
4316                                   root, dev,
4317                                   &i915_forcewake_fops);
4318         if (!ent)
4319                 return -ENOMEM;
4320
4321         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4322 }
4323
4324 static int i915_debugfs_create(struct dentry *root,
4325                                struct drm_minor *minor,
4326                                const char *name,
4327                                const struct file_operations *fops)
4328 {
4329         struct drm_device *dev = minor->dev;
4330         struct dentry *ent;
4331
4332         ent = debugfs_create_file(name,
4333                                   S_IRUGO | S_IWUSR,
4334                                   root, dev,
4335                                   fops);
4336         if (!ent)
4337                 return -ENOMEM;
4338
4339         return drm_add_fake_info_node(minor, ent, fops);
4340 }
4341
4342 static const struct drm_info_list i915_debugfs_list[] = {
4343         {"i915_capabilities", i915_capabilities, 0},
4344         {"i915_gem_objects", i915_gem_object_info, 0},
4345         {"i915_gem_gtt", i915_gem_gtt_info, 0},
4346         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
4347         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
4348         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
4349         {"i915_gem_stolen", i915_gem_stolen_list_info },
4350         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
4351         {"i915_gem_request", i915_gem_request_info, 0},
4352         {"i915_gem_seqno", i915_gem_seqno_info, 0},
4353         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
4354         {"i915_gem_interrupt", i915_interrupt_info, 0},
4355         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4356         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4357         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
4358         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
4359         {"i915_frequency_info", i915_frequency_info, 0},
4360         {"i915_drpc_info", i915_drpc_info, 0},
4361         {"i915_emon_status", i915_emon_status, 0},
4362         {"i915_ring_freq_table", i915_ring_freq_table, 0},
4363         {"i915_fbc_status", i915_fbc_status, 0},
4364         {"i915_ips_status", i915_ips_status, 0},
4365         {"i915_sr_status", i915_sr_status, 0},
4366         {"i915_opregion", i915_opregion, 0},
4367         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
4368         {"i915_context_status", i915_context_status, 0},
4369         {"i915_dump_lrc", i915_dump_lrc, 0},
4370         {"i915_execlists", i915_execlists, 0},
4371         {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
4372         {"i915_swizzle_info", i915_swizzle_info, 0},
4373         {"i915_ppgtt_info", i915_ppgtt_info, 0},
4374         {"i915_llc", i915_llc, 0},
4375         {"i915_edp_psr_status", i915_edp_psr_status, 0},
4376         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
4377         {"i915_energy_uJ", i915_energy_uJ, 0},
4378         {"i915_pc8_status", i915_pc8_status, 0},
4379         {"i915_power_domain_info", i915_power_domain_info, 0},
4380         {"i915_display_info", i915_display_info, 0},
4381         {"i915_semaphore_status", i915_semaphore_status, 0},
4382         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
4383         {"i915_dp_mst_info", i915_dp_mst_info, 0},
4384         {"i915_wa_registers", i915_wa_registers, 0},
4385         {"i915_ddb_info", i915_ddb_info, 0},
4386 };
4387 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
4388
4389 static const struct i915_debugfs_files {
4390         const char *name;
4391         const struct file_operations *fops;
4392 } i915_debugfs_files[] = {
4393         {"i915_wedged", &i915_wedged_fops},
4394         {"i915_max_freq", &i915_max_freq_fops},
4395         {"i915_min_freq", &i915_min_freq_fops},
4396         {"i915_cache_sharing", &i915_cache_sharing_fops},
4397         {"i915_ring_stop", &i915_ring_stop_fops},
4398         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4399         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
4400         {"i915_gem_drop_caches", &i915_drop_caches_fops},
4401         {"i915_error_state", &i915_error_state_fops},
4402         {"i915_next_seqno", &i915_next_seqno_fops},
4403         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
4404         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4405         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4406         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
4407         {"i915_fbc_false_color", &i915_fbc_fc_fops},
4408 };
4409
4410 void intel_display_crc_init(struct drm_device *dev)
4411 {
4412         struct drm_i915_private *dev_priv = dev->dev_private;
4413         enum pipe pipe;
4414
4415         for_each_pipe(dev_priv, pipe) {
4416                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4417
4418                 pipe_crc->opened = false;
4419                 spin_lock_init(&pipe_crc->lock);
4420                 init_waitqueue_head(&pipe_crc->wq);
4421         }
4422 }
4423
4424 int i915_debugfs_init(struct drm_minor *minor)
4425 {
4426         int ret, i;
4427
4428         ret = i915_forcewake_create(minor->debugfs_root, minor);
4429         if (ret)
4430                 return ret;
4431
4432         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4433                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4434                 if (ret)
4435                         return ret;
4436         }
4437
4438         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4439                 ret = i915_debugfs_create(minor->debugfs_root, minor,
4440                                           i915_debugfs_files[i].name,
4441                                           i915_debugfs_files[i].fops);
4442                 if (ret)
4443                         return ret;
4444         }
4445
4446         return drm_debugfs_create_files(i915_debugfs_list,
4447                                         I915_DEBUGFS_ENTRIES,
4448                                         minor->debugfs_root, minor);
4449 }
4450
4451 void i915_debugfs_cleanup(struct drm_minor *minor)
4452 {
4453         int i;
4454
4455         drm_debugfs_remove_files(i915_debugfs_list,
4456                                  I915_DEBUGFS_ENTRIES, minor);
4457
4458         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4459                                  1, minor);
4460
4461         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4462                 struct drm_info_list *info_list =
4463                         (struct drm_info_list *)&i915_pipe_crc_data[i];
4464
4465                 drm_debugfs_remove_files(info_list, 1, minor);
4466         }
4467
4468         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4469                 struct drm_info_list *info_list =
4470                         (struct drm_info_list *) i915_debugfs_files[i].fops;
4471
4472                 drm_debugfs_remove_files(info_list, 1, minor);
4473         }
4474 }