2 * timbgpio.c timberdale FPGA GPIO driver
3 * Copyright (c) 2009 Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 * Timberdale FPGA GPIO
23 #include <linux/module.h>
24 #include <linux/gpio.h>
25 #include <linux/platform_device.h>
26 #include <linux/irq.h>
28 #include <linux/timb_gpio.h>
29 #include <linux/interrupt.h>
30 #include <linux/slab.h>
32 #define DRIVER_NAME "timb-gpio"
36 #define TGPIO_IER 0x08
37 #define TGPIO_ISR 0x0c
38 #define TGPIO_IPR 0x10
39 #define TGPIO_ICR 0x14
40 #define TGPIO_FLR 0x18
41 #define TGPIO_LVR 0x1c
42 #define TGPIO_VER 0x20
43 #define TGPIO_BFLR 0x24
46 void __iomem *membase;
47 spinlock_t lock; /* mutual exclusion */
48 struct gpio_chip gpio;
52 static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
53 unsigned offset, bool enabled)
55 struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
58 spin_lock(&tgpio->lock);
59 reg = ioread32(tgpio->membase + offset);
66 iowrite32(reg, tgpio->membase + offset);
67 spin_unlock(&tgpio->lock);
72 static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
74 return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
77 static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
79 struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
82 value = ioread32(tgpio->membase + TGPIOVAL);
83 return (value & (1 << nr)) ? 1 : 0;
86 static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
89 return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
92 static void timbgpio_gpio_set(struct gpio_chip *gpio,
95 timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
98 static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
100 struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
102 if (tgpio->irq_base <= 0)
105 return tgpio->irq_base + offset;
111 static void timbgpio_irq_disable(unsigned irq)
113 struct timbgpio *tgpio = get_irq_chip_data(irq);
114 int offset = irq - tgpio->irq_base;
116 timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
119 static void timbgpio_irq_enable(unsigned irq)
121 struct timbgpio *tgpio = get_irq_chip_data(irq);
122 int offset = irq - tgpio->irq_base;
124 timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
127 static int timbgpio_irq_type(unsigned irq, unsigned trigger)
129 struct timbgpio *tgpio = get_irq_chip_data(irq);
130 int offset = irq - tgpio->irq_base;
132 u32 lvr, flr, bflr = 0;
135 if (offset < 0 || offset > tgpio->gpio.ngpio)
138 ver = ioread32(tgpio->membase + TGPIO_VER);
140 spin_lock_irqsave(&tgpio->lock, flags);
142 lvr = ioread32(tgpio->membase + TGPIO_LVR);
143 flr = ioread32(tgpio->membase + TGPIO_FLR);
145 bflr = ioread32(tgpio->membase + TGPIO_BFLR);
147 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
148 bflr &= ~(1 << offset);
149 flr &= ~(1 << offset);
150 if (trigger & IRQ_TYPE_LEVEL_HIGH)
153 lvr &= ~(1 << offset);
156 if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
164 bflr &= ~(1 << offset);
166 if (trigger & IRQ_TYPE_EDGE_FALLING)
167 lvr &= ~(1 << offset);
172 iowrite32(lvr, tgpio->membase + TGPIO_LVR);
173 iowrite32(flr, tgpio->membase + TGPIO_FLR);
175 iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
177 iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
178 spin_unlock_irqrestore(&tgpio->lock, flags);
183 static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
185 struct timbgpio *tgpio = get_irq_data(irq);
189 desc->chip->ack(irq);
190 ipr = ioread32(tgpio->membase + TGPIO_IPR);
191 iowrite32(ipr, tgpio->membase + TGPIO_ICR);
193 for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
194 generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
197 static struct irq_chip timbgpio_irqchip = {
199 .enable = timbgpio_irq_enable,
200 .disable = timbgpio_irq_disable,
201 .set_type = timbgpio_irq_type,
204 static int __devinit timbgpio_probe(struct platform_device *pdev)
207 struct gpio_chip *gc;
208 struct timbgpio *tgpio;
209 struct resource *iomem;
210 struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
211 int irq = platform_get_irq(pdev, 0);
213 if (!pdata || pdata->nr_pins > 32) {
218 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224 tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
229 tgpio->irq_base = pdata->irq_base;
231 spin_lock_init(&tgpio->lock);
233 if (!request_mem_region(iomem->start, resource_size(iomem),
239 tgpio->membase = ioremap(iomem->start, resource_size(iomem));
240 if (!tgpio->membase) {
247 gc->label = dev_name(&pdev->dev);
248 gc->owner = THIS_MODULE;
249 gc->dev = &pdev->dev;
250 gc->direction_input = timbgpio_gpio_direction_input;
251 gc->get = timbgpio_gpio_get;
252 gc->direction_output = timbgpio_gpio_direction_output;
253 gc->set = timbgpio_gpio_set;
254 gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
256 gc->base = pdata->gpio_base;
257 gc->ngpio = pdata->nr_pins;
260 err = gpiochip_add(gc);
264 platform_set_drvdata(pdev, tgpio);
266 /* make sure to disable interrupts */
267 iowrite32(0x0, tgpio->membase + TGPIO_IER);
269 if (irq < 0 || tgpio->irq_base <= 0)
272 for (i = 0; i < pdata->nr_pins; i++) {
273 set_irq_chip_and_handler_name(tgpio->irq_base + i,
274 &timbgpio_irqchip, handle_simple_irq, "mux");
275 set_irq_chip_data(tgpio->irq_base + i, tgpio);
277 set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
281 set_irq_data(irq, tgpio);
282 set_irq_chained_handler(irq, timbgpio_irq);
287 iounmap(tgpio->membase);
289 release_mem_region(iomem->start, resource_size(iomem));
293 printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);
298 static int __devexit timbgpio_remove(struct platform_device *pdev)
301 struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
302 struct timbgpio *tgpio = platform_get_drvdata(pdev);
303 struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
304 int irq = platform_get_irq(pdev, 0);
306 if (irq >= 0 && tgpio->irq_base > 0) {
308 for (i = 0; i < pdata->nr_pins; i++) {
309 set_irq_chip(tgpio->irq_base + i, NULL);
310 set_irq_chip_data(tgpio->irq_base + i, NULL);
313 set_irq_handler(irq, NULL);
314 set_irq_data(irq, NULL);
317 err = gpiochip_remove(&tgpio->gpio);
319 printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");
321 iounmap(tgpio->membase);
322 release_mem_region(iomem->start, resource_size(iomem));
325 platform_set_drvdata(pdev, NULL);
330 static struct platform_driver timbgpio_platform_driver = {
333 .owner = THIS_MODULE,
335 .probe = timbgpio_probe,
336 .remove = timbgpio_remove,
339 /*--------------------------------------------------------------------------*/
341 static int __init timbgpio_init(void)
343 return platform_driver_register(&timbgpio_platform_driver);
346 static void __exit timbgpio_exit(void)
348 platform_driver_unregister(&timbgpio_platform_driver);
351 module_init(timbgpio_init);
352 module_exit(timbgpio_exit);
354 MODULE_DESCRIPTION("Timberdale GPIO driver");
355 MODULE_LICENSE("GPL v2");
356 MODULE_AUTHOR("Mocean Laboratories");
357 MODULE_ALIAS("platform:"DRIVER_NAME);