2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/pci.h>
20 #include <linux/gpio.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
24 #define PCH_EDGE_FALLING 0
25 #define PCH_EDGE_RISING BIT(0)
26 #define PCH_LEVEL_L BIT(1)
27 #define PCH_LEVEL_H (BIT(0) | BIT(1))
28 #define PCH_EDGE_BOTH BIT(2)
29 #define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31 #define PCH_IRQ_BASE 24
52 OKISEMI_ML7223m_IOH, /* OKISEMI ML7223 IOH PCIe Bus-m */
53 OKISEMI_ML7223n_IOH /* OKISEMI ML7223 IOH PCIe Bus-n */
56 /* Specifies number of GPIO PINS */
57 static int gpio_pins[] = {
58 [INTEL_EG20T_PCH] = 12,
59 [OKISEMI_ML7223m_IOH] = 8,
60 [OKISEMI_ML7223n_IOH] = 8,
64 * struct pch_gpio_reg_data - The register store data.
65 * @ien_reg: To store contents of IEN register.
66 * @imask_reg: To store contents of IMASK register.
67 * @po_reg: To store contents of PO register.
68 * @pm_reg: To store contents of PM register.
69 * @im0_reg: To store contents of IM0 register.
70 * @im1_reg: To store contents of IM1 register.
71 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
74 struct pch_gpio_reg_data {
85 * struct pch_gpio - GPIO private data structure.
86 * @base: PCI base address of Memory mapped I/O register.
87 * @reg: Memory mapped PCH GPIO register list.
88 * @dev: Pointer to device structure.
89 * @gpio: Data for GPIO infrastructure.
90 * @pch_gpio_reg: Memory mapped Register data is saved here
92 * @lock: Used for register access protection
93 * @irq_base: Save base of IRQ number for interrupt
95 * @spinlock: Used for register access protection in
96 * interrupt context pch_irq_mask,
97 * pch_irq_unmask and pch_irq_type;
101 struct pch_regs __iomem *reg;
103 struct gpio_chip gpio;
104 struct pch_gpio_reg_data pch_gpio_reg;
111 static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
114 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
116 mutex_lock(&chip->lock);
117 reg_val = ioread32(&chip->reg->po);
119 reg_val |= (1 << nr);
121 reg_val &= ~(1 << nr);
123 iowrite32(reg_val, &chip->reg->po);
124 mutex_unlock(&chip->lock);
127 static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
129 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
131 return ioread32(&chip->reg->pi) & (1 << nr);
134 static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
137 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
141 mutex_lock(&chip->lock);
142 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
144 iowrite32(pm, &chip->reg->pm);
146 reg_val = ioread32(&chip->reg->po);
148 reg_val |= (1 << nr);
150 reg_val &= ~(1 << nr);
151 iowrite32(reg_val, &chip->reg->po);
153 mutex_unlock(&chip->lock);
158 static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
160 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
163 mutex_lock(&chip->lock);
164 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
166 iowrite32(pm, &chip->reg->pm);
167 mutex_unlock(&chip->lock);
173 * Save register configuration and disable interrupts.
175 static void pch_gpio_save_reg_conf(struct pch_gpio *chip)
177 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
178 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
179 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
180 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
181 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
182 if (chip->ioh == INTEL_EG20T_PCH)
183 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
184 if (chip->ioh == OKISEMI_ML7223n_IOH)
185 chip->pch_gpio_reg.gpio_use_sel_reg =\
186 ioread32(&chip->reg->gpio_use_sel);
190 * This function restores the register configuration of the GPIO device.
192 static void pch_gpio_restore_reg_conf(struct pch_gpio *chip)
194 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
195 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
196 /* to store contents of PO register */
197 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
198 /* to store contents of PM register */
199 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
200 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
201 if (chip->ioh == INTEL_EG20T_PCH)
202 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
203 if (chip->ioh == OKISEMI_ML7223n_IOH)
204 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg,
205 &chip->reg->gpio_use_sel);
208 static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
210 struct pch_gpio *chip = container_of(gpio, struct pch_gpio, gpio);
211 return chip->irq_base + offset;
214 static void pch_gpio_setup(struct pch_gpio *chip)
216 struct gpio_chip *gpio = &chip->gpio;
218 gpio->label = dev_name(chip->dev);
219 gpio->owner = THIS_MODULE;
220 gpio->direction_input = pch_gpio_direction_input;
221 gpio->get = pch_gpio_get;
222 gpio->direction_output = pch_gpio_direction_output;
223 gpio->set = pch_gpio_set;
224 gpio->dbg_show = NULL;
226 gpio->ngpio = gpio_pins[chip->ioh];
228 gpio->to_irq = pch_gpio_to_irq;
231 static int pch_irq_type(struct irq_data *d, unsigned int type)
241 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
242 struct pch_gpio *chip = gc->private;
244 ch = irq - chip->irq_base;
245 if (irq <= chip->irq_base + 7) {
246 im_reg = &chip->reg->im0;
249 im_reg = &chip->reg->im1;
252 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n",
253 __func__, irq, type, ch, im_pos);
255 spin_lock_irqsave(&chip->spinlock, flags);
258 case IRQ_TYPE_EDGE_RISING:
259 val = PCH_EDGE_RISING;
261 case IRQ_TYPE_EDGE_FALLING:
262 val = PCH_EDGE_FALLING;
264 case IRQ_TYPE_EDGE_BOTH:
267 case IRQ_TYPE_LEVEL_HIGH:
270 case IRQ_TYPE_LEVEL_LOW:
276 dev_warn(chip->dev, "%s: unknown type(%dd)",
281 /* Set interrupt mode */
282 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
283 iowrite32(im | (val << (im_pos * 4)), im_reg);
286 iowrite32(BIT(ch), &chip->reg->iclr);
289 iowrite32(BIT(ch), &chip->reg->imaskclr);
291 /* Enable interrupt */
292 ien = ioread32(&chip->reg->ien);
293 iowrite32(ien | BIT(ch), &chip->reg->ien);
295 spin_unlock_irqrestore(&chip->spinlock, flags);
300 static void pch_irq_unmask(struct irq_data *d)
302 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
303 struct pch_gpio *chip = gc->private;
305 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
308 static void pch_irq_mask(struct irq_data *d)
310 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
311 struct pch_gpio *chip = gc->private;
313 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
316 static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
318 struct pch_gpio *chip = dev_id;
319 u32 reg_val = ioread32(&chip->reg->istatus);
323 for (i = 0; i < gpio_pins[chip->ioh]; i++) {
324 if (reg_val & BIT(i)) {
325 dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n",
326 __func__, i, irq, reg_val);
327 iowrite32(BIT(i), &chip->reg->iclr);
328 generic_handle_irq(chip->irq_base + i);
335 static __devinit void pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
336 unsigned int irq_start, unsigned int num)
338 struct irq_chip_generic *gc;
339 struct irq_chip_type *ct;
341 gc = irq_alloc_generic_chip("pch_gpio", 1, irq_start, chip->base,
346 ct->chip.irq_mask = pch_irq_mask;
347 ct->chip.irq_unmask = pch_irq_unmask;
348 ct->chip.irq_set_type = pch_irq_type;
350 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
351 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
354 static int __devinit pch_gpio_probe(struct pci_dev *pdev,
355 const struct pci_device_id *id)
358 struct pch_gpio *chip;
361 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
365 chip->dev = &pdev->dev;
366 ret = pci_enable_device(pdev);
368 dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__);
372 ret = pci_request_regions(pdev, KBUILD_MODNAME);
374 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
375 goto err_request_regions;
378 chip->base = pci_iomap(pdev, 1, 0);
379 if (chip->base == 0) {
380 dev_err(&pdev->dev, "%s : pci_iomap FAILED", __func__);
385 if (pdev->device == 0x8803)
386 chip->ioh = INTEL_EG20T_PCH;
387 else if (pdev->device == 0x8014)
388 chip->ioh = OKISEMI_ML7223m_IOH;
389 else if (pdev->device == 0x8043)
390 chip->ioh = OKISEMI_ML7223n_IOH;
392 chip->reg = chip->base;
393 pci_set_drvdata(pdev, chip);
394 mutex_init(&chip->lock);
395 spin_lock_init(&chip->spinlock);
396 pch_gpio_setup(chip);
397 ret = gpiochip_add(&chip->gpio);
399 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
400 goto err_gpiochip_add;
403 irq_base = irq_alloc_descs(-1, 0, gpio_pins[chip->ioh], NUMA_NO_NODE);
405 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
409 chip->irq_base = irq_base;
411 ret = request_irq(pdev->irq, pch_gpio_handler,
412 IRQF_SHARED, KBUILD_MODNAME, chip);
415 "%s request_irq failed\n", __func__);
416 goto err_request_irq;
419 pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
421 /* Initialize interrupt ien register */
422 iowrite32(0, &chip->reg->ien);
427 irq_free_descs(irq_base, gpio_pins[chip->ioh]);
429 ret = gpiochip_remove(&chip->gpio);
431 dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__);
434 pci_iounmap(pdev, chip->base);
437 pci_release_regions(pdev);
440 pci_disable_device(pdev);
444 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
448 static void __devexit pch_gpio_remove(struct pci_dev *pdev)
451 struct pch_gpio *chip = pci_get_drvdata(pdev);
453 if (chip->irq_base != -1) {
454 free_irq(pdev->irq, chip);
456 irq_free_descs(chip->irq_base, gpio_pins[chip->ioh]);
459 err = gpiochip_remove(&chip->gpio);
461 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
463 pci_iounmap(pdev, chip->base);
464 pci_release_regions(pdev);
465 pci_disable_device(pdev);
470 static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
473 struct pch_gpio *chip = pci_get_drvdata(pdev);
476 spin_lock_irqsave(&chip->spinlock, flags);
477 pch_gpio_save_reg_conf(chip);
478 spin_unlock_irqrestore(&chip->spinlock, flags);
480 ret = pci_save_state(pdev);
482 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
485 pci_disable_device(pdev);
486 pci_set_power_state(pdev, PCI_D0);
487 ret = pci_enable_wake(pdev, PCI_D0, 1);
489 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
494 static int pch_gpio_resume(struct pci_dev *pdev)
497 struct pch_gpio *chip = pci_get_drvdata(pdev);
500 ret = pci_enable_wake(pdev, PCI_D0, 0);
502 pci_set_power_state(pdev, PCI_D0);
503 ret = pci_enable_device(pdev);
505 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
508 pci_restore_state(pdev);
510 spin_lock_irqsave(&chip->spinlock, flags);
511 iowrite32(0x01, &chip->reg->reset);
512 iowrite32(0x00, &chip->reg->reset);
513 pch_gpio_restore_reg_conf(chip);
514 spin_unlock_irqrestore(&chip->spinlock, flags);
519 #define pch_gpio_suspend NULL
520 #define pch_gpio_resume NULL
523 #define PCI_VENDOR_ID_ROHM 0x10DB
524 static DEFINE_PCI_DEVICE_TABLE(pch_gpio_pcidev_id) = {
525 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
526 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
527 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
528 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
531 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
533 static struct pci_driver pch_gpio_driver = {
535 .id_table = pch_gpio_pcidev_id,
536 .probe = pch_gpio_probe,
537 .remove = __devexit_p(pch_gpio_remove),
538 .suspend = pch_gpio_suspend,
539 .resume = pch_gpio_resume
542 static int __init pch_gpio_pci_init(void)
544 return pci_register_driver(&pch_gpio_driver);
546 module_init(pch_gpio_pci_init);
548 static void __exit pch_gpio_pci_exit(void)
550 pci_unregister_driver(&pch_gpio_driver);
552 module_exit(pch_gpio_pci_exit);
554 MODULE_DESCRIPTION("PCH GPIO PCI Driver");
555 MODULE_LICENSE("GPL");