2 * driver/dma/ste_dma40.c
4 * Copyright (C) ST-Ericsson 2007-2010
5 * License terms: GNU General Public License (GPL) version 2
6 * Author: Per Friden <per.friden@stericsson.com>
7 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
18 #include <plat/ste_dma40.h>
20 #include "ste_dma40_ll.h"
22 #define D40_NAME "dma40"
24 #define D40_PHY_CHAN -1
26 /* For masking out/in 2 bit channel positions */
27 #define D40_CHAN_POS(chan) (2 * (chan / 2))
28 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
30 /* Maximum iterations taken before giving up suspending a channel */
31 #define D40_SUSPEND_MAX_IT 500
33 /* Hardware requirement on LCLA alignment */
34 #define LCLA_ALIGNMENT 0x40000
35 /* Attempts before giving up to trying to get pages that are aligned */
36 #define MAX_LCLA_ALLOC_ATTEMPTS 256
38 /* Bit markings for allocation map */
39 #define D40_ALLOC_FREE (1 << 31)
40 #define D40_ALLOC_PHY (1 << 30)
41 #define D40_ALLOC_LOG_FREE 0
43 /* Hardware designer of the block */
44 #define D40_PERIPHID2_DESIGNER 0x8
47 * enum 40_command - The different commands and/or statuses.
49 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
50 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
51 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
52 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
57 D40_DMA_SUSPEND_REQ = 2,
62 * struct d40_lli_pool - Structure for keeping LLIs in memory
64 * @base: Pointer to memory area when the pre_alloc_lli's are not large
65 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
66 * pre_alloc_lli is used.
67 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
68 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
69 * one buffer to one buffer.
74 /* Space for dst and src, plus an extra for padding */
75 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
79 * struct d40_desc - A descriptor is one DMA job.
81 * @lli_phy: LLI settings for physical channel. Both src and dst=
82 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
84 * @lli_log: Same as above but for logical channels.
85 * @lli_pool: The pool with two entries pre-allocated.
86 * @lli_len: Number of llis of current descriptor.
87 * @lli_count: Number of transfered llis.
88 * @lli_tx_len: Max number of LLIs per transfer, there can be
89 * many transfer for one descriptor.
90 * @txd: DMA engine struct. Used for among other things for communication
93 * @dir: The transfer direction of this job.
94 * @is_in_client_list: true if the client owns this descriptor.
96 * This descriptor is used for both logical and physical transfers.
101 struct d40_phy_lli_bidir lli_phy;
103 struct d40_log_lli_bidir lli_log;
105 struct d40_lli_pool lli_pool;
110 struct dma_async_tx_descriptor txd;
111 struct list_head node;
113 enum dma_data_direction dir;
114 bool is_in_client_list;
118 * struct d40_lcla_pool - LCLA pool settings and data.
120 * @base: The virtual address of LCLA. 18 bit aligned.
121 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
122 * This pointer is only there for clean-up on error.
123 * @pages: The number of pages needed for all physical channels.
124 * Only used later for clean-up on error
125 * @lock: Lock to protect the content in this struct.
126 * @alloc_map: Bitmap mapping between physical channel and LCLA entries.
127 * @num_blocks: The number of entries of alloc_map. Equals to the
128 * number of physical channels.
130 struct d40_lcla_pool {
132 void *base_unaligned;
140 * struct d40_phy_res - struct for handling eventlines mapped to physical
143 * @lock: A lock protection this entity.
144 * @num: The physical channel number of this entity.
145 * @allocated_src: Bit mapped to show which src event line's are mapped to
146 * this physical channel. Can also be free or physically allocated.
147 * @allocated_dst: Same as for src but is dst.
148 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
149 * event line number. Both allocated_src and allocated_dst can not be
150 * allocated to a physical channel, since the interrupt handler has then
151 * no way of figure out which one the interrupt belongs to.
163 * struct d40_chan - Struct that describes a channel.
165 * @lock: A spinlock to protect this struct.
166 * @log_num: The logical number, if any of this channel.
167 * @completed: Starts with 1, after first interrupt it is set to dma engine's
169 * @pending_tx: The number of pending transfers. Used between interrupt handler
171 * @busy: Set to true when transfer is ongoing on this channel.
172 * @phy_chan: Pointer to physical channel which this instance runs on. If this
173 * point is NULL, then the channel is not allocated.
174 * @chan: DMA engine handle.
175 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
176 * transfer and call client callback.
177 * @client: Cliented owned descriptor list.
178 * @active: Active descriptor.
179 * @queue: Queued jobs.
180 * @dma_cfg: The client configuration of this dma channel.
181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
188 * This struct can either "be" a logical or a physical channel.
193 /* ID of the most recent completed transfer */
197 struct d40_phy_res *phy_chan;
198 struct dma_chan chan;
199 struct tasklet_struct tasklet;
200 struct list_head client;
201 struct list_head active;
202 struct list_head queue;
203 struct stedma40_chan_cfg dma_cfg;
204 struct d40_base *base;
205 /* Default register configurations */
208 struct d40_def_lcsp log_def;
209 struct d40_lcla_elem lcla;
210 struct d40_log_lli_full *lcpa;
211 /* Runtime reconfiguration */
212 dma_addr_t runtime_addr;
213 enum dma_data_direction runtime_direction;
217 * struct d40_base - The big global struct, one for each probe'd instance.
219 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220 * @execmd_lock: Lock for execute command usage since several channels share
221 * the same physical register.
222 * @dev: The device structure.
223 * @virtbase: The virtual base address of the DMA's register.
224 * @rev: silicon revision detected.
225 * @clk: Pointer to the DMA clock structure.
226 * @phy_start: Physical memory start of the DMA registers.
227 * @phy_size: Size of the DMA register map.
228 * @irq: The IRQ number.
229 * @num_phy_chans: The number of physical channels. Read from HW. This
230 * is the number of available channels for this driver, not counting "Secure
231 * mode" allocated physical channels.
232 * @num_log_chans: The number of logical channels. Calculated from
234 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235 * @dma_slave: dma_device channels that can do only do slave transfers.
236 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
237 * @phy_chans: Room for all possible physical channels in system.
238 * @log_chans: Room for all possible logical channels in system.
239 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
240 * to log_chans entries.
241 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
242 * to phy_chans entries.
243 * @plat_data: Pointer to provided platform_data which is the driver
245 * @phy_res: Vector containing all physical channels.
246 * @lcla_pool: lcla pool settings and data.
247 * @lcpa_base: The virtual mapped address of LCPA.
248 * @phy_lcpa: The physical address of the LCPA.
249 * @lcpa_size: The size of the LCPA area.
250 * @desc_slab: cache for descriptors.
253 spinlock_t interrupt_lock;
254 spinlock_t execmd_lock;
256 void __iomem *virtbase;
259 phys_addr_t phy_start;
260 resource_size_t phy_size;
264 struct dma_device dma_both;
265 struct dma_device dma_slave;
266 struct dma_device dma_memcpy;
267 struct d40_chan *phy_chans;
268 struct d40_chan *log_chans;
269 struct d40_chan **lookup_log_chans;
270 struct d40_chan **lookup_phy_chans;
271 struct stedma40_platform_data *plat_data;
272 /* Physical half channels */
273 struct d40_phy_res *phy_res;
274 struct d40_lcla_pool lcla_pool;
277 resource_size_t lcpa_size;
278 struct kmem_cache *desc_slab;
282 * struct d40_interrupt_lookup - lookup table for interrupt handler
284 * @src: Interrupt mask register.
285 * @clr: Interrupt clear register.
286 * @is_error: true if this is an error interrupt.
287 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
288 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
290 struct d40_interrupt_lookup {
298 * struct d40_reg_val - simple lookup struct
300 * @reg: The register.
301 * @val: The value that belongs to the register in reg.
308 static int d40_pool_lli_alloc(struct d40_desc *d40d,
309 int lli_len, bool is_log)
315 align = sizeof(struct d40_log_lli);
317 align = sizeof(struct d40_phy_lli);
320 base = d40d->lli_pool.pre_alloc_lli;
321 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
322 d40d->lli_pool.base = NULL;
324 d40d->lli_pool.size = ALIGN(lli_len * 2 * align, align);
326 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
327 d40d->lli_pool.base = base;
329 if (d40d->lli_pool.base == NULL)
334 d40d->lli_log.src = PTR_ALIGN((struct d40_log_lli *) base,
336 d40d->lli_log.dst = PTR_ALIGN(d40d->lli_log.src + lli_len,
339 d40d->lli_phy.src = PTR_ALIGN((struct d40_phy_lli *)base,
341 d40d->lli_phy.dst = PTR_ALIGN(d40d->lli_phy.src + lli_len,
344 d40d->lli_phy.src_addr = virt_to_phys(d40d->lli_phy.src);
345 d40d->lli_phy.dst_addr = virt_to_phys(d40d->lli_phy.dst);
351 static void d40_pool_lli_free(struct d40_desc *d40d)
353 kfree(d40d->lli_pool.base);
354 d40d->lli_pool.base = NULL;
355 d40d->lli_pool.size = 0;
356 d40d->lli_log.src = NULL;
357 d40d->lli_log.dst = NULL;
358 d40d->lli_phy.src = NULL;
359 d40d->lli_phy.dst = NULL;
360 d40d->lli_phy.src_addr = 0;
361 d40d->lli_phy.dst_addr = 0;
364 static dma_cookie_t d40_assign_cookie(struct d40_chan *d40c,
365 struct d40_desc *desc)
367 dma_cookie_t cookie = d40c->chan.cookie;
372 d40c->chan.cookie = cookie;
373 desc->txd.cookie = cookie;
378 static void d40_desc_remove(struct d40_desc *d40d)
380 list_del(&d40d->node);
383 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
388 if (!list_empty(&d40c->client)) {
389 list_for_each_entry_safe(d, _d, &d40c->client, node)
390 if (async_tx_test_ack(&d->txd)) {
391 d40_pool_lli_free(d);
396 d = kmem_cache_alloc(d40c->base->desc_slab, GFP_NOWAIT);
398 memset(d, 0, sizeof(struct d40_desc));
399 INIT_LIST_HEAD(&d->node);
405 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
407 kmem_cache_free(d40c->base->desc_slab, d40d);
410 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
412 list_add_tail(&desc->node, &d40c->active);
415 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
419 if (list_empty(&d40c->active))
422 d = list_first_entry(&d40c->active,
428 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
430 list_add_tail(&desc->node, &d40c->queue);
433 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
437 if (list_empty(&d40c->queue))
440 d = list_first_entry(&d40c->queue,
446 /* Support functions for logical channels */
448 static int d40_lcla_id_get(struct d40_chan *d40c)
452 struct d40_log_lli *lcla_lidx_base =
453 d40c->base->lcla_pool.base + d40c->phy_chan->num * 1024;
455 int lli_per_log = d40c->base->plat_data->llis_per_log;
458 if (d40c->lcla.src_id >= 0 && d40c->lcla.dst_id >= 0)
461 if (d40c->base->lcla_pool.num_blocks > 32)
464 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
466 for (i = 0; i < d40c->base->lcla_pool.num_blocks; i++) {
467 if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
469 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
475 if (src_id >= d40c->base->lcla_pool.num_blocks)
478 for (; i < d40c->base->lcla_pool.num_blocks; i++) {
479 if (!(d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &
481 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] |=
488 if (dst_id == src_id)
491 d40c->lcla.src_id = src_id;
492 d40c->lcla.dst_id = dst_id;
493 d40c->lcla.dst = lcla_lidx_base + dst_id * lli_per_log + 1;
494 d40c->lcla.src = lcla_lidx_base + src_id * lli_per_log + 1;
496 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
499 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
504 static int d40_channel_execute_command(struct d40_chan *d40c,
505 enum d40_command command)
508 void __iomem *active_reg;
513 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
515 if (d40c->phy_chan->num % 2 == 0)
516 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
518 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
520 if (command == D40_DMA_SUSPEND_REQ) {
521 status = (readl(active_reg) &
522 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
523 D40_CHAN_POS(d40c->phy_chan->num);
525 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
529 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
530 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
533 if (command == D40_DMA_SUSPEND_REQ) {
535 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
536 status = (readl(active_reg) &
537 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
538 D40_CHAN_POS(d40c->phy_chan->num);
542 * Reduce the number of bus accesses while
543 * waiting for the DMA to suspend.
547 if (status == D40_DMA_STOP ||
548 status == D40_DMA_SUSPENDED)
552 if (i == D40_SUSPEND_MAX_IT) {
553 dev_err(&d40c->chan.dev->device,
554 "[%s]: unable to suspend the chl %d (log: %d) status %x\n",
555 __func__, d40c->phy_chan->num, d40c->log_num,
563 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
567 static void d40_term_all(struct d40_chan *d40c)
569 struct d40_desc *d40d;
572 /* Release active descriptors */
573 while ((d40d = d40_first_active_get(d40c))) {
574 d40_desc_remove(d40d);
576 /* Return desc to free-list */
577 d40_desc_free(d40c, d40d);
580 /* Release queued descriptors waiting for transfer */
581 while ((d40d = d40_first_queued(d40c))) {
582 d40_desc_remove(d40d);
584 /* Return desc to free-list */
585 d40_desc_free(d40c, d40d);
588 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
590 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
591 (~(0x1 << d40c->lcla.dst_id));
592 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num] &=
593 (~(0x1 << d40c->lcla.src_id));
595 d40c->lcla.src_id = -1;
596 d40c->lcla.dst_id = -1;
598 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
600 d40c->pending_tx = 0;
604 static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
609 /* Notice, that disable requires the physical channel to be stopped */
611 val = D40_ACTIVATE_EVENTLINE;
613 val = D40_DEACTIVATE_EVENTLINE;
615 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
617 /* Enable event line connected to device (or memcpy) */
618 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
619 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
620 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
622 writel((val << D40_EVENTLINE_POS(event)) |
623 ~D40_EVENTLINE_MASK(event),
624 d40c->base->virtbase + D40_DREG_PCBASE +
625 d40c->phy_chan->num * D40_DREG_PCDELTA +
628 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
629 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
631 writel((val << D40_EVENTLINE_POS(event)) |
632 ~D40_EVENTLINE_MASK(event),
633 d40c->base->virtbase + D40_DREG_PCBASE +
634 d40c->phy_chan->num * D40_DREG_PCDELTA +
638 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
641 static u32 d40_chan_has_events(struct d40_chan *d40c)
645 val = readl(d40c->base->virtbase + D40_DREG_PCBASE +
646 d40c->phy_chan->num * D40_DREG_PCDELTA +
649 val |= readl(d40c->base->virtbase + D40_DREG_PCBASE +
650 d40c->phy_chan->num * D40_DREG_PCDELTA +
655 static void d40_config_enable_lidx(struct d40_chan *d40c)
657 /* Set LIDX for lcla */
658 writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
659 D40_SREG_ELEM_LOG_LIDX_MASK,
660 d40c->base->virtbase + D40_DREG_PCBASE +
661 d40c->phy_chan->num * D40_DREG_PCDELTA + D40_CHAN_REG_SDELT);
663 writel((d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS) &
664 D40_SREG_ELEM_LOG_LIDX_MASK,
665 d40c->base->virtbase + D40_DREG_PCBASE +
666 d40c->phy_chan->num * D40_DREG_PCDELTA + D40_CHAN_REG_SSELT);
669 static int d40_config_write(struct d40_chan *d40c)
675 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
679 /* Odd addresses are even addresses + 4 */
680 addr_base = (d40c->phy_chan->num % 2) * 4;
681 /* Setup channel mode to logical or physical */
682 var = ((u32)(d40c->log_num != D40_PHY_CHAN) + 1) <<
683 D40_CHAN_POS(d40c->phy_chan->num);
684 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
686 /* Setup operational mode option register */
687 var = ((d40c->dma_cfg.channel_type >> STEDMA40_INFO_CH_MODE_OPT_POS) &
688 0x3) << D40_CHAN_POS(d40c->phy_chan->num);
690 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
692 if (d40c->log_num != D40_PHY_CHAN) {
693 /* Set default config for CFG reg */
694 writel(d40c->src_def_cfg,
695 d40c->base->virtbase + D40_DREG_PCBASE +
696 d40c->phy_chan->num * D40_DREG_PCDELTA +
698 writel(d40c->dst_def_cfg,
699 d40c->base->virtbase + D40_DREG_PCBASE +
700 d40c->phy_chan->num * D40_DREG_PCDELTA +
703 d40_config_enable_lidx(d40c);
708 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
710 if (d40d->lli_phy.dst && d40d->lli_phy.src) {
711 d40_phy_lli_write(d40c->base->virtbase,
715 } else if (d40d->lli_log.dst && d40d->lli_log.src) {
716 struct d40_log_lli *src = d40d->lli_log.src;
717 struct d40_log_lli *dst = d40d->lli_log.dst;
720 src += d40d->lli_count;
721 dst += d40d->lli_count;
722 s = d40_log_lli_write(d40c->lcpa,
723 d40c->lcla.src, d40c->lcla.dst,
725 d40c->base->plat_data->llis_per_log);
727 /* If s equals to zero, the job is not linked */
729 (void) dma_map_single(d40c->base->dev, d40c->lcla.src,
730 s * sizeof(struct d40_log_lli),
732 (void) dma_map_single(d40c->base->dev, d40c->lcla.dst,
733 s * sizeof(struct d40_log_lli),
737 d40d->lli_count += d40d->lli_tx_len;
740 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
742 struct d40_chan *d40c = container_of(tx->chan,
745 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
748 spin_lock_irqsave(&d40c->lock, flags);
750 tx->cookie = d40_assign_cookie(d40c, d40d);
752 d40_desc_queue(d40c, d40d);
754 spin_unlock_irqrestore(&d40c->lock, flags);
759 static int d40_start(struct d40_chan *d40c)
761 if (d40c->base->rev == 0) {
764 if (d40c->log_num != D40_PHY_CHAN) {
765 err = d40_channel_execute_command(d40c,
766 D40_DMA_SUSPEND_REQ);
772 if (d40c->log_num != D40_PHY_CHAN)
773 d40_config_set_event(d40c, true);
775 return d40_channel_execute_command(d40c, D40_DMA_RUN);
778 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
780 struct d40_desc *d40d;
783 /* Start queued jobs, if any */
784 d40d = d40_first_queued(d40c);
789 /* Remove from queue */
790 d40_desc_remove(d40d);
792 /* Add to active queue */
793 d40_desc_submit(d40c, d40d);
795 /* Initiate DMA job */
796 d40_desc_load(d40c, d40d);
799 err = d40_start(d40c);
808 /* called from interrupt context */
809 static void dma_tc_handle(struct d40_chan *d40c)
811 struct d40_desc *d40d;
816 /* Get first active entry from list */
817 d40d = d40_first_active_get(d40c);
822 if (d40d->lli_count < d40d->lli_len) {
824 d40_desc_load(d40c, d40d);
826 (void) d40_start(d40c);
830 if (d40_queue_start(d40c) == NULL)
834 tasklet_schedule(&d40c->tasklet);
838 static void dma_tasklet(unsigned long data)
840 struct d40_chan *d40c = (struct d40_chan *) data;
841 struct d40_desc *d40d_fin;
843 dma_async_tx_callback callback;
844 void *callback_param;
846 spin_lock_irqsave(&d40c->lock, flags);
848 /* Get first active entry from list */
849 d40d_fin = d40_first_active_get(d40c);
851 if (d40d_fin == NULL)
854 d40c->completed = d40d_fin->txd.cookie;
857 * If terminating a channel pending_tx is set to zero.
858 * This prevents any finished active jobs to return to the client.
860 if (d40c->pending_tx == 0) {
861 spin_unlock_irqrestore(&d40c->lock, flags);
865 /* Callback to client */
866 callback = d40d_fin->txd.callback;
867 callback_param = d40d_fin->txd.callback_param;
869 if (async_tx_test_ack(&d40d_fin->txd)) {
870 d40_pool_lli_free(d40d_fin);
871 d40_desc_remove(d40d_fin);
872 /* Return desc to free-list */
873 d40_desc_free(d40c, d40d_fin);
875 if (!d40d_fin->is_in_client_list) {
876 d40_desc_remove(d40d_fin);
877 list_add_tail(&d40d_fin->node, &d40c->client);
878 d40d_fin->is_in_client_list = true;
884 if (d40c->pending_tx)
885 tasklet_schedule(&d40c->tasklet);
887 spin_unlock_irqrestore(&d40c->lock, flags);
890 callback(callback_param);
895 /* Rescue manouver if receiving double interrupts */
896 if (d40c->pending_tx > 0)
898 spin_unlock_irqrestore(&d40c->lock, flags);
901 static irqreturn_t d40_handle_interrupt(int irq, void *data)
903 static const struct d40_interrupt_lookup il[] = {
904 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
905 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
906 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
907 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
908 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
909 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
910 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
911 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
912 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
913 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
917 u32 regs[ARRAY_SIZE(il)];
921 struct d40_chan *d40c;
923 struct d40_base *base = data;
925 spin_lock_irqsave(&base->interrupt_lock, flags);
927 /* Read interrupt status of both logical and physical channels */
928 for (i = 0; i < ARRAY_SIZE(il); i++)
929 regs[i] = readl(base->virtbase + il[i].src);
933 chan = find_next_bit((unsigned long *)regs,
934 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
936 /* No more set bits found? */
937 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
940 row = chan / BITS_PER_LONG;
941 idx = chan & (BITS_PER_LONG - 1);
944 writel(1 << idx, base->virtbase + il[row].clr);
946 if (il[row].offset == D40_PHY_CHAN)
947 d40c = base->lookup_phy_chans[idx];
949 d40c = base->lookup_log_chans[il[row].offset + idx];
950 spin_lock(&d40c->lock);
952 if (!il[row].is_error)
956 "[%s] IRQ chan: %ld offset %d idx %d\n",
957 __func__, chan, il[row].offset, idx);
959 spin_unlock(&d40c->lock);
962 spin_unlock_irqrestore(&base->interrupt_lock, flags);
968 static int d40_validate_conf(struct d40_chan *d40c,
969 struct stedma40_chan_cfg *conf)
972 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
973 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
974 bool is_log = (conf->channel_type & STEDMA40_CHANNEL_IN_OPER_MODE)
975 == STEDMA40_CHANNEL_IN_LOG_MODE;
978 dev_err(&d40c->chan.dev->device, "[%s] Invalid direction.\n",
983 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
984 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
985 d40c->runtime_addr == 0) {
987 dev_err(&d40c->chan.dev->device,
988 "[%s] Invalid TX channel address (%d)\n",
989 __func__, conf->dst_dev_type);
993 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
994 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
995 d40c->runtime_addr == 0) {
996 dev_err(&d40c->chan.dev->device,
997 "[%s] Invalid RX channel address (%d)\n",
998 __func__, conf->src_dev_type);
1002 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
1003 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
1004 dev_err(&d40c->chan.dev->device, "[%s] Invalid dst\n",
1009 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
1010 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1011 dev_err(&d40c->chan.dev->device, "[%s] Invalid src\n",
1016 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1017 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1018 dev_err(&d40c->chan.dev->device,
1019 "[%s] No event line\n", __func__);
1023 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1024 (src_event_group != dst_event_group)) {
1025 dev_err(&d40c->chan.dev->device,
1026 "[%s] Invalid event group\n", __func__);
1030 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1032 * DMAC HW supports it. Will be added to this driver,
1033 * in case any dma client requires it.
1035 dev_err(&d40c->chan.dev->device,
1036 "[%s] periph to periph not supported\n",
1044 static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
1045 int log_event_line, bool is_log)
1047 unsigned long flags;
1048 spin_lock_irqsave(&phy->lock, flags);
1050 /* Physical interrupts are masked per physical full channel */
1051 if (phy->allocated_src == D40_ALLOC_FREE &&
1052 phy->allocated_dst == D40_ALLOC_FREE) {
1053 phy->allocated_dst = D40_ALLOC_PHY;
1054 phy->allocated_src = D40_ALLOC_PHY;
1060 /* Logical channel */
1062 if (phy->allocated_src == D40_ALLOC_PHY)
1065 if (phy->allocated_src == D40_ALLOC_FREE)
1066 phy->allocated_src = D40_ALLOC_LOG_FREE;
1068 if (!(phy->allocated_src & (1 << log_event_line))) {
1069 phy->allocated_src |= 1 << log_event_line;
1074 if (phy->allocated_dst == D40_ALLOC_PHY)
1077 if (phy->allocated_dst == D40_ALLOC_FREE)
1078 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1080 if (!(phy->allocated_dst & (1 << log_event_line))) {
1081 phy->allocated_dst |= 1 << log_event_line;
1088 spin_unlock_irqrestore(&phy->lock, flags);
1091 spin_unlock_irqrestore(&phy->lock, flags);
1095 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1098 unsigned long flags;
1099 bool is_free = false;
1101 spin_lock_irqsave(&phy->lock, flags);
1102 if (!log_event_line) {
1103 /* Physical interrupts are masked per physical full channel */
1104 phy->allocated_dst = D40_ALLOC_FREE;
1105 phy->allocated_src = D40_ALLOC_FREE;
1110 /* Logical channel */
1112 phy->allocated_src &= ~(1 << log_event_line);
1113 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1114 phy->allocated_src = D40_ALLOC_FREE;
1116 phy->allocated_dst &= ~(1 << log_event_line);
1117 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1118 phy->allocated_dst = D40_ALLOC_FREE;
1121 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1125 spin_unlock_irqrestore(&phy->lock, flags);
1130 static int d40_allocate_channel(struct d40_chan *d40c)
1135 struct d40_phy_res *phys;
1140 bool is_log = (d40c->dma_cfg.channel_type &
1141 STEDMA40_CHANNEL_IN_OPER_MODE)
1142 == STEDMA40_CHANNEL_IN_LOG_MODE;
1145 phys = d40c->base->phy_res;
1147 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1148 dev_type = d40c->dma_cfg.src_dev_type;
1149 log_num = 2 * dev_type;
1151 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1152 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1153 /* dst event lines are used for logical memcpy */
1154 dev_type = d40c->dma_cfg.dst_dev_type;
1155 log_num = 2 * dev_type + 1;
1160 event_group = D40_TYPE_TO_GROUP(dev_type);
1161 event_line = D40_TYPE_TO_EVENT(dev_type);
1164 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1165 /* Find physical half channel */
1166 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1168 if (d40_alloc_mask_set(&phys[i], is_src,
1173 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1174 int phy_num = j + event_group * 2;
1175 for (i = phy_num; i < phy_num + 2; i++) {
1176 if (d40_alloc_mask_set(&phys[i],
1185 d40c->phy_chan = &phys[i];
1186 d40c->log_num = D40_PHY_CHAN;
1192 /* Find logical channel */
1193 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1194 int phy_num = j + event_group * 2;
1196 * Spread logical channels across all available physical rather
1197 * than pack every logical channel at the first available phy
1201 for (i = phy_num; i < phy_num + 2; i++) {
1202 if (d40_alloc_mask_set(&phys[i], is_src,
1203 event_line, is_log))
1207 for (i = phy_num + 1; i >= phy_num; i--) {
1208 if (d40_alloc_mask_set(&phys[i], is_src,
1209 event_line, is_log))
1217 d40c->phy_chan = &phys[i];
1218 d40c->log_num = log_num;
1222 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1224 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1230 static int d40_config_memcpy(struct d40_chan *d40c)
1232 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1234 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1235 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1236 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1237 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1238 memcpy[d40c->chan.chan_id];
1240 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1241 dma_has_cap(DMA_SLAVE, cap)) {
1242 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1244 dev_err(&d40c->chan.dev->device, "[%s] No memcpy\n",
1253 static int d40_free_dma(struct d40_chan *d40c)
1258 struct d40_phy_res *phy = d40c->phy_chan;
1261 struct d40_desc *_d;
1264 /* Terminate all queued and active transfers */
1267 /* Release client owned descriptors */
1268 if (!list_empty(&d40c->client))
1269 list_for_each_entry_safe(d, _d, &d40c->client, node) {
1270 d40_pool_lli_free(d);
1272 /* Return desc to free-list */
1273 d40_desc_free(d40c, d);
1277 dev_err(&d40c->chan.dev->device, "[%s] phy == null\n",
1282 if (phy->allocated_src == D40_ALLOC_FREE &&
1283 phy->allocated_dst == D40_ALLOC_FREE) {
1284 dev_err(&d40c->chan.dev->device, "[%s] channel already free\n",
1289 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1290 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1291 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1293 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1294 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1297 dev_err(&d40c->chan.dev->device,
1298 "[%s] Unknown direction\n", __func__);
1302 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1304 dev_err(&d40c->chan.dev->device, "[%s] suspend failed\n",
1309 if (d40c->log_num != D40_PHY_CHAN) {
1310 /* Release logical channel, deactivate the event line */
1312 d40_config_set_event(d40c, false);
1313 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1316 * Check if there are more logical allocation
1317 * on this phy channel.
1319 if (!d40_alloc_mask_free(phy, is_src, event)) {
1320 /* Resume the other logical channels if any */
1321 if (d40_chan_has_events(d40c)) {
1322 res = d40_channel_execute_command(d40c,
1325 dev_err(&d40c->chan.dev->device,
1326 "[%s] Executing RUN command\n",
1334 (void) d40_alloc_mask_free(phy, is_src, 0);
1337 /* Release physical channel */
1338 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1340 dev_err(&d40c->chan.dev->device,
1341 "[%s] Failed to stop channel\n", __func__);
1344 d40c->phy_chan = NULL;
1345 /* Invalidate channel type */
1346 d40c->dma_cfg.channel_type = 0;
1347 d40c->base->lookup_phy_chans[phy->num] = NULL;
1352 static int d40_pause(struct dma_chan *chan)
1354 struct d40_chan *d40c =
1355 container_of(chan, struct d40_chan, chan);
1357 unsigned long flags;
1359 spin_lock_irqsave(&d40c->lock, flags);
1361 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1363 if (d40c->log_num != D40_PHY_CHAN) {
1364 d40_config_set_event(d40c, false);
1365 /* Resume the other logical channels if any */
1366 if (d40_chan_has_events(d40c))
1367 res = d40_channel_execute_command(d40c,
1372 spin_unlock_irqrestore(&d40c->lock, flags);
1376 static bool d40_is_paused(struct d40_chan *d40c)
1378 bool is_paused = false;
1379 unsigned long flags;
1380 void __iomem *active_reg;
1384 spin_lock_irqsave(&d40c->lock, flags);
1386 if (d40c->log_num == D40_PHY_CHAN) {
1387 if (d40c->phy_chan->num % 2 == 0)
1388 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1390 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1392 status = (readl(active_reg) &
1393 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1394 D40_CHAN_POS(d40c->phy_chan->num);
1395 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1401 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1402 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM)
1403 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1404 else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1405 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1407 dev_err(&d40c->chan.dev->device,
1408 "[%s] Unknown direction\n", __func__);
1411 status = d40_chan_has_events(d40c);
1412 status = (status & D40_EVENTLINE_MASK(event)) >>
1413 D40_EVENTLINE_POS(event);
1415 if (status != D40_DMA_RUN)
1418 spin_unlock_irqrestore(&d40c->lock, flags);
1424 static bool d40_tx_is_linked(struct d40_chan *d40c)
1428 if (d40c->log_num != D40_PHY_CHAN)
1429 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1431 is_link = readl(d40c->base->virtbase + D40_DREG_PCBASE +
1432 d40c->phy_chan->num * D40_DREG_PCDELTA +
1433 D40_CHAN_REG_SDLNK) &
1434 D40_SREG_LNK_PHYS_LNK_MASK;
1438 static u32 d40_residue(struct d40_chan *d40c)
1442 if (d40c->log_num != D40_PHY_CHAN)
1443 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1444 >> D40_MEM_LCSP2_ECNT_POS;
1446 num_elt = (readl(d40c->base->virtbase + D40_DREG_PCBASE +
1447 d40c->phy_chan->num * D40_DREG_PCDELTA +
1448 D40_CHAN_REG_SDELT) &
1449 D40_SREG_ELEM_PHY_ECNT_MASK) >>
1450 D40_SREG_ELEM_PHY_ECNT_POS;
1451 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1454 static int d40_resume(struct dma_chan *chan)
1456 struct d40_chan *d40c =
1457 container_of(chan, struct d40_chan, chan);
1459 unsigned long flags;
1461 spin_lock_irqsave(&d40c->lock, flags);
1463 if (d40c->base->rev == 0)
1464 if (d40c->log_num != D40_PHY_CHAN) {
1465 res = d40_channel_execute_command(d40c,
1466 D40_DMA_SUSPEND_REQ);
1470 /* If bytes left to transfer or linked tx resume job */
1471 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
1472 if (d40c->log_num != D40_PHY_CHAN)
1473 d40_config_set_event(d40c, true);
1474 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1478 spin_unlock_irqrestore(&d40c->lock, flags);
1482 static u32 stedma40_residue(struct dma_chan *chan)
1484 struct d40_chan *d40c =
1485 container_of(chan, struct d40_chan, chan);
1487 unsigned long flags;
1489 spin_lock_irqsave(&d40c->lock, flags);
1490 bytes_left = d40_residue(d40c);
1491 spin_unlock_irqrestore(&d40c->lock, flags);
1496 /* Public DMA functions in addition to the DMA engine framework */
1498 int stedma40_set_psize(struct dma_chan *chan,
1502 struct d40_chan *d40c =
1503 container_of(chan, struct d40_chan, chan);
1504 unsigned long flags;
1506 spin_lock_irqsave(&d40c->lock, flags);
1508 if (d40c->log_num != D40_PHY_CHAN) {
1509 d40c->log_def.lcsp1 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
1510 d40c->log_def.lcsp3 &= ~D40_MEM_LCSP1_SCFG_PSIZE_MASK;
1511 d40c->log_def.lcsp1 |= src_psize <<
1512 D40_MEM_LCSP1_SCFG_PSIZE_POS;
1513 d40c->log_def.lcsp3 |= dst_psize <<
1514 D40_MEM_LCSP1_SCFG_PSIZE_POS;
1518 if (src_psize == STEDMA40_PSIZE_PHY_1)
1519 d40c->src_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
1521 d40c->src_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
1522 d40c->src_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
1523 D40_SREG_CFG_PSIZE_POS);
1524 d40c->src_def_cfg |= src_psize << D40_SREG_CFG_PSIZE_POS;
1527 if (dst_psize == STEDMA40_PSIZE_PHY_1)
1528 d40c->dst_def_cfg &= ~(1 << D40_SREG_CFG_PHY_PEN_POS);
1530 d40c->dst_def_cfg |= 1 << D40_SREG_CFG_PHY_PEN_POS;
1531 d40c->dst_def_cfg &= ~(STEDMA40_PSIZE_PHY_16 <<
1532 D40_SREG_CFG_PSIZE_POS);
1533 d40c->dst_def_cfg |= dst_psize << D40_SREG_CFG_PSIZE_POS;
1536 spin_unlock_irqrestore(&d40c->lock, flags);
1539 EXPORT_SYMBOL(stedma40_set_psize);
1541 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
1542 struct scatterlist *sgl_dst,
1543 struct scatterlist *sgl_src,
1544 unsigned int sgl_len,
1545 unsigned long dma_flags)
1548 struct d40_desc *d40d;
1549 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1551 unsigned long flags;
1553 if (d40c->phy_chan == NULL) {
1554 dev_err(&d40c->chan.dev->device,
1555 "[%s] Unallocated channel.\n", __func__);
1556 return ERR_PTR(-EINVAL);
1559 spin_lock_irqsave(&d40c->lock, flags);
1560 d40d = d40_desc_get(d40c);
1565 d40d->lli_len = sgl_len;
1566 d40d->lli_tx_len = d40d->lli_len;
1567 d40d->txd.flags = dma_flags;
1569 if (d40c->log_num != D40_PHY_CHAN) {
1570 if (d40d->lli_len > d40c->base->plat_data->llis_per_log)
1571 d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
1575 * Check if there is space available in lcla. If not,
1576 * split list into 1-length and run only in lcpa
1579 if (d40_lcla_id_get(d40c) != 0)
1580 d40d->lli_tx_len = 1;
1582 if (d40_pool_lli_alloc(d40d, sgl_len, true) < 0) {
1583 dev_err(&d40c->chan.dev->device,
1584 "[%s] Out of memory\n", __func__);
1588 (void) d40_log_sg_to_lli(d40c->lcla.src_id,
1592 d40c->log_def.lcsp1,
1593 d40c->dma_cfg.src_info.data_width,
1594 dma_flags & DMA_PREP_INTERRUPT,
1596 d40c->base->plat_data->llis_per_log);
1598 (void) d40_log_sg_to_lli(d40c->lcla.dst_id,
1602 d40c->log_def.lcsp3,
1603 d40c->dma_cfg.dst_info.data_width,
1604 dma_flags & DMA_PREP_INTERRUPT,
1606 d40c->base->plat_data->llis_per_log);
1610 if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
1611 dev_err(&d40c->chan.dev->device,
1612 "[%s] Out of memory\n", __func__);
1616 res = d40_phy_sg_to_lli(sgl_src,
1620 d40d->lli_phy.src_addr,
1622 d40c->dma_cfg.src_info.data_width,
1623 d40c->dma_cfg.src_info.psize,
1629 res = d40_phy_sg_to_lli(sgl_dst,
1633 d40d->lli_phy.dst_addr,
1635 d40c->dma_cfg.dst_info.data_width,
1636 d40c->dma_cfg.dst_info.psize,
1642 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1643 d40d->lli_pool.size, DMA_TO_DEVICE);
1646 dma_async_tx_descriptor_init(&d40d->txd, chan);
1648 d40d->txd.tx_submit = d40_tx_submit;
1650 spin_unlock_irqrestore(&d40c->lock, flags);
1654 spin_unlock_irqrestore(&d40c->lock, flags);
1657 EXPORT_SYMBOL(stedma40_memcpy_sg);
1659 bool stedma40_filter(struct dma_chan *chan, void *data)
1661 struct stedma40_chan_cfg *info = data;
1662 struct d40_chan *d40c =
1663 container_of(chan, struct d40_chan, chan);
1667 err = d40_validate_conf(d40c, info);
1669 d40c->dma_cfg = *info;
1671 err = d40_config_memcpy(d40c);
1675 EXPORT_SYMBOL(stedma40_filter);
1677 /* DMA ENGINE functions */
1678 static int d40_alloc_chan_resources(struct dma_chan *chan)
1681 unsigned long flags;
1682 struct d40_chan *d40c =
1683 container_of(chan, struct d40_chan, chan);
1685 spin_lock_irqsave(&d40c->lock, flags);
1687 d40c->completed = chan->cookie = 1;
1690 * If no dma configuration is set (channel_type == 0)
1691 * use default configuration (memcpy)
1693 if (d40c->dma_cfg.channel_type == 0) {
1694 err = d40_config_memcpy(d40c);
1696 dev_err(&d40c->chan.dev->device,
1697 "[%s] Failed to configure memcpy channel\n",
1702 is_free_phy = (d40c->phy_chan == NULL);
1704 err = d40_allocate_channel(d40c);
1706 dev_err(&d40c->chan.dev->device,
1707 "[%s] Failed to allocate channel\n", __func__);
1711 /* Fill in basic CFG register values */
1712 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
1713 &d40c->dst_def_cfg, d40c->log_num != D40_PHY_CHAN);
1715 if (d40c->log_num != D40_PHY_CHAN) {
1716 d40_log_cfg(&d40c->dma_cfg,
1717 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
1719 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
1720 d40c->lcpa = d40c->base->lcpa_base +
1721 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
1723 d40c->lcpa = d40c->base->lcpa_base +
1724 d40c->dma_cfg.dst_dev_type *
1725 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
1729 * Only write channel configuration to the DMA if the physical
1730 * resource is free. In case of multiple logical channels
1731 * on the same physical resource, only the first write is necessary.
1734 err = d40_config_write(d40c);
1736 dev_err(&d40c->chan.dev->device,
1737 "[%s] Failed to configure channel\n",
1742 spin_unlock_irqrestore(&d40c->lock, flags);
1746 static void d40_free_chan_resources(struct dma_chan *chan)
1748 struct d40_chan *d40c =
1749 container_of(chan, struct d40_chan, chan);
1751 unsigned long flags;
1753 if (d40c->phy_chan == NULL) {
1754 dev_err(&d40c->chan.dev->device,
1755 "[%s] Cannot free unallocated channel\n", __func__);
1760 spin_lock_irqsave(&d40c->lock, flags);
1762 err = d40_free_dma(d40c);
1765 dev_err(&d40c->chan.dev->device,
1766 "[%s] Failed to free channel\n", __func__);
1767 spin_unlock_irqrestore(&d40c->lock, flags);
1770 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
1774 unsigned long dma_flags)
1776 struct d40_desc *d40d;
1777 struct d40_chan *d40c = container_of(chan, struct d40_chan,
1779 unsigned long flags;
1782 if (d40c->phy_chan == NULL) {
1783 dev_err(&d40c->chan.dev->device,
1784 "[%s] Channel is not allocated.\n", __func__);
1785 return ERR_PTR(-EINVAL);
1788 spin_lock_irqsave(&d40c->lock, flags);
1789 d40d = d40_desc_get(d40c);
1792 dev_err(&d40c->chan.dev->device,
1793 "[%s] Descriptor is NULL\n", __func__);
1797 d40d->txd.flags = dma_flags;
1799 dma_async_tx_descriptor_init(&d40d->txd, chan);
1801 d40d->txd.tx_submit = d40_tx_submit;
1803 if (d40c->log_num != D40_PHY_CHAN) {
1805 if (d40_pool_lli_alloc(d40d, 1, true) < 0) {
1806 dev_err(&d40c->chan.dev->device,
1807 "[%s] Out of memory\n", __func__);
1811 d40d->lli_tx_len = 1;
1813 d40_log_fill_lli(d40d->lli_log.src,
1817 d40c->log_def.lcsp1,
1818 d40c->dma_cfg.src_info.data_width,
1821 d40_log_fill_lli(d40d->lli_log.dst,
1825 d40c->log_def.lcsp3,
1826 d40c->dma_cfg.dst_info.data_width,
1831 if (d40_pool_lli_alloc(d40d, 1, false) < 0) {
1832 dev_err(&d40c->chan.dev->device,
1833 "[%s] Out of memory\n", __func__);
1837 err = d40_phy_fill_lli(d40d->lli_phy.src,
1840 d40c->dma_cfg.src_info.psize,
1844 d40c->dma_cfg.src_info.data_width,
1849 err = d40_phy_fill_lli(d40d->lli_phy.dst,
1852 d40c->dma_cfg.dst_info.psize,
1856 d40c->dma_cfg.dst_info.data_width,
1862 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
1863 d40d->lli_pool.size, DMA_TO_DEVICE);
1866 spin_unlock_irqrestore(&d40c->lock, flags);
1870 dev_err(&d40c->chan.dev->device,
1871 "[%s] Failed filling in PHY LLI\n", __func__);
1872 d40_pool_lli_free(d40d);
1874 spin_unlock_irqrestore(&d40c->lock, flags);
1878 static int d40_prep_slave_sg_log(struct d40_desc *d40d,
1879 struct d40_chan *d40c,
1880 struct scatterlist *sgl,
1881 unsigned int sg_len,
1882 enum dma_data_direction direction,
1883 unsigned long dma_flags)
1885 dma_addr_t dev_addr = 0;
1888 if (d40_pool_lli_alloc(d40d, sg_len, true) < 0) {
1889 dev_err(&d40c->chan.dev->device,
1890 "[%s] Out of memory\n", __func__);
1894 d40d->lli_len = sg_len;
1895 if (d40d->lli_len <= d40c->base->plat_data->llis_per_log)
1896 d40d->lli_tx_len = d40d->lli_len;
1898 d40d->lli_tx_len = d40c->base->plat_data->llis_per_log;
1902 * Check if there is space available in lcla.
1903 * If not, split list into 1-length and run only
1906 if (d40_lcla_id_get(d40c) != 0)
1907 d40d->lli_tx_len = 1;
1909 if (direction == DMA_FROM_DEVICE)
1910 if (d40c->runtime_addr)
1911 dev_addr = d40c->runtime_addr;
1913 dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1914 else if (direction == DMA_TO_DEVICE)
1915 if (d40c->runtime_addr)
1916 dev_addr = d40c->runtime_addr;
1918 dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1923 total_size = d40_log_sg_to_dev(&d40c->lcla,
1927 d40c->dma_cfg.src_info.data_width,
1928 d40c->dma_cfg.dst_info.data_width,
1930 dma_flags & DMA_PREP_INTERRUPT,
1931 dev_addr, d40d->lli_tx_len,
1932 d40c->base->plat_data->llis_per_log);
1940 static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
1941 struct d40_chan *d40c,
1942 struct scatterlist *sgl,
1943 unsigned int sgl_len,
1944 enum dma_data_direction direction,
1945 unsigned long dma_flags)
1947 dma_addr_t src_dev_addr;
1948 dma_addr_t dst_dev_addr;
1951 if (d40_pool_lli_alloc(d40d, sgl_len, false) < 0) {
1952 dev_err(&d40c->chan.dev->device,
1953 "[%s] Out of memory\n", __func__);
1957 d40d->lli_len = sgl_len;
1958 d40d->lli_tx_len = sgl_len;
1960 if (direction == DMA_FROM_DEVICE) {
1962 if (d40c->runtime_addr)
1963 src_dev_addr = d40c->runtime_addr;
1965 src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
1966 } else if (direction == DMA_TO_DEVICE) {
1967 if (d40c->runtime_addr)
1968 dst_dev_addr = d40c->runtime_addr;
1970 dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
1975 res = d40_phy_sg_to_lli(sgl,
1979 d40d->lli_phy.src_addr,
1981 d40c->dma_cfg.src_info.data_width,
1982 d40c->dma_cfg.src_info.psize,
1987 res = d40_phy_sg_to_lli(sgl,
1991 d40d->lli_phy.dst_addr,
1993 d40c->dma_cfg.dst_info.data_width,
1994 d40c->dma_cfg.dst_info.psize,
1999 (void) dma_map_single(d40c->base->dev, d40d->lli_phy.src,
2000 d40d->lli_pool.size, DMA_TO_DEVICE);
2004 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2005 struct scatterlist *sgl,
2006 unsigned int sg_len,
2007 enum dma_data_direction direction,
2008 unsigned long dma_flags)
2010 struct d40_desc *d40d;
2011 struct d40_chan *d40c = container_of(chan, struct d40_chan,
2013 unsigned long flags;
2016 if (d40c->phy_chan == NULL) {
2017 dev_err(&d40c->chan.dev->device,
2018 "[%s] Cannot prepare unallocated channel\n", __func__);
2019 return ERR_PTR(-EINVAL);
2022 if (d40c->dma_cfg.pre_transfer)
2023 d40c->dma_cfg.pre_transfer(chan,
2024 d40c->dma_cfg.pre_transfer_data,
2027 spin_lock_irqsave(&d40c->lock, flags);
2028 d40d = d40_desc_get(d40c);
2029 spin_unlock_irqrestore(&d40c->lock, flags);
2034 if (d40c->log_num != D40_PHY_CHAN)
2035 err = d40_prep_slave_sg_log(d40d, d40c, sgl, sg_len,
2036 direction, dma_flags);
2038 err = d40_prep_slave_sg_phy(d40d, d40c, sgl, sg_len,
2039 direction, dma_flags);
2041 dev_err(&d40c->chan.dev->device,
2042 "[%s] Failed to prepare %s slave sg job: %d\n",
2044 d40c->log_num != D40_PHY_CHAN ? "log" : "phy", err);
2048 d40d->txd.flags = dma_flags;
2050 dma_async_tx_descriptor_init(&d40d->txd, chan);
2052 d40d->txd.tx_submit = d40_tx_submit;
2057 static enum dma_status d40_tx_status(struct dma_chan *chan,
2058 dma_cookie_t cookie,
2059 struct dma_tx_state *txstate)
2061 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2062 dma_cookie_t last_used;
2063 dma_cookie_t last_complete;
2066 if (d40c->phy_chan == NULL) {
2067 dev_err(&d40c->chan.dev->device,
2068 "[%s] Cannot read status of unallocated channel\n",
2073 last_complete = d40c->completed;
2074 last_used = chan->cookie;
2076 if (d40_is_paused(d40c))
2079 ret = dma_async_is_complete(cookie, last_complete, last_used);
2081 dma_set_tx_state(txstate, last_complete, last_used,
2082 stedma40_residue(chan));
2087 static void d40_issue_pending(struct dma_chan *chan)
2089 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2090 unsigned long flags;
2092 if (d40c->phy_chan == NULL) {
2093 dev_err(&d40c->chan.dev->device,
2094 "[%s] Channel is not allocated!\n", __func__);
2098 spin_lock_irqsave(&d40c->lock, flags);
2100 /* Busy means that pending jobs are already being processed */
2102 (void) d40_queue_start(d40c);
2104 spin_unlock_irqrestore(&d40c->lock, flags);
2107 /* Runtime reconfiguration extension */
2108 static void d40_set_runtime_config(struct dma_chan *chan,
2109 struct dma_slave_config *config)
2111 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2112 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2113 enum dma_slave_buswidth config_addr_width;
2114 dma_addr_t config_addr;
2115 u32 config_maxburst;
2116 enum stedma40_periph_data_width addr_width;
2119 if (config->direction == DMA_FROM_DEVICE) {
2120 dma_addr_t dev_addr_rx =
2121 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2123 config_addr = config->src_addr;
2125 dev_dbg(d40c->base->dev,
2126 "channel has a pre-wired RX address %08x "
2127 "overriding with %08x\n",
2128 dev_addr_rx, config_addr);
2129 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2130 dev_dbg(d40c->base->dev,
2131 "channel was not configured for peripheral "
2132 "to memory transfer (%d) overriding\n",
2134 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2136 config_addr_width = config->src_addr_width;
2137 config_maxburst = config->src_maxburst;
2139 } else if (config->direction == DMA_TO_DEVICE) {
2140 dma_addr_t dev_addr_tx =
2141 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2143 config_addr = config->dst_addr;
2145 dev_dbg(d40c->base->dev,
2146 "channel has a pre-wired TX address %08x "
2147 "overriding with %08x\n",
2148 dev_addr_tx, config_addr);
2149 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2150 dev_dbg(d40c->base->dev,
2151 "channel was not configured for memory "
2152 "to peripheral transfer (%d) overriding\n",
2154 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2156 config_addr_width = config->dst_addr_width;
2157 config_maxburst = config->dst_maxburst;
2160 dev_err(d40c->base->dev,
2161 "unrecognized channel direction %d\n",
2166 switch (config_addr_width) {
2167 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2168 addr_width = STEDMA40_BYTE_WIDTH;
2170 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2171 addr_width = STEDMA40_HALFWORD_WIDTH;
2173 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2174 addr_width = STEDMA40_WORD_WIDTH;
2176 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2177 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2180 dev_err(d40c->base->dev,
2181 "illegal peripheral address width "
2183 config->src_addr_width);
2187 if (config_maxburst >= 16)
2188 psize = STEDMA40_PSIZE_LOG_16;
2189 else if (config_maxburst >= 8)
2190 psize = STEDMA40_PSIZE_LOG_8;
2191 else if (config_maxburst >= 4)
2192 psize = STEDMA40_PSIZE_LOG_4;
2194 psize = STEDMA40_PSIZE_LOG_1;
2196 /* Set up all the endpoint configs */
2197 cfg->src_info.data_width = addr_width;
2198 cfg->src_info.psize = psize;
2199 cfg->src_info.endianess = STEDMA40_LITTLE_ENDIAN;
2200 cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2201 cfg->dst_info.data_width = addr_width;
2202 cfg->dst_info.psize = psize;
2203 cfg->dst_info.endianess = STEDMA40_LITTLE_ENDIAN;
2204 cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2206 /* These settings will take precedence later */
2207 d40c->runtime_addr = config_addr;
2208 d40c->runtime_direction = config->direction;
2209 dev_dbg(d40c->base->dev,
2210 "configured channel %s for %s, data width %d, "
2211 "maxburst %d bytes, LE, no flow control\n",
2212 dma_chan_name(chan),
2213 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2218 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2221 unsigned long flags;
2222 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2224 if (d40c->phy_chan == NULL) {
2225 dev_err(&d40c->chan.dev->device,
2226 "[%s] Channel is not allocated!\n", __func__);
2231 case DMA_TERMINATE_ALL:
2232 spin_lock_irqsave(&d40c->lock, flags);
2234 spin_unlock_irqrestore(&d40c->lock, flags);
2237 return d40_pause(chan);
2239 return d40_resume(chan);
2240 case DMA_SLAVE_CONFIG:
2241 d40_set_runtime_config(chan,
2242 (struct dma_slave_config *) arg);
2248 /* Other commands are unimplemented */
2252 /* Initialization functions */
2254 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2255 struct d40_chan *chans, int offset,
2259 struct d40_chan *d40c;
2261 INIT_LIST_HEAD(&dma->channels);
2263 for (i = offset; i < offset + num_chans; i++) {
2266 d40c->chan.device = dma;
2268 /* Invalidate lcla element */
2269 d40c->lcla.src_id = -1;
2270 d40c->lcla.dst_id = -1;
2272 spin_lock_init(&d40c->lock);
2274 d40c->log_num = D40_PHY_CHAN;
2276 INIT_LIST_HEAD(&d40c->active);
2277 INIT_LIST_HEAD(&d40c->queue);
2278 INIT_LIST_HEAD(&d40c->client);
2280 tasklet_init(&d40c->tasklet, dma_tasklet,
2281 (unsigned long) d40c);
2283 list_add_tail(&d40c->chan.device_node,
2288 static int __init d40_dmaengine_init(struct d40_base *base,
2289 int num_reserved_chans)
2293 d40_chan_init(base, &base->dma_slave, base->log_chans,
2294 0, base->num_log_chans);
2296 dma_cap_zero(base->dma_slave.cap_mask);
2297 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2299 base->dma_slave.device_alloc_chan_resources = d40_alloc_chan_resources;
2300 base->dma_slave.device_free_chan_resources = d40_free_chan_resources;
2301 base->dma_slave.device_prep_dma_memcpy = d40_prep_memcpy;
2302 base->dma_slave.device_prep_slave_sg = d40_prep_slave_sg;
2303 base->dma_slave.device_tx_status = d40_tx_status;
2304 base->dma_slave.device_issue_pending = d40_issue_pending;
2305 base->dma_slave.device_control = d40_control;
2306 base->dma_slave.dev = base->dev;
2308 err = dma_async_device_register(&base->dma_slave);
2312 "[%s] Failed to register slave channels\n",
2317 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2318 base->num_log_chans, base->plat_data->memcpy_len);
2320 dma_cap_zero(base->dma_memcpy.cap_mask);
2321 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2323 base->dma_memcpy.device_alloc_chan_resources = d40_alloc_chan_resources;
2324 base->dma_memcpy.device_free_chan_resources = d40_free_chan_resources;
2325 base->dma_memcpy.device_prep_dma_memcpy = d40_prep_memcpy;
2326 base->dma_memcpy.device_prep_slave_sg = d40_prep_slave_sg;
2327 base->dma_memcpy.device_tx_status = d40_tx_status;
2328 base->dma_memcpy.device_issue_pending = d40_issue_pending;
2329 base->dma_memcpy.device_control = d40_control;
2330 base->dma_memcpy.dev = base->dev;
2332 * This controller can only access address at even
2333 * 32bit boundaries, i.e. 2^2
2335 base->dma_memcpy.copy_align = 2;
2337 err = dma_async_device_register(&base->dma_memcpy);
2341 "[%s] Failed to regsiter memcpy only channels\n",
2346 d40_chan_init(base, &base->dma_both, base->phy_chans,
2347 0, num_reserved_chans);
2349 dma_cap_zero(base->dma_both.cap_mask);
2350 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2351 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2353 base->dma_both.device_alloc_chan_resources = d40_alloc_chan_resources;
2354 base->dma_both.device_free_chan_resources = d40_free_chan_resources;
2355 base->dma_both.device_prep_dma_memcpy = d40_prep_memcpy;
2356 base->dma_both.device_prep_slave_sg = d40_prep_slave_sg;
2357 base->dma_both.device_tx_status = d40_tx_status;
2358 base->dma_both.device_issue_pending = d40_issue_pending;
2359 base->dma_both.device_control = d40_control;
2360 base->dma_both.dev = base->dev;
2361 base->dma_both.copy_align = 2;
2362 err = dma_async_device_register(&base->dma_both);
2366 "[%s] Failed to register logical and physical capable channels\n",
2372 dma_async_device_unregister(&base->dma_memcpy);
2374 dma_async_device_unregister(&base->dma_slave);
2379 /* Initialization functions. */
2381 static int __init d40_phy_res_init(struct d40_base *base)
2384 int num_phy_chans_avail = 0;
2386 int odd_even_bit = -2;
2388 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2389 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2391 for (i = 0; i < base->num_phy_chans; i++) {
2392 base->phy_res[i].num = i;
2393 odd_even_bit += 2 * ((i % 2) == 0);
2394 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2395 /* Mark security only channels as occupied */
2396 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2397 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2399 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2400 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2401 num_phy_chans_avail++;
2403 spin_lock_init(&base->phy_res[i].lock);
2406 /* Mark disabled channels as occupied */
2407 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
2408 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2409 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2410 num_phy_chans_avail--;
2413 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2414 num_phy_chans_avail, base->num_phy_chans);
2416 /* Verify settings extended vs standard */
2417 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2419 for (i = 0; i < base->num_phy_chans; i++) {
2421 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2422 (val[0] & 0x3) != 1)
2424 "[%s] INFO: channel %d is misconfigured (%d)\n",
2425 __func__, i, val[0] & 0x3);
2427 val[0] = val[0] >> 2;
2430 return num_phy_chans_avail;
2433 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2435 static const struct d40_reg_val dma_id_regs[] = {
2437 { .reg = D40_DREG_PERIPHID0, .val = 0x0040},
2438 { .reg = D40_DREG_PERIPHID1, .val = 0x0000},
2440 * D40_DREG_PERIPHID2 Depends on HW revision:
2441 * MOP500/HREF ED has 0x0008,
2443 * HREF V1 has 0x0028
2445 { .reg = D40_DREG_PERIPHID3, .val = 0x0000},
2448 { .reg = D40_DREG_CELLID0, .val = 0x000d},
2449 { .reg = D40_DREG_CELLID1, .val = 0x00f0},
2450 { .reg = D40_DREG_CELLID2, .val = 0x0005},
2451 { .reg = D40_DREG_CELLID3, .val = 0x00b1}
2453 struct stedma40_platform_data *plat_data;
2454 struct clk *clk = NULL;
2455 void __iomem *virtbase = NULL;
2456 struct resource *res = NULL;
2457 struct d40_base *base = NULL;
2458 int num_log_chans = 0;
2463 clk = clk_get(&pdev->dev, NULL);
2466 dev_err(&pdev->dev, "[%s] No matching clock found\n",
2473 /* Get IO for DMAC base address */
2474 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2478 if (request_mem_region(res->start, resource_size(res),
2479 D40_NAME " I/O base") == NULL)
2482 virtbase = ioremap(res->start, resource_size(res));
2486 /* HW version check */
2487 for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) {
2488 if (dma_id_regs[i].val !=
2489 readl(virtbase + dma_id_regs[i].reg)) {
2491 "[%s] Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2495 readl(virtbase + dma_id_regs[i].reg));
2500 /* Get silicon revision */
2501 val = readl(virtbase + D40_DREG_PERIPHID2);
2503 if ((val & 0xf) != D40_PERIPHID2_DESIGNER) {
2505 "[%s] Unknown designer! Got %x wanted %x\n",
2506 __func__, val & 0xf, D40_PERIPHID2_DESIGNER);
2510 /* The number of physical channels on this HW */
2511 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2513 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
2514 (val >> 4) & 0xf, res->start);
2516 plat_data = pdev->dev.platform_data;
2518 /* Count the number of logical channels in use */
2519 for (i = 0; i < plat_data->dev_len; i++)
2520 if (plat_data->dev_rx[i] != 0)
2523 for (i = 0; i < plat_data->dev_len; i++)
2524 if (plat_data->dev_tx[i] != 0)
2527 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2528 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2529 sizeof(struct d40_chan), GFP_KERNEL);
2532 dev_err(&pdev->dev, "[%s] Out of memory\n", __func__);
2536 base->rev = (val >> 4) & 0xf;
2538 base->num_phy_chans = num_phy_chans;
2539 base->num_log_chans = num_log_chans;
2540 base->phy_start = res->start;
2541 base->phy_size = resource_size(res);
2542 base->virtbase = virtbase;
2543 base->plat_data = plat_data;
2544 base->dev = &pdev->dev;
2545 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2546 base->log_chans = &base->phy_chans[num_phy_chans];
2548 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2553 base->lookup_phy_chans = kzalloc(num_phy_chans *
2554 sizeof(struct d40_chan *),
2556 if (!base->lookup_phy_chans)
2559 if (num_log_chans + plat_data->memcpy_len) {
2561 * The max number of logical channels are event lines for all
2562 * src devices and dst devices
2564 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2565 sizeof(struct d40_chan *),
2567 if (!base->lookup_log_chans)
2570 base->lcla_pool.alloc_map = kzalloc(num_phy_chans * sizeof(u32),
2572 if (!base->lcla_pool.alloc_map)
2575 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2576 0, SLAB_HWCACHE_ALIGN,
2578 if (base->desc_slab == NULL)
2591 release_mem_region(res->start,
2592 resource_size(res));
2597 kfree(base->lcla_pool.alloc_map);
2598 kfree(base->lookup_log_chans);
2599 kfree(base->lookup_phy_chans);
2600 kfree(base->phy_res);
2607 static void __init d40_hw_init(struct d40_base *base)
2610 static const struct d40_reg_val dma_init_reg[] = {
2611 /* Clock every part of the DMA block from start */
2612 { .reg = D40_DREG_GCC, .val = 0x0000ff01},
2614 /* Interrupts on all logical channels */
2615 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2616 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2617 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2618 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2619 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2620 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2621 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2622 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2623 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2624 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2625 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2626 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2629 u32 prmseo[2] = {0, 0};
2630 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2634 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2635 writel(dma_init_reg[i].val,
2636 base->virtbase + dma_init_reg[i].reg);
2638 /* Configure all our dma channels to default settings */
2639 for (i = 0; i < base->num_phy_chans; i++) {
2641 activeo[i % 2] = activeo[i % 2] << 2;
2643 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2645 activeo[i % 2] |= 3;
2649 /* Enable interrupt # */
2650 pcmis = (pcmis << 1) | 1;
2652 /* Clear interrupt # */
2653 pcicr = (pcicr << 1) | 1;
2655 /* Set channel to physical mode */
2656 prmseo[i % 2] = prmseo[i % 2] << 2;
2661 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2662 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2663 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2664 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2666 /* Write which interrupt to enable */
2667 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2669 /* Write which interrupt to clear */
2670 writel(pcicr, base->virtbase + D40_DREG_PCICR);
2674 static int __init d40_lcla_allocate(struct d40_base *base)
2676 unsigned long *page_list;
2681 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2682 * To full fill this hardware requirement without wasting 256 kb
2683 * we allocate pages until we get an aligned one.
2685 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2693 /* Calculating how many pages that are required */
2694 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2696 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2697 page_list[i] = __get_free_pages(GFP_KERNEL,
2698 base->lcla_pool.pages);
2699 if (!page_list[i]) {
2702 "[%s] Failed to allocate %d pages.\n",
2703 __func__, base->lcla_pool.pages);
2705 for (j = 0; j < i; j++)
2706 free_pages(page_list[j], base->lcla_pool.pages);
2710 if ((virt_to_phys((void *)page_list[i]) &
2711 (LCLA_ALIGNMENT - 1)) == 0)
2715 for (j = 0; j < i; j++)
2716 free_pages(page_list[j], base->lcla_pool.pages);
2718 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2719 base->lcla_pool.base = (void *)page_list[i];
2721 /* After many attempts, no succees with finding the correct
2722 * alignment try with allocating a big buffer */
2724 "[%s] Failed to get %d pages @ 18 bit align.\n",
2725 __func__, base->lcla_pool.pages);
2726 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2727 base->num_phy_chans +
2730 if (!base->lcla_pool.base_unaligned) {
2735 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2739 writel(virt_to_phys(base->lcla_pool.base),
2740 base->virtbase + D40_DREG_LCLA);
2746 static int __init d40_probe(struct platform_device *pdev)
2750 struct d40_base *base;
2751 struct resource *res = NULL;
2752 int num_reserved_chans;
2755 base = d40_hw_detect_init(pdev);
2760 num_reserved_chans = d40_phy_res_init(base);
2762 platform_set_drvdata(pdev, base);
2764 spin_lock_init(&base->interrupt_lock);
2765 spin_lock_init(&base->execmd_lock);
2767 /* Get IO for logical channel parameter address */
2768 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2772 "[%s] No \"lcpa\" memory resource\n",
2776 base->lcpa_size = resource_size(res);
2777 base->phy_lcpa = res->start;
2779 if (request_mem_region(res->start, resource_size(res),
2780 D40_NAME " I/O lcpa") == NULL) {
2783 "[%s] Failed to request LCPA region 0x%x-0x%x\n",
2784 __func__, res->start, res->end);
2788 /* We make use of ESRAM memory for this. */
2789 val = readl(base->virtbase + D40_DREG_LCPA);
2790 if (res->start != val && val != 0) {
2791 dev_warn(&pdev->dev,
2792 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2793 __func__, val, res->start);
2795 writel(res->start, base->virtbase + D40_DREG_LCPA);
2797 base->lcpa_base = ioremap(res->start, resource_size(res));
2798 if (!base->lcpa_base) {
2801 "[%s] Failed to ioremap LCPA region\n",
2806 ret = d40_lcla_allocate(base);
2808 dev_err(&pdev->dev, "[%s] Failed to allocate LCLA area\n",
2813 spin_lock_init(&base->lcla_pool.lock);
2815 base->lcla_pool.num_blocks = base->num_phy_chans;
2817 base->irq = platform_get_irq(pdev, 0);
2819 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
2822 dev_err(&pdev->dev, "[%s] No IRQ defined\n", __func__);
2826 err = d40_dmaengine_init(base, num_reserved_chans);
2832 dev_info(base->dev, "initialized\n");
2837 if (base->desc_slab)
2838 kmem_cache_destroy(base->desc_slab);
2840 iounmap(base->virtbase);
2841 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2842 free_pages((unsigned long)base->lcla_pool.base,
2843 base->lcla_pool.pages);
2844 if (base->lcla_pool.base_unaligned)
2845 kfree(base->lcla_pool.base_unaligned);
2847 release_mem_region(base->phy_lcpa,
2849 if (base->phy_start)
2850 release_mem_region(base->phy_start,
2853 clk_disable(base->clk);
2857 kfree(base->lcla_pool.alloc_map);
2858 kfree(base->lookup_log_chans);
2859 kfree(base->lookup_phy_chans);
2860 kfree(base->phy_res);
2864 dev_err(&pdev->dev, "[%s] probe failed\n", __func__);
2868 static struct platform_driver d40_driver = {
2870 .owner = THIS_MODULE,
2875 int __init stedma40_init(void)
2877 return platform_driver_probe(&d40_driver, d40_probe);
2879 arch_initcall(stedma40_init);