drivers/dma/dw/core.c

   1 /*
   2  * Core driver for the Synopsys DesignWare DMA Controller
   3  *
   4  * Copyright (C) 2007-2008 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  * Copyright (C) 2013 Intel Corporation
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/bitops.h>
  14 #include <linux/clk.h>
  15 #include <linux/delay.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/mm.h>
  24 #include <linux/module.h>
  25 #include <linux/slab.h>
  26
  27 #include "../dmaengine.h"
  28 #include "internal.h"
  29
  30 /*
  31  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  32  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  33  * of which use ARM any more).  See the "Databook" from Synopsys for
  34  * information beyond what licensees probably provide.
  35  *
  36  * The driver has currently been tested only with the Atmel AT32AP7000,
  37  * which does not support descriptor writeback.
  38  */
  39
  40 static inline bool is_request_line_unset(struct dw_dma_chan *dwc)
  41 {
  42         return dwc->request_line == (typeof(dwc->request_line))~0;
  43 }
  44
  45 static inline void dwc_set_masters(struct dw_dma_chan *dwc)
  46 {
  47         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
  48         struct dw_dma_slave *dws = dwc->chan.private;
  49         unsigned char mmax = dw->nr_masters - 1;
  50
  51         if (!is_request_line_unset(dwc))
  52                 return;
  53
  54         dwc->src_master = min_t(unsigned char, mmax, dwc_get_sms(dws));
  55         dwc->dst_master = min_t(unsigned char, mmax, dwc_get_dms(dws));
  56 }
  57
  58 #define DWC_DEFAULT_CTLLO(_chan) ({                             \
  59                 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan);       \
  60                 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \
  61                 bool _is_slave = is_slave_direction(_dwc->direction);   \
  62                 u8 _smsize = _is_slave ? _sconfig->src_maxburst :       \
  63                         DW_DMA_MSIZE_16;                        \
  64                 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst :       \
  65                         DW_DMA_MSIZE_16;                        \
  66                                                                 \
  67                 (DWC_CTLL_DST_MSIZE(_dmsize)                    \
  68                  | DWC_CTLL_SRC_MSIZE(_smsize)                  \
  69                  | DWC_CTLL_LLP_D_EN                            \
  70                  | DWC_CTLL_LLP_S_EN                            \
  71                  | DWC_CTLL_DMS(_dwc->dst_master)               \
  72                  | DWC_CTLL_SMS(_dwc->src_master));             \
  73         })
  74
  75 /*
  76  * Number of descriptors to allocate for each channel. This should be
  77  * made configurable somehow; preferably, the clients (at least the
  78  * ones using slave transfers) should be able to give us a hint.
  79  */
  80 #define NR_DESCS_PER_CHANNEL    64
  81
  82 /*----------------------------------------------------------------------*/
  83
  84 static struct device *chan2dev(struct dma_chan *chan)
  85 {
  86         return &chan->dev->device;
  87 }
  88
  89 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  90 {
  91         return to_dw_desc(dwc->active_list.next);
  92 }
  93
  94 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  95 {
  96         struct dw_desc *desc, *_desc;
  97         struct dw_desc *ret = NULL;
  98         unsigned int i = 0;
  99         unsigned long flags;
 100
 101         spin_lock_irqsave(&dwc->lock, flags);
 102         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
 103                 i++;
 104                 if (async_tx_test_ack(&desc->txd)) {
 105                         list_del(&desc->desc_node);
 106                         ret = desc;
 107                         break;
 108                 }
 109                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
 110         }
 111         spin_unlock_irqrestore(&dwc->lock, flags);
 112
 113         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 114
 115         return ret;
 116 }
 117
 118 /*
 119  * Move a descriptor, including any children, to the free list.
 120  * `desc' must not be on any lists.
 121  */
 122 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 123 {
 124         unsigned long flags;
 125
 126         if (desc) {
 127                 struct dw_desc *child;
 128
 129                 spin_lock_irqsave(&dwc->lock, flags);
 130                 list_for_each_entry(child, &desc->tx_list, desc_node)
 131                         dev_vdbg(chan2dev(&dwc->chan),
 132                                         "moving child desc %p to freelist\n",
 133                                         child);
 134                 list_splice_init(&desc->tx_list, &dwc->free_list);
 135                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 136                 list_add(&desc->desc_node, &dwc->free_list);
 137                 spin_unlock_irqrestore(&dwc->lock, flags);
 138         }
 139 }
 140
 141 static void dwc_initialize(struct dw_dma_chan *dwc)
 142 {
 143         struct dw_dma *dw = to_dw_dma(dwc->chan.device);
 144         struct dw_dma_slave *dws = dwc->chan.private;
 145         u32 cfghi = DWC_CFGH_FIFO_MODE;
 146         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
 147
 148         if (dwc->initialized == true)
 149                 return;
 150
 151         if (dws) {
 152                 /*
 153                  * We need controller-specific data to set up slave
 154                  * transfers.
 155                  */
 156                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 157
 158                 cfghi = dws->cfg_hi;
 159                 cfglo |= dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
 160         } else {
 161                 if (dwc->direction == DMA_MEM_TO_DEV)
 162                         cfghi = DWC_CFGH_DST_PER(dwc->request_line);
 163                 else if (dwc->direction == DMA_DEV_TO_MEM)
 164                         cfghi = DWC_CFGH_SRC_PER(dwc->request_line);
 165         }
 166
 167         channel_writel(dwc, CFG_LO, cfglo);
 168         channel_writel(dwc, CFG_HI, cfghi);
 169
 170         /* Enable interrupts */
 171         channel_set_bit(dw, MASK.XFER, dwc->mask);
 172         channel_set_bit(dw, MASK.ERROR, dwc->mask);
 173
 174         dwc->initialized = true;
 175 }
 176
 177 /*----------------------------------------------------------------------*/
 178
 179 static inline unsigned int dwc_fast_fls(unsigned long long v)
 180 {
 181         /*
 182          * We can be a lot more clever here, but this should take care
 183          * of the most common optimization.
 184          */
 185         if (!(v & 7))
 186                 return 3;
 187         else if (!(v & 3))
 188                 return 2;
 189         else if (!(v & 1))
 190                 return 1;
 191         return 0;
 192 }
 193
 194 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc)
 195 {
 196         dev_err(chan2dev(&dwc->chan),
 197                 "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 198                 channel_readl(dwc, SAR),
 199                 channel_readl(dwc, DAR),
 200                 channel_readl(dwc, LLP),
 201                 channel_readl(dwc, CTL_HI),
 202                 channel_readl(dwc, CTL_LO));
 203 }
 204
 205 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc)
 206 {
 207         channel_clear_bit(dw, CH_EN, dwc->mask);
 208         while (dma_readl(dw, CH_EN) & dwc->mask)
 209                 cpu_relax();
 210 }
 211
 212 /*----------------------------------------------------------------------*/
 213
 214 /* Perform single block transfer */
 215 static inline void dwc_do_single_block(struct dw_dma_chan *dwc,
 216                                        struct dw_desc *desc)
 217 {
 218         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 219         u32             ctllo;
 220
 221         /*
 222          * Software emulation of LLP mode relies on interrupts to continue
 223          * multi block transfer.
 224          */
 225         ctllo = desc->lli.ctllo | DWC_CTLL_INT_EN;
 226
 227         channel_writel(dwc, SAR, desc->lli.sar);
 228         channel_writel(dwc, DAR, desc->lli.dar);
 229         channel_writel(dwc, CTL_LO, ctllo);
 230         channel_writel(dwc, CTL_HI, desc->lli.ctlhi);
 231         channel_set_bit(dw, CH_EN, dwc->mask);
 232
 233         /* Move pointer to next descriptor */
 234         dwc->tx_node_active = dwc->tx_node_active->next;
 235 }
 236
 237 /* Called with dwc->lock held and bh disabled */
 238 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 239 {
 240         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 241         unsigned long   was_soft_llp;
 242
 243         /* ASSERT:  channel is idle */
 244         if (dma_readl(dw, CH_EN) & dwc->mask) {
 245                 dev_err(chan2dev(&dwc->chan),
 246                         "BUG: Attempted to start non-idle channel\n");
 247                 dwc_dump_chan_regs(dwc);
 248
 249                 /* The tasklet will hopefully advance the queue... */
 250                 return;
 251         }
 252
 253         if (dwc->nollp) {
 254                 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP,
 255                                                 &dwc->flags);
 256                 if (was_soft_llp) {
 257                         dev_err(chan2dev(&dwc->chan),
 258                                 "BUG: Attempted to start new LLP transfer inside ongoing one\n");
 259                         return;
 260                 }
 261
 262                 dwc_initialize(dwc);
 263
 264                 dwc->residue = first->total_len;
 265                 dwc->tx_node_active = &first->tx_list;
 266
 267                 /* Submit first block */
 268                 dwc_do_single_block(dwc, first);
 269
 270                 return;
 271         }
 272
 273         dwc_initialize(dwc);
 274
 275         channel_writel(dwc, LLP, first->txd.phys);
 276         channel_writel(dwc, CTL_LO,
 277                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 278         channel_writel(dwc, CTL_HI, 0);
 279         channel_set_bit(dw, CH_EN, dwc->mask);
 280 }
 281
 282 /*----------------------------------------------------------------------*/
 283
 284 static void
 285 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 286                 bool callback_required)
 287 {
 288         dma_async_tx_callback           callback = NULL;
 289         void                            *param = NULL;
 290         struct dma_async_tx_descriptor  *txd = &desc->txd;
 291         struct dw_desc                  *child;
 292         unsigned long                   flags;
 293
 294         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 295
 296         spin_lock_irqsave(&dwc->lock, flags);
 297         dma_cookie_complete(txd);
 298         if (callback_required) {
 299                 callback = txd->callback;
 300                 param = txd->callback_param;
 301         }
 302
 303         /* async_tx_ack */
 304         list_for_each_entry(child, &desc->tx_list, desc_node)
 305                 async_tx_ack(&child->txd);
 306         async_tx_ack(&desc->txd);
 307
 308         list_splice_init(&desc->tx_list, &dwc->free_list);
 309         list_move(&desc->desc_node, &dwc->free_list);
 310
 311         dma_descriptor_unmap(txd);
 312         spin_unlock_irqrestore(&dwc->lock, flags);
 313
 314         if (callback)
 315                 callback(param);
 316 }
 317
 318 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 319 {
 320         struct dw_desc *desc, *_desc;
 321         LIST_HEAD(list);
 322         unsigned long flags;
 323
 324         spin_lock_irqsave(&dwc->lock, flags);
 325         if (dma_readl(dw, CH_EN) & dwc->mask) {
 326                 dev_err(chan2dev(&dwc->chan),
 327                         "BUG: XFER bit set, but channel not idle!\n");
 328
 329                 /* Try to continue after resetting the channel... */
 330                 dwc_chan_disable(dw, dwc);
 331         }
 332
 333         /*
 334          * Submit queued descriptors ASAP, i.e. before we go through
 335          * the completed ones.
 336          */
 337         list_splice_init(&dwc->active_list, &list);
 338         if (!list_empty(&dwc->queue)) {
 339                 list_move(dwc->queue.next, &dwc->active_list);
 340                 dwc_dostart(dwc, dwc_first_active(dwc));
 341         }
 342
 343         spin_unlock_irqrestore(&dwc->lock, flags);
 344
 345         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 346                 dwc_descriptor_complete(dwc, desc, true);
 347 }
 348
 349 /* Returns how many bytes were already received from source */
 350 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc)
 351 {
 352         u32 ctlhi = channel_readl(dwc, CTL_HI);
 353         u32 ctllo = channel_readl(dwc, CTL_LO);
 354
 355         return (ctlhi & DWC_CTLH_BLOCK_TS_MASK) * (1 << (ctllo >> 4 & 7));
 356 }
 357
 358 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 359 {
 360         dma_addr_t llp;
 361         struct dw_desc *desc, *_desc;
 362         struct dw_desc *child;
 363         u32 status_xfer;
 364         unsigned long flags;
 365
 366         spin_lock_irqsave(&dwc->lock, flags);
 367         llp = channel_readl(dwc, LLP);
 368         status_xfer = dma_readl(dw, RAW.XFER);
 369
 370         if (status_xfer & dwc->mask) {
 371                 /* Everything we've submitted is done */
 372                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 373
 374                 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 375                         struct list_head *head, *active = dwc->tx_node_active;
 376
 377                         /*
 378                          * We are inside first active descriptor.
 379                          * Otherwise something is really wrong.
 380                          */
 381                         desc = dwc_first_active(dwc);
 382
 383                         head = &desc->tx_list;
 384                         if (active != head) {
 385                                 /* Update desc to reflect last sent one */
 386                                 if (active != head->next)
 387                                         desc = to_dw_desc(active->prev);
 388
 389                                 dwc->residue -= desc->len;
 390
 391                                 child = to_dw_desc(active);
 392
 393                                 /* Submit next block */
 394                                 dwc_do_single_block(dwc, child);
 395
 396                                 spin_unlock_irqrestore(&dwc->lock, flags);
 397                                 return;
 398                         }
 399
 400                         /* We are done here */
 401                         clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
 402                 }
 403
 404                 dwc->residue = 0;
 405
 406                 spin_unlock_irqrestore(&dwc->lock, flags);
 407
 408                 dwc_complete_all(dw, dwc);
 409                 return;
 410         }
 411
 412         if (list_empty(&dwc->active_list)) {
 413                 dwc->residue = 0;
 414                 spin_unlock_irqrestore(&dwc->lock, flags);
 415                 return;
 416         }
 417
 418         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) {
 419                 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__);
 420                 spin_unlock_irqrestore(&dwc->lock, flags);
 421                 return;
 422         }
 423
 424         dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp);
 425
 426         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 427                 /* Initial residue value */
 428                 dwc->residue = desc->total_len;
 429
 430                 /* Check first descriptors addr */
 431                 if (desc->txd.phys == llp) {
 432                         spin_unlock_irqrestore(&dwc->lock, flags);
 433                         return;
 434                 }
 435
 436                 /* Check first descriptors llp */
 437                 if (desc->lli.llp == llp) {
 438                         /* This one is currently in progress */
 439                         dwc->residue -= dwc_get_sent(dwc);
 440                         spin_unlock_irqrestore(&dwc->lock, flags);
 441                         return;
 442                 }
 443
 444                 dwc->residue -= desc->len;
 445                 list_for_each_entry(child, &desc->tx_list, desc_node) {
 446                         if (child->lli.llp == llp) {
 447                                 /* Currently in progress */
 448                                 dwc->residue -= dwc_get_sent(dwc);
 449                                 spin_unlock_irqrestore(&dwc->lock, flags);
 450                                 return;
 451                         }
 452                         dwc->residue -= child->len;
 453                 }
 454
 455                 /*
 456                  * No descriptors so far seem to be in progress, i.e.
 457                  * this one must be done.
 458                  */
 459                 spin_unlock_irqrestore(&dwc->lock, flags);
 460                 dwc_descriptor_complete(dwc, desc, true);
 461                 spin_lock_irqsave(&dwc->lock, flags);
 462         }
 463
 464         dev_err(chan2dev(&dwc->chan),
 465                 "BUG: All descriptors done, but channel not idle!\n");
 466
 467         /* Try to continue after resetting the channel... */
 468         dwc_chan_disable(dw, dwc);
 469
 470         if (!list_empty(&dwc->queue)) {
 471                 list_move(dwc->queue.next, &dwc->active_list);
 472                 dwc_dostart(dwc, dwc_first_active(dwc));
 473         }
 474         spin_unlock_irqrestore(&dwc->lock, flags);
 475 }
 476
 477 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 478 {
 479         dev_crit(chan2dev(&dwc->chan), "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 480                  lli->sar, lli->dar, lli->llp, lli->ctlhi, lli->ctllo);
 481 }
 482
 483 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 484 {
 485         struct dw_desc *bad_desc;
 486         struct dw_desc *child;
 487         unsigned long flags;
 488
 489         dwc_scan_descriptors(dw, dwc);
 490
 491         spin_lock_irqsave(&dwc->lock, flags);
 492
 493         /*
 494          * The descriptor currently at the head of the active list is
 495          * borked. Since we don't have any way to report errors, we'll
 496          * just have to scream loudly and try to carry on.
 497          */
 498         bad_desc = dwc_first_active(dwc);
 499         list_del_init(&bad_desc->desc_node);
 500         list_move(dwc->queue.next, dwc->active_list.prev);
 501
 502         /* Clear the error flag and try to restart the controller */
 503         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 504         if (!list_empty(&dwc->active_list))
 505                 dwc_dostart(dwc, dwc_first_active(dwc));
 506
 507         /*
 508          * WARN may seem harsh, but since this only happens
 509          * when someone submits a bad physical address in a
 510          * descriptor, we should consider ourselves lucky that the
 511          * controller flagged an error instead of scribbling over
 512          * random memory locations.
 513          */
 514         dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n"
 515                                        "  cookie: %d\n", bad_desc->txd.cookie);
 516         dwc_dump_lli(dwc, &bad_desc->lli);
 517         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 518                 dwc_dump_lli(dwc, &child->lli);
 519
 520         spin_unlock_irqrestore(&dwc->lock, flags);
 521
 522         /* Pretend the descriptor completed successfully */
 523         dwc_descriptor_complete(dwc, bad_desc, true);
 524 }
 525
 526 /* --------------------- Cyclic DMA API extensions -------------------- */
 527
 528 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 529 {
 530         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 531         return channel_readl(dwc, SAR);
 532 }
 533 EXPORT_SYMBOL(dw_dma_get_src_addr);
 534
 535 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 536 {
 537         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 538         return channel_readl(dwc, DAR);
 539 }
 540 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 541
 542 /* Called with dwc->lock held and all DMAC interrupts disabled */
 543 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 544                 u32 status_err, u32 status_xfer)
 545 {
 546         unsigned long flags;
 547
 548         if (dwc->mask) {
 549                 void (*callback)(void *param);
 550                 void *callback_param;
 551
 552                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 553                                 channel_readl(dwc, LLP));
 554
 555                 callback = dwc->cdesc->period_callback;
 556                 callback_param = dwc->cdesc->period_callback_param;
 557
 558                 if (callback)
 559                         callback(callback_param);
 560         }
 561
 562         /*
 563          * Error and transfer complete are highly unlikely, and will most
 564          * likely be due to a configuration error by the user.
 565          */
 566         if (unlikely(status_err & dwc->mask) ||
 567                         unlikely(status_xfer & dwc->mask)) {
 568                 int i;
 569
 570                 dev_err(chan2dev(&dwc->chan),
 571                         "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n",
 572                         status_xfer ? "xfer" : "error");
 573
 574                 spin_lock_irqsave(&dwc->lock, flags);
 575
 576                 dwc_dump_chan_regs(dwc);
 577
 578                 dwc_chan_disable(dw, dwc);
 579
 580                 /* Make sure DMA does not restart by loading a new list */
 581                 channel_writel(dwc, LLP, 0);
 582                 channel_writel(dwc, CTL_LO, 0);
 583                 channel_writel(dwc, CTL_HI, 0);
 584
 585                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 586                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 587
 588                 for (i = 0; i < dwc->cdesc->periods; i++)
 589                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 590
 591                 spin_unlock_irqrestore(&dwc->lock, flags);
 592         }
 593 }
 594
 595 /* ------------------------------------------------------------------------- */
 596
 597 static void dw_dma_tasklet(unsigned long data)
 598 {
 599         struct dw_dma *dw = (struct dw_dma *)data;
 600         struct dw_dma_chan *dwc;
 601         u32 status_xfer;
 602         u32 status_err;
 603         int i;
 604
 605         status_xfer = dma_readl(dw, RAW.XFER);
 606         status_err = dma_readl(dw, RAW.ERROR);
 607
 608         dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err);
 609
 610         for (i = 0; i < dw->dma.chancnt; i++) {
 611                 dwc = &dw->chan[i];
 612                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 613                         dwc_handle_cyclic(dw, dwc, status_err, status_xfer);
 614                 else if (status_err & (1 << i))
 615                         dwc_handle_error(dw, dwc);
 616                 else if (status_xfer & (1 << i))
 617                         dwc_scan_descriptors(dw, dwc);
 618         }
 619
 620         /*
 621          * Re-enable interrupts.
 622          */
 623         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 624         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 625 }
 626
 627 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 628 {
 629         struct dw_dma *dw = dev_id;
 630         u32 status = dma_readl(dw, STATUS_INT);
 631
 632         dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status);
 633
 634         /* Check if we have any interrupt from the DMAC */
 635         if (!status)
 636                 return IRQ_NONE;
 637
 638         /*
 639          * Just disable the interrupts. We'll turn them back on in the
 640          * softirq handler.
 641          */
 642         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 643         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 644
 645         status = dma_readl(dw, STATUS_INT);
 646         if (status) {
 647                 dev_err(dw->dma.dev,
 648                         "BUG: Unexpected interrupts pending: 0x%x\n",
 649                         status);
 650
 651                 /* Try to recover */
 652                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 653                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 654                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 655                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 656         }
 657
 658         tasklet_schedule(&dw->tasklet);
 659
 660         return IRQ_HANDLED;
 661 }
 662
 663 /*----------------------------------------------------------------------*/
 664
 665 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 666 {
 667         struct dw_desc          *desc = txd_to_dw_desc(tx);
 668         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 669         dma_cookie_t            cookie;
 670         unsigned long           flags;
 671
 672         spin_lock_irqsave(&dwc->lock, flags);
 673         cookie = dma_cookie_assign(tx);
 674
 675         /*
 676          * REVISIT: We should attempt to chain as many descriptors as
 677          * possible, perhaps even appending to those already submitted
 678          * for DMA. But this is hard to do in a race-free manner.
 679          */
 680         if (list_empty(&dwc->active_list)) {
 681                 dev_vdbg(chan2dev(tx->chan), "%s: started %u\n", __func__,
 682                                 desc->txd.cookie);
 683                 list_add_tail(&desc->desc_node, &dwc->active_list);
 684                 dwc_dostart(dwc, dwc_first_active(dwc));
 685         } else {
 686                 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", __func__,
 687                                 desc->txd.cookie);
 688
 689                 list_add_tail(&desc->desc_node, &dwc->queue);
 690         }
 691
 692         spin_unlock_irqrestore(&dwc->lock, flags);
 693
 694         return cookie;
 695 }
 696
 697 static struct dma_async_tx_descriptor *
 698 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 699                 size_t len, unsigned long flags)
 700 {
 701         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 702         struct dw_dma           *dw = to_dw_dma(chan->device);
 703         struct dw_desc          *desc;
 704         struct dw_desc          *first;
 705         struct dw_desc          *prev;
 706         size_t                  xfer_count;
 707         size_t                  offset;
 708         unsigned int            src_width;
 709         unsigned int            dst_width;
 710         unsigned int            data_width;
 711         u32                     ctllo;
 712
 713         dev_vdbg(chan2dev(chan),
 714                         "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__,
 715                         &dest, &src, len, flags);
 716
 717         if (unlikely(!len)) {
 718                 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__);
 719                 return NULL;
 720         }
 721
 722         dwc->direction = DMA_MEM_TO_MEM;
 723
 724         data_width = min_t(unsigned int, dw->data_width[dwc->src_master],
 725                            dw->data_width[dwc->dst_master]);
 726
 727         src_width = dst_width = min_t(unsigned int, data_width,
 728                                       dwc_fast_fls(src | dest | len));
 729
 730         ctllo = DWC_DEFAULT_CTLLO(chan)
 731                         | DWC_CTLL_DST_WIDTH(dst_width)
 732                         | DWC_CTLL_SRC_WIDTH(src_width)
 733                         | DWC_CTLL_DST_INC
 734                         | DWC_CTLL_SRC_INC
 735                         | DWC_CTLL_FC_M2M;
 736         prev = first = NULL;
 737
 738         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 739                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 740                                            dwc->block_size);
 741
 742                 desc = dwc_desc_get(dwc);
 743                 if (!desc)
 744                         goto err_desc_get;
 745
 746                 desc->lli.sar = src + offset;
 747                 desc->lli.dar = dest + offset;
 748                 desc->lli.ctllo = ctllo;
 749                 desc->lli.ctlhi = xfer_count;
 750                 desc->len = xfer_count << src_width;
 751
 752                 if (!first) {
 753                         first = desc;
 754                 } else {
 755                         prev->lli.llp = desc->txd.phys;
 756                         list_add_tail(&desc->desc_node,
 757                                         &first->tx_list);
 758                 }
 759                 prev = desc;
 760         }
 761
 762         if (flags & DMA_PREP_INTERRUPT)
 763                 /* Trigger interrupt after last block */
 764                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 765
 766         prev->lli.llp = 0;
 767         first->txd.flags = flags;
 768         first->total_len = len;
 769
 770         return &first->txd;
 771
 772 err_desc_get:
 773         dwc_desc_put(dwc, first);
 774         return NULL;
 775 }
 776
 777 static struct dma_async_tx_descriptor *
 778 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 779                 unsigned int sg_len, enum dma_transfer_direction direction,
 780                 unsigned long flags, void *context)
 781 {
 782         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 783         struct dw_dma           *dw = to_dw_dma(chan->device);
 784         struct dma_slave_config *sconfig = &dwc->dma_sconfig;
 785         struct dw_desc          *prev;
 786         struct dw_desc          *first;
 787         u32                     ctllo;
 788         dma_addr_t              reg;
 789         unsigned int            reg_width;
 790         unsigned int            mem_width;
 791         unsigned int            data_width;
 792         unsigned int            i;
 793         struct scatterlist      *sg;
 794         size_t                  total_len = 0;
 795
 796         dev_vdbg(chan2dev(chan), "%s\n", __func__);
 797
 798         if (unlikely(!is_slave_direction(direction) || !sg_len))
 799                 return NULL;
 800
 801         dwc->direction = direction;
 802
 803         prev = first = NULL;
 804
 805         switch (direction) {
 806         case DMA_MEM_TO_DEV:
 807                 reg_width = __fls(sconfig->dst_addr_width);
 808                 reg = sconfig->dst_addr;
 809                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 810                                 | DWC_CTLL_DST_WIDTH(reg_width)
 811                                 | DWC_CTLL_DST_FIX
 812                                 | DWC_CTLL_SRC_INC);
 813
 814                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
 815                         DWC_CTLL_FC(DW_DMA_FC_D_M2P);
 816
 817                 data_width = dw->data_width[dwc->src_master];
 818
 819                 for_each_sg(sgl, sg, sg_len, i) {
 820                         struct dw_desc  *desc;
 821                         u32             len, dlen, mem;
 822
 823                         mem = sg_dma_address(sg);
 824                         len = sg_dma_len(sg);
 825
 826                         mem_width = min_t(unsigned int,
 827                                           data_width, dwc_fast_fls(mem | len));
 828
 829 slave_sg_todev_fill_desc:
 830                         desc = dwc_desc_get(dwc);
 831                         if (!desc) {
 832                                 dev_err(chan2dev(chan),
 833                                         "not enough descriptors available\n");
 834                                 goto err_desc_get;
 835                         }
 836
 837                         desc->lli.sar = mem;
 838                         desc->lli.dar = reg;
 839                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 840                         if ((len >> mem_width) > dwc->block_size) {
 841                                 dlen = dwc->block_size << mem_width;
 842                                 mem += dlen;
 843                                 len -= dlen;
 844                         } else {
 845                                 dlen = len;
 846                                 len = 0;
 847                         }
 848
 849                         desc->lli.ctlhi = dlen >> mem_width;
 850                         desc->len = dlen;
 851
 852                         if (!first) {
 853                                 first = desc;
 854                         } else {
 855                                 prev->lli.llp = desc->txd.phys;
 856                                 list_add_tail(&desc->desc_node,
 857                                                 &first->tx_list);
 858                         }
 859                         prev = desc;
 860                         total_len += dlen;
 861
 862                         if (len)
 863                                 goto slave_sg_todev_fill_desc;
 864                 }
 865                 break;
 866         case DMA_DEV_TO_MEM:
 867                 reg_width = __fls(sconfig->src_addr_width);
 868                 reg = sconfig->src_addr;
 869                 ctllo = (DWC_DEFAULT_CTLLO(chan)
 870                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 871                                 | DWC_CTLL_DST_INC
 872                                 | DWC_CTLL_SRC_FIX);
 873
 874                 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
 875                         DWC_CTLL_FC(DW_DMA_FC_D_P2M);
 876
 877                 data_width = dw->data_width[dwc->dst_master];
 878
 879                 for_each_sg(sgl, sg, sg_len, i) {
 880                         struct dw_desc  *desc;
 881                         u32             len, dlen, mem;
 882
 883                         mem = sg_dma_address(sg);
 884                         len = sg_dma_len(sg);
 885
 886                         mem_width = min_t(unsigned int,
 887                                           data_width, dwc_fast_fls(mem | len));
 888
 889 slave_sg_fromdev_fill_desc:
 890                         desc = dwc_desc_get(dwc);
 891                         if (!desc) {
 892                                 dev_err(chan2dev(chan),
 893                                                 "not enough descriptors available\n");
 894                                 goto err_desc_get;
 895                         }
 896
 897                         desc->lli.sar = reg;
 898                         desc->lli.dar = mem;
 899                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 900                         if ((len >> reg_width) > dwc->block_size) {
 901                                 dlen = dwc->block_size << reg_width;
 902                                 mem += dlen;
 903                                 len -= dlen;
 904                         } else {
 905                                 dlen = len;
 906                                 len = 0;
 907                         }
 908                         desc->lli.ctlhi = dlen >> reg_width;
 909                         desc->len = dlen;
 910
 911                         if (!first) {
 912                                 first = desc;
 913                         } else {
 914                                 prev->lli.llp = desc->txd.phys;
 915                                 list_add_tail(&desc->desc_node,
 916                                                 &first->tx_list);
 917                         }
 918                         prev = desc;
 919                         total_len += dlen;
 920
 921                         if (len)
 922                                 goto slave_sg_fromdev_fill_desc;
 923                 }
 924                 break;
 925         default:
 926                 return NULL;
 927         }
 928
 929         if (flags & DMA_PREP_INTERRUPT)
 930                 /* Trigger interrupt after last block */
 931                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 932
 933         prev->lli.llp = 0;
 934         first->total_len = total_len;
 935
 936         return &first->txd;
 937
 938 err_desc_get:
 939         dwc_desc_put(dwc, first);
 940         return NULL;
 941 }
 942
 943 /*
 944  * Fix sconfig's burst size according to dw_dmac. We need to convert them as:
 945  * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
 946  *
 947  * NOTE: burst size 2 is not supported by controller.
 948  *
 949  * This can be done by finding least significant bit set: n & (n - 1)
 950  */
 951 static inline void convert_burst(u32 *maxburst)
 952 {
 953         if (*maxburst > 1)
 954                 *maxburst = fls(*maxburst) - 2;
 955         else
 956                 *maxburst = 0;
 957 }
 958
 959 static int
 960 set_runtime_config(struct dma_chan *chan, struct dma_slave_config *sconfig)
 961 {
 962         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 963
 964         /* Check if chan will be configured for slave transfers */
 965         if (!is_slave_direction(sconfig->direction))
 966                 return -EINVAL;
 967
 968         memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig));
 969         dwc->direction = sconfig->direction;
 970
 971         /* Take the request line from slave_id member */
 972         if (is_request_line_unset(dwc))
 973                 dwc->request_line = sconfig->slave_id;
 974
 975         convert_burst(&dwc->dma_sconfig.src_maxburst);
 976         convert_burst(&dwc->dma_sconfig.dst_maxburst);
 977
 978         return 0;
 979 }
 980
 981 static inline void dwc_chan_pause(struct dw_dma_chan *dwc)
 982 {
 983         u32 cfglo = channel_readl(dwc, CFG_LO);
 984         unsigned int count = 20;        /* timeout iterations */
 985
 986         channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 987         while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--)
 988                 udelay(2);
 989
 990         dwc->paused = true;
 991 }
 992
 993 static inline void dwc_chan_resume(struct dw_dma_chan *dwc)
 994 {
 995         u32 cfglo = channel_readl(dwc, CFG_LO);
 996
 997         channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
 998
 999         dwc->paused = false;
1000 }
1001
1002 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1003                        unsigned long arg)
1004 {
1005         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1006         struct dw_dma           *dw = to_dw_dma(chan->device);
1007         struct dw_desc          *desc, *_desc;
1008         unsigned long           flags;
1009         LIST_HEAD(list);
1010
1011         if (cmd == DMA_PAUSE) {
1012                 spin_lock_irqsave(&dwc->lock, flags);
1013
1014                 dwc_chan_pause(dwc);
1015
1016                 spin_unlock_irqrestore(&dwc->lock, flags);
1017         } else if (cmd == DMA_RESUME) {
1018                 if (!dwc->paused)
1019                         return 0;
1020
1021                 spin_lock_irqsave(&dwc->lock, flags);
1022
1023                 dwc_chan_resume(dwc);
1024
1025                 spin_unlock_irqrestore(&dwc->lock, flags);
1026         } else if (cmd == DMA_TERMINATE_ALL) {
1027                 spin_lock_irqsave(&dwc->lock, flags);
1028
1029                 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags);
1030
1031                 dwc_chan_disable(dw, dwc);
1032
1033                 dwc_chan_resume(dwc);
1034
1035                 /* active_list entries will end up before queued entries */
1036                 list_splice_init(&dwc->queue, &list);
1037                 list_splice_init(&dwc->active_list, &list);
1038
1039                 spin_unlock_irqrestore(&dwc->lock, flags);
1040
1041                 /* Flush all pending and queued descriptors */
1042                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1043                         dwc_descriptor_complete(dwc, desc, false);
1044         } else if (cmd == DMA_SLAVE_CONFIG) {
1045                 return set_runtime_config(chan, (struct dma_slave_config *)arg);
1046         } else {
1047                 return -ENXIO;
1048         }
1049
1050         return 0;
1051 }
1052
1053 static inline u32 dwc_get_residue(struct dw_dma_chan *dwc)
1054 {
1055         unsigned long flags;
1056         u32 residue;
1057
1058         spin_lock_irqsave(&dwc->lock, flags);
1059
1060         residue = dwc->residue;
1061         if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue)
1062                 residue -= dwc_get_sent(dwc);
1063
1064         spin_unlock_irqrestore(&dwc->lock, flags);
1065         return residue;
1066 }
1067
1068 static enum dma_status
1069 dwc_tx_status(struct dma_chan *chan,
1070               dma_cookie_t cookie,
1071               struct dma_tx_state *txstate)
1072 {
1073         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1074         enum dma_status         ret;
1075
1076         ret = dma_cookie_status(chan, cookie, txstate);
1077         if (ret == DMA_COMPLETE)
1078                 return ret;
1079
1080         dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1081
1082         ret = dma_cookie_status(chan, cookie, txstate);
1083         if (ret != DMA_COMPLETE)
1084                 dma_set_residue(txstate, dwc_get_residue(dwc));
1085
1086         if (dwc->paused && ret == DMA_IN_PROGRESS)
1087                 return DMA_PAUSED;
1088
1089         return ret;
1090 }
1091
1092 static void dwc_issue_pending(struct dma_chan *chan)
1093 {
1094         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1095
1096         if (!list_empty(&dwc->queue))
1097                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
1098 }
1099
1100 static int dwc_alloc_chan_resources(struct dma_chan *chan)
1101 {
1102         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1103         struct dw_dma           *dw = to_dw_dma(chan->device);
1104         struct dw_desc          *desc;
1105         int                     i;
1106         unsigned long           flags;
1107
1108         dev_vdbg(chan2dev(chan), "%s\n", __func__);
1109
1110         /* ASSERT:  channel is idle */
1111         if (dma_readl(dw, CH_EN) & dwc->mask) {
1112                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
1113                 return -EIO;
1114         }
1115
1116         dma_cookie_init(chan);
1117
1118         /*
1119          * NOTE: some controllers may have additional features that we
1120          * need to initialize here, like "scatter-gather" (which
1121          * doesn't mean what you think it means), and status writeback.
1122          */
1123
1124         dwc_set_masters(dwc);
1125
1126         spin_lock_irqsave(&dwc->lock, flags);
1127         i = dwc->descs_allocated;
1128         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1129                 dma_addr_t phys;
1130
1131                 spin_unlock_irqrestore(&dwc->lock, flags);
1132
1133                 desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
1134                 if (!desc)
1135                         goto err_desc_alloc;
1136
1137                 memset(desc, 0, sizeof(struct dw_desc));
1138
1139                 INIT_LIST_HEAD(&desc->tx_list);
1140                 dma_async_tx_descriptor_init(&desc->txd, chan);
1141                 desc->txd.tx_submit = dwc_tx_submit;
1142                 desc->txd.flags = DMA_CTRL_ACK;
1143                 desc->txd.phys = phys;
1144
1145                 dwc_desc_put(dwc, desc);
1146
1147                 spin_lock_irqsave(&dwc->lock, flags);
1148                 i = ++dwc->descs_allocated;
1149         }
1150
1151         spin_unlock_irqrestore(&dwc->lock, flags);
1152
1153         dev_dbg(chan2dev(chan), "%s: allocated %d descriptors\n", __func__, i);
1154
1155         return i;
1156
1157 err_desc_alloc:
1158         dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
1159
1160         return i;
1161 }
1162
1163 static void dwc_free_chan_resources(struct dma_chan *chan)
1164 {
1165         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1166         struct dw_dma           *dw = to_dw_dma(chan->device);
1167         struct dw_desc          *desc, *_desc;
1168         unsigned long           flags;
1169         LIST_HEAD(list);
1170
1171         dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__,
1172                         dwc->descs_allocated);
1173
1174         /* ASSERT:  channel is idle */
1175         BUG_ON(!list_empty(&dwc->active_list));
1176         BUG_ON(!list_empty(&dwc->queue));
1177         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1178
1179         spin_lock_irqsave(&dwc->lock, flags);
1180         list_splice_init(&dwc->free_list, &list);
1181         dwc->descs_allocated = 0;
1182         dwc->initialized = false;
1183         dwc->request_line = ~0;
1184
1185         /* Disable interrupts */
1186         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1187         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1188
1189         spin_unlock_irqrestore(&dwc->lock, flags);
1190
1191         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1192                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1193                 dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
1194         }
1195
1196         dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
1197 }
1198
1199 /* --------------------- Cyclic DMA API extensions -------------------- */
1200
1201 /**
1202  * dw_dma_cyclic_start - start the cyclic DMA transfer
1203  * @chan: the DMA channel to start
1204  *
1205  * Must be called with soft interrupts disabled. Returns zero on success or
1206  * -errno on failure.
1207  */
1208 int dw_dma_cyclic_start(struct dma_chan *chan)
1209 {
1210         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1211         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1212         unsigned long           flags;
1213
1214         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1215                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1216                 return -ENODEV;
1217         }
1218
1219         spin_lock_irqsave(&dwc->lock, flags);
1220
1221         /* Assert channel is idle */
1222         if (dma_readl(dw, CH_EN) & dwc->mask) {
1223                 dev_err(chan2dev(&dwc->chan),
1224                         "BUG: Attempted to start non-idle channel\n");
1225                 dwc_dump_chan_regs(dwc);
1226                 spin_unlock_irqrestore(&dwc->lock, flags);
1227                 return -EBUSY;
1228         }
1229
1230         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1231         dma_writel(dw, CLEAR.XFER, dwc->mask);
1232
1233         /* Setup DMAC channel registers */
1234         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1235         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1236         channel_writel(dwc, CTL_HI, 0);
1237
1238         channel_set_bit(dw, CH_EN, dwc->mask);
1239
1240         spin_unlock_irqrestore(&dwc->lock, flags);
1241
1242         return 0;
1243 }
1244 EXPORT_SYMBOL(dw_dma_cyclic_start);
1245
1246 /**
1247  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1248  * @chan: the DMA channel to stop
1249  *
1250  * Must be called with soft interrupts disabled.
1251  */
1252 void dw_dma_cyclic_stop(struct dma_chan *chan)
1253 {
1254         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1255         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1256         unsigned long           flags;
1257
1258         spin_lock_irqsave(&dwc->lock, flags);
1259
1260         dwc_chan_disable(dw, dwc);
1261
1262         spin_unlock_irqrestore(&dwc->lock, flags);
1263 }
1264 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1265
1266 /**
1267  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1268  * @chan: the DMA channel to prepare
1269  * @buf_addr: physical DMA address where the buffer starts
1270  * @buf_len: total number of bytes for the entire buffer
1271  * @period_len: number of bytes for each period
1272  * @direction: transfer direction, to or from device
1273  *
1274  * Must be called before trying to start the transfer. Returns a valid struct
1275  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1276  */
1277 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1278                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1279                 enum dma_transfer_direction direction)
1280 {
1281         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1282         struct dma_slave_config         *sconfig = &dwc->dma_sconfig;
1283         struct dw_cyclic_desc           *cdesc;
1284         struct dw_cyclic_desc           *retval = NULL;
1285         struct dw_desc                  *desc;
1286         struct dw_desc                  *last = NULL;
1287         unsigned long                   was_cyclic;
1288         unsigned int                    reg_width;
1289         unsigned int                    periods;
1290         unsigned int                    i;
1291         unsigned long                   flags;
1292
1293         spin_lock_irqsave(&dwc->lock, flags);
1294         if (dwc->nollp) {
1295                 spin_unlock_irqrestore(&dwc->lock, flags);
1296                 dev_dbg(chan2dev(&dwc->chan),
1297                                 "channel doesn't support LLP transfers\n");
1298                 return ERR_PTR(-EINVAL);
1299         }
1300
1301         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1302                 spin_unlock_irqrestore(&dwc->lock, flags);
1303                 dev_dbg(chan2dev(&dwc->chan),
1304                                 "queue and/or active list are not empty\n");
1305                 return ERR_PTR(-EBUSY);
1306         }
1307
1308         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1309         spin_unlock_irqrestore(&dwc->lock, flags);
1310         if (was_cyclic) {
1311                 dev_dbg(chan2dev(&dwc->chan),
1312                                 "channel already prepared for cyclic DMA\n");
1313                 return ERR_PTR(-EBUSY);
1314         }
1315
1316         retval = ERR_PTR(-EINVAL);
1317
1318         if (unlikely(!is_slave_direction(direction)))
1319                 goto out_err;
1320
1321         dwc->direction = direction;
1322
1323         if (direction == DMA_MEM_TO_DEV)
1324                 reg_width = __ffs(sconfig->dst_addr_width);
1325         else
1326                 reg_width = __ffs(sconfig->src_addr_width);
1327
1328         periods = buf_len / period_len;
1329
1330         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1331         if (period_len > (dwc->block_size << reg_width))
1332                 goto out_err;
1333         if (unlikely(period_len & ((1 << reg_width) - 1)))
1334                 goto out_err;
1335         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1336                 goto out_err;
1337
1338         retval = ERR_PTR(-ENOMEM);
1339
1340         if (periods > NR_DESCS_PER_CHANNEL)
1341                 goto out_err;
1342
1343         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1344         if (!cdesc)
1345                 goto out_err;
1346
1347         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1348         if (!cdesc->desc)
1349                 goto out_err_alloc;
1350
1351         for (i = 0; i < periods; i++) {
1352                 desc = dwc_desc_get(dwc);
1353                 if (!desc)
1354                         goto out_err_desc_get;
1355
1356                 switch (direction) {
1357                 case DMA_MEM_TO_DEV:
1358                         desc->lli.dar = sconfig->dst_addr;
1359                         desc->lli.sar = buf_addr + (period_len * i);
1360                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1361                                         | DWC_CTLL_DST_WIDTH(reg_width)
1362                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1363                                         | DWC_CTLL_DST_FIX
1364                                         | DWC_CTLL_SRC_INC
1365                                         | DWC_CTLL_INT_EN);
1366
1367                         desc->lli.ctllo |= sconfig->device_fc ?
1368                                 DWC_CTLL_FC(DW_DMA_FC_P_M2P) :
1369                                 DWC_CTLL_FC(DW_DMA_FC_D_M2P);
1370
1371                         break;
1372                 case DMA_DEV_TO_MEM:
1373                         desc->lli.dar = buf_addr + (period_len * i);
1374                         desc->lli.sar = sconfig->src_addr;
1375                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan)
1376                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1377                                         | DWC_CTLL_DST_WIDTH(reg_width)
1378                                         | DWC_CTLL_DST_INC
1379                                         | DWC_CTLL_SRC_FIX
1380                                         | DWC_CTLL_INT_EN);
1381
1382                         desc->lli.ctllo |= sconfig->device_fc ?
1383                                 DWC_CTLL_FC(DW_DMA_FC_P_P2M) :
1384                                 DWC_CTLL_FC(DW_DMA_FC_D_P2M);
1385
1386                         break;
1387                 default:
1388                         break;
1389                 }
1390
1391                 desc->lli.ctlhi = (period_len >> reg_width);
1392                 cdesc->desc[i] = desc;
1393
1394                 if (last)
1395                         last->lli.llp = desc->txd.phys;
1396
1397                 last = desc;
1398         }
1399
1400         /* Let's make a cyclic list */
1401         last->lli.llp = cdesc->desc[0]->txd.phys;
1402
1403         dev_dbg(chan2dev(&dwc->chan),
1404                         "cyclic prepared buf %pad len %zu period %zu periods %d\n",
1405                         &buf_addr, buf_len, period_len, periods);
1406
1407         cdesc->periods = periods;
1408         dwc->cdesc = cdesc;
1409
1410         return cdesc;
1411
1412 out_err_desc_get:
1413         while (i--)
1414                 dwc_desc_put(dwc, cdesc->desc[i]);
1415 out_err_alloc:
1416         kfree(cdesc);
1417 out_err:
1418         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1419         return (struct dw_cyclic_desc *)retval;
1420 }
1421 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1422
1423 /**
1424  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1425  * @chan: the DMA channel to free
1426  */
1427 void dw_dma_cyclic_free(struct dma_chan *chan)
1428 {
1429         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1430         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1431         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1432         int                     i;
1433         unsigned long           flags;
1434
1435         dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__);
1436
1437         if (!cdesc)
1438                 return;
1439
1440         spin_lock_irqsave(&dwc->lock, flags);
1441
1442         dwc_chan_disable(dw, dwc);
1443
1444         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1445         dma_writel(dw, CLEAR.XFER, dwc->mask);
1446
1447         spin_unlock_irqrestore(&dwc->lock, flags);
1448
1449         for (i = 0; i < cdesc->periods; i++)
1450                 dwc_desc_put(dwc, cdesc->desc[i]);
1451
1452         kfree(cdesc->desc);
1453         kfree(cdesc);
1454
1455         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1456 }
1457 EXPORT_SYMBOL(dw_dma_cyclic_free);
1458
1459 /*----------------------------------------------------------------------*/
1460
1461 static void dw_dma_off(struct dw_dma *dw)
1462 {
1463         int i;
1464
1465         dma_writel(dw, CFG, 0);
1466
1467         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1468         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1469         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1470         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1471
1472         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1473                 cpu_relax();
1474
1475         for (i = 0; i < dw->dma.chancnt; i++)
1476                 dw->chan[i].initialized = false;
1477 }
1478
1479 int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1480 {
1481         struct dw_dma           *dw;
1482         size_t                  size;
1483         bool                    autocfg;
1484         unsigned int            dw_params;
1485         unsigned int            nr_channels;
1486         unsigned int            max_blk_size = 0;
1487         int                     err;
1488         int                     i;
1489
1490         dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1491         autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1492
1493         dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params);
1494
1495         if (!pdata && autocfg) {
1496                 pdata = devm_kzalloc(chip->dev, sizeof(*pdata), GFP_KERNEL);
1497                 if (!pdata)
1498                         return -ENOMEM;
1499
1500                 /* Fill platform data with the default values */
1501                 pdata->is_private = true;
1502                 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;
1503                 pdata->chan_priority = CHAN_PRIORITY_ASCENDING;
1504         } else if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1505                 return -EINVAL;
1506
1507         if (autocfg)
1508                 nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 0x7) + 1;
1509         else
1510                 nr_channels = pdata->nr_channels;
1511
1512         size = sizeof(struct dw_dma) + nr_channels * sizeof(struct dw_dma_chan);
1513         dw = devm_kzalloc(chip->dev, size, GFP_KERNEL);
1514         if (!dw)
1515                 return -ENOMEM;
1516
1517         dw->clk = devm_clk_get(chip->dev, "hclk");
1518         if (IS_ERR(dw->clk))
1519                 return PTR_ERR(dw->clk);
1520         clk_prepare_enable(dw->clk);
1521
1522         dw->regs = chip->regs;
1523         chip->dw = dw;
1524
1525         /* Get hardware configuration parameters */
1526         if (autocfg) {
1527                 max_blk_size = dma_readl(dw, MAX_BLK_SIZE);
1528
1529                 dw->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1;
1530                 for (i = 0; i < dw->nr_masters; i++) {
1531                         dw->data_width[i] =
1532                                 (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3) + 2;
1533                 }
1534         } else {
1535                 dw->nr_masters = pdata->nr_masters;
1536                 memcpy(dw->data_width, pdata->data_width, 4);
1537         }
1538
1539         /* Calculate all channel mask before DMA setup */
1540         dw->all_chan_mask = (1 << nr_channels) - 1;
1541
1542         /* Force dma off, just in case */
1543         dw_dma_off(dw);
1544
1545         /* Disable BLOCK interrupts as well */
1546         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1547
1548         err = devm_request_irq(chip->dev, chip->irq, dw_dma_interrupt,
1549                                IRQF_SHARED, "dw_dmac", dw);
1550         if (err)
1551                 return err;
1552
1553         /* Create a pool of consistent memory blocks for hardware descriptors */
1554         dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", chip->dev,
1555                                          sizeof(struct dw_desc), 4, 0);
1556         if (!dw->desc_pool) {
1557                 dev_err(chip->dev, "No memory for descriptors dma pool\n");
1558                 return -ENOMEM;
1559         }
1560
1561         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1562
1563         INIT_LIST_HEAD(&dw->dma.channels);
1564         for (i = 0; i < nr_channels; i++) {
1565                 struct dw_dma_chan      *dwc = &dw->chan[i];
1566                 int                     r = nr_channels - i - 1;
1567
1568                 dwc->chan.device = &dw->dma;
1569                 dma_cookie_init(&dwc->chan);
1570                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1571                         list_add_tail(&dwc->chan.device_node,
1572                                         &dw->dma.channels);
1573                 else
1574                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1575
1576                 /* 7 is highest priority & 0 is lowest. */
1577                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1578                         dwc->priority = r;
1579                 else
1580                         dwc->priority = i;
1581
1582                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1583                 spin_lock_init(&dwc->lock);
1584                 dwc->mask = 1 << i;
1585
1586                 INIT_LIST_HEAD(&dwc->active_list);
1587                 INIT_LIST_HEAD(&dwc->queue);
1588                 INIT_LIST_HEAD(&dwc->free_list);
1589
1590                 channel_clear_bit(dw, CH_EN, dwc->mask);
1591
1592                 dwc->direction = DMA_TRANS_NONE;
1593                 dwc->request_line = ~0;
1594
1595                 /* Hardware configuration */
1596                 if (autocfg) {
1597                         unsigned int dwc_params;
1598                         void __iomem *addr = chip->regs + r * sizeof(u32);
1599
1600                         dwc_params = dma_read_byaddr(addr, DWC_PARAMS);
1601
1602                         dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i,
1603                                            dwc_params);
1604
1605                         /*
1606                          * Decode maximum block size for given channel. The
1607                          * stored 4 bit value represents blocks from 0x00 for 3
1608                          * up to 0x0a for 4095.
1609                          */
1610                         dwc->block_size =
1611                                 (4 << ((max_blk_size >> 4 * i) & 0xf)) - 1;
1612                         dwc->nollp =
1613                                 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
1614                 } else {
1615                         dwc->block_size = pdata->block_size;
1616
1617                         /* Check if channel supports multi block transfer */
1618                         channel_writel(dwc, LLP, 0xfffffffc);
1619                         dwc->nollp =
1620                                 (channel_readl(dwc, LLP) & 0xfffffffc) == 0;
1621                         channel_writel(dwc, LLP, 0);
1622                 }
1623         }
1624
1625         /* Clear all interrupts on all channels. */
1626         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1627         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1628         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1629         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1630         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1631
1632         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1633         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1634         if (pdata->is_private)
1635                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1636         dw->dma.dev = chip->dev;
1637         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1638         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1639
1640         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1641
1642         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1643         dw->dma.device_control = dwc_control;
1644
1645         dw->dma.device_tx_status = dwc_tx_status;
1646         dw->dma.device_issue_pending = dwc_issue_pending;
1647
1648         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1649
1650         dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1651                  nr_channels);
1652
1653         dma_async_device_register(&dw->dma);
1654
1655         return 0;
1656 }
1657 EXPORT_SYMBOL_GPL(dw_dma_probe);
1658
1659 int dw_dma_remove(struct dw_dma_chip *chip)
1660 {
1661         struct dw_dma           *dw = chip->dw;
1662         struct dw_dma_chan      *dwc, *_dwc;
1663
1664         dw_dma_off(dw);
1665         dma_async_device_unregister(&dw->dma);
1666
1667         tasklet_kill(&dw->tasklet);
1668
1669         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1670                         chan.device_node) {
1671                 list_del(&dwc->chan.device_node);
1672                 channel_clear_bit(dw, CH_EN, dwc->mask);
1673         }
1674
1675         return 0;
1676 }
1677 EXPORT_SYMBOL_GPL(dw_dma_remove);
1678
1679 void dw_dma_shutdown(struct dw_dma_chip *chip)
1680 {
1681         struct dw_dma *dw = chip->dw;
1682
1683         dw_dma_off(dw);
1684         clk_disable_unprepare(dw->clk);
1685 }
1686 EXPORT_SYMBOL_GPL(dw_dma_shutdown);
1687
1688 #ifdef CONFIG_PM_SLEEP
1689
1690 int dw_dma_suspend(struct dw_dma_chip *chip)
1691 {
1692         struct dw_dma *dw = chip->dw;
1693
1694         dw_dma_off(dw);
1695         clk_disable_unprepare(dw->clk);
1696
1697         return 0;
1698 }
1699 EXPORT_SYMBOL_GPL(dw_dma_suspend);
1700
1701 int dw_dma_resume(struct dw_dma_chip *chip)
1702 {
1703         struct dw_dma *dw = chip->dw;
1704
1705         clk_prepare_enable(dw->clk);
1706         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1707
1708         return 0;
1709 }
1710 EXPORT_SYMBOL_GPL(dw_dma_resume);
1711
1712 #endif /* CONFIG_PM_SLEEP */
1713
1714 MODULE_LICENSE("GPL v2");
1715 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver");
1716 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1717 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");