drivers/clk/ux500/u8500_of_clk.c

   1 /*
   2  * Clock definitions for u8500 platform.
   3  *
   4  * Copyright (C) 2012 ST-Ericsson SA
   5  * Author: Ulf Hansson <ulf.hansson@linaro.org>
   6  *
   7  * License terms: GNU General Public License (GPL) version 2
   8  */
   9
  10 #include <linux/of.h>
  11 #include <linux/clk.h>
  12 #include <linux/clkdev.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/mfd/dbx500-prcmu.h>
  15 #include <linux/platform_data/clk-ux500.h>
  16 #include "clk.h"
  17
  18 #define PRCC_NUM_PERIPH_CLUSTERS 6
  19 #define PRCC_PERIPHS_PER_CLUSTER 32
  20
  21 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
  22 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  23 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
  24
  25 #define PRCC_SHOW(clk, base, bit) \
  26         clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
  27 #define PRCC_PCLK_STORE(clk, base, bit) \
  28         prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  29 #define PRCC_KCLK_STORE(clk, base, bit)        \
  30         prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
  31
  32 struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, void *data)
  33 {
  34         struct clk **clk_data = data;
  35         unsigned int base, bit;
  36
  37         if (clkspec->args_count != 2)
  38                 return  ERR_PTR(-EINVAL);
  39
  40         base = clkspec->args[0];
  41         bit = clkspec->args[1];
  42
  43         if (base != 1 && base != 2 && base != 3 && base != 5 && base != 6) {
  44                 pr_err("%s: invalid PRCC base %d\n", __func__, base);
  45                 return ERR_PTR(-EINVAL);
  46         }
  47
  48         return PRCC_SHOW(clk_data, base, bit);
  49 }
  50
  51 static const struct of_device_id u8500_clk_of_match[] = {
  52         { .compatible = "stericsson,u8500-clks", },
  53         { },
  54 };
  55
  56 void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
  57                        u32 clkrst5_base, u32 clkrst6_base)
  58 {
  59         struct prcmu_fw_version *fw_version;
  60         struct device_node *np = NULL;
  61         struct device_node *child = NULL;
  62         const char *sgaclk_parent = NULL;
  63         struct clk *clk;
  64
  65         if (of_have_populated_dt())
  66                 np = of_find_matching_node(NULL, u8500_clk_of_match);
  67         if (!np) {
  68                 pr_err("Either DT or U8500 Clock node not found\n");
  69                 return;
  70         }
  71
  72         /* Clock sources */
  73         clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0,
  74                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  75         prcmu_clk[PRCMU_PLLSOC0] = clk;
  76
  77         clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1,
  78                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  79         prcmu_clk[PRCMU_PLLSOC1] = clk;
  80
  81         clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR,
  82                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED);
  83         prcmu_clk[PRCMU_PLLDDR] = clk;
  84
  85         /* FIXME: Add sys, ulp and int clocks here. */
  86
  87         clk = clk_register_fixed_rate(NULL, "rtc32k", "NULL",
  88                                 CLK_IS_ROOT|CLK_IGNORE_UNUSED,
  89                                 32768);
  90
  91         /* PRCMU clocks */
  92         fw_version = prcmu_get_fw_version();
  93         if (fw_version != NULL) {
  94                 switch (fw_version->project) {
  95                 case PRCMU_FW_PROJECT_U8500_C2:
  96                 case PRCMU_FW_PROJECT_U8520:
  97                 case PRCMU_FW_PROJECT_U8420:
  98                         sgaclk_parent = "soc0_pll";
  99                         break;
 100                 default:
 101                         break;
 102                 }
 103         }
 104
 105         if (sgaclk_parent)
 106                 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent,
 107                                         PRCMU_SGACLK, 0);
 108         else
 109                 clk = clk_reg_prcmu_gate("sgclk", NULL,
 110                                         PRCMU_SGACLK, CLK_IS_ROOT);
 111         prcmu_clk[PRCMU_SGACLK] = clk;
 112
 113         clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT);
 114         prcmu_clk[PRCMU_UARTCLK] = clk;
 115
 116         clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT);
 117         prcmu_clk[PRCMU_MSP02CLK] = clk;
 118
 119         clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT);
 120         prcmu_clk[PRCMU_MSP1CLK] = clk;
 121
 122         clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT);
 123         prcmu_clk[PRCMU_I2CCLK] = clk;
 124
 125         clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT);
 126         prcmu_clk[PRCMU_SLIMCLK] = clk;
 127
 128         clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT);
 129         prcmu_clk[PRCMU_PER1CLK] = clk;
 130
 131         clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT);
 132         prcmu_clk[PRCMU_PER2CLK] = clk;
 133
 134         clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT);
 135         prcmu_clk[PRCMU_PER3CLK] = clk;
 136
 137         clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT);
 138         prcmu_clk[PRCMU_PER5CLK] = clk;
 139
 140         clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT);
 141         prcmu_clk[PRCMU_PER6CLK] = clk;
 142
 143         clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT);
 144         prcmu_clk[PRCMU_PER7CLK] = clk;
 145
 146         clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0,
 147                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 148         prcmu_clk[PRCMU_LCDCLK] = clk;
 149
 150         clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT);
 151         prcmu_clk[PRCMU_BMLCLK] = clk;
 152
 153         clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0,
 154                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 155         prcmu_clk[PRCMU_HSITXCLK] = clk;
 156
 157         clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0,
 158                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 159         prcmu_clk[PRCMU_HSIRXCLK] = clk;
 160
 161         clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0,
 162                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 163         prcmu_clk[PRCMU_HDMICLK] = clk;
 164
 165         clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT);
 166         prcmu_clk[PRCMU_APEATCLK] = clk;
 167
 168         clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK,
 169                                 CLK_IS_ROOT);
 170         prcmu_clk[PRCMU_APETRACECLK] = clk;
 171
 172         clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT);
 173         prcmu_clk[PRCMU_MCDECLK] = clk;
 174
 175         clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK,
 176                                 CLK_IS_ROOT);
 177         prcmu_clk[PRCMU_IPI2CCLK] = clk;
 178
 179         clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK,
 180                                 CLK_IS_ROOT);
 181         prcmu_clk[PRCMU_DSIALTCLK] = clk;
 182
 183         clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT);
 184         prcmu_clk[PRCMU_DMACLK] = clk;
 185
 186         clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT);
 187         prcmu_clk[PRCMU_B2R2CLK] = clk;
 188
 189         clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0,
 190                                 CLK_IS_ROOT|CLK_SET_RATE_GATE);
 191         prcmu_clk[PRCMU_TVCLK] = clk;
 192
 193         clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT);
 194         prcmu_clk[PRCMU_SSPCLK] = clk;
 195
 196         clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT);
 197         prcmu_clk[PRCMU_RNGCLK] = clk;
 198
 199         clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT);
 200         prcmu_clk[PRCMU_UICCCLK] = clk;
 201
 202         clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT);
 203         prcmu_clk[PRCMU_TIMCLK] = clk;
 204
 205         clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
 206                                         100000000,
 207                                         CLK_IS_ROOT|CLK_SET_RATE_GATE);
 208         prcmu_clk[PRCMU_SDMMCCLK] = clk;
 209
 210         clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
 211                                 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
 212         prcmu_clk[PRCMU_PLLDSI] = clk;
 213
 214         clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll",
 215                                 PRCMU_DSI0CLK, 0, CLK_SET_RATE_GATE);
 216         prcmu_clk[PRCMU_DSI0CLK] = clk;
 217
 218         clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll",
 219                                 PRCMU_DSI1CLK, 0, CLK_SET_RATE_GATE);
 220         prcmu_clk[PRCMU_DSI1CLK] = clk;
 221
 222         clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk",
 223                                 PRCMU_DSI0ESCCLK, 0, CLK_SET_RATE_GATE);
 224         prcmu_clk[PRCMU_DSI0ESCCLK] = clk;
 225
 226         clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk",
 227                                 PRCMU_DSI1ESCCLK, 0, CLK_SET_RATE_GATE);
 228         prcmu_clk[PRCMU_DSI1ESCCLK] = clk;
 229
 230         clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk",
 231                                 PRCMU_DSI2ESCCLK, 0, CLK_SET_RATE_GATE);
 232         prcmu_clk[PRCMU_DSI2ESCCLK] = clk;
 233
 234         clk = clk_reg_prcmu_scalable_rate("armss", NULL,
 235                                 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
 236
 237         clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
 238                                 CLK_IGNORE_UNUSED, 1, 2);
 239
 240         /*
 241          * FIXME: Add special handled PRCMU clocks here:
 242          * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
 243          * 2. ab9540_clkout1yuv, see clkout0yuv
 244          */
 245
 246         /* PRCC P-clocks */
 247         clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", clkrst1_base,
 248                                 BIT(0), 0);
 249         PRCC_PCLK_STORE(clk, 1, 0);
 250
 251         clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", clkrst1_base,
 252                                 BIT(1), 0);
 253         PRCC_PCLK_STORE(clk, 1, 1);
 254
 255         clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", clkrst1_base,
 256                                 BIT(2), 0);
 257         PRCC_PCLK_STORE(clk, 1, 2);
 258
 259         clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", clkrst1_base,
 260                                 BIT(3), 0);
 261         PRCC_PCLK_STORE(clk, 1, 3);
 262
 263         clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", clkrst1_base,
 264                                 BIT(4), 0);
 265         PRCC_PCLK_STORE(clk, 1, 4);
 266
 267         clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", clkrst1_base,
 268                                 BIT(5), 0);
 269         PRCC_PCLK_STORE(clk, 1, 5);
 270
 271         clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", clkrst1_base,
 272                                 BIT(6), 0);
 273         PRCC_PCLK_STORE(clk, 1, 6);
 274
 275         clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", clkrst1_base,
 276                                 BIT(7), 0);
 277         PRCC_PCLK_STORE(clk, 1, 7);
 278
 279         clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", clkrst1_base,
 280                                 BIT(8), 0);
 281         PRCC_PCLK_STORE(clk, 1, 8);
 282
 283         clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", clkrst1_base,
 284                                 BIT(9), 0);
 285         PRCC_PCLK_STORE(clk, 1, 9);
 286
 287         clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", clkrst1_base,
 288                                 BIT(10), 0);
 289         PRCC_PCLK_STORE(clk, 1, 10);
 290
 291         clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", clkrst1_base,
 292                                 BIT(11), 0);
 293         PRCC_PCLK_STORE(clk, 1, 11);
 294
 295         clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", clkrst2_base,
 296                                 BIT(0), 0);
 297         PRCC_PCLK_STORE(clk, 2, 0);
 298
 299         clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", clkrst2_base,
 300                                 BIT(1), 0);
 301         PRCC_PCLK_STORE(clk, 2, 1);
 302
 303         clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", clkrst2_base,
 304                                 BIT(2), 0);
 305         PRCC_PCLK_STORE(clk, 2, 2);
 306
 307         clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", clkrst2_base,
 308                                 BIT(3), 0);
 309         PRCC_PCLK_STORE(clk, 2, 3);
 310
 311         clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", clkrst2_base,
 312                                 BIT(4), 0);
 313         PRCC_PCLK_STORE(clk, 2, 4);
 314
 315         clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", clkrst2_base,
 316                                 BIT(5), 0);
 317         PRCC_PCLK_STORE(clk, 2, 5);
 318
 319         clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", clkrst2_base,
 320                                 BIT(6), 0);
 321         PRCC_PCLK_STORE(clk, 2, 6);
 322
 323         clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", clkrst2_base,
 324                                 BIT(7), 0);
 325         PRCC_PCLK_STORE(clk, 2, 7);
 326
 327         clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", clkrst2_base,
 328                                 BIT(8), 0);
 329         PRCC_PCLK_STORE(clk, 2, 8);
 330
 331         clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", clkrst2_base,
 332                                 BIT(9), 0);
 333         PRCC_PCLK_STORE(clk, 2, 9);
 334
 335         clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", clkrst2_base,
 336                                 BIT(10), 0);
 337         PRCC_PCLK_STORE(clk, 2, 10);
 338
 339         clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
 340                                 BIT(11), 0);
 341         PRCC_PCLK_STORE(clk, 2, 1);
 342
 343         clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
 344                                 BIT(12), 0);
 345         PRCC_PCLK_STORE(clk, 2, 12);
 346
 347         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
 348                                 BIT(0), 0);
 349         PRCC_PCLK_STORE(clk, 3, 0);
 350
 351         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
 352                                 BIT(1), 0);
 353         PRCC_PCLK_STORE(clk, 3, 1);
 354
 355         clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", clkrst3_base,
 356                                 BIT(2), 0);
 357         PRCC_PCLK_STORE(clk, 3, 2);
 358
 359         clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", clkrst3_base,
 360                                 BIT(3), 0);
 361         PRCC_PCLK_STORE(clk, 3, 3);
 362
 363         clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", clkrst3_base,
 364                                 BIT(4), 0);
 365         PRCC_PCLK_STORE(clk, 3, 4);
 366
 367         clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", clkrst3_base,
 368                                 BIT(5), 0);
 369         PRCC_PCLK_STORE(clk, 3, 5);
 370
 371         clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", clkrst3_base,
 372                                 BIT(6), 0);
 373         PRCC_PCLK_STORE(clk, 3, 6);
 374
 375         clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", clkrst3_base,
 376                                 BIT(7), 0);
 377         PRCC_PCLK_STORE(clk, 3, 7);
 378
 379         clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", clkrst3_base,
 380                                 BIT(8), 0);
 381         PRCC_PCLK_STORE(clk, 3, 8);
 382
 383         clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", clkrst5_base,
 384                                 BIT(0), 0);
 385         PRCC_PCLK_STORE(clk, 5, 0);
 386
 387         clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", clkrst5_base,
 388                                 BIT(1), 0);
 389         PRCC_PCLK_STORE(clk, 5, 1);
 390
 391         clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", clkrst6_base,
 392                                 BIT(0), 0);
 393         PRCC_PCLK_STORE(clk, 6, 0);
 394
 395         clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", clkrst6_base,
 396                                 BIT(1), 0);
 397         PRCC_PCLK_STORE(clk, 6, 1);
 398
 399         clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", clkrst6_base,
 400                                 BIT(2), 0);
 401         PRCC_PCLK_STORE(clk, 6, 2);
 402
 403         clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", clkrst6_base,
 404                                 BIT(3), 0);
 405         PRCC_PCLK_STORE(clk, 6, 3);
 406
 407         clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", clkrst6_base,
 408                                 BIT(4), 0);
 409         PRCC_PCLK_STORE(clk, 6, 4);
 410
 411         clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", clkrst6_base,
 412                                 BIT(5), 0);
 413         PRCC_PCLK_STORE(clk, 6, 5);
 414
 415         clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", clkrst6_base,
 416                                 BIT(6), 0);
 417         PRCC_PCLK_STORE(clk, 6, 6);
 418
 419         clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", clkrst6_base,
 420                                 BIT(7), 0);
 421         PRCC_PCLK_STORE(clk, 6, 7);
 422
 423         /* PRCC K-clocks
 424          *
 425          * FIXME: Some drivers requires PERPIH[n| to be automatically enabled
 426          * by enabling just the K-clock, even if it is not a valid parent to
 427          * the K-clock. Until drivers get fixed we might need some kind of
 428          * "parent muxed join".
 429          */
 430
 431         /* Periph1 */
 432         clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk",
 433                         clkrst1_base, BIT(0), CLK_SET_RATE_GATE);
 434         PRCC_KCLK_STORE(clk, 1, 0);
 435
 436         clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk",
 437                         clkrst1_base, BIT(1), CLK_SET_RATE_GATE);
 438         PRCC_KCLK_STORE(clk, 1, 1);
 439
 440         clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk",
 441                         clkrst1_base, BIT(2), CLK_SET_RATE_GATE);
 442         PRCC_KCLK_STORE(clk, 1, 2);
 443
 444         clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk",
 445                         clkrst1_base, BIT(3), CLK_SET_RATE_GATE);
 446         PRCC_KCLK_STORE(clk, 1, 3);
 447
 448         clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk",
 449                         clkrst1_base, BIT(4), CLK_SET_RATE_GATE);
 450         PRCC_KCLK_STORE(clk, 1, 4);
 451
 452         clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk",
 453                         clkrst1_base, BIT(5), CLK_SET_RATE_GATE);
 454         PRCC_KCLK_STORE(clk, 1, 5);
 455
 456         clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk",
 457                         clkrst1_base, BIT(6), CLK_SET_RATE_GATE);
 458         PRCC_KCLK_STORE(clk, 1, 6);
 459
 460         clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk",
 461                         clkrst1_base, BIT(8), CLK_SET_RATE_GATE);
 462         PRCC_KCLK_STORE(clk, 1, 8);
 463
 464         clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk",
 465                         clkrst1_base, BIT(9), CLK_SET_RATE_GATE);
 466         PRCC_KCLK_STORE(clk, 1, 9);
 467
 468         clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk",
 469                         clkrst1_base, BIT(10), CLK_SET_RATE_GATE);
 470         PRCC_KCLK_STORE(clk, 1, 10);
 471
 472         /* Periph2 */
 473         clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk",
 474                         clkrst2_base, BIT(0), CLK_SET_RATE_GATE);
 475         PRCC_KCLK_STORE(clk, 2, 0);
 476
 477         clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk",
 478                         clkrst2_base, BIT(2), CLK_SET_RATE_GATE);
 479         PRCC_KCLK_STORE(clk, 2, 2);
 480
 481         clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk",
 482                         clkrst2_base, BIT(3), CLK_SET_RATE_GATE);
 483         PRCC_KCLK_STORE(clk, 2, 3);
 484
 485         clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk",
 486                         clkrst2_base, BIT(4), CLK_SET_RATE_GATE);
 487         PRCC_KCLK_STORE(clk, 2, 4);
 488
 489         clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk",
 490                         clkrst2_base, BIT(5), CLK_SET_RATE_GATE);
 491         PRCC_KCLK_STORE(clk, 2, 5);
 492
 493         /* Note that rate is received from parent. */
 494         clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk",
 495                         clkrst2_base, BIT(6),
 496                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 497         PRCC_KCLK_STORE(clk, 2, 6);
 498
 499         clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk",
 500                         clkrst2_base, BIT(7),
 501                         CLK_SET_RATE_GATE|CLK_SET_RATE_PARENT);
 502         PRCC_KCLK_STORE(clk, 2, 7);
 503
 504         /* Periph3 */
 505         clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk",
 506                         clkrst3_base, BIT(1), CLK_SET_RATE_GATE);
 507         PRCC_KCLK_STORE(clk, 3, 1);
 508
 509         clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk",
 510                         clkrst3_base, BIT(2), CLK_SET_RATE_GATE);
 511         PRCC_KCLK_STORE(clk, 3, 2);
 512
 513         clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk",
 514                         clkrst3_base, BIT(3), CLK_SET_RATE_GATE);
 515         PRCC_KCLK_STORE(clk, 3, 3);
 516
 517         clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk",
 518                         clkrst3_base, BIT(4), CLK_SET_RATE_GATE);
 519         PRCC_KCLK_STORE(clk, 3, 4);
 520
 521         clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
 522                         clkrst3_base, BIT(5), CLK_SET_RATE_GATE);
 523         PRCC_KCLK_STORE(clk, 3, 5);
 524
 525         clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
 526                         clkrst3_base, BIT(6), CLK_SET_RATE_GATE);
 527         PRCC_KCLK_STORE(clk, 3, 6);
 528
 529         clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk",
 530                         clkrst3_base, BIT(7), CLK_SET_RATE_GATE);
 531         PRCC_KCLK_STORE(clk, 3, 7);
 532
 533         /* Periph6 */
 534         clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
 535                         clkrst6_base, BIT(0), CLK_SET_RATE_GATE);
 536         PRCC_KCLK_STORE(clk, 6, 0);
 537
 538         for_each_child_of_node(np, child) {
 539                 static struct clk_onecell_data clk_data;
 540
 541                 if (!of_node_cmp(child->name, "prcmu-clock")) {
 542                         clk_data.clks = prcmu_clk;
 543                         clk_data.clk_num = ARRAY_SIZE(prcmu_clk);
 544                         of_clk_add_provider(child, of_clk_src_onecell_get, &clk_data);
 545                 }
 546                 if (!of_node_cmp(child->name, "prcc-periph-clock"))
 547                         of_clk_add_provider(child, ux500_twocell_get, prcc_pclk);
 548
 549                 if (!of_node_cmp(child->name, "prcc-kernel-clock"))
 550                         of_clk_add_provider(child, ux500_twocell_get, prcc_kclk);
 551         }
 552 }