1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * Author: Andy Yan <andy.yan@rock-chips.com>
9 #include <clk-uclass.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/cru_rv1108.h>
18 #include <asm/arch-rockchip/hardware.h>
20 #include <dt-bindings/clock/rv1108-cru.h>
21 #include <linux/stringify.h>
23 DECLARE_GLOBAL_DATA_PTR;
26 VCO_MAX_HZ = 2400U * 1000000,
27 VCO_MIN_HZ = 600 * 1000000,
28 OUTPUT_MAX_HZ = 2400U * 1000000,
29 OUTPUT_MIN_HZ = 24 * 1000000,
32 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
34 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
36 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
37 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
38 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
39 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
40 #hz "Hz cannot be hit with PLL "\
41 "divisors on line " __stringify(__LINE__));
43 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
44 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
46 /* use integer mode */
47 static inline int rv1108_pll_id(enum rk_clk_id clk_id)
60 printf("invalid pll id:%d\n", clk_id);
68 static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id,
69 const struct pll_div *div)
71 int pll_id = rv1108_pll_id(clk_id);
72 struct rv1108_pll *pll = &cru->pll[pll_id];
74 /* All PLLs have same VCO and output frequency range restrictions. */
75 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
76 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
78 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
79 pll, div->fbdiv, div->refdiv, div->postdiv1,
80 div->postdiv2, vco_hz, output_hz);
81 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
82 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
85 * When power on or changing PLL setting,
86 * we must force PLL into slow mode to ensure output stable clock.
88 rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
89 WORK_MODE_SLOW << WORK_MODE_SHIFT);
91 /* use integer mode */
92 rk_setreg(&pll->con3, 1 << DSMPD_SHIFT);
94 rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
96 rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT);
97 rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK,
98 (div->postdiv1 << POSTDIV1_SHIFT |
99 div->postdiv2 << POSTDIV2_SHIFT |
100 div->refdiv << REFDIV_SHIFT));
101 rk_clrsetreg(&pll->con2, FRACDIV_MASK,
102 (div->refdiv << REFDIV_SHIFT));
105 rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
107 /* waiting for pll lock */
108 while (readl(&pll->con2) & (1 << LOCK_STA_SHIFT))
112 * set PLL into normal mode.
114 rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
115 WORK_MODE_NORMAL << WORK_MODE_SHIFT);
120 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
121 enum rk_clk_id clk_id)
123 uint32_t refdiv, fbdiv, postdiv1, postdiv2;
124 uint32_t con0, con1, con3;
125 int pll_id = rv1108_pll_id(clk_id);
126 struct rv1108_pll *pll = &cru->pll[pll_id];
129 con3 = readl(&pll->con3);
131 if (con3 & WORK_MODE_MASK) {
132 con0 = readl(&pll->con0);
133 con1 = readl(&pll->con1);
134 fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK;
135 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT;
136 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
137 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK;
138 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
146 static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate)
148 uint32_t con = readl(&cru->clksel_con[24]);
152 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL)
153 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
155 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM);
157 /*default set 50MHZ for gmac*/
161 div = DIV_ROUND_UP(pll_rate, rate) - 1;
163 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK,
164 div << MAC_CLK_DIV_SHIFT);
166 debug("Unsupported div for gmac:%d\n", div);
168 return DIV_TO_RATE(pll_rate, div);
171 static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)
173 u32 con = readl(&cru->clksel_con[27]);
177 if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL)
178 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
180 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR);
182 div = DIV_ROUND_UP(pll_rate, rate) - 1;
184 rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK,
185 div << SFC_CLK_DIV_SHIFT);
187 debug("Unsupported sfc clk rate:%d\n", rate);
189 return DIV_TO_RATE(pll_rate, div);
192 static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)
196 val = readl(&cru->clksel_con[22]);
197 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
198 CLK_SARADC_DIV_CON_WIDTH);
200 return DIV_TO_RATE(OSC_HZ, div);
203 static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
207 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
208 assert(src_clk_div < 128);
210 rk_clrsetreg(&cru->clksel_con[22],
211 CLK_SARADC_DIV_CON_MASK,
212 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
214 return rv1108_saradc_get_clk(cru);
217 static ulong rv1108_aclk_vio1_get_clk(struct rv1108_cru *cru)
221 val = readl(&cru->clksel_con[28]);
222 div = bitfield_extract(val, ACLK_VIO1_CLK_DIV_SHIFT,
223 CLK_VIO_DIV_CON_WIDTH);
225 return DIV_TO_RATE(GPLL_HZ, div);
228 static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz)
232 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
233 assert(src_clk_div < 32);
235 rk_clrsetreg(&cru->clksel_con[28],
236 ACLK_VIO1_CLK_DIV_MASK | ACLK_VIO1_PLL_SEL_MASK,
237 (src_clk_div << ACLK_VIO1_CLK_DIV_SHIFT) |
238 (VIO_PLL_SEL_GPLL << ACLK_VIO1_PLL_SEL_SHIFT));
240 return rv1108_aclk_vio1_get_clk(cru);
243 static ulong rv1108_aclk_vio0_get_clk(struct rv1108_cru *cru)
247 val = readl(&cru->clksel_con[28]);
248 div = bitfield_extract(val, ACLK_VIO0_CLK_DIV_SHIFT,
249 CLK_VIO_DIV_CON_WIDTH);
251 return DIV_TO_RATE(GPLL_HZ, div);
254 static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz)
258 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
259 assert(src_clk_div < 32);
261 rk_clrsetreg(&cru->clksel_con[28],
262 ACLK_VIO0_CLK_DIV_MASK | ACLK_VIO0_PLL_SEL_MASK,
263 (src_clk_div << ACLK_VIO0_CLK_DIV_SHIFT) |
264 (VIO_PLL_SEL_GPLL << ACLK_VIO0_PLL_SEL_SHIFT));
266 /*HCLK_VIO default div = 4*/
267 rk_clrsetreg(&cru->clksel_con[29],
268 HCLK_VIO_CLK_DIV_MASK,
269 3 << HCLK_VIO_CLK_DIV_SHIFT);
270 /*PCLK_VIO default div = 4*/
271 rk_clrsetreg(&cru->clksel_con[29],
272 PCLK_VIO_CLK_DIV_MASK,
273 3 << PCLK_VIO_CLK_DIV_SHIFT);
275 return rv1108_aclk_vio0_get_clk(cru);
278 static ulong rv1108_dclk_vop_get_clk(struct rv1108_cru *cru)
282 val = readl(&cru->clksel_con[32]);
283 div = bitfield_extract(val, DCLK_VOP_CLK_DIV_SHIFT,
284 DCLK_VOP_DIV_CON_WIDTH);
286 return DIV_TO_RATE(GPLL_HZ, div);
289 static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz)
293 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
294 assert(src_clk_div < 64);
296 rk_clrsetreg(&cru->clksel_con[32],
297 DCLK_VOP_CLK_DIV_MASK | DCLK_VOP_PLL_SEL_MASK |
299 (src_clk_div << DCLK_VOP_CLK_DIV_SHIFT) |
300 (DCLK_VOP_PLL_SEL_GPLL << DCLK_VOP_PLL_SEL_SHIFT) |
301 (DCLK_VOP_SEL_PLL << DCLK_VOP_SEL_SHIFT));
303 return rv1108_dclk_vop_get_clk(cru);
306 static ulong rv1108_aclk_bus_get_clk(struct rv1108_cru *cru)
309 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
311 val = readl(&cru->clksel_con[2]);
312 div = bitfield_extract(val, ACLK_BUS_DIV_CON_SHIFT,
313 ACLK_BUS_DIV_CON_WIDTH);
315 return DIV_TO_RATE(parent_rate, div);
318 static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz)
321 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
323 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
324 assert(src_clk_div < 32);
326 rk_clrsetreg(&cru->clksel_con[2],
327 ACLK_BUS_DIV_CON_MASK | ACLK_BUS_PLL_SEL_MASK,
328 (src_clk_div << ACLK_BUS_DIV_CON_SHIFT) |
329 (ACLK_BUS_PLL_SEL_GPLL << ACLK_BUS_PLL_SEL_SHIFT));
331 return rv1108_aclk_bus_get_clk(cru);
334 static ulong rv1108_aclk_peri_get_clk(struct rv1108_cru *cru)
337 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
339 val = readl(&cru->clksel_con[23]);
340 div = bitfield_extract(val, ACLK_PERI_DIV_CON_SHIFT,
343 return DIV_TO_RATE(parent_rate, div);
346 static ulong rv1108_hclk_peri_get_clk(struct rv1108_cru *cru)
349 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
351 val = readl(&cru->clksel_con[23]);
352 div = bitfield_extract(val, HCLK_PERI_DIV_CON_SHIFT,
355 return DIV_TO_RATE(parent_rate, div);
358 static ulong rv1108_pclk_peri_get_clk(struct rv1108_cru *cru)
361 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
363 val = readl(&cru->clksel_con[23]);
364 div = bitfield_extract(val, PCLK_PERI_DIV_CON_SHIFT,
367 return DIV_TO_RATE(parent_rate, div);
370 static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
373 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
375 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
376 assert(src_clk_div < 32);
378 rk_clrsetreg(&cru->clksel_con[23],
379 ACLK_PERI_DIV_CON_MASK | ACLK_PERI_PLL_SEL_MASK,
380 (src_clk_div << ACLK_PERI_DIV_CON_SHIFT) |
381 (ACLK_PERI_PLL_SEL_GPLL << ACLK_PERI_PLL_SEL_SHIFT));
383 return rv1108_aclk_peri_get_clk(cru);
386 static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
389 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
391 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
392 assert(src_clk_div < 32);
394 rk_clrsetreg(&cru->clksel_con[23],
395 HCLK_PERI_DIV_CON_MASK,
396 (src_clk_div << HCLK_PERI_DIV_CON_SHIFT));
398 return rv1108_hclk_peri_get_clk(cru);
401 static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
404 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
406 src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
407 assert(src_clk_div < 32);
409 rk_clrsetreg(&cru->clksel_con[23],
410 PCLK_PERI_DIV_CON_MASK,
411 (src_clk_div << PCLK_PERI_DIV_CON_SHIFT));
413 return rv1108_pclk_peri_get_clk(cru);
416 static ulong rv1108_i2c_get_clk(struct rv1108_cru *cru, ulong clk_id)
422 con = readl(&cru->clksel_con[19]);
423 div = bitfield_extract(con, CLK_I2C0_DIV_CON_SHIFT,
427 con = readl(&cru->clksel_con[19]);
428 div = bitfield_extract(con, CLK_I2C1_DIV_CON_SHIFT,
432 con = readl(&cru->clksel_con[20]);
433 div = bitfield_extract(con, CLK_I2C2_DIV_CON_SHIFT,
437 con = readl(&cru->clksel_con[20]);
438 div = bitfield_extract(con, CLK_I2C3_DIV_CON_SHIFT,
442 printf("do not support this i2c bus\n");
446 return DIV_TO_RATE(GPLL_HZ, div);
449 static ulong rv1108_i2c_set_clk(struct rv1108_cru *cru, ulong clk_id, uint hz)
453 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
454 src_clk_div = GPLL_HZ / hz;
455 assert(src_clk_div - 1 <= 127);
459 rk_clrsetreg(&cru->clksel_con[19],
460 CLK_I2C0_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK,
461 (src_clk_div << CLK_I2C0_DIV_CON_SHIFT) |
462 (CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT));
465 rk_clrsetreg(&cru->clksel_con[19],
466 CLK_I2C1_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK,
467 (src_clk_div << CLK_I2C1_DIV_CON_SHIFT) |
468 (CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT));
471 rk_clrsetreg(&cru->clksel_con[20],
472 CLK_I2C2_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK,
473 (src_clk_div << CLK_I2C2_DIV_CON_SHIFT) |
474 (CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT));
477 rk_clrsetreg(&cru->clksel_con[20],
478 CLK_I2C3_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK,
479 (src_clk_div << CLK_I2C3_DIV_CON_SHIFT) |
480 (CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT));
483 printf("do not support this i2c bus\n");
487 return rv1108_i2c_get_clk(cru, clk_id);
490 static ulong rv1108_mmc_get_clk(struct rv1108_cru *cru)
495 con = readl(&cru->clksel_con[26]);
496 div = bitfield_extract(con, EMMC_CLK_DIV_SHIFT, 8);
498 con = readl(&cru->clksel_con[25]);
500 if ((con & EMMC_PLL_SEL_MASK) >> EMMC_PLL_SEL_SHIFT == EMMC_PLL_SEL_OSC)
501 mmc_clk = DIV_TO_RATE(OSC_HZ, div) / 2;
503 mmc_clk = DIV_TO_RATE(GPLL_HZ, div) / 2;
505 debug("%s div %d get_clk %ld\n", __func__, div, mmc_clk);
509 static ulong rv1108_mmc_set_clk(struct rv1108_cru *cru, ulong rate)
514 div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate);
517 debug("%s source gpll\n", __func__);
518 rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,
519 (EMMC_PLL_SEL_GPLL << EMMC_PLL_SEL_SHIFT));
520 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
522 debug("%s source 24m\n", __func__);
523 rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,
524 (EMMC_PLL_SEL_OSC << EMMC_PLL_SEL_SHIFT));
528 div = DIV_ROUND_UP(pll_rate / 2, rate);
529 rk_clrsetreg(&cru->clksel_con[26], EMMC_CLK_DIV_MASK,
530 ((div - 1) << EMMC_CLK_DIV_SHIFT));
532 debug("%s set_rate %ld div %d\n", __func__, rate, div);
534 return DIV_TO_RATE(pll_rate, div);
537 static ulong rv1108_clk_get_rate(struct clk *clk)
539 struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
543 return rkclk_pll_get_rate(priv->cru, clk->id);
545 return rv1108_saradc_get_clk(priv->cru);
547 return rv1108_aclk_vio0_get_clk(priv->cru);
549 return rv1108_aclk_vio1_get_clk(priv->cru);
551 return rv1108_dclk_vop_get_clk(priv->cru);
553 return rv1108_aclk_bus_get_clk(priv->cru);
555 return rv1108_aclk_peri_get_clk(priv->cru);
557 return rv1108_hclk_peri_get_clk(priv->cru);
559 return rv1108_pclk_peri_get_clk(priv->cru);
564 return rv1108_i2c_get_clk(priv->cru, clk->id);
567 case SCLK_EMMC_SAMPLE:
568 return rv1108_mmc_get_clk(priv->cru);
574 static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
576 struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
581 new_rate = rv1108_mac_set_clk(priv->cru, rate);
584 new_rate = rv1108_sfc_set_clk(priv->cru, rate);
587 new_rate = rv1108_saradc_set_clk(priv->cru, rate);
590 new_rate = rv1108_aclk_vio0_set_clk(priv->cru, rate);
593 new_rate = rv1108_aclk_vio1_set_clk(priv->cru, rate);
596 new_rate = rv1108_dclk_vop_set_clk(priv->cru, rate);
599 new_rate = rv1108_aclk_bus_set_clk(priv->cru, rate);
602 new_rate = rv1108_aclk_peri_set_clk(priv->cru, rate);
605 new_rate = rv1108_hclk_peri_set_clk(priv->cru, rate);
608 new_rate = rv1108_pclk_peri_set_clk(priv->cru, rate);
614 new_rate = rv1108_i2c_set_clk(priv->cru, clk->id, rate);
618 new_rate = rv1108_mmc_set_clk(priv->cru, rate);
627 static const struct clk_ops rv1108_clk_ops = {
628 .get_rate = rv1108_clk_get_rate,
629 .set_rate = rv1108_clk_set_rate,
632 static void rkclk_init(struct rv1108_cru *cru)
634 unsigned int apll, dpll, gpll;
635 unsigned int aclk_bus, aclk_peri, hclk_peri, pclk_peri;
637 aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ / 2);
638 aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ / 2);
639 hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ / 2);
640 pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ / 2);
641 rv1108_aclk_vio0_set_clk(cru, 297000000);
642 rv1108_aclk_vio1_set_clk(cru, 297000000);
645 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
646 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
647 aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ);
648 aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ);
649 hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ);
650 pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ);
652 apll = rkclk_pll_get_rate(cru, CLK_ARM);
653 dpll = rkclk_pll_get_rate(cru, CLK_DDR);
654 gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
656 rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,
657 0 << MAC_CLK_DIV_SHIFT);
659 printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
660 printf("ACLK_BUS: %d ACLK_PERI:%d HCLK_PERI:%d PCLK_PERI:%d\n",
661 aclk_bus, aclk_peri, hclk_peri, pclk_peri);
664 static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
666 struct rv1108_clk_priv *priv = dev_get_priv(dev);
668 priv->cru = dev_read_addr_ptr(dev);
673 static int rv1108_clk_probe(struct udevice *dev)
675 struct rv1108_clk_priv *priv = dev_get_priv(dev);
677 rkclk_init(priv->cru);
682 static int rv1108_clk_bind(struct udevice *dev)
685 struct udevice *sys_child;
686 struct sysreset_reg *priv;
688 /* The reset driver does not have a device node, so bind it here */
689 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
692 debug("Warning: No sysreset driver: ret=%d\n", ret);
694 priv = malloc(sizeof(struct sysreset_reg));
695 priv->glb_srst_fst_value = offsetof(struct rv1108_cru,
697 priv->glb_srst_snd_value = offsetof(struct rv1108_cru,
699 sys_child->priv = priv;
702 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
703 ret = offsetof(struct rv1108_cru, softrst_con[0]);
704 ret = rockchip_reset_bind(dev, ret, 13);
706 debug("Warning: software reset driver bind faile\n");
712 static const struct udevice_id rv1108_clk_ids[] = {
713 { .compatible = "rockchip,rv1108-cru" },
717 U_BOOT_DRIVER(clk_rv1108) = {
718 .name = "clk_rv1108",
720 .of_match = rv1108_clk_ids,
721 .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
722 .ops = &rv1108_clk_ops,
723 .bind = rv1108_clk_bind,
724 .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
725 .probe = rv1108_clk_probe,