drivers/char/drm/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drm.h"
  33 #include "i915_drv.h"
  34
  35 #include "drm_pciids.h"
  36
  37 static struct pci_device_id pciidlist[] = {
  38         i915_PCI_IDS
  39 };
  40
  41 enum pipe {
  42     PIPE_A = 0,
  43     PIPE_B,
  44 };
  45
  46 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
  47 {
  48         struct drm_i915_private *dev_priv = dev->dev_private;
  49
  50         if (pipe == PIPE_A)
  51                 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
  52         else
  53                 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
  54 }
  55
  56 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
  57 {
  58         struct drm_i915_private *dev_priv = dev->dev_private;
  59         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  60         u32 *array;
  61         int i;
  62
  63         if (!i915_pipe_enabled(dev, pipe))
  64                 return;
  65
  66         if (pipe == PIPE_A)
  67                 array = dev_priv->save_palette_a;
  68         else
  69                 array = dev_priv->save_palette_b;
  70
  71         for(i = 0; i < 256; i++)
  72                 array[i] = I915_READ(reg + (i << 2));
  73 }
  74
  75 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
  76 {
  77         struct drm_i915_private *dev_priv = dev->dev_private;
  78         unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
  79         u32 *array;
  80         int i;
  81
  82         if (!i915_pipe_enabled(dev, pipe))
  83                 return;
  84
  85         if (pipe == PIPE_A)
  86                 array = dev_priv->save_palette_a;
  87         else
  88                 array = dev_priv->save_palette_b;
  89
  90         for(i = 0; i < 256; i++)
  91                 I915_WRITE(reg + (i << 2), array[i]);
  92 }
  93
  94 static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
  95 {
  96         outb(reg, index_port);
  97         return inb(data_port);
  98 }
  99
 100 static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
 101 {
 102         inb(st01);
 103         outb(palette_enable | reg, VGA_AR_INDEX);
 104         return inb(VGA_AR_DATA_READ);
 105 }
 106
 107 static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
 108 {
 109         inb(st01);
 110         outb(palette_enable | reg, VGA_AR_INDEX);
 111         outb(val, VGA_AR_DATA_WRITE);
 112 }
 113
 114 static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
 115 {
 116         outb(reg, index_port);
 117         outb(val, data_port);
 118 }
 119
 120 static void i915_save_vga(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123         int i;
 124         u16 cr_index, cr_data, st01;
 125
 126         /* VGA color palette registers */
 127         dev_priv->saveDACMASK = inb(VGA_DACMASK);
 128         /* DACCRX automatically increments during read */
 129         outb(0, VGA_DACRX);
 130         /* Read 3 bytes of color data from each index */
 131         for (i = 0; i < 256 * 3; i++)
 132                 dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
 133
 134         /* MSR bits */
 135         dev_priv->saveMSR = inb(VGA_MSR_READ);
 136         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 137                 cr_index = VGA_CR_INDEX_CGA;
 138                 cr_data = VGA_CR_DATA_CGA;
 139                 st01 = VGA_ST01_CGA;
 140         } else {
 141                 cr_index = VGA_CR_INDEX_MDA;
 142                 cr_data = VGA_CR_DATA_MDA;
 143                 st01 = VGA_ST01_MDA;
 144         }
 145
 146         /* CRT controller regs */
 147         i915_write_indexed(cr_index, cr_data, 0x11,
 148                            i915_read_indexed(cr_index, cr_data, 0x11) &
 149                            (~0x80));
 150         for (i = 0; i < 0x24; i++)
 151                 dev_priv->saveCR[i] =
 152                         i915_read_indexed(cr_index, cr_data, i);
 153         /* Make sure we don't turn off CR group 0 writes */
 154         dev_priv->saveCR[0x11] &= ~0x80;
 155
 156         /* Attribute controller registers */
 157         inb(st01);
 158         dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
 159         for (i = 0; i < 20; i++)
 160                 dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
 161         inb(st01);
 162         outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
 163         inb(st01);
 164
 165         /* Graphics controller registers */
 166         for (i = 0; i < 9; i++)
 167                 dev_priv->saveGR[i] =
 168                         i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
 169
 170         dev_priv->saveGR[0x10] =
 171                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
 172         dev_priv->saveGR[0x11] =
 173                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
 174         dev_priv->saveGR[0x18] =
 175                 i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
 176
 177         /* Sequencer registers */
 178         for (i = 0; i < 8; i++)
 179                 dev_priv->saveSR[i] =
 180                         i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
 181 }
 182
 183 static void i915_restore_vga(struct drm_device *dev)
 184 {
 185         struct drm_i915_private *dev_priv = dev->dev_private;
 186         int i;
 187         u16 cr_index, cr_data, st01;
 188
 189         /* MSR bits */
 190         outb(dev_priv->saveMSR, VGA_MSR_WRITE);
 191         if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
 192                 cr_index = VGA_CR_INDEX_CGA;
 193                 cr_data = VGA_CR_DATA_CGA;
 194                 st01 = VGA_ST01_CGA;
 195         } else {
 196                 cr_index = VGA_CR_INDEX_MDA;
 197                 cr_data = VGA_CR_DATA_MDA;
 198                 st01 = VGA_ST01_MDA;
 199         }
 200
 201         /* Sequencer registers, don't write SR07 */
 202         for (i = 0; i < 7; i++)
 203                 i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
 204                                    dev_priv->saveSR[i]);
 205
 206         /* CRT controller regs */
 207         /* Enable CR group 0 writes */
 208         i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
 209         for (i = 0; i < 0x24; i++)
 210                 i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
 211
 212         /* Graphics controller regs */
 213         for (i = 0; i < 9; i++)
 214                 i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
 215                                    dev_priv->saveGR[i]);
 216
 217         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
 218                            dev_priv->saveGR[0x10]);
 219         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
 220                            dev_priv->saveGR[0x11]);
 221         i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
 222                            dev_priv->saveGR[0x18]);
 223
 224         /* Attribute controller registers */
 225         for (i = 0; i < 20; i++)
 226                 i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
 227         inb(st01); /* switch back to index mode */
 228         outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
 229         inb(st01);
 230
 231         /* VGA color palette registers */
 232         outb(dev_priv->saveDACMASK, VGA_DACMASK);
 233         /* DACCRX automatically increments during read */
 234         outb(0, VGA_DACWX);
 235         /* Read 3 bytes of color data from each index */
 236         for (i = 0; i < 256 * 3; i++)
 237                 outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
 238
 239 }
 240
 241 static int i915_suspend(struct drm_device *dev, pm_message_t state)
 242 {
 243         struct drm_i915_private *dev_priv = dev->dev_private;
 244         int i;
 245
 246         if (!dev || !dev_priv) {
 247                 printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
 248                 printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
 249                 return -ENODEV;
 250         }
 251
 252         if (state.event == PM_EVENT_PRETHAW)
 253                 return 0;
 254
 255         pci_save_state(dev->pdev);
 256         pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
 257
 258         /* Pipe & plane A info */
 259         dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
 260         dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
 261         dev_priv->saveFPA0 = I915_READ(FPA0);
 262         dev_priv->saveFPA1 = I915_READ(FPA1);
 263         dev_priv->saveDPLL_A = I915_READ(DPLL_A);
 264         if (IS_I965G(dev))
 265                 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
 266         dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
 267         dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
 268         dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
 269         dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
 270         dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
 271         dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
 272         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 273
 274         dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
 275         dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
 276         dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
 277         dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
 278         dev_priv->saveDSPABASE = I915_READ(DSPABASE);
 279         if (IS_I965G(dev)) {
 280                 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
 281                 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
 282         }
 283         i915_save_palette(dev, PIPE_A);
 284         dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
 285
 286         /* Pipe & plane B info */
 287         dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
 288         dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
 289         dev_priv->saveFPB0 = I915_READ(FPB0);
 290         dev_priv->saveFPB1 = I915_READ(FPB1);
 291         dev_priv->saveDPLL_B = I915_READ(DPLL_B);
 292         if (IS_I965G(dev))
 293                 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
 294         dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
 295         dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
 296         dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
 297         dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
 298         dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
 299         dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
 300         dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
 301
 302         dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
 303         dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
 304         dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
 305         dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
 306         dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
 307         if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
 308                 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
 309                 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
 310         }
 311         i915_save_palette(dev, PIPE_B);
 312         dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
 313
 314         /* CRT state */
 315         dev_priv->saveADPA = I915_READ(ADPA);
 316
 317         /* LVDS state */
 318         dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
 319         dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
 320         dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
 321         if (IS_I965G(dev))
 322                 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
 323         if (IS_MOBILE(dev) && !IS_I830(dev))
 324                 dev_priv->saveLVDS = I915_READ(LVDS);
 325         if (!IS_I830(dev) && !IS_845G(dev))
 326                 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
 327         dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
 328         dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
 329         dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
 330
 331         /* FIXME: save TV & SDVO state */
 332
 333         /* FBC state */
 334         dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
 335         dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
 336         dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
 337         dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
 338
 339         /* Interrupt state */
 340         dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
 341         dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
 342         dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
 343
 344         /* VGA state */
 345         dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
 346         dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
 347         dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
 348         dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
 349
 350         /* Clock gating state */
 351         dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
 352
 353         /* Cache mode state */
 354         dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
 355
 356         /* Memory Arbitration state */
 357         dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
 358
 359         /* Scratch space */
 360         for (i = 0; i < 16; i++) {
 361                 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
 362                 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
 363         }
 364         for (i = 0; i < 3; i++)
 365                 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
 366
 367         i915_save_vga(dev);
 368
 369         if (state.event == PM_EVENT_SUSPEND) {
 370                 /* Shut down the device */
 371                 pci_disable_device(dev->pdev);
 372                 pci_set_power_state(dev->pdev, PCI_D3hot);
 373         }
 374
 375         return 0;
 376 }
 377
 378 static int i915_resume(struct drm_device *dev)
 379 {
 380         struct drm_i915_private *dev_priv = dev->dev_private;
 381         int i;
 382
 383         pci_set_power_state(dev->pdev, PCI_D0);
 384         pci_restore_state(dev->pdev);
 385         if (pci_enable_device(dev->pdev))
 386                 return -1;
 387
 388         pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
 389
 390         /* Pipe & plane A info */
 391         /* Prime the clock */
 392         if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
 393                 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
 394                            ~DPLL_VCO_ENABLE);
 395                 udelay(150);
 396         }
 397         I915_WRITE(FPA0, dev_priv->saveFPA0);
 398         I915_WRITE(FPA1, dev_priv->saveFPA1);
 399         /* Actually enable it */
 400         I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
 401         udelay(150);
 402         if (IS_I965G(dev))
 403                 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
 404         udelay(150);
 405
 406         /* Restore mode */
 407         I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
 408         I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
 409         I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
 410         I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
 411         I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
 412         I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
 413         I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
 414
 415         /* Restore plane info */
 416         I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
 417         I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
 418         I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
 419         I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
 420         I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
 421         if (IS_I965G(dev)) {
 422                 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
 423                 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
 424         }
 425
 426         I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
 427
 428         i915_restore_palette(dev, PIPE_A);
 429         /* Enable the plane */
 430         I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
 431         I915_WRITE(DSPABASE, I915_READ(DSPABASE));
 432
 433         /* Pipe & plane B info */
 434         if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
 435                 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
 436                            ~DPLL_VCO_ENABLE);
 437                 udelay(150);
 438         }
 439         I915_WRITE(FPB0, dev_priv->saveFPB0);
 440         I915_WRITE(FPB1, dev_priv->saveFPB1);
 441         /* Actually enable it */
 442         I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
 443         udelay(150);
 444         if (IS_I965G(dev))
 445                 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
 446         udelay(150);
 447
 448         /* Restore mode */
 449         I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
 450         I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
 451         I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
 452         I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
 453         I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
 454         I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
 455         I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
 456
 457         /* Restore plane info */
 458         I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
 459         I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
 460         I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
 461         I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
 462         I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
 463         if (IS_I965G(dev)) {
 464                 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
 465                 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
 466         }
 467
 468         I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
 469
 470         i915_restore_palette(dev, PIPE_B);
 471         /* Enable the plane */
 472         I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
 473         I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
 474
 475         /* CRT state */
 476         I915_WRITE(ADPA, dev_priv->saveADPA);
 477
 478         /* LVDS state */
 479         if (IS_I965G(dev))
 480                 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
 481         if (IS_MOBILE(dev) && !IS_I830(dev))
 482                 I915_WRITE(LVDS, dev_priv->saveLVDS);
 483         if (!IS_I830(dev) && !IS_845G(dev))
 484                 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
 485
 486         I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
 487         I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
 488         I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
 489         I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
 490         I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
 491         I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
 492
 493         /* FIXME: restore TV & SDVO state */
 494
 495         /* FBC info */
 496         I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
 497         I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
 498         I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
 499         I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
 500
 501         /* VGA state */
 502         I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
 503         I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
 504         I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
 505         I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
 506         udelay(150);
 507
 508         /* Clock gating state */
 509         I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
 510
 511         /* Cache mode state */
 512         I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
 513
 514         /* Memory arbitration state */
 515         I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
 516
 517         for (i = 0; i < 16; i++) {
 518                 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
 519                 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
 520         }
 521         for (i = 0; i < 3; i++)
 522                 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
 523
 524         i915_restore_vga(dev);
 525
 526         return 0;
 527 }
 528
 529 static struct drm_driver driver = {
 530         /* don't use mtrr's here, the Xserver or user space app should
 531          * deal with them for intel hardware.
 532          */
 533         .driver_features =
 534             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 535             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
 536             DRIVER_IRQ_VBL2,
 537         .load = i915_driver_load,
 538         .unload = i915_driver_unload,
 539         .lastclose = i915_driver_lastclose,
 540         .preclose = i915_driver_preclose,
 541         .suspend = i915_suspend,
 542         .resume = i915_resume,
 543         .device_is_agp = i915_driver_device_is_agp,
 544         .vblank_wait = i915_driver_vblank_wait,
 545         .vblank_wait2 = i915_driver_vblank_wait2,
 546         .irq_preinstall = i915_driver_irq_preinstall,
 547         .irq_postinstall = i915_driver_irq_postinstall,
 548         .irq_uninstall = i915_driver_irq_uninstall,
 549         .irq_handler = i915_driver_irq_handler,
 550         .reclaim_buffers = drm_core_reclaim_buffers,
 551         .get_map_ofs = drm_core_get_map_ofs,
 552         .get_reg_ofs = drm_core_get_reg_ofs,
 553         .ioctls = i915_ioctls,
 554         .fops = {
 555                  .owner = THIS_MODULE,
 556                  .open = drm_open,
 557                  .release = drm_release,
 558                  .ioctl = drm_ioctl,
 559                  .mmap = drm_mmap,
 560                  .poll = drm_poll,
 561                  .fasync = drm_fasync,
 562 #ifdef CONFIG_COMPAT
 563                  .compat_ioctl = i915_compat_ioctl,
 564 #endif
 565         },
 566
 567         .pci_driver = {
 568                  .name = DRIVER_NAME,
 569                  .id_table = pciidlist,
 570         },
 571
 572         .name = DRIVER_NAME,
 573         .desc = DRIVER_DESC,
 574         .date = DRIVER_DATE,
 575         .major = DRIVER_MAJOR,
 576         .minor = DRIVER_MINOR,
 577         .patchlevel = DRIVER_PATCHLEVEL,
 578 };
 579
 580 static int __init i915_init(void)
 581 {
 582         driver.num_ioctls = i915_max_ioctl;
 583         return drm_init(&driver);
 584 }
 585
 586 static void __exit i915_exit(void)
 587 {
 588         drm_exit(&driver);
 589 }
 590
 591 module_init(i915_init);
 592 module_exit(i915_exit);
 593
 594 MODULE_AUTHOR(DRIVER_AUTHOR);
 595 MODULE_DESCRIPTION(DRIVER_DESC);
 596 MODULE_LICENSE("GPL and additional rights");