drivers/char/agp/intel-gtt.c

   1 /*
   2  * Intel GTT (Graphics Translation Table) routines
   3  *
   4  * Caveat: This driver implements the linux agp interface, but this is far from
   5  * a agp driver! GTT support ended up here for purely historical reasons: The
   6  * old userspace intel graphics drivers needed an interface to map memory into
   7  * the GTT. And the drm provides a default interface for graphic devices sitting
   8  * on an agp port. So it made sense to fake the GTT support as an agp port to
   9  * avoid having to create a new api.
  10  *
  11  * With gem this does not make much sense anymore, just needlessly complicates
  12  * the code. But as long as the old graphics stack is still support, it's stuck
  13  * here.
  14  *
  15  * /fairy-tale-mode off
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/pci.h>
  20 #include <linux/init.h>
  21 #include <linux/kernel.h>
  22 #include <linux/pagemap.h>
  23 #include <linux/agp_backend.h>
  24 #include <asm/smp.h>
  25 #include "agp.h"
  26 #include "intel-agp.h"
  27 #include <linux/intel-gtt.h>
  28 #include <drm/intel-gtt.h>
  29
  30 /*
  31  * If we have Intel graphics, we're not going to have anything other than
  32  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  33  * on the Intel IOMMU support (CONFIG_DMAR).
  34  * Only newer chipsets need to bother with this, of course.
  35  */
  36 #ifdef CONFIG_DMAR
  37 #define USE_PCI_DMA_API 1
  38 #else
  39 #define USE_PCI_DMA_API 0
  40 #endif
  41
  42 #define AGP_DCACHE_MEMORY       1
  43 #define AGP_PHYS_MEMORY         2
  44 #define INTEL_AGP_CACHED_MEMORY 3
  45
  46 struct intel_gtt_driver {
  47         unsigned int gen : 8;
  48         unsigned int is_g33 : 1;
  49         unsigned int is_pineview : 1;
  50         unsigned int is_ironlake : 1;
  51         unsigned int has_pgtbl_enable : 1;
  52         unsigned int dma_mask_size : 8;
  53         /* Chipset specific GTT setup */
  54         int (*setup)(void);
  55         /* This should undo anything done in ->setup() save the unmapping
  56          * of the mmio register file, that's done in the generic code. */
  57         void (*cleanup)(void);
  58         void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags);
  59         /* Flags is a more or less chipset specific opaque value.
  60          * For chipsets that need to support old ums (non-gem) code, this
  61          * needs to be identical to the various supported agp memory types! */
  62         bool (*check_flags)(unsigned int flags);
  63         void (*chipset_flush)(void);
  64 };
  65
  66 static struct _intel_private {
  67         struct intel_gtt base;
  68         const struct intel_gtt_driver *driver;
  69         struct pci_dev *pcidev; /* device one */
  70         struct pci_dev *bridge_dev;
  71         u8 __iomem *registers;
  72         phys_addr_t gtt_bus_addr;
  73         phys_addr_t gma_bus_addr;
  74         u32 PGETBL_save;
  75         u32 __iomem *gtt;               /* I915G */
  76         int num_dcache_entries;
  77         union {
  78                 void __iomem *i9xx_flush_page;
  79                 void *i8xx_flush_page;
  80         };
  81         char *i81x_gtt_table;
  82         struct page *i8xx_page;
  83         struct resource ifp_resource;
  84         int resource_valid;
  85         struct page *scratch_page;
  86         dma_addr_t scratch_page_dma;
  87 } intel_private;
  88
  89 #define INTEL_GTT_GEN   intel_private.driver->gen
  90 #define IS_G33          intel_private.driver->is_g33
  91 #define IS_PINEVIEW     intel_private.driver->is_pineview
  92 #define IS_IRONLAKE     intel_private.driver->is_ironlake
  93 #define HAS_PGTBL_EN    intel_private.driver->has_pgtbl_enable
  94
  95 static void intel_agp_free_sglist(struct agp_memory *mem)
  96 {
  97         struct sg_table st;
  98
  99         st.sgl = mem->sg_list;
 100         st.orig_nents = st.nents = mem->page_count;
 101
 102         sg_free_table(&st);
 103
 104         mem->sg_list = NULL;
 105         mem->num_sg = 0;
 106 }
 107
 108 static int intel_agp_map_memory(struct agp_memory *mem)
 109 {
 110         struct sg_table st;
 111         struct scatterlist *sg;
 112         int i;
 113
 114         if (mem->sg_list)
 115                 return 0; /* already mapped (for e.g. resume */
 116
 117         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 118
 119         if (sg_alloc_table(&st, mem->page_count, GFP_KERNEL))
 120                 goto err;
 121
 122         mem->sg_list = sg = st.sgl;
 123
 124         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 125                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 126
 127         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 128                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 129         if (unlikely(!mem->num_sg))
 130                 goto err;
 131
 132         return 0;
 133
 134 err:
 135         sg_free_table(&st);
 136         return -ENOMEM;
 137 }
 138
 139 static void intel_agp_unmap_memory(struct agp_memory *mem)
 140 {
 141         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 142
 143         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 144                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 145         intel_agp_free_sglist(mem);
 146 }
 147
 148 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 149 {
 150         return;
 151 }
 152
 153 /* Exists to support ARGB cursors */
 154 static struct page *i8xx_alloc_pages(void)
 155 {
 156         struct page *page;
 157
 158         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 159         if (page == NULL)
 160                 return NULL;
 161
 162         if (set_pages_uc(page, 4) < 0) {
 163                 set_pages_wb(page, 4);
 164                 __free_pages(page, 2);
 165                 return NULL;
 166         }
 167         get_page(page);
 168         atomic_inc(&agp_bridge->current_memory_agp);
 169         return page;
 170 }
 171
 172 static void i8xx_destroy_pages(struct page *page)
 173 {
 174         if (page == NULL)
 175                 return;
 176
 177         set_pages_wb(page, 4);
 178         put_page(page);
 179         __free_pages(page, 2);
 180         atomic_dec(&agp_bridge->current_memory_agp);
 181 }
 182
 183 #define I810_GTT_ORDER 4
 184 static int i810_setup(void)
 185 {
 186         u32 reg_addr;
 187         char *gtt_table;
 188
 189         /* i81x does not preallocate the gtt. It's always 64kb in size. */
 190         gtt_table = alloc_gatt_pages(I810_GTT_ORDER);
 191         if (gtt_table == NULL)
 192                 return -ENOMEM;
 193         intel_private.i81x_gtt_table = gtt_table;
 194
 195         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 196         reg_addr &= 0xfff80000;
 197
 198         intel_private.registers = ioremap(reg_addr, KB(64));
 199         if (!intel_private.registers)
 200                 return -ENOMEM;
 201
 202         writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED,
 203                intel_private.registers+I810_PGETBL_CTL);
 204
 205         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 206
 207         if ((readl(intel_private.registers+I810_DRAM_CTL)
 208                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 209                 dev_info(&intel_private.pcidev->dev,
 210                          "detected 4MB dedicated video ram\n");
 211                 intel_private.num_dcache_entries = 1024;
 212         }
 213
 214         return 0;
 215 }
 216
 217 static void i810_cleanup(void)
 218 {
 219         writel(0, intel_private.registers+I810_PGETBL_CTL);
 220         free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
 221 }
 222
 223 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
 224                                       int type)
 225 {
 226         int i;
 227
 228         if ((pg_start + mem->page_count)
 229                         > intel_private.num_dcache_entries)
 230                 return -EINVAL;
 231
 232         if (!mem->is_flushed)
 233                 global_cache_flush();
 234
 235         for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 236                 dma_addr_t addr = i << PAGE_SHIFT;
 237                 intel_private.driver->write_entry(addr,
 238                                                   i, type);
 239         }
 240         readl(intel_private.gtt+i-1);
 241
 242         return 0;
 243 }
 244
 245 /*
 246  * The i810/i830 requires a physical address to program its mouse
 247  * pointer into hardware.
 248  * However the Xserver still writes to it through the agp aperture.
 249  */
 250 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 251 {
 252         struct agp_memory *new;
 253         struct page *page;
 254
 255         switch (pg_count) {
 256         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 257                 break;
 258         case 4:
 259                 /* kludge to get 4 physical pages for ARGB cursor */
 260                 page = i8xx_alloc_pages();
 261                 break;
 262         default:
 263                 return NULL;
 264         }
 265
 266         if (page == NULL)
 267                 return NULL;
 268
 269         new = agp_create_memory(pg_count);
 270         if (new == NULL)
 271                 return NULL;
 272
 273         new->pages[0] = page;
 274         if (pg_count == 4) {
 275                 /* kludge to get 4 physical pages for ARGB cursor */
 276                 new->pages[1] = new->pages[0] + 1;
 277                 new->pages[2] = new->pages[1] + 1;
 278                 new->pages[3] = new->pages[2] + 1;
 279         }
 280         new->page_count = pg_count;
 281         new->num_scratch_pages = pg_count;
 282         new->type = AGP_PHYS_MEMORY;
 283         new->physical = page_to_phys(new->pages[0]);
 284         return new;
 285 }
 286
 287 static void intel_i810_free_by_type(struct agp_memory *curr)
 288 {
 289         agp_free_key(curr->key);
 290         if (curr->type == AGP_PHYS_MEMORY) {
 291                 if (curr->page_count == 4)
 292                         i8xx_destroy_pages(curr->pages[0]);
 293                 else {
 294                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 295                                                              AGP_PAGE_DESTROY_UNMAP);
 296                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 297                                                              AGP_PAGE_DESTROY_FREE);
 298                 }
 299                 agp_free_page_array(curr);
 300         }
 301         kfree(curr);
 302 }
 303
 304 static int intel_gtt_setup_scratch_page(void)
 305 {
 306         struct page *page;
 307         dma_addr_t dma_addr;
 308
 309         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
 310         if (page == NULL)
 311                 return -ENOMEM;
 312         get_page(page);
 313         set_pages_uc(page, 1);
 314
 315         if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
 316                 dma_addr = pci_map_page(intel_private.pcidev, page, 0,
 317                                     PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 318                 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr))
 319                         return -EINVAL;
 320
 321                 intel_private.scratch_page_dma = dma_addr;
 322         } else
 323                 intel_private.scratch_page_dma = page_to_phys(page);
 324
 325         intel_private.scratch_page = page;
 326
 327         return 0;
 328 }
 329
 330 static void i810_write_entry(dma_addr_t addr, unsigned int entry,
 331                              unsigned int flags)
 332 {
 333         u32 pte_flags = I810_PTE_VALID;
 334
 335         switch (flags) {
 336         case AGP_DCACHE_MEMORY:
 337                 pte_flags |= I810_PTE_LOCAL;
 338                 break;
 339         case AGP_USER_CACHED_MEMORY:
 340                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 341                 break;
 342         }
 343
 344         writel(addr | pte_flags, intel_private.gtt + entry);
 345 }
 346
 347 static const struct aper_size_info_fixed const intel_fake_agp_sizes[] = {
 348         {32, 8192, 3},
 349         {64, 16384, 4},
 350         {128, 32768, 5},
 351         {256, 65536, 6},
 352         {512, 131072, 7},
 353 };
 354
 355 static unsigned int intel_gtt_stolen_size(void)
 356 {
 357         u16 gmch_ctrl;
 358         u8 rdct;
 359         int local = 0;
 360         static const int ddt[4] = { 0, 16, 32, 64 };
 361         unsigned int stolen_size = 0;
 362
 363         if (INTEL_GTT_GEN == 1)
 364                 return 0; /* no stolen mem on i81x */
 365
 366         pci_read_config_word(intel_private.bridge_dev,
 367                              I830_GMCH_CTRL, &gmch_ctrl);
 368
 369         if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 370             intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 371                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 372                 case I830_GMCH_GMS_STOLEN_512:
 373                         stolen_size = KB(512);
 374                         break;
 375                 case I830_GMCH_GMS_STOLEN_1024:
 376                         stolen_size = MB(1);
 377                         break;
 378                 case I830_GMCH_GMS_STOLEN_8192:
 379                         stolen_size = MB(8);
 380                         break;
 381                 case I830_GMCH_GMS_LOCAL:
 382                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 383                         stolen_size = (I830_RDRAM_ND(rdct) + 1) *
 384                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 385                         local = 1;
 386                         break;
 387                 default:
 388                         stolen_size = 0;
 389                         break;
 390                 }
 391         } else if (INTEL_GTT_GEN == 6) {
 392                 /*
 393                  * SandyBridge has new memory control reg at 0x50.w
 394                  */
 395                 u16 snb_gmch_ctl;
 396                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 397                 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) {
 398                 case SNB_GMCH_GMS_STOLEN_32M:
 399                         stolen_size = MB(32);
 400                         break;
 401                 case SNB_GMCH_GMS_STOLEN_64M:
 402                         stolen_size = MB(64);
 403                         break;
 404                 case SNB_GMCH_GMS_STOLEN_96M:
 405                         stolen_size = MB(96);
 406                         break;
 407                 case SNB_GMCH_GMS_STOLEN_128M:
 408                         stolen_size = MB(128);
 409                         break;
 410                 case SNB_GMCH_GMS_STOLEN_160M:
 411                         stolen_size = MB(160);
 412                         break;
 413                 case SNB_GMCH_GMS_STOLEN_192M:
 414                         stolen_size = MB(192);
 415                         break;
 416                 case SNB_GMCH_GMS_STOLEN_224M:
 417                         stolen_size = MB(224);
 418                         break;
 419                 case SNB_GMCH_GMS_STOLEN_256M:
 420                         stolen_size = MB(256);
 421                         break;
 422                 case SNB_GMCH_GMS_STOLEN_288M:
 423                         stolen_size = MB(288);
 424                         break;
 425                 case SNB_GMCH_GMS_STOLEN_320M:
 426                         stolen_size = MB(320);
 427                         break;
 428                 case SNB_GMCH_GMS_STOLEN_352M:
 429                         stolen_size = MB(352);
 430                         break;
 431                 case SNB_GMCH_GMS_STOLEN_384M:
 432                         stolen_size = MB(384);
 433                         break;
 434                 case SNB_GMCH_GMS_STOLEN_416M:
 435                         stolen_size = MB(416);
 436                         break;
 437                 case SNB_GMCH_GMS_STOLEN_448M:
 438                         stolen_size = MB(448);
 439                         break;
 440                 case SNB_GMCH_GMS_STOLEN_480M:
 441                         stolen_size = MB(480);
 442                         break;
 443                 case SNB_GMCH_GMS_STOLEN_512M:
 444                         stolen_size = MB(512);
 445                         break;
 446                 }
 447         } else {
 448                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 449                 case I855_GMCH_GMS_STOLEN_1M:
 450                         stolen_size = MB(1);
 451                         break;
 452                 case I855_GMCH_GMS_STOLEN_4M:
 453                         stolen_size = MB(4);
 454                         break;
 455                 case I855_GMCH_GMS_STOLEN_8M:
 456                         stolen_size = MB(8);
 457                         break;
 458                 case I855_GMCH_GMS_STOLEN_16M:
 459                         stolen_size = MB(16);
 460                         break;
 461                 case I855_GMCH_GMS_STOLEN_32M:
 462                         stolen_size = MB(32);
 463                         break;
 464                 case I915_GMCH_GMS_STOLEN_48M:
 465                         stolen_size = MB(48);
 466                         break;
 467                 case I915_GMCH_GMS_STOLEN_64M:
 468                         stolen_size = MB(64);
 469                         break;
 470                 case G33_GMCH_GMS_STOLEN_128M:
 471                         stolen_size = MB(128);
 472                         break;
 473                 case G33_GMCH_GMS_STOLEN_256M:
 474                         stolen_size = MB(256);
 475                         break;
 476                 case INTEL_GMCH_GMS_STOLEN_96M:
 477                         stolen_size = MB(96);
 478                         break;
 479                 case INTEL_GMCH_GMS_STOLEN_160M:
 480                         stolen_size = MB(160);
 481                         break;
 482                 case INTEL_GMCH_GMS_STOLEN_224M:
 483                         stolen_size = MB(224);
 484                         break;
 485                 case INTEL_GMCH_GMS_STOLEN_352M:
 486                         stolen_size = MB(352);
 487                         break;
 488                 default:
 489                         stolen_size = 0;
 490                         break;
 491                 }
 492         }
 493
 494         if (stolen_size > 0) {
 495                 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n",
 496                        stolen_size / KB(1), local ? "local" : "stolen");
 497         } else {
 498                 dev_info(&intel_private.bridge_dev->dev,
 499                        "no pre-allocated video memory detected\n");
 500                 stolen_size = 0;
 501         }
 502
 503         return stolen_size;
 504 }
 505
 506 static void i965_adjust_pgetbl_size(unsigned int size_flag)
 507 {
 508         u32 pgetbl_ctl, pgetbl_ctl2;
 509
 510         /* ensure that ppgtt is disabled */
 511         pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2);
 512         pgetbl_ctl2 &= ~I810_PGETBL_ENABLED;
 513         writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2);
 514
 515         /* write the new ggtt size */
 516         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 517         pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK;
 518         pgetbl_ctl |= size_flag;
 519         writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL);
 520 }
 521
 522 static unsigned int i965_gtt_total_entries(void)
 523 {
 524         int size;
 525         u32 pgetbl_ctl;
 526         u16 gmch_ctl;
 527
 528         pci_read_config_word(intel_private.bridge_dev,
 529                              I830_GMCH_CTRL, &gmch_ctl);
 530
 531         if (INTEL_GTT_GEN == 5) {
 532                 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) {
 533                 case G4x_GMCH_SIZE_1M:
 534                 case G4x_GMCH_SIZE_VT_1M:
 535                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB);
 536                         break;
 537                 case G4x_GMCH_SIZE_VT_1_5M:
 538                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB);
 539                         break;
 540                 case G4x_GMCH_SIZE_2M:
 541                 case G4x_GMCH_SIZE_VT_2M:
 542                         i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB);
 543                         break;
 544                 }
 545         }
 546
 547         pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 548
 549         switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 550         case I965_PGETBL_SIZE_128KB:
 551                 size = KB(128);
 552                 break;
 553         case I965_PGETBL_SIZE_256KB:
 554                 size = KB(256);
 555                 break;
 556         case I965_PGETBL_SIZE_512KB:
 557                 size = KB(512);
 558                 break;
 559         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
 560         case I965_PGETBL_SIZE_1MB:
 561                 size = KB(1024);
 562                 break;
 563         case I965_PGETBL_SIZE_2MB:
 564                 size = KB(2048);
 565                 break;
 566         case I965_PGETBL_SIZE_1_5MB:
 567                 size = KB(1024 + 512);
 568                 break;
 569         default:
 570                 dev_info(&intel_private.pcidev->dev,
 571                          "unknown page table size, assuming 512KB\n");
 572                 size = KB(512);
 573         }
 574
 575         return size/4;
 576 }
 577
 578 static unsigned int intel_gtt_total_entries(void)
 579 {
 580         int size;
 581
 582         if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5)
 583                 return i965_gtt_total_entries();
 584         else if (INTEL_GTT_GEN == 6) {
 585                 u16 snb_gmch_ctl;
 586
 587                 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl);
 588                 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) {
 589                 default:
 590                 case SNB_GTT_SIZE_0M:
 591                         printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl);
 592                         size = MB(0);
 593                         break;
 594                 case SNB_GTT_SIZE_1M:
 595                         size = MB(1);
 596                         break;
 597                 case SNB_GTT_SIZE_2M:
 598                         size = MB(2);
 599                         break;
 600                 }
 601                 return size/4;
 602         } else {
 603                 /* On previous hardware, the GTT size was just what was
 604                  * required to map the aperture.
 605                  */
 606                 return intel_private.base.gtt_mappable_entries;
 607         }
 608 }
 609
 610 static unsigned int intel_gtt_mappable_entries(void)
 611 {
 612         unsigned int aperture_size;
 613
 614         if (INTEL_GTT_GEN == 1) {
 615                 u32 smram_miscc;
 616
 617                 pci_read_config_dword(intel_private.bridge_dev,
 618                                       I810_SMRAM_MISCC, &smram_miscc);
 619
 620                 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE)
 621                                 == I810_GFX_MEM_WIN_32M)
 622                         aperture_size = MB(32);
 623                 else
 624                         aperture_size = MB(64);
 625         } else if (INTEL_GTT_GEN == 2) {
 626                 u16 gmch_ctrl;
 627
 628                 pci_read_config_word(intel_private.bridge_dev,
 629                                      I830_GMCH_CTRL, &gmch_ctrl);
 630
 631                 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M)
 632                         aperture_size = MB(64);
 633                 else
 634                         aperture_size = MB(128);
 635         } else {
 636                 /* 9xx supports large sizes, just look at the length */
 637                 aperture_size = pci_resource_len(intel_private.pcidev, 2);
 638         }
 639
 640         return aperture_size >> PAGE_SHIFT;
 641 }
 642
 643 static void intel_gtt_teardown_scratch_page(void)
 644 {
 645         set_pages_wb(intel_private.scratch_page, 1);
 646         pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma,
 647                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 648         put_page(intel_private.scratch_page);
 649         __free_page(intel_private.scratch_page);
 650 }
 651
 652 static void intel_gtt_cleanup(void)
 653 {
 654         intel_private.driver->cleanup();
 655
 656         iounmap(intel_private.gtt);
 657         iounmap(intel_private.registers);
 658
 659         intel_gtt_teardown_scratch_page();
 660 }
 661
 662 static int intel_gtt_init(void)
 663 {
 664         u32 gtt_map_size;
 665         int ret;
 666
 667         ret = intel_private.driver->setup();
 668         if (ret != 0)
 669                 return ret;
 670
 671         intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries();
 672         intel_private.base.gtt_total_entries = intel_gtt_total_entries();
 673
 674         /* save the PGETBL reg for resume */
 675         intel_private.PGETBL_save =
 676                 readl(intel_private.registers+I810_PGETBL_CTL)
 677                         & ~I810_PGETBL_ENABLED;
 678         /* we only ever restore the register when enabling the PGTBL... */
 679         if (HAS_PGTBL_EN)
 680                 intel_private.PGETBL_save |= I810_PGETBL_ENABLED;
 681
 682         dev_info(&intel_private.bridge_dev->dev,
 683                         "detected gtt size: %dK total, %dK mappable\n",
 684                         intel_private.base.gtt_total_entries * 4,
 685                         intel_private.base.gtt_mappable_entries * 4);
 686
 687         gtt_map_size = intel_private.base.gtt_total_entries * 4;
 688
 689         intel_private.gtt = ioremap(intel_private.gtt_bus_addr,
 690                                     gtt_map_size);
 691         if (!intel_private.gtt) {
 692                 intel_private.driver->cleanup();
 693                 iounmap(intel_private.registers);
 694                 return -ENOMEM;
 695         }
 696
 697         global_cache_flush();   /* FIXME: ? */
 698
 699         intel_private.base.stolen_size = intel_gtt_stolen_size();
 700
 701         ret = intel_gtt_setup_scratch_page();
 702         if (ret != 0) {
 703                 intel_gtt_cleanup();
 704                 return ret;
 705         }
 706
 707         return 0;
 708 }
 709
 710 static int intel_fake_agp_fetch_size(void)
 711 {
 712         int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
 713         unsigned int aper_size;
 714         int i;
 715
 716         aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT)
 717                     / MB(1);
 718
 719         for (i = 0; i < num_sizes; i++) {
 720                 if (aper_size == intel_fake_agp_sizes[i].size) {
 721                         agp_bridge->current_size =
 722                                 (void *) (intel_fake_agp_sizes + i);
 723                         return aper_size;
 724                 }
 725         }
 726
 727         return 0;
 728 }
 729
 730 static void i830_cleanup(void)
 731 {
 732         kunmap(intel_private.i8xx_page);
 733         intel_private.i8xx_flush_page = NULL;
 734
 735         __free_page(intel_private.i8xx_page);
 736         intel_private.i8xx_page = NULL;
 737 }
 738
 739 static void intel_i830_setup_flush(void)
 740 {
 741         /* return if we've already set the flush mechanism up */
 742         if (intel_private.i8xx_page)
 743                 return;
 744
 745         intel_private.i8xx_page = alloc_page(GFP_KERNEL);
 746         if (!intel_private.i8xx_page)
 747                 return;
 748
 749         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 750         if (!intel_private.i8xx_flush_page)
 751                 i830_cleanup();
 752 }
 753
 754 /* The chipset_flush interface needs to get data that has already been
 755  * flushed out of the CPU all the way out to main memory, because the GPU
 756  * doesn't snoop those buffers.
 757  *
 758  * The 8xx series doesn't have the same lovely interface for flushing the
 759  * chipset write buffers that the later chips do. According to the 865
 760  * specs, it's 64 octwords, or 1KB.  So, to get those previous things in
 761  * that buffer out, we just fill 1KB and clflush it out, on the assumption
 762  * that it'll push whatever was in there out.  It appears to work.
 763  */
 764 static void i830_chipset_flush(void)
 765 {
 766         unsigned int *pg = intel_private.i8xx_flush_page;
 767
 768         memset(pg, 0, 1024);
 769
 770         if (cpu_has_clflush)
 771                 clflush_cache_range(pg, 1024);
 772         else if (wbinvd_on_all_cpus() != 0)
 773                 printk(KERN_ERR "Timed out waiting for cache flush.\n");
 774 }
 775
 776 static void i830_write_entry(dma_addr_t addr, unsigned int entry,
 777                              unsigned int flags)
 778 {
 779         u32 pte_flags = I810_PTE_VALID;
 780
 781         if (flags ==  AGP_USER_CACHED_MEMORY)
 782                 pte_flags |= I830_PTE_SYSTEM_CACHED;
 783
 784         writel(addr | pte_flags, intel_private.gtt + entry);
 785 }
 786
 787 static bool intel_enable_gtt(void)
 788 {
 789         u32 gma_addr;
 790         u8 __iomem *reg;
 791
 792         if (INTEL_GTT_GEN <= 2)
 793                 pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
 794                                       &gma_addr);
 795         else
 796                 pci_read_config_dword(intel_private.pcidev, I915_GMADDR,
 797                                       &gma_addr);
 798
 799         intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK);
 800
 801         if (INTEL_GTT_GEN >= 6)
 802             return true;
 803
 804         if (INTEL_GTT_GEN == 2) {
 805                 u16 gmch_ctrl;
 806
 807                 pci_read_config_word(intel_private.bridge_dev,
 808                                      I830_GMCH_CTRL, &gmch_ctrl);
 809                 gmch_ctrl |= I830_GMCH_ENABLED;
 810                 pci_write_config_word(intel_private.bridge_dev,
 811                                       I830_GMCH_CTRL, gmch_ctrl);
 812
 813                 pci_read_config_word(intel_private.bridge_dev,
 814                                      I830_GMCH_CTRL, &gmch_ctrl);
 815                 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) {
 816                         dev_err(&intel_private.pcidev->dev,
 817                                 "failed to enable the GTT: GMCH_CTRL=%x\n",
 818                                 gmch_ctrl);
 819                         return false;
 820                 }
 821         }
 822
 823         reg = intel_private.registers+I810_PGETBL_CTL;
 824         writel(intel_private.PGETBL_save, reg);
 825         if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) {
 826                 dev_err(&intel_private.pcidev->dev,
 827                         "failed to enable the GTT: PGETBL=%x [expected %x]\n",
 828                         readl(reg), intel_private.PGETBL_save);
 829                 return false;
 830         }
 831
 832         return true;
 833 }
 834
 835 static int i830_setup(void)
 836 {
 837         u32 reg_addr;
 838
 839         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &reg_addr);
 840         reg_addr &= 0xfff80000;
 841
 842         intel_private.registers = ioremap(reg_addr, KB(64));
 843         if (!intel_private.registers)
 844                 return -ENOMEM;
 845
 846         intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
 847
 848         intel_i830_setup_flush();
 849
 850         return 0;
 851 }
 852
 853 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
 854 {
 855         agp_bridge->gatt_table_real = NULL;
 856         agp_bridge->gatt_table = NULL;
 857         agp_bridge->gatt_bus_addr = 0;
 858
 859         return 0;
 860 }
 861
 862 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge)
 863 {
 864         return 0;
 865 }
 866
 867 static int intel_fake_agp_configure(void)
 868 {
 869         int i;
 870
 871         if (!intel_enable_gtt())
 872             return -EIO;
 873
 874         agp_bridge->gart_bus_addr = intel_private.gma_bus_addr;
 875
 876         for (i = 0; i < intel_private.base.gtt_total_entries; i++) {
 877                 intel_private.driver->write_entry(intel_private.scratch_page_dma,
 878                                                   i, 0);
 879         }
 880         readl(intel_private.gtt+i-1);   /* PCI Posting. */
 881
 882         global_cache_flush();
 883
 884         return 0;
 885 }
 886
 887 static bool i830_check_flags(unsigned int flags)
 888 {
 889         switch (flags) {
 890         case 0:
 891         case AGP_PHYS_MEMORY:
 892         case AGP_USER_CACHED_MEMORY:
 893         case AGP_USER_MEMORY:
 894                 return true;
 895         }
 896
 897         return false;
 898 }
 899
 900 static void intel_gtt_insert_sg_entries(struct scatterlist *sg_list,
 901                                         unsigned int sg_len,
 902                                         unsigned int pg_start,
 903                                         unsigned int flags)
 904 {
 905         struct scatterlist *sg;
 906         unsigned int len, m;
 907         int i, j;
 908
 909         j = pg_start;
 910
 911         /* sg may merge pages, but we have to separate
 912          * per-page addr for GTT */
 913         for_each_sg(sg_list, sg, sg_len, i) {
 914                 len = sg_dma_len(sg) >> PAGE_SHIFT;
 915                 for (m = 0; m < len; m++) {
 916                         dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT);
 917                         intel_private.driver->write_entry(addr,
 918                                                           j, flags);
 919                         j++;
 920                 }
 921         }
 922         readl(intel_private.gtt+j-1);
 923 }
 924
 925 static int intel_fake_agp_insert_entries(struct agp_memory *mem,
 926                                          off_t pg_start, int type)
 927 {
 928         int i, j;
 929         int ret = -EINVAL;
 930
 931         if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY)
 932                 return i810_insert_dcache_entries(mem, pg_start, type);
 933
 934         if (mem->page_count == 0)
 935                 goto out;
 936
 937         if (pg_start + mem->page_count > intel_private.base.gtt_total_entries)
 938                 goto out_err;
 939
 940         if (type != mem->type)
 941                 goto out_err;
 942
 943         if (!intel_private.driver->check_flags(type))
 944                 goto out_err;
 945
 946         if (!mem->is_flushed)
 947                 global_cache_flush();
 948
 949         if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2) {
 950                 ret = intel_agp_map_memory(mem);
 951                 if (ret != 0)
 952                         return ret;
 953
 954                 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg,
 955                                             pg_start, type);
 956         } else {
 957                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 958                         dma_addr_t addr = page_to_phys(mem->pages[i]);
 959                         intel_private.driver->write_entry(addr,
 960                                                           j, type);
 961                 }
 962                 readl(intel_private.gtt+j-1);
 963         }
 964
 965 out:
 966         ret = 0;
 967 out_err:
 968         mem->is_flushed = true;
 969         return ret;
 970 }
 971
 972 static int intel_fake_agp_remove_entries(struct agp_memory *mem,
 973                                          off_t pg_start, int type)
 974 {
 975         int i;
 976
 977         if (mem->page_count == 0)
 978                 return 0;
 979
 980         if (USE_PCI_DMA_API && INTEL_GTT_GEN > 2)
 981                 intel_agp_unmap_memory(mem);
 982
 983         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 984                 intel_private.driver->write_entry(intel_private.scratch_page_dma,
 985                                                   i, 0);
 986         }
 987         readl(intel_private.gtt+i-1);
 988
 989         return 0;
 990 }
 991
 992 static void intel_fake_agp_chipset_flush(struct agp_bridge_data *bridge)
 993 {
 994         intel_private.driver->chipset_flush();
 995 }
 996
 997 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
 998                                                        int type)
 999 {
1000         struct agp_memory *new;
1001
1002         if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) {
1003                 if (pg_count != intel_private.num_dcache_entries)
1004                         return NULL;
1005
1006                 new = agp_create_memory(1);
1007                 if (new == NULL)
1008                         return NULL;
1009
1010                 new->type = AGP_DCACHE_MEMORY;
1011                 new->page_count = pg_count;
1012                 new->num_scratch_pages = 0;
1013                 agp_free_page_array(new);
1014                 return new;
1015         }
1016         if (type == AGP_PHYS_MEMORY)
1017                 return alloc_agpphysmem_i8xx(pg_count, type);
1018         /* always return NULL for other allocation types for now */
1019         return NULL;
1020 }
1021
1022 static int intel_alloc_chipset_flush_resource(void)
1023 {
1024         int ret;
1025         ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1026                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1027                                      pcibios_align_resource, intel_private.bridge_dev);
1028
1029         return ret;
1030 }
1031
1032 static void intel_i915_setup_chipset_flush(void)
1033 {
1034         int ret;
1035         u32 temp;
1036
1037         pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp);
1038         if (!(temp & 0x1)) {
1039                 intel_alloc_chipset_flush_resource();
1040                 intel_private.resource_valid = 1;
1041                 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1042         } else {
1043                 temp &= ~1;
1044
1045                 intel_private.resource_valid = 1;
1046                 intel_private.ifp_resource.start = temp;
1047                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1048                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1049                 /* some BIOSes reserve this area in a pnp some don't */
1050                 if (ret)
1051                         intel_private.resource_valid = 0;
1052         }
1053 }
1054
1055 static void intel_i965_g33_setup_chipset_flush(void)
1056 {
1057         u32 temp_hi, temp_lo;
1058         int ret;
1059
1060         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi);
1061         pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo);
1062
1063         if (!(temp_lo & 0x1)) {
1064
1065                 intel_alloc_chipset_flush_resource();
1066
1067                 intel_private.resource_valid = 1;
1068                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4,
1069                         upper_32_bits(intel_private.ifp_resource.start));
1070                 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1071         } else {
1072                 u64 l64;
1073
1074                 temp_lo &= ~0x1;
1075                 l64 = ((u64)temp_hi << 32) | temp_lo;
1076
1077                 intel_private.resource_valid = 1;
1078                 intel_private.ifp_resource.start = l64;
1079                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1080                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1081                 /* some BIOSes reserve this area in a pnp some don't */
1082                 if (ret)
1083                         intel_private.resource_valid = 0;
1084         }
1085 }
1086
1087 static void intel_i9xx_setup_flush(void)
1088 {
1089         /* return if already configured */
1090         if (intel_private.ifp_resource.start)
1091                 return;
1092
1093         if (INTEL_GTT_GEN == 6)
1094                 return;
1095
1096         /* setup a resource for this object */
1097         intel_private.ifp_resource.name = "Intel Flush Page";
1098         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1099
1100         /* Setup chipset flush for 915 */
1101         if (IS_G33 || INTEL_GTT_GEN >= 4) {
1102                 intel_i965_g33_setup_chipset_flush();
1103         } else {
1104                 intel_i915_setup_chipset_flush();
1105         }
1106
1107         if (intel_private.ifp_resource.start)
1108                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1109         if (!intel_private.i9xx_flush_page)
1110                 dev_err(&intel_private.pcidev->dev,
1111                         "can't ioremap flush page - no chipset flushing\n");
1112 }
1113
1114 static void i9xx_cleanup(void)
1115 {
1116         if (intel_private.i9xx_flush_page)
1117                 iounmap(intel_private.i9xx_flush_page);
1118         if (intel_private.resource_valid)
1119                 release_resource(&intel_private.ifp_resource);
1120         intel_private.ifp_resource.start = 0;
1121         intel_private.resource_valid = 0;
1122 }
1123
1124 static void i9xx_chipset_flush(void)
1125 {
1126         if (intel_private.i9xx_flush_page)
1127                 writel(1, intel_private.i9xx_flush_page);
1128 }
1129
1130 static void i965_write_entry(dma_addr_t addr, unsigned int entry,
1131                              unsigned int flags)
1132 {
1133         /* Shift high bits down */
1134         addr |= (addr >> 28) & 0xf0;
1135         writel(addr | I810_PTE_VALID, intel_private.gtt + entry);
1136 }
1137
1138 static bool gen6_check_flags(unsigned int flags)
1139 {
1140         return true;
1141 }
1142
1143 static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
1144                              unsigned int flags)
1145 {
1146         unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
1147         unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
1148         u32 pte_flags;
1149
1150         if (type_mask == AGP_USER_MEMORY)
1151                 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
1152         else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) {
1153                 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID;
1154                 if (gfdt)
1155                         pte_flags |= GEN6_PTE_GFDT;
1156         } else { /* set 'normal'/'cached' to LLC by default */
1157                 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID;
1158                 if (gfdt)
1159                         pte_flags |= GEN6_PTE_GFDT;
1160         }
1161
1162         /* gen6 has bit11-4 for physical addr bit39-32 */
1163         addr |= (addr >> 28) & 0xff0;
1164         writel(addr | pte_flags, intel_private.gtt + entry);
1165 }
1166
1167 static void gen6_cleanup(void)
1168 {
1169 }
1170
1171 static int i9xx_setup(void)
1172 {
1173         u32 reg_addr;
1174
1175         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &reg_addr);
1176
1177         reg_addr &= 0xfff80000;
1178
1179         intel_private.registers = ioremap(reg_addr, 128 * 4096);
1180         if (!intel_private.registers)
1181                 return -ENOMEM;
1182
1183         if (INTEL_GTT_GEN == 3) {
1184                 u32 gtt_addr;
1185
1186                 pci_read_config_dword(intel_private.pcidev,
1187                                       I915_PTEADDR, &gtt_addr);
1188                 intel_private.gtt_bus_addr = gtt_addr;
1189         } else {
1190                 u32 gtt_offset;
1191
1192                 switch (INTEL_GTT_GEN) {
1193                 case 5:
1194                 case 6:
1195                         gtt_offset = MB(2);
1196                         break;
1197                 case 4:
1198                 default:
1199                         gtt_offset =  KB(512);
1200                         break;
1201                 }
1202                 intel_private.gtt_bus_addr = reg_addr + gtt_offset;
1203         }
1204
1205         intel_i9xx_setup_flush();
1206
1207         return 0;
1208 }
1209
1210 static const struct agp_bridge_driver intel_fake_agp_driver = {
1211         .owner                  = THIS_MODULE,
1212         .size_type              = FIXED_APER_SIZE,
1213         .aperture_sizes         = intel_fake_agp_sizes,
1214         .num_aperture_sizes     = ARRAY_SIZE(intel_fake_agp_sizes),
1215         .configure              = intel_fake_agp_configure,
1216         .fetch_size             = intel_fake_agp_fetch_size,
1217         .cleanup                = intel_gtt_cleanup,
1218         .agp_enable             = intel_fake_agp_enable,
1219         .cache_flush            = global_cache_flush,
1220         .create_gatt_table      = intel_fake_agp_create_gatt_table,
1221         .free_gatt_table        = intel_fake_agp_free_gatt_table,
1222         .insert_memory          = intel_fake_agp_insert_entries,
1223         .remove_memory          = intel_fake_agp_remove_entries,
1224         .alloc_by_type          = intel_fake_agp_alloc_by_type,
1225         .free_by_type           = intel_i810_free_by_type,
1226         .agp_alloc_page         = agp_generic_alloc_page,
1227         .agp_alloc_pages        = agp_generic_alloc_pages,
1228         .agp_destroy_page       = agp_generic_destroy_page,
1229         .agp_destroy_pages      = agp_generic_destroy_pages,
1230         .chipset_flush          = intel_fake_agp_chipset_flush,
1231 };
1232
1233 static const struct intel_gtt_driver i81x_gtt_driver = {
1234         .gen = 1,
1235         .has_pgtbl_enable = 1,
1236         .dma_mask_size = 32,
1237         .setup = i810_setup,
1238         .cleanup = i810_cleanup,
1239         .check_flags = i830_check_flags,
1240         .write_entry = i810_write_entry,
1241 };
1242 static const struct intel_gtt_driver i8xx_gtt_driver = {
1243         .gen = 2,
1244         .has_pgtbl_enable = 1,
1245         .setup = i830_setup,
1246         .cleanup = i830_cleanup,
1247         .write_entry = i830_write_entry,
1248         .dma_mask_size = 32,
1249         .check_flags = i830_check_flags,
1250         .chipset_flush = i830_chipset_flush,
1251 };
1252 static const struct intel_gtt_driver i915_gtt_driver = {
1253         .gen = 3,
1254         .has_pgtbl_enable = 1,
1255         .setup = i9xx_setup,
1256         .cleanup = i9xx_cleanup,
1257         /* i945 is the last gpu to need phys mem (for overlay and cursors). */
1258         .write_entry = i830_write_entry,
1259         .dma_mask_size = 32,
1260         .check_flags = i830_check_flags,
1261         .chipset_flush = i9xx_chipset_flush,
1262 };
1263 static const struct intel_gtt_driver g33_gtt_driver = {
1264         .gen = 3,
1265         .is_g33 = 1,
1266         .setup = i9xx_setup,
1267         .cleanup = i9xx_cleanup,
1268         .write_entry = i965_write_entry,
1269         .dma_mask_size = 36,
1270         .check_flags = i830_check_flags,
1271         .chipset_flush = i9xx_chipset_flush,
1272 };
1273 static const struct intel_gtt_driver pineview_gtt_driver = {
1274         .gen = 3,
1275         .is_pineview = 1, .is_g33 = 1,
1276         .setup = i9xx_setup,
1277         .cleanup = i9xx_cleanup,
1278         .write_entry = i965_write_entry,
1279         .dma_mask_size = 36,
1280         .check_flags = i830_check_flags,
1281         .chipset_flush = i9xx_chipset_flush,
1282 };
1283 static const struct intel_gtt_driver i965_gtt_driver = {
1284         .gen = 4,
1285         .has_pgtbl_enable = 1,
1286         .setup = i9xx_setup,
1287         .cleanup = i9xx_cleanup,
1288         .write_entry = i965_write_entry,
1289         .dma_mask_size = 36,
1290         .check_flags = i830_check_flags,
1291         .chipset_flush = i9xx_chipset_flush,
1292 };
1293 static const struct intel_gtt_driver g4x_gtt_driver = {
1294         .gen = 5,
1295         .setup = i9xx_setup,
1296         .cleanup = i9xx_cleanup,
1297         .write_entry = i965_write_entry,
1298         .dma_mask_size = 36,
1299         .check_flags = i830_check_flags,
1300         .chipset_flush = i9xx_chipset_flush,
1301 };
1302 static const struct intel_gtt_driver ironlake_gtt_driver = {
1303         .gen = 5,
1304         .is_ironlake = 1,
1305         .setup = i9xx_setup,
1306         .cleanup = i9xx_cleanup,
1307         .write_entry = i965_write_entry,
1308         .dma_mask_size = 36,
1309         .check_flags = i830_check_flags,
1310         .chipset_flush = i9xx_chipset_flush,
1311 };
1312 static const struct intel_gtt_driver sandybridge_gtt_driver = {
1313         .gen = 6,
1314         .setup = i9xx_setup,
1315         .cleanup = gen6_cleanup,
1316         .write_entry = gen6_write_entry,
1317         .dma_mask_size = 40,
1318         .check_flags = gen6_check_flags,
1319         .chipset_flush = i9xx_chipset_flush,
1320 };
1321
1322 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1323  * driver and gmch_driver must be non-null, and find_gmch will determine
1324  * which one should be used if a gmch_chip_id is present.
1325  */
1326 static const struct intel_gtt_driver_description {
1327         unsigned int gmch_chip_id;
1328         char *name;
1329         const struct intel_gtt_driver *gtt_driver;
1330 } intel_gtt_chipsets[] = {
1331         { PCI_DEVICE_ID_INTEL_82810_IG1, "i810",
1332                 &i81x_gtt_driver},
1333         { PCI_DEVICE_ID_INTEL_82810_IG3, "i810",
1334                 &i81x_gtt_driver},
1335         { PCI_DEVICE_ID_INTEL_82810E_IG, "i810",
1336                 &i81x_gtt_driver},
1337         { PCI_DEVICE_ID_INTEL_82815_CGC, "i815",
1338                 &i81x_gtt_driver},
1339         { PCI_DEVICE_ID_INTEL_82830_CGC, "830M",
1340                 &i8xx_gtt_driver},
1341         { PCI_DEVICE_ID_INTEL_82845G_IG, "830M",
1342                 &i8xx_gtt_driver},
1343         { PCI_DEVICE_ID_INTEL_82854_IG, "854",
1344                 &i8xx_gtt_driver},
1345         { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM",
1346                 &i8xx_gtt_driver},
1347         { PCI_DEVICE_ID_INTEL_82865_IG, "865",
1348                 &i8xx_gtt_driver},
1349         { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)",
1350                 &i915_gtt_driver },
1351         { PCI_DEVICE_ID_INTEL_82915G_IG, "915G",
1352                 &i915_gtt_driver },
1353         { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM",
1354                 &i915_gtt_driver },
1355         { PCI_DEVICE_ID_INTEL_82945G_IG, "945G",
1356                 &i915_gtt_driver },
1357         { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM",
1358                 &i915_gtt_driver },
1359         { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME",
1360                 &i915_gtt_driver },
1361         { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ",
1362                 &i965_gtt_driver },
1363         { PCI_DEVICE_ID_INTEL_82G35_IG, "G35",
1364                 &i965_gtt_driver },
1365         { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q",
1366                 &i965_gtt_driver },
1367         { PCI_DEVICE_ID_INTEL_82965G_IG, "965G",
1368                 &i965_gtt_driver },
1369         { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM",
1370                 &i965_gtt_driver },
1371         { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE",
1372                 &i965_gtt_driver },
1373         { PCI_DEVICE_ID_INTEL_G33_IG, "G33",
1374                 &g33_gtt_driver },
1375         { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35",
1376                 &g33_gtt_driver },
1377         { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33",
1378                 &g33_gtt_driver },
1379         { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150",
1380                 &pineview_gtt_driver },
1381         { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150",
1382                 &pineview_gtt_driver },
1383         { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45",
1384                 &g4x_gtt_driver },
1385         { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake",
1386                 &g4x_gtt_driver },
1387         { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43",
1388                 &g4x_gtt_driver },
1389         { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43",
1390                 &g4x_gtt_driver },
1391         { PCI_DEVICE_ID_INTEL_B43_IG, "B43",
1392                 &g4x_gtt_driver },
1393         { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43",
1394                 &g4x_gtt_driver },
1395         { PCI_DEVICE_ID_INTEL_G41_IG, "G41",
1396                 &g4x_gtt_driver },
1397         { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG,
1398             "HD Graphics", &ironlake_gtt_driver },
1399         { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG,
1400             "HD Graphics", &ironlake_gtt_driver },
1401         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG,
1402             "Sandybridge", &sandybridge_gtt_driver },
1403         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG,
1404             "Sandybridge", &sandybridge_gtt_driver },
1405         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG,
1406             "Sandybridge", &sandybridge_gtt_driver },
1407         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG,
1408             "Sandybridge", &sandybridge_gtt_driver },
1409         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG,
1410             "Sandybridge", &sandybridge_gtt_driver },
1411         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG,
1412             "Sandybridge", &sandybridge_gtt_driver },
1413         { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
1414             "Sandybridge", &sandybridge_gtt_driver },
1415         { 0, NULL, NULL }
1416 };
1417
1418 static int find_gmch(u16 device)
1419 {
1420         struct pci_dev *gmch_device;
1421
1422         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1423         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1424                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1425                                              device, gmch_device);
1426         }
1427
1428         if (!gmch_device)
1429                 return 0;
1430
1431         intel_private.pcidev = gmch_device;
1432         return 1;
1433 }
1434
1435 int intel_gmch_probe(struct pci_dev *pdev,
1436                                       struct agp_bridge_data *bridge)
1437 {
1438         int i, mask;
1439         intel_private.driver = NULL;
1440
1441         for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) {
1442                 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) {
1443                         intel_private.driver =
1444                                 intel_gtt_chipsets[i].gtt_driver;
1445                         break;
1446                 }
1447         }
1448
1449         if (!intel_private.driver)
1450                 return 0;
1451
1452         bridge->driver = &intel_fake_agp_driver;
1453         bridge->dev_private_data = &intel_private;
1454         bridge->dev = pdev;
1455
1456         intel_private.bridge_dev = pci_dev_get(pdev);
1457
1458         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
1459
1460         mask = intel_private.driver->dma_mask_size;
1461         if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
1462                 dev_err(&intel_private.pcidev->dev,
1463                         "set gfx device dma mask %d-bit failed!\n", mask);
1464         else
1465                 pci_set_consistent_dma_mask(intel_private.pcidev,
1466                                             DMA_BIT_MASK(mask));
1467
1468         /*if (bridge->driver == &intel_810_driver)
1469                 return 1;*/
1470
1471         if (intel_gtt_init() != 0)
1472                 return 0;
1473
1474         return 1;
1475 }
1476 EXPORT_SYMBOL(intel_gmch_probe);
1477
1478 const struct intel_gtt *intel_gtt_get(void)
1479 {
1480         return &intel_private.base;
1481 }
1482 EXPORT_SYMBOL(intel_gtt_get);
1483
1484 void intel_gmch_remove(struct pci_dev *pdev)
1485 {
1486         if (intel_private.pcidev)
1487                 pci_dev_put(intel_private.pcidev);
1488         if (intel_private.bridge_dev)
1489                 pci_dev_put(intel_private.bridge_dev);
1490 }
1491 EXPORT_SYMBOL(intel_gmch_remove);
1492
1493 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1494 MODULE_LICENSE("GPL and additional rights");