drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 /*
  14  * If we have Intel graphics, we're not going to have anything other than
  15  * an Intel IOMMU. So make the correct use of the PCI DMA API contingent
  16  * on the Intel IOMMU support (CONFIG_DMAR).
  17  * Only newer chipsets need to bother with this, of course.
  18  */
  19 #ifdef CONFIG_DMAR
  20 #define USE_PCI_DMA_API 1
  21 #endif
  22
  23 #define PCI_DEVICE_ID_INTEL_E7221_HB    0x2588
  24 #define PCI_DEVICE_ID_INTEL_E7221_IG    0x258a
  25 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  26 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  27 #define PCI_DEVICE_ID_INTEL_82G35_HB     0x2980
  28 #define PCI_DEVICE_ID_INTEL_82G35_IG     0x2982
  29 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  30 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  31 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  32 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  33 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  34 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  35 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  36 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  37 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  38 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  39 #define PCI_DEVICE_ID_INTEL_IGDGM_HB        0xA010
  40 #define PCI_DEVICE_ID_INTEL_IGDGM_IG        0xA011
  41 #define PCI_DEVICE_ID_INTEL_IGDG_HB         0xA000
  42 #define PCI_DEVICE_ID_INTEL_IGDG_IG         0xA001
  43 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  44 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  45 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  46 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  47 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  48 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  49 #define PCI_DEVICE_ID_INTEL_GM45_HB         0x2A40
  50 #define PCI_DEVICE_ID_INTEL_GM45_IG         0x2A42
  51 #define PCI_DEVICE_ID_INTEL_IGD_E_HB        0x2E00
  52 #define PCI_DEVICE_ID_INTEL_IGD_E_IG        0x2E02
  53 #define PCI_DEVICE_ID_INTEL_Q45_HB          0x2E10
  54 #define PCI_DEVICE_ID_INTEL_Q45_IG          0x2E12
  55 #define PCI_DEVICE_ID_INTEL_G45_HB          0x2E20
  56 #define PCI_DEVICE_ID_INTEL_G45_IG          0x2E22
  57 #define PCI_DEVICE_ID_INTEL_G41_HB          0x2E30
  58 #define PCI_DEVICE_ID_INTEL_G41_IG          0x2E32
  59 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB      0x0040
  60 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG      0x0042
  61 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB      0x0044
  62 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG      0x0046
  63
  64 /* cover 915 and 945 variants */
  65 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
  66                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
  67                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
  68                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
  69                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
  70                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
  71
  72 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  73                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
  74                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  75                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  76                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  77                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  78
  79 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  80                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  81                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
  82                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  83                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  84
  85 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
  86                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
  87
  88 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
  89                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
  90                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
  91                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
  92                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
  93                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
  94                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB)
  95
  96 extern int agp_memory_reserved;
  97
  98
  99 /* Intel 815 register */
 100 #define INTEL_815_APCONT        0x51
 101 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
 102
 103 /* Intel i820 registers */
 104 #define INTEL_I820_RDCR         0x51
 105 #define INTEL_I820_ERRSTS       0xc8
 106
 107 /* Intel i840 registers */
 108 #define INTEL_I840_MCHCFG       0x50
 109 #define INTEL_I840_ERRSTS       0xc8
 110
 111 /* Intel i850 registers */
 112 #define INTEL_I850_MCHCFG       0x50
 113 #define INTEL_I850_ERRSTS       0xc8
 114
 115 /* intel 915G registers */
 116 #define I915_GMADDR     0x18
 117 #define I915_MMADDR     0x10
 118 #define I915_PTEADDR    0x1C
 119 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
 120 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
 121 #define G33_GMCH_GMS_STOLEN_128M        (0x8 << 4)
 122 #define G33_GMCH_GMS_STOLEN_256M        (0x9 << 4)
 123 #define INTEL_GMCH_GMS_STOLEN_96M       (0xa << 4)
 124 #define INTEL_GMCH_GMS_STOLEN_160M      (0xb << 4)
 125 #define INTEL_GMCH_GMS_STOLEN_224M      (0xc << 4)
 126 #define INTEL_GMCH_GMS_STOLEN_352M      (0xd << 4)
 127
 128 #define I915_IFPADDR    0x60
 129
 130 /* Intel 965G registers */
 131 #define I965_MSAC 0x62
 132 #define I965_IFPADDR    0x70
 133
 134 /* Intel 7505 registers */
 135 #define INTEL_I7505_APSIZE      0x74
 136 #define INTEL_I7505_NCAPID      0x60
 137 #define INTEL_I7505_NISTAT      0x6c
 138 #define INTEL_I7505_ATTBASE     0x78
 139 #define INTEL_I7505_ERRSTS      0x42
 140 #define INTEL_I7505_AGPCTRL     0x70
 141 #define INTEL_I7505_MCHCFG      0x50
 142
 143 static const struct aper_size_info_fixed intel_i810_sizes[] =
 144 {
 145         {64, 16384, 4},
 146         /* The 32M mode still requires a 64k gatt */
 147         {32, 8192, 4}
 148 };
 149
 150 #define AGP_DCACHE_MEMORY       1
 151 #define AGP_PHYS_MEMORY         2
 152 #define INTEL_AGP_CACHED_MEMORY 3
 153
 154 static struct gatt_mask intel_i810_masks[] =
 155 {
 156         {.mask = I810_PTE_VALID, .type = 0},
 157         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 158         {.mask = I810_PTE_VALID, .type = 0},
 159         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 160          .type = INTEL_AGP_CACHED_MEMORY}
 161 };
 162
 163 static struct _intel_private {
 164         struct pci_dev *pcidev; /* device one */
 165         u8 __iomem *registers;
 166         u32 __iomem *gtt;               /* I915G */
 167         int num_dcache_entries;
 168         /* gtt_entries is the number of gtt entries that are already mapped
 169          * to stolen memory.  Stolen memory is larger than the memory mapped
 170          * through gtt_entries, as it includes some reserved space for the BIOS
 171          * popup and for the GTT.
 172          */
 173         int gtt_entries;                        /* i830+ */
 174         union {
 175                 void __iomem *i9xx_flush_page;
 176                 void *i8xx_flush_page;
 177         };
 178         struct page *i8xx_page;
 179         struct resource ifp_resource;
 180         int resource_valid;
 181 } intel_private;
 182
 183 #ifdef USE_PCI_DMA_API
 184 static int intel_agp_map_page(struct page *page, dma_addr_t *ret)
 185 {
 186         *ret = pci_map_page(intel_private.pcidev, page, 0,
 187                             PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 188         if (pci_dma_mapping_error(intel_private.pcidev, *ret))
 189                 return -EINVAL;
 190         return 0;
 191 }
 192
 193 static void intel_agp_unmap_page(struct page *page, dma_addr_t dma)
 194 {
 195         pci_unmap_page(intel_private.pcidev, dma,
 196                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
 197 }
 198
 199 static void intel_agp_free_sglist(struct agp_memory *mem)
 200 {
 201
 202         if (mem->sg_vmalloc_flag)
 203                 vfree(mem->sg_list);
 204         else
 205                 kfree(mem->sg_list);
 206         mem->sg_vmalloc_flag = 0;
 207         mem->sg_list = NULL;
 208         mem->num_sg = 0;
 209 }
 210
 211 static int intel_agp_map_memory(struct agp_memory *mem)
 212 {
 213         struct scatterlist *sg;
 214         int i;
 215
 216         DBG("try mapping %lu pages\n", (unsigned long)mem->page_count);
 217
 218         if ((mem->page_count * sizeof(*mem->sg_list)) < 2*PAGE_SIZE)
 219                 mem->sg_list = kcalloc(mem->page_count, sizeof(*mem->sg_list),
 220                                        GFP_KERNEL);
 221
 222         if (mem->sg_list == NULL) {
 223                 mem->sg_list = vmalloc(mem->page_count * sizeof(*mem->sg_list));
 224                 mem->sg_vmalloc_flag = 1;
 225         }
 226
 227         if (!mem->sg_list) {
 228                 mem->sg_vmalloc_flag = 0;
 229                 return -ENOMEM;
 230         }
 231         sg_init_table(mem->sg_list, mem->page_count);
 232
 233         sg = mem->sg_list;
 234         for (i = 0 ; i < mem->page_count; i++, sg = sg_next(sg))
 235                 sg_set_page(sg, mem->pages[i], PAGE_SIZE, 0);
 236
 237         mem->num_sg = pci_map_sg(intel_private.pcidev, mem->sg_list,
 238                                  mem->page_count, PCI_DMA_BIDIRECTIONAL);
 239         if (unlikely(!mem->num_sg)) {
 240                 intel_agp_free_sglist(mem);
 241                 return -ENOMEM;
 242         }
 243         return 0;
 244 }
 245
 246 static void intel_agp_unmap_memory(struct agp_memory *mem)
 247 {
 248         DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count);
 249
 250         pci_unmap_sg(intel_private.pcidev, mem->sg_list,
 251                      mem->page_count, PCI_DMA_BIDIRECTIONAL);
 252         intel_agp_free_sglist(mem);
 253 }
 254
 255 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 256                                         off_t pg_start, int mask_type)
 257 {
 258         struct scatterlist *sg;
 259         int i, j;
 260
 261         j = pg_start;
 262
 263         WARN_ON(!mem->num_sg);
 264
 265         if (mem->num_sg == mem->page_count) {
 266                 for_each_sg(mem->sg_list, sg, mem->page_count, i) {
 267                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 268                                         sg_dma_address(sg), mask_type),
 269                                         intel_private.gtt+j);
 270                         j++;
 271                 }
 272         } else {
 273                 /* sg may merge pages, but we have to seperate
 274                  * per-page addr for GTT */
 275                 unsigned int len, m;
 276
 277                 for_each_sg(mem->sg_list, sg, mem->num_sg, i) {
 278                         len = sg_dma_len(sg) / PAGE_SIZE;
 279                         for (m = 0; m < len; m++) {
 280                                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 281                                                                        sg_dma_address(sg) + m * PAGE_SIZE,
 282                                                                        mask_type),
 283                                        intel_private.gtt+j);
 284                                 j++;
 285                         }
 286                 }
 287         }
 288         readl(intel_private.gtt+j-1);
 289 }
 290
 291 #else
 292
 293 static void intel_agp_insert_sg_entries(struct agp_memory *mem,
 294                                         off_t pg_start, int mask_type)
 295 {
 296         int i, j;
 297
 298         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 299                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 300                                phys_to_gart(page_to_phys(mem->pages[i])), mask_type),
 301                        intel_private.gtt+j);
 302         }
 303
 304         readl(intel_private.gtt+j-1);
 305 }
 306
 307 #endif
 308
 309 static int intel_i810_fetch_size(void)
 310 {
 311         u32 smram_miscc;
 312         struct aper_size_info_fixed *values;
 313
 314         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 315         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 316
 317         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 318                 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
 319                 return 0;
 320         }
 321         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 322                 agp_bridge->previous_size =
 323                         agp_bridge->current_size = (void *) (values + 1);
 324                 agp_bridge->aperture_size_idx = 1;
 325                 return values[1].size;
 326         } else {
 327                 agp_bridge->previous_size =
 328                         agp_bridge->current_size = (void *) (values);
 329                 agp_bridge->aperture_size_idx = 0;
 330                 return values[0].size;
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int intel_i810_configure(void)
 337 {
 338         struct aper_size_info_fixed *current_size;
 339         u32 temp;
 340         int i;
 341
 342         current_size = A_SIZE_FIX(agp_bridge->current_size);
 343
 344         if (!intel_private.registers) {
 345                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 346                 temp &= 0xfff80000;
 347
 348                 intel_private.registers = ioremap(temp, 128 * 4096);
 349                 if (!intel_private.registers) {
 350                         dev_err(&intel_private.pcidev->dev,
 351                                 "can't remap memory\n");
 352                         return -ENOMEM;
 353                 }
 354         }
 355
 356         if ((readl(intel_private.registers+I810_DRAM_CTL)
 357                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 358                 /* This will need to be dynamically assigned */
 359                 dev_info(&intel_private.pcidev->dev,
 360                          "detected 4MB dedicated video ram\n");
 361                 intel_private.num_dcache_entries = 1024;
 362         }
 363         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 364         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 365         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 366         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 367
 368         if (agp_bridge->driver->needs_scratch_page) {
 369                 for (i = 0; i < current_size->num_entries; i++) {
 370                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 371                 }
 372                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
 373         }
 374         global_cache_flush();
 375         return 0;
 376 }
 377
 378 static void intel_i810_cleanup(void)
 379 {
 380         writel(0, intel_private.registers+I810_PGETBL_CTL);
 381         readl(intel_private.registers); /* PCI Posting. */
 382         iounmap(intel_private.registers);
 383 }
 384
 385 static void intel_i810_tlbflush(struct agp_memory *mem)
 386 {
 387         return;
 388 }
 389
 390 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 391 {
 392         return;
 393 }
 394
 395 /* Exists to support ARGB cursors */
 396 static struct page *i8xx_alloc_pages(void)
 397 {
 398         struct page *page;
 399
 400         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 401         if (page == NULL)
 402                 return NULL;
 403
 404         if (set_pages_uc(page, 4) < 0) {
 405                 set_pages_wb(page, 4);
 406                 __free_pages(page, 2);
 407                 return NULL;
 408         }
 409         get_page(page);
 410         atomic_inc(&agp_bridge->current_memory_agp);
 411         return page;
 412 }
 413
 414 static void i8xx_destroy_pages(struct page *page)
 415 {
 416         if (page == NULL)
 417                 return;
 418
 419         set_pages_wb(page, 4);
 420         put_page(page);
 421         __free_pages(page, 2);
 422         atomic_dec(&agp_bridge->current_memory_agp);
 423 }
 424
 425 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 426                                         int type)
 427 {
 428         if (type < AGP_USER_TYPES)
 429                 return type;
 430         else if (type == AGP_USER_CACHED_MEMORY)
 431                 return INTEL_AGP_CACHED_MEMORY;
 432         else
 433                 return 0;
 434 }
 435
 436 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 437                                 int type)
 438 {
 439         int i, j, num_entries;
 440         void *temp;
 441         int ret = -EINVAL;
 442         int mask_type;
 443
 444         if (mem->page_count == 0)
 445                 goto out;
 446
 447         temp = agp_bridge->current_size;
 448         num_entries = A_SIZE_FIX(temp)->num_entries;
 449
 450         if ((pg_start + mem->page_count) > num_entries)
 451                 goto out_err;
 452
 453
 454         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 455                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 456                         ret = -EBUSY;
 457                         goto out_err;
 458                 }
 459         }
 460
 461         if (type != mem->type)
 462                 goto out_err;
 463
 464         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 465
 466         switch (mask_type) {
 467         case AGP_DCACHE_MEMORY:
 468                 if (!mem->is_flushed)
 469                         global_cache_flush();
 470                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 471                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 472                                intel_private.registers+I810_PTE_BASE+(i*4));
 473                 }
 474                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 475                 break;
 476         case AGP_PHYS_MEMORY:
 477         case AGP_NORMAL_MEMORY:
 478                 if (!mem->is_flushed)
 479                         global_cache_flush();
 480                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 481                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 482                                                                phys_to_gart(page_to_phys(mem->pages[i])),
 483                                                                mask_type),
 484                                intel_private.registers+I810_PTE_BASE+(j*4));
 485                 }
 486                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 487                 break;
 488         default:
 489                 goto out_err;
 490         }
 491
 492         agp_bridge->driver->tlb_flush(mem);
 493 out:
 494         ret = 0;
 495 out_err:
 496         mem->is_flushed = true;
 497         return ret;
 498 }
 499
 500 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 501                                 int type)
 502 {
 503         int i;
 504
 505         if (mem->page_count == 0)
 506                 return 0;
 507
 508         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 509                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 510         }
 511         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 512
 513         agp_bridge->driver->tlb_flush(mem);
 514         return 0;
 515 }
 516
 517 /*
 518  * The i810/i830 requires a physical address to program its mouse
 519  * pointer into hardware.
 520  * However the Xserver still writes to it through the agp aperture.
 521  */
 522 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 523 {
 524         struct agp_memory *new;
 525         struct page *page;
 526
 527         switch (pg_count) {
 528         case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
 529                 break;
 530         case 4:
 531                 /* kludge to get 4 physical pages for ARGB cursor */
 532                 page = i8xx_alloc_pages();
 533                 break;
 534         default:
 535                 return NULL;
 536         }
 537
 538         if (page == NULL)
 539                 return NULL;
 540
 541         new = agp_create_memory(pg_count);
 542         if (new == NULL)
 543                 return NULL;
 544
 545         new->pages[0] = page;
 546         if (pg_count == 4) {
 547                 /* kludge to get 4 physical pages for ARGB cursor */
 548                 new->pages[1] = new->pages[0] + 1;
 549                 new->pages[2] = new->pages[1] + 1;
 550                 new->pages[3] = new->pages[2] + 1;
 551         }
 552         new->page_count = pg_count;
 553         new->num_scratch_pages = pg_count;
 554         new->type = AGP_PHYS_MEMORY;
 555         new->physical = page_to_phys(new->pages[0]);
 556         return new;
 557 }
 558
 559 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 560 {
 561         struct agp_memory *new;
 562
 563         if (type == AGP_DCACHE_MEMORY) {
 564                 if (pg_count != intel_private.num_dcache_entries)
 565                         return NULL;
 566
 567                 new = agp_create_memory(1);
 568                 if (new == NULL)
 569                         return NULL;
 570
 571                 new->type = AGP_DCACHE_MEMORY;
 572                 new->page_count = pg_count;
 573                 new->num_scratch_pages = 0;
 574                 agp_free_page_array(new);
 575                 return new;
 576         }
 577         if (type == AGP_PHYS_MEMORY)
 578                 return alloc_agpphysmem_i8xx(pg_count, type);
 579         return NULL;
 580 }
 581
 582 static void intel_i810_free_by_type(struct agp_memory *curr)
 583 {
 584         agp_free_key(curr->key);
 585         if (curr->type == AGP_PHYS_MEMORY) {
 586                 if (curr->page_count == 4)
 587                         i8xx_destroy_pages(curr->pages[0]);
 588                 else {
 589                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 590                                                              AGP_PAGE_DESTROY_UNMAP);
 591                         agp_bridge->driver->agp_destroy_page(curr->pages[0],
 592                                                              AGP_PAGE_DESTROY_FREE);
 593                 }
 594                 agp_free_page_array(curr);
 595         }
 596         kfree(curr);
 597 }
 598
 599 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 600                                             dma_addr_t addr, int type)
 601 {
 602         /* Type checking must be done elsewhere */
 603         return addr | bridge->driver->masks[type].mask;
 604 }
 605
 606 static struct aper_size_info_fixed intel_i830_sizes[] =
 607 {
 608         {128, 32768, 5},
 609         /* The 64M mode still requires a 128k gatt */
 610         {64, 16384, 5},
 611         {256, 65536, 6},
 612         {512, 131072, 7},
 613 };
 614
 615 static void intel_i830_init_gtt_entries(void)
 616 {
 617         u16 gmch_ctrl;
 618         int gtt_entries;
 619         u8 rdct;
 620         int local = 0;
 621         static const int ddt[4] = { 0, 16, 32, 64 };
 622         int size; /* reserved space (in kb) at the top of stolen memory */
 623
 624         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 625
 626         if (IS_I965) {
 627                 u32 pgetbl_ctl;
 628                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 629
 630                 /* The 965 has a field telling us the size of the GTT,
 631                  * which may be larger than what is necessary to map the
 632                  * aperture.
 633                  */
 634                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 635                 case I965_PGETBL_SIZE_128KB:
 636                         size = 128;
 637                         break;
 638                 case I965_PGETBL_SIZE_256KB:
 639                         size = 256;
 640                         break;
 641                 case I965_PGETBL_SIZE_512KB:
 642                         size = 512;
 643                         break;
 644                 case I965_PGETBL_SIZE_1MB:
 645                         size = 1024;
 646                         break;
 647                 case I965_PGETBL_SIZE_2MB:
 648                         size = 2048;
 649                         break;
 650                 case I965_PGETBL_SIZE_1_5MB:
 651                         size = 1024 + 512;
 652                         break;
 653                 default:
 654                         dev_info(&intel_private.pcidev->dev,
 655                                  "unknown page table size, assuming 512KB\n");
 656                         size = 512;
 657                 }
 658                 size += 4; /* add in BIOS popup space */
 659         } else if (IS_G33 && !IS_IGD) {
 660         /* G33's GTT size defined in gmch_ctrl */
 661                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 662                 case G33_PGETBL_SIZE_1M:
 663                         size = 1024;
 664                         break;
 665                 case G33_PGETBL_SIZE_2M:
 666                         size = 2048;
 667                         break;
 668                 default:
 669                         dev_info(&agp_bridge->dev->dev,
 670                                  "unknown page table size 0x%x, assuming 512KB\n",
 671                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 672                         size = 512;
 673                 }
 674                 size += 4;
 675         } else if (IS_G4X || IS_IGD) {
 676                 /* On 4 series hardware, GTT stolen is separate from graphics
 677                  * stolen, ignore it in stolen gtt entries counting.  However,
 678                  * 4KB of the stolen memory doesn't get mapped to the GTT.
 679                  */
 680                 size = 4;
 681         } else {
 682                 /* On previous hardware, the GTT size was just what was
 683                  * required to map the aperture.
 684                  */
 685                 size = agp_bridge->driver->fetch_size() + 4;
 686         }
 687
 688         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 689             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 690                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 691                 case I830_GMCH_GMS_STOLEN_512:
 692                         gtt_entries = KB(512) - KB(size);
 693                         break;
 694                 case I830_GMCH_GMS_STOLEN_1024:
 695                         gtt_entries = MB(1) - KB(size);
 696                         break;
 697                 case I830_GMCH_GMS_STOLEN_8192:
 698                         gtt_entries = MB(8) - KB(size);
 699                         break;
 700                 case I830_GMCH_GMS_LOCAL:
 701                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 702                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 703                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 704                         local = 1;
 705                         break;
 706                 default:
 707                         gtt_entries = 0;
 708                         break;
 709                 }
 710         } else {
 711                 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
 712                 case I855_GMCH_GMS_STOLEN_1M:
 713                         gtt_entries = MB(1) - KB(size);
 714                         break;
 715                 case I855_GMCH_GMS_STOLEN_4M:
 716                         gtt_entries = MB(4) - KB(size);
 717                         break;
 718                 case I855_GMCH_GMS_STOLEN_8M:
 719                         gtt_entries = MB(8) - KB(size);
 720                         break;
 721                 case I855_GMCH_GMS_STOLEN_16M:
 722                         gtt_entries = MB(16) - KB(size);
 723                         break;
 724                 case I855_GMCH_GMS_STOLEN_32M:
 725                         gtt_entries = MB(32) - KB(size);
 726                         break;
 727                 case I915_GMCH_GMS_STOLEN_48M:
 728                         /* Check it's really I915G */
 729                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 730                                 gtt_entries = MB(48) - KB(size);
 731                         else
 732                                 gtt_entries = 0;
 733                         break;
 734                 case I915_GMCH_GMS_STOLEN_64M:
 735                         /* Check it's really I915G */
 736                         if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
 737                                 gtt_entries = MB(64) - KB(size);
 738                         else
 739                                 gtt_entries = 0;
 740                         break;
 741                 case G33_GMCH_GMS_STOLEN_128M:
 742                         if (IS_G33 || IS_I965 || IS_G4X)
 743                                 gtt_entries = MB(128) - KB(size);
 744                         else
 745                                 gtt_entries = 0;
 746                         break;
 747                 case G33_GMCH_GMS_STOLEN_256M:
 748                         if (IS_G33 || IS_I965 || IS_G4X)
 749                                 gtt_entries = MB(256) - KB(size);
 750                         else
 751                                 gtt_entries = 0;
 752                         break;
 753                 case INTEL_GMCH_GMS_STOLEN_96M:
 754                         if (IS_I965 || IS_G4X)
 755                                 gtt_entries = MB(96) - KB(size);
 756                         else
 757                                 gtt_entries = 0;
 758                         break;
 759                 case INTEL_GMCH_GMS_STOLEN_160M:
 760                         if (IS_I965 || IS_G4X)
 761                                 gtt_entries = MB(160) - KB(size);
 762                         else
 763                                 gtt_entries = 0;
 764                         break;
 765                 case INTEL_GMCH_GMS_STOLEN_224M:
 766                         if (IS_I965 || IS_G4X)
 767                                 gtt_entries = MB(224) - KB(size);
 768                         else
 769                                 gtt_entries = 0;
 770                         break;
 771                 case INTEL_GMCH_GMS_STOLEN_352M:
 772                         if (IS_I965 || IS_G4X)
 773                                 gtt_entries = MB(352) - KB(size);
 774                         else
 775                                 gtt_entries = 0;
 776                         break;
 777                 default:
 778                         gtt_entries = 0;
 779                         break;
 780                 }
 781         }
 782         if (gtt_entries > 0) {
 783                 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
 784                        gtt_entries / KB(1), local ? "local" : "stolen");
 785                 gtt_entries /= KB(4);
 786         } else {
 787                 dev_info(&agp_bridge->dev->dev,
 788                        "no pre-allocated video memory detected\n");
 789                 gtt_entries = 0;
 790         }
 791
 792         intel_private.gtt_entries = gtt_entries;
 793 }
 794
 795 static void intel_i830_fini_flush(void)
 796 {
 797         kunmap(intel_private.i8xx_page);
 798         intel_private.i8xx_flush_page = NULL;
 799         unmap_page_from_agp(intel_private.i8xx_page);
 800
 801         __free_page(intel_private.i8xx_page);
 802         intel_private.i8xx_page = NULL;
 803 }
 804
 805 static void intel_i830_setup_flush(void)
 806 {
 807         /* return if we've already set the flush mechanism up */
 808         if (intel_private.i8xx_page)
 809                 return;
 810
 811         intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
 812         if (!intel_private.i8xx_page)
 813                 return;
 814
 815         /* make page uncached */
 816         map_page_into_agp(intel_private.i8xx_page);
 817
 818         intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
 819         if (!intel_private.i8xx_flush_page)
 820                 intel_i830_fini_flush();
 821 }
 822
 823 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
 824 {
 825         unsigned int *pg = intel_private.i8xx_flush_page;
 826         int i;
 827
 828         for (i = 0; i < 256; i += 2)
 829                 *(pg + i) = i;
 830
 831         wmb();
 832 }
 833
 834 /* The intel i830 automatically initializes the agp aperture during POST.
 835  * Use the memory already set aside for in the GTT.
 836  */
 837 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 838 {
 839         int page_order;
 840         struct aper_size_info_fixed *size;
 841         int num_entries;
 842         u32 temp;
 843
 844         size = agp_bridge->current_size;
 845         page_order = size->page_order;
 846         num_entries = size->num_entries;
 847         agp_bridge->gatt_table_real = NULL;
 848
 849         pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 850         temp &= 0xfff80000;
 851
 852         intel_private.registers = ioremap(temp, 128 * 4096);
 853         if (!intel_private.registers)
 854                 return -ENOMEM;
 855
 856         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 857         global_cache_flush();   /* FIXME: ?? */
 858
 859         /* we have to call this as early as possible after the MMIO base address is known */
 860         intel_i830_init_gtt_entries();
 861
 862         agp_bridge->gatt_table = NULL;
 863
 864         agp_bridge->gatt_bus_addr = temp;
 865
 866         return 0;
 867 }
 868
 869 /* Return the gatt table to a sane state. Use the top of stolen
 870  * memory for the GTT.
 871  */
 872 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 873 {
 874         return 0;
 875 }
 876
 877 static int intel_i830_fetch_size(void)
 878 {
 879         u16 gmch_ctrl;
 880         struct aper_size_info_fixed *values;
 881
 882         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 883
 884         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 885             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 886                 /* 855GM/852GM/865G has 128MB aperture size */
 887                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 888                 agp_bridge->aperture_size_idx = 0;
 889                 return values[0].size;
 890         }
 891
 892         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 893
 894         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 895                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 896                 agp_bridge->aperture_size_idx = 0;
 897                 return values[0].size;
 898         } else {
 899                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 900                 agp_bridge->aperture_size_idx = 1;
 901                 return values[1].size;
 902         }
 903
 904         return 0;
 905 }
 906
 907 static int intel_i830_configure(void)
 908 {
 909         struct aper_size_info_fixed *current_size;
 910         u32 temp;
 911         u16 gmch_ctrl;
 912         int i;
 913
 914         current_size = A_SIZE_FIX(agp_bridge->current_size);
 915
 916         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 917         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 918
 919         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
 920         gmch_ctrl |= I830_GMCH_ENABLED;
 921         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
 922
 923         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 924         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 925
 926         if (agp_bridge->driver->needs_scratch_page) {
 927                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 928                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 929                 }
 930                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
 931         }
 932
 933         global_cache_flush();
 934
 935         intel_i830_setup_flush();
 936         return 0;
 937 }
 938
 939 static void intel_i830_cleanup(void)
 940 {
 941         iounmap(intel_private.registers);
 942 }
 943
 944 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
 945                                      int type)
 946 {
 947         int i, j, num_entries;
 948         void *temp;
 949         int ret = -EINVAL;
 950         int mask_type;
 951
 952         if (mem->page_count == 0)
 953                 goto out;
 954
 955         temp = agp_bridge->current_size;
 956         num_entries = A_SIZE_FIX(temp)->num_entries;
 957
 958         if (pg_start < intel_private.gtt_entries) {
 959                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
 960                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
 961                            pg_start, intel_private.gtt_entries);
 962
 963                 dev_info(&intel_private.pcidev->dev,
 964                          "trying to insert into local/stolen memory\n");
 965                 goto out_err;
 966         }
 967
 968         if ((pg_start + mem->page_count) > num_entries)
 969                 goto out_err;
 970
 971         /* The i830 can't check the GTT for entries since its read only,
 972          * depend on the caller to make the correct offset decisions.
 973          */
 974
 975         if (type != mem->type)
 976                 goto out_err;
 977
 978         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 979
 980         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 981             mask_type != INTEL_AGP_CACHED_MEMORY)
 982                 goto out_err;
 983
 984         if (!mem->is_flushed)
 985                 global_cache_flush();
 986
 987         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 988                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 989                                phys_to_gart(page_to_phys(mem->pages[i])), mask_type),
 990                        intel_private.registers+I810_PTE_BASE+(j*4));
 991         }
 992         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 993         agp_bridge->driver->tlb_flush(mem);
 994
 995 out:
 996         ret = 0;
 997 out_err:
 998         mem->is_flushed = true;
 999         return ret;
1000 }
1001
1002 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
1003                                      int type)
1004 {
1005         int i;
1006
1007         if (mem->page_count == 0)
1008                 return 0;
1009
1010         if (pg_start < intel_private.gtt_entries) {
1011                 dev_info(&intel_private.pcidev->dev,
1012                          "trying to disable local/stolen memory\n");
1013                 return -EINVAL;
1014         }
1015
1016         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
1017                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
1018         }
1019         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
1020
1021         agp_bridge->driver->tlb_flush(mem);
1022         return 0;
1023 }
1024
1025 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
1026 {
1027         if (type == AGP_PHYS_MEMORY)
1028                 return alloc_agpphysmem_i8xx(pg_count, type);
1029         /* always return NULL for other allocation types for now */
1030         return NULL;
1031 }
1032
1033 static int intel_alloc_chipset_flush_resource(void)
1034 {
1035         int ret;
1036         ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
1037                                      PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
1038                                      pcibios_align_resource, agp_bridge->dev);
1039
1040         return ret;
1041 }
1042
1043 static void intel_i915_setup_chipset_flush(void)
1044 {
1045         int ret;
1046         u32 temp;
1047
1048         pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
1049         if (!(temp & 0x1)) {
1050                 intel_alloc_chipset_flush_resource();
1051                 intel_private.resource_valid = 1;
1052                 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1053         } else {
1054                 temp &= ~1;
1055
1056                 intel_private.resource_valid = 1;
1057                 intel_private.ifp_resource.start = temp;
1058                 intel_private.ifp_resource.end = temp + PAGE_SIZE;
1059                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1060                 /* some BIOSes reserve this area in a pnp some don't */
1061                 if (ret)
1062                         intel_private.resource_valid = 0;
1063         }
1064 }
1065
1066 static void intel_i965_g33_setup_chipset_flush(void)
1067 {
1068         u32 temp_hi, temp_lo;
1069         int ret;
1070
1071         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
1072         pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
1073
1074         if (!(temp_lo & 0x1)) {
1075
1076                 intel_alloc_chipset_flush_resource();
1077
1078                 intel_private.resource_valid = 1;
1079                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
1080                         upper_32_bits(intel_private.ifp_resource.start));
1081                 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
1082         } else {
1083                 u64 l64;
1084
1085                 temp_lo &= ~0x1;
1086                 l64 = ((u64)temp_hi << 32) | temp_lo;
1087
1088                 intel_private.resource_valid = 1;
1089                 intel_private.ifp_resource.start = l64;
1090                 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
1091                 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
1092                 /* some BIOSes reserve this area in a pnp some don't */
1093                 if (ret)
1094                         intel_private.resource_valid = 0;
1095         }
1096 }
1097
1098 static void intel_i9xx_setup_flush(void)
1099 {
1100         /* return if already configured */
1101         if (intel_private.ifp_resource.start)
1102                 return;
1103
1104         /* setup a resource for this object */
1105         intel_private.ifp_resource.name = "Intel Flush Page";
1106         intel_private.ifp_resource.flags = IORESOURCE_MEM;
1107
1108         /* Setup chipset flush for 915 */
1109         if (IS_I965 || IS_G33 || IS_G4X) {
1110                 intel_i965_g33_setup_chipset_flush();
1111         } else {
1112                 intel_i915_setup_chipset_flush();
1113         }
1114
1115         if (intel_private.ifp_resource.start) {
1116                 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
1117                 if (!intel_private.i9xx_flush_page)
1118                         dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
1119         }
1120 }
1121
1122 static int intel_i915_configure(void)
1123 {
1124         struct aper_size_info_fixed *current_size;
1125         u32 temp;
1126         u16 gmch_ctrl;
1127         int i;
1128
1129         current_size = A_SIZE_FIX(agp_bridge->current_size);
1130
1131         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
1132
1133         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1134
1135         pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1136         gmch_ctrl |= I830_GMCH_ENABLED;
1137         pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1138
1139         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1140         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1141
1142         if (agp_bridge->driver->needs_scratch_page) {
1143                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1144                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
1145                 }
1146                 readl(intel_private.gtt+i-1);   /* PCI Posting. */
1147         }
1148
1149         global_cache_flush();
1150
1151         intel_i9xx_setup_flush();
1152
1153         return 0;
1154 }
1155
1156 static void intel_i915_cleanup(void)
1157 {
1158         if (intel_private.i9xx_flush_page)
1159                 iounmap(intel_private.i9xx_flush_page);
1160         if (intel_private.resource_valid)
1161                 release_resource(&intel_private.ifp_resource);
1162         intel_private.ifp_resource.start = 0;
1163         intel_private.resource_valid = 0;
1164         iounmap(intel_private.gtt);
1165         iounmap(intel_private.registers);
1166 }
1167
1168 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1169 {
1170         if (intel_private.i9xx_flush_page)
1171                 writel(1, intel_private.i9xx_flush_page);
1172 }
1173
1174 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1175                                      int type)
1176 {
1177         int num_entries;
1178         void *temp;
1179         int ret = -EINVAL;
1180         int mask_type;
1181
1182         if (mem->page_count == 0)
1183                 goto out;
1184
1185         temp = agp_bridge->current_size;
1186         num_entries = A_SIZE_FIX(temp)->num_entries;
1187
1188         if (pg_start < intel_private.gtt_entries) {
1189                 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1190                            "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1191                            pg_start, intel_private.gtt_entries);
1192
1193                 dev_info(&intel_private.pcidev->dev,
1194                          "trying to insert into local/stolen memory\n");
1195                 goto out_err;
1196         }
1197
1198         if ((pg_start + mem->page_count) > num_entries)
1199                 goto out_err;
1200
1201         /* The i915 can't check the GTT for entries since it's read only;
1202          * depend on the caller to make the correct offset decisions.
1203          */
1204
1205         if (type != mem->type)
1206                 goto out_err;
1207
1208         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1209
1210         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1211             mask_type != INTEL_AGP_CACHED_MEMORY)
1212                 goto out_err;
1213
1214         if (!mem->is_flushed)
1215                 global_cache_flush();
1216
1217         intel_agp_insert_sg_entries(mem, pg_start, mask_type);
1218         agp_bridge->driver->tlb_flush(mem);
1219
1220  out:
1221         ret = 0;
1222  out_err:
1223         mem->is_flushed = true;
1224         return ret;
1225 }
1226
1227 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1228                                      int type)
1229 {
1230         int i;
1231
1232         if (mem->page_count == 0)
1233                 return 0;
1234
1235         if (pg_start < intel_private.gtt_entries) {
1236                 dev_info(&intel_private.pcidev->dev,
1237                          "trying to disable local/stolen memory\n");
1238                 return -EINVAL;
1239         }
1240
1241         for (i = pg_start; i < (mem->page_count + pg_start); i++)
1242                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1243
1244         readl(intel_private.gtt+i-1);
1245
1246         agp_bridge->driver->tlb_flush(mem);
1247         return 0;
1248 }
1249
1250 /* Return the aperture size by just checking the resource length.  The effect
1251  * described in the spec of the MSAC registers is just changing of the
1252  * resource size.
1253  */
1254 static int intel_i9xx_fetch_size(void)
1255 {
1256         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1257         int aper_size; /* size in megabytes */
1258         int i;
1259
1260         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1261
1262         for (i = 0; i < num_sizes; i++) {
1263                 if (aper_size == intel_i830_sizes[i].size) {
1264                         agp_bridge->current_size = intel_i830_sizes + i;
1265                         agp_bridge->previous_size = agp_bridge->current_size;
1266                         return aper_size;
1267                 }
1268         }
1269
1270         return 0;
1271 }
1272
1273 /* The intel i915 automatically initializes the agp aperture during POST.
1274  * Use the memory already set aside for in the GTT.
1275  */
1276 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1277 {
1278         int page_order;
1279         struct aper_size_info_fixed *size;
1280         int num_entries;
1281         u32 temp, temp2;
1282         int gtt_map_size = 256 * 1024;
1283
1284         size = agp_bridge->current_size;
1285         page_order = size->page_order;
1286         num_entries = size->num_entries;
1287         agp_bridge->gatt_table_real = NULL;
1288
1289         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1290         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1291
1292         if (IS_G33)
1293             gtt_map_size = 1024 * 1024; /* 1M on G33 */
1294         intel_private.gtt = ioremap(temp2, gtt_map_size);
1295         if (!intel_private.gtt)
1296                 return -ENOMEM;
1297
1298         temp &= 0xfff80000;
1299
1300         intel_private.registers = ioremap(temp, 128 * 4096);
1301         if (!intel_private.registers) {
1302                 iounmap(intel_private.gtt);
1303                 return -ENOMEM;
1304         }
1305
1306         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1307         global_cache_flush();   /* FIXME: ? */
1308
1309         /* we have to call this as early as possible after the MMIO base address is known */
1310         intel_i830_init_gtt_entries();
1311
1312         agp_bridge->gatt_table = NULL;
1313
1314         agp_bridge->gatt_bus_addr = temp;
1315
1316         return 0;
1317 }
1318
1319 /*
1320  * The i965 supports 36-bit physical addresses, but to keep
1321  * the format of the GTT the same, the bits that don't fit
1322  * in a 32-bit word are shifted down to bits 4..7.
1323  *
1324  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1325  * is always zero on 32-bit architectures, so no need to make
1326  * this conditional.
1327  */
1328 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1329                                             dma_addr_t addr, int type)
1330 {
1331         /* Shift high bits down */
1332         addr |= (addr >> 28) & 0xf0;
1333
1334         /* Type checking must be done elsewhere */
1335         return addr | bridge->driver->masks[type].mask;
1336 }
1337
1338 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1339 {
1340         switch (agp_bridge->dev->device) {
1341         case PCI_DEVICE_ID_INTEL_GM45_HB:
1342         case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1343         case PCI_DEVICE_ID_INTEL_Q45_HB:
1344         case PCI_DEVICE_ID_INTEL_G45_HB:
1345         case PCI_DEVICE_ID_INTEL_G41_HB:
1346         case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1347         case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1348                 *gtt_offset = *gtt_size = MB(2);
1349                 break;
1350         default:
1351                 *gtt_offset = *gtt_size = KB(512);
1352         }
1353 }
1354
1355 /* The intel i965 automatically initializes the agp aperture during POST.
1356  * Use the memory already set aside for in the GTT.
1357  */
1358 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1359 {
1360         int page_order;
1361         struct aper_size_info_fixed *size;
1362         int num_entries;
1363         u32 temp;
1364         int gtt_offset, gtt_size;
1365
1366         size = agp_bridge->current_size;
1367         page_order = size->page_order;
1368         num_entries = size->num_entries;
1369         agp_bridge->gatt_table_real = NULL;
1370
1371         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1372
1373         temp &= 0xfff00000;
1374
1375         intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1376
1377         intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1378
1379         if (!intel_private.gtt)
1380                 return -ENOMEM;
1381
1382         intel_private.registers = ioremap(temp, 128 * 4096);
1383         if (!intel_private.registers) {
1384                 iounmap(intel_private.gtt);
1385                 return -ENOMEM;
1386         }
1387
1388         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1389         global_cache_flush();   /* FIXME: ? */
1390
1391         /* we have to call this as early as possible after the MMIO base address is known */
1392         intel_i830_init_gtt_entries();
1393
1394         agp_bridge->gatt_table = NULL;
1395
1396         agp_bridge->gatt_bus_addr = temp;
1397
1398         return 0;
1399 }
1400
1401
1402 static int intel_fetch_size(void)
1403 {
1404         int i;
1405         u16 temp;
1406         struct aper_size_info_16 *values;
1407
1408         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1409         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1410
1411         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1412                 if (temp == values[i].size_value) {
1413                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1414                         agp_bridge->aperture_size_idx = i;
1415                         return values[i].size;
1416                 }
1417         }
1418
1419         return 0;
1420 }
1421
1422 static int __intel_8xx_fetch_size(u8 temp)
1423 {
1424         int i;
1425         struct aper_size_info_8 *values;
1426
1427         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1428
1429         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1430                 if (temp == values[i].size_value) {
1431                         agp_bridge->previous_size =
1432                                 agp_bridge->current_size = (void *) (values + i);
1433                         agp_bridge->aperture_size_idx = i;
1434                         return values[i].size;
1435                 }
1436         }
1437         return 0;
1438 }
1439
1440 static int intel_8xx_fetch_size(void)
1441 {
1442         u8 temp;
1443
1444         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1445         return __intel_8xx_fetch_size(temp);
1446 }
1447
1448 static int intel_815_fetch_size(void)
1449 {
1450         u8 temp;
1451
1452         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1453          * one non-reserved bit, so mask the others out ... */
1454         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1455         temp &= (1 << 3);
1456
1457         return __intel_8xx_fetch_size(temp);
1458 }
1459
1460 static void intel_tlbflush(struct agp_memory *mem)
1461 {
1462         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1463         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1464 }
1465
1466
1467 static void intel_8xx_tlbflush(struct agp_memory *mem)
1468 {
1469         u32 temp;
1470         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1471         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1472         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1473         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1474 }
1475
1476
1477 static void intel_cleanup(void)
1478 {
1479         u16 temp;
1480         struct aper_size_info_16 *previous_size;
1481
1482         previous_size = A_SIZE_16(agp_bridge->previous_size);
1483         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1484         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1485         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1486 }
1487
1488
1489 static void intel_8xx_cleanup(void)
1490 {
1491         u16 temp;
1492         struct aper_size_info_8 *previous_size;
1493
1494         previous_size = A_SIZE_8(agp_bridge->previous_size);
1495         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1496         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1497         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1498 }
1499
1500
1501 static int intel_configure(void)
1502 {
1503         u32 temp;
1504         u16 temp2;
1505         struct aper_size_info_16 *current_size;
1506
1507         current_size = A_SIZE_16(agp_bridge->current_size);
1508
1509         /* aperture size */
1510         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1511
1512         /* address to map to */
1513         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1514         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1515
1516         /* attbase - aperture base */
1517         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1518
1519         /* agpctrl */
1520         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1521
1522         /* paccfg/nbxcfg */
1523         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1524         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1525                         (temp2 & ~(1 << 10)) | (1 << 9));
1526         /* clear any possible error conditions */
1527         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1528         return 0;
1529 }
1530
1531 static int intel_815_configure(void)
1532 {
1533         u32 temp, addr;
1534         u8 temp2;
1535         struct aper_size_info_8 *current_size;
1536
1537         /* attbase - aperture base */
1538         /* the Intel 815 chipset spec. says that bits 29-31 in the
1539         * ATTBASE register are reserved -> try not to write them */
1540         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1541                 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1542                 return -EINVAL;
1543         }
1544
1545         current_size = A_SIZE_8(agp_bridge->current_size);
1546
1547         /* aperture size */
1548         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1549                         current_size->size_value);
1550
1551         /* address to map to */
1552         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1553         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1554
1555         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1556         addr &= INTEL_815_ATTBASE_MASK;
1557         addr |= agp_bridge->gatt_bus_addr;
1558         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1559
1560         /* agpctrl */
1561         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1562
1563         /* apcont */
1564         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1565         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1566
1567         /* clear any possible error conditions */
1568         /* Oddness : this chipset seems to have no ERRSTS register ! */
1569         return 0;
1570 }
1571
1572 static void intel_820_tlbflush(struct agp_memory *mem)
1573 {
1574         return;
1575 }
1576
1577 static void intel_820_cleanup(void)
1578 {
1579         u8 temp;
1580         struct aper_size_info_8 *previous_size;
1581
1582         previous_size = A_SIZE_8(agp_bridge->previous_size);
1583         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1584         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1585                         temp & ~(1 << 1));
1586         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1587                         previous_size->size_value);
1588 }
1589
1590
1591 static int intel_820_configure(void)
1592 {
1593         u32 temp;
1594         u8 temp2;
1595         struct aper_size_info_8 *current_size;
1596
1597         current_size = A_SIZE_8(agp_bridge->current_size);
1598
1599         /* aperture size */
1600         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1601
1602         /* address to map to */
1603         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1604         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1605
1606         /* attbase - aperture base */
1607         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1608
1609         /* agpctrl */
1610         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1611
1612         /* global enable aperture access */
1613         /* This flag is not accessed through MCHCFG register as in */
1614         /* i850 chipset. */
1615         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1616         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1617         /* clear any possible AGP-related error conditions */
1618         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1619         return 0;
1620 }
1621
1622 static int intel_840_configure(void)
1623 {
1624         u32 temp;
1625         u16 temp2;
1626         struct aper_size_info_8 *current_size;
1627
1628         current_size = A_SIZE_8(agp_bridge->current_size);
1629
1630         /* aperture size */
1631         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1632
1633         /* address to map to */
1634         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1635         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1636
1637         /* attbase - aperture base */
1638         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1639
1640         /* agpctrl */
1641         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1642
1643         /* mcgcfg */
1644         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1645         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1646         /* clear any possible error conditions */
1647         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1648         return 0;
1649 }
1650
1651 static int intel_845_configure(void)
1652 {
1653         u32 temp;
1654         u8 temp2;
1655         struct aper_size_info_8 *current_size;
1656
1657         current_size = A_SIZE_8(agp_bridge->current_size);
1658
1659         /* aperture size */
1660         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1661
1662         if (agp_bridge->apbase_config != 0) {
1663                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1664                                        agp_bridge->apbase_config);
1665         } else {
1666                 /* address to map to */
1667                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1668                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1669                 agp_bridge->apbase_config = temp;
1670         }
1671
1672         /* attbase - aperture base */
1673         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1674
1675         /* agpctrl */
1676         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1677
1678         /* agpm */
1679         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1680         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1681         /* clear any possible error conditions */
1682         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1683
1684         intel_i830_setup_flush();
1685         return 0;
1686 }
1687
1688 static int intel_850_configure(void)
1689 {
1690         u32 temp;
1691         u16 temp2;
1692         struct aper_size_info_8 *current_size;
1693
1694         current_size = A_SIZE_8(agp_bridge->current_size);
1695
1696         /* aperture size */
1697         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1698
1699         /* address to map to */
1700         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1701         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1702
1703         /* attbase - aperture base */
1704         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1705
1706         /* agpctrl */
1707         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1708
1709         /* mcgcfg */
1710         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1711         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1712         /* clear any possible AGP-related error conditions */
1713         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1714         return 0;
1715 }
1716
1717 static int intel_860_configure(void)
1718 {
1719         u32 temp;
1720         u16 temp2;
1721         struct aper_size_info_8 *current_size;
1722
1723         current_size = A_SIZE_8(agp_bridge->current_size);
1724
1725         /* aperture size */
1726         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1727
1728         /* address to map to */
1729         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1730         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1731
1732         /* attbase - aperture base */
1733         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1734
1735         /* agpctrl */
1736         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1737
1738         /* mcgcfg */
1739         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1740         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1741         /* clear any possible AGP-related error conditions */
1742         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1743         return 0;
1744 }
1745
1746 static int intel_830mp_configure(void)
1747 {
1748         u32 temp;
1749         u16 temp2;
1750         struct aper_size_info_8 *current_size;
1751
1752         current_size = A_SIZE_8(agp_bridge->current_size);
1753
1754         /* aperture size */
1755         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1756
1757         /* address to map to */
1758         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1759         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1760
1761         /* attbase - aperture base */
1762         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1763
1764         /* agpctrl */
1765         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1766
1767         /* gmch */
1768         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1769         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1770         /* clear any possible AGP-related error conditions */
1771         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1772         return 0;
1773 }
1774
1775 static int intel_7505_configure(void)
1776 {
1777         u32 temp;
1778         u16 temp2;
1779         struct aper_size_info_8 *current_size;
1780
1781         current_size = A_SIZE_8(agp_bridge->current_size);
1782
1783         /* aperture size */
1784         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1785
1786         /* address to map to */
1787         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1788         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1789
1790         /* attbase - aperture base */
1791         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1792
1793         /* agpctrl */
1794         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1795
1796         /* mchcfg */
1797         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1798         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1799
1800         return 0;
1801 }
1802
1803 /* Setup function */
1804 static const struct gatt_mask intel_generic_masks[] =
1805 {
1806         {.mask = 0x00000017, .type = 0}
1807 };
1808
1809 static const struct aper_size_info_8 intel_815_sizes[2] =
1810 {
1811         {64, 16384, 4, 0},
1812         {32, 8192, 3, 8},
1813 };
1814
1815 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1816 {
1817         {256, 65536, 6, 0},
1818         {128, 32768, 5, 32},
1819         {64, 16384, 4, 48},
1820         {32, 8192, 3, 56},
1821         {16, 4096, 2, 60},
1822         {8, 2048, 1, 62},
1823         {4, 1024, 0, 63}
1824 };
1825
1826 static const struct aper_size_info_16 intel_generic_sizes[7] =
1827 {
1828         {256, 65536, 6, 0},
1829         {128, 32768, 5, 32},
1830         {64, 16384, 4, 48},
1831         {32, 8192, 3, 56},
1832         {16, 4096, 2, 60},
1833         {8, 2048, 1, 62},
1834         {4, 1024, 0, 63}
1835 };
1836
1837 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1838 {
1839         {256, 65536, 6, 0},
1840         {128, 32768, 5, 32},
1841         {64, 16384, 4, 48},
1842         {32, 8192, 3, 56}
1843 };
1844
1845 static const struct agp_bridge_driver intel_generic_driver = {
1846         .owner                  = THIS_MODULE,
1847         .aperture_sizes         = intel_generic_sizes,
1848         .size_type              = U16_APER_SIZE,
1849         .num_aperture_sizes     = 7,
1850         .configure              = intel_configure,
1851         .fetch_size             = intel_fetch_size,
1852         .cleanup                = intel_cleanup,
1853         .tlb_flush              = intel_tlbflush,
1854         .mask_memory            = agp_generic_mask_memory,
1855         .masks                  = intel_generic_masks,
1856         .agp_enable             = agp_generic_enable,
1857         .cache_flush            = global_cache_flush,
1858         .create_gatt_table      = agp_generic_create_gatt_table,
1859         .free_gatt_table        = agp_generic_free_gatt_table,
1860         .insert_memory          = agp_generic_insert_memory,
1861         .remove_memory          = agp_generic_remove_memory,
1862         .alloc_by_type          = agp_generic_alloc_by_type,
1863         .free_by_type           = agp_generic_free_by_type,
1864         .agp_alloc_page         = agp_generic_alloc_page,
1865         .agp_alloc_pages        = agp_generic_alloc_pages,
1866         .agp_destroy_page       = agp_generic_destroy_page,
1867         .agp_destroy_pages      = agp_generic_destroy_pages,
1868         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1869 };
1870
1871 static const struct agp_bridge_driver intel_810_driver = {
1872         .owner                  = THIS_MODULE,
1873         .aperture_sizes         = intel_i810_sizes,
1874         .size_type              = FIXED_APER_SIZE,
1875         .num_aperture_sizes     = 2,
1876         .needs_scratch_page     = true,
1877         .configure              = intel_i810_configure,
1878         .fetch_size             = intel_i810_fetch_size,
1879         .cleanup                = intel_i810_cleanup,
1880         .tlb_flush              = intel_i810_tlbflush,
1881         .mask_memory            = intel_i810_mask_memory,
1882         .masks                  = intel_i810_masks,
1883         .agp_enable             = intel_i810_agp_enable,
1884         .cache_flush            = global_cache_flush,
1885         .create_gatt_table      = agp_generic_create_gatt_table,
1886         .free_gatt_table        = agp_generic_free_gatt_table,
1887         .insert_memory          = intel_i810_insert_entries,
1888         .remove_memory          = intel_i810_remove_entries,
1889         .alloc_by_type          = intel_i810_alloc_by_type,
1890         .free_by_type           = intel_i810_free_by_type,
1891         .agp_alloc_page         = agp_generic_alloc_page,
1892         .agp_alloc_pages        = agp_generic_alloc_pages,
1893         .agp_destroy_page       = agp_generic_destroy_page,
1894         .agp_destroy_pages      = agp_generic_destroy_pages,
1895         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1896 };
1897
1898 static const struct agp_bridge_driver intel_815_driver = {
1899         .owner                  = THIS_MODULE,
1900         .aperture_sizes         = intel_815_sizes,
1901         .size_type              = U8_APER_SIZE,
1902         .num_aperture_sizes     = 2,
1903         .configure              = intel_815_configure,
1904         .fetch_size             = intel_815_fetch_size,
1905         .cleanup                = intel_8xx_cleanup,
1906         .tlb_flush              = intel_8xx_tlbflush,
1907         .mask_memory            = agp_generic_mask_memory,
1908         .masks                  = intel_generic_masks,
1909         .agp_enable             = agp_generic_enable,
1910         .cache_flush            = global_cache_flush,
1911         .create_gatt_table      = agp_generic_create_gatt_table,
1912         .free_gatt_table        = agp_generic_free_gatt_table,
1913         .insert_memory          = agp_generic_insert_memory,
1914         .remove_memory          = agp_generic_remove_memory,
1915         .alloc_by_type          = agp_generic_alloc_by_type,
1916         .free_by_type           = agp_generic_free_by_type,
1917         .agp_alloc_page         = agp_generic_alloc_page,
1918         .agp_alloc_pages        = agp_generic_alloc_pages,
1919         .agp_destroy_page       = agp_generic_destroy_page,
1920         .agp_destroy_pages      = agp_generic_destroy_pages,
1921         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1922 };
1923
1924 static const struct agp_bridge_driver intel_830_driver = {
1925         .owner                  = THIS_MODULE,
1926         .aperture_sizes         = intel_i830_sizes,
1927         .size_type              = FIXED_APER_SIZE,
1928         .num_aperture_sizes     = 4,
1929         .needs_scratch_page     = true,
1930         .configure              = intel_i830_configure,
1931         .fetch_size             = intel_i830_fetch_size,
1932         .cleanup                = intel_i830_cleanup,
1933         .tlb_flush              = intel_i810_tlbflush,
1934         .mask_memory            = intel_i810_mask_memory,
1935         .masks                  = intel_i810_masks,
1936         .agp_enable             = intel_i810_agp_enable,
1937         .cache_flush            = global_cache_flush,
1938         .create_gatt_table      = intel_i830_create_gatt_table,
1939         .free_gatt_table        = intel_i830_free_gatt_table,
1940         .insert_memory          = intel_i830_insert_entries,
1941         .remove_memory          = intel_i830_remove_entries,
1942         .alloc_by_type          = intel_i830_alloc_by_type,
1943         .free_by_type           = intel_i810_free_by_type,
1944         .agp_alloc_page         = agp_generic_alloc_page,
1945         .agp_alloc_pages        = agp_generic_alloc_pages,
1946         .agp_destroy_page       = agp_generic_destroy_page,
1947         .agp_destroy_pages      = agp_generic_destroy_pages,
1948         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1949         .chipset_flush          = intel_i830_chipset_flush,
1950 };
1951
1952 static const struct agp_bridge_driver intel_820_driver = {
1953         .owner                  = THIS_MODULE,
1954         .aperture_sizes         = intel_8xx_sizes,
1955         .size_type              = U8_APER_SIZE,
1956         .num_aperture_sizes     = 7,
1957         .configure              = intel_820_configure,
1958         .fetch_size             = intel_8xx_fetch_size,
1959         .cleanup                = intel_820_cleanup,
1960         .tlb_flush              = intel_820_tlbflush,
1961         .mask_memory            = agp_generic_mask_memory,
1962         .masks                  = intel_generic_masks,
1963         .agp_enable             = agp_generic_enable,
1964         .cache_flush            = global_cache_flush,
1965         .create_gatt_table      = agp_generic_create_gatt_table,
1966         .free_gatt_table        = agp_generic_free_gatt_table,
1967         .insert_memory          = agp_generic_insert_memory,
1968         .remove_memory          = agp_generic_remove_memory,
1969         .alloc_by_type          = agp_generic_alloc_by_type,
1970         .free_by_type           = agp_generic_free_by_type,
1971         .agp_alloc_page         = agp_generic_alloc_page,
1972         .agp_alloc_pages        = agp_generic_alloc_pages,
1973         .agp_destroy_page       = agp_generic_destroy_page,
1974         .agp_destroy_pages      = agp_generic_destroy_pages,
1975         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1976 };
1977
1978 static const struct agp_bridge_driver intel_830mp_driver = {
1979         .owner                  = THIS_MODULE,
1980         .aperture_sizes         = intel_830mp_sizes,
1981         .size_type              = U8_APER_SIZE,
1982         .num_aperture_sizes     = 4,
1983         .configure              = intel_830mp_configure,
1984         .fetch_size             = intel_8xx_fetch_size,
1985         .cleanup                = intel_8xx_cleanup,
1986         .tlb_flush              = intel_8xx_tlbflush,
1987         .mask_memory            = agp_generic_mask_memory,
1988         .masks                  = intel_generic_masks,
1989         .agp_enable             = agp_generic_enable,
1990         .cache_flush            = global_cache_flush,
1991         .create_gatt_table      = agp_generic_create_gatt_table,
1992         .free_gatt_table        = agp_generic_free_gatt_table,
1993         .insert_memory          = agp_generic_insert_memory,
1994         .remove_memory          = agp_generic_remove_memory,
1995         .alloc_by_type          = agp_generic_alloc_by_type,
1996         .free_by_type           = agp_generic_free_by_type,
1997         .agp_alloc_page         = agp_generic_alloc_page,
1998         .agp_alloc_pages        = agp_generic_alloc_pages,
1999         .agp_destroy_page       = agp_generic_destroy_page,
2000         .agp_destroy_pages      = agp_generic_destroy_pages,
2001         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2002 };
2003
2004 static const struct agp_bridge_driver intel_840_driver = {
2005         .owner                  = THIS_MODULE,
2006         .aperture_sizes         = intel_8xx_sizes,
2007         .size_type              = U8_APER_SIZE,
2008         .num_aperture_sizes     = 7,
2009         .configure              = intel_840_configure,
2010         .fetch_size             = intel_8xx_fetch_size,
2011         .cleanup                = intel_8xx_cleanup,
2012         .tlb_flush              = intel_8xx_tlbflush,
2013         .mask_memory            = agp_generic_mask_memory,
2014         .masks                  = intel_generic_masks,
2015         .agp_enable             = agp_generic_enable,
2016         .cache_flush            = global_cache_flush,
2017         .create_gatt_table      = agp_generic_create_gatt_table,
2018         .free_gatt_table        = agp_generic_free_gatt_table,
2019         .insert_memory          = agp_generic_insert_memory,
2020         .remove_memory          = agp_generic_remove_memory,
2021         .alloc_by_type          = agp_generic_alloc_by_type,
2022         .free_by_type           = agp_generic_free_by_type,
2023         .agp_alloc_page         = agp_generic_alloc_page,
2024         .agp_alloc_pages        = agp_generic_alloc_pages,
2025         .agp_destroy_page       = agp_generic_destroy_page,
2026         .agp_destroy_pages      = agp_generic_destroy_pages,
2027         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2028 };
2029
2030 static const struct agp_bridge_driver intel_845_driver = {
2031         .owner                  = THIS_MODULE,
2032         .aperture_sizes         = intel_8xx_sizes,
2033         .size_type              = U8_APER_SIZE,
2034         .num_aperture_sizes     = 7,
2035         .configure              = intel_845_configure,
2036         .fetch_size             = intel_8xx_fetch_size,
2037         .cleanup                = intel_8xx_cleanup,
2038         .tlb_flush              = intel_8xx_tlbflush,
2039         .mask_memory            = agp_generic_mask_memory,
2040         .masks                  = intel_generic_masks,
2041         .agp_enable             = agp_generic_enable,
2042         .cache_flush            = global_cache_flush,
2043         .create_gatt_table      = agp_generic_create_gatt_table,
2044         .free_gatt_table        = agp_generic_free_gatt_table,
2045         .insert_memory          = agp_generic_insert_memory,
2046         .remove_memory          = agp_generic_remove_memory,
2047         .alloc_by_type          = agp_generic_alloc_by_type,
2048         .free_by_type           = agp_generic_free_by_type,
2049         .agp_alloc_page         = agp_generic_alloc_page,
2050         .agp_alloc_pages        = agp_generic_alloc_pages,
2051         .agp_destroy_page       = agp_generic_destroy_page,
2052         .agp_destroy_pages      = agp_generic_destroy_pages,
2053         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2054         .chipset_flush          = intel_i830_chipset_flush,
2055 };
2056
2057 static const struct agp_bridge_driver intel_850_driver = {
2058         .owner                  = THIS_MODULE,
2059         .aperture_sizes         = intel_8xx_sizes,
2060         .size_type              = U8_APER_SIZE,
2061         .num_aperture_sizes     = 7,
2062         .configure              = intel_850_configure,
2063         .fetch_size             = intel_8xx_fetch_size,
2064         .cleanup                = intel_8xx_cleanup,
2065         .tlb_flush              = intel_8xx_tlbflush,
2066         .mask_memory            = agp_generic_mask_memory,
2067         .masks                  = intel_generic_masks,
2068         .agp_enable             = agp_generic_enable,
2069         .cache_flush            = global_cache_flush,
2070         .create_gatt_table      = agp_generic_create_gatt_table,
2071         .free_gatt_table        = agp_generic_free_gatt_table,
2072         .insert_memory          = agp_generic_insert_memory,
2073         .remove_memory          = agp_generic_remove_memory,
2074         .alloc_by_type          = agp_generic_alloc_by_type,
2075         .free_by_type           = agp_generic_free_by_type,
2076         .agp_alloc_page         = agp_generic_alloc_page,
2077         .agp_alloc_pages        = agp_generic_alloc_pages,
2078         .agp_destroy_page       = agp_generic_destroy_page,
2079         .agp_destroy_pages      = agp_generic_destroy_pages,
2080         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2081 };
2082
2083 static const struct agp_bridge_driver intel_860_driver = {
2084         .owner                  = THIS_MODULE,
2085         .aperture_sizes         = intel_8xx_sizes,
2086         .size_type              = U8_APER_SIZE,
2087         .num_aperture_sizes     = 7,
2088         .configure              = intel_860_configure,
2089         .fetch_size             = intel_8xx_fetch_size,
2090         .cleanup                = intel_8xx_cleanup,
2091         .tlb_flush              = intel_8xx_tlbflush,
2092         .mask_memory            = agp_generic_mask_memory,
2093         .masks                  = intel_generic_masks,
2094         .agp_enable             = agp_generic_enable,
2095         .cache_flush            = global_cache_flush,
2096         .create_gatt_table      = agp_generic_create_gatt_table,
2097         .free_gatt_table        = agp_generic_free_gatt_table,
2098         .insert_memory          = agp_generic_insert_memory,
2099         .remove_memory          = agp_generic_remove_memory,
2100         .alloc_by_type          = agp_generic_alloc_by_type,
2101         .free_by_type           = agp_generic_free_by_type,
2102         .agp_alloc_page         = agp_generic_alloc_page,
2103         .agp_alloc_pages        = agp_generic_alloc_pages,
2104         .agp_destroy_page       = agp_generic_destroy_page,
2105         .agp_destroy_pages      = agp_generic_destroy_pages,
2106         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2107 };
2108
2109 static const struct agp_bridge_driver intel_915_driver = {
2110         .owner                  = THIS_MODULE,
2111         .aperture_sizes         = intel_i830_sizes,
2112         .size_type              = FIXED_APER_SIZE,
2113         .num_aperture_sizes     = 4,
2114         .needs_scratch_page     = true,
2115         .configure              = intel_i915_configure,
2116         .fetch_size             = intel_i9xx_fetch_size,
2117         .cleanup                = intel_i915_cleanup,
2118         .tlb_flush              = intel_i810_tlbflush,
2119         .mask_memory            = intel_i810_mask_memory,
2120         .masks                  = intel_i810_masks,
2121         .agp_enable             = intel_i810_agp_enable,
2122         .cache_flush            = global_cache_flush,
2123         .create_gatt_table      = intel_i915_create_gatt_table,
2124         .free_gatt_table        = intel_i830_free_gatt_table,
2125         .insert_memory          = intel_i915_insert_entries,
2126         .remove_memory          = intel_i915_remove_entries,
2127         .alloc_by_type          = intel_i830_alloc_by_type,
2128         .free_by_type           = intel_i810_free_by_type,
2129         .agp_alloc_page         = agp_generic_alloc_page,
2130         .agp_alloc_pages        = agp_generic_alloc_pages,
2131         .agp_destroy_page       = agp_generic_destroy_page,
2132         .agp_destroy_pages      = agp_generic_destroy_pages,
2133         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2134         .chipset_flush          = intel_i915_chipset_flush,
2135 #ifdef USE_PCI_DMA_API
2136         .agp_map_page           = intel_agp_map_page,
2137         .agp_unmap_page         = intel_agp_unmap_page,
2138         .agp_map_memory         = intel_agp_map_memory,
2139         .agp_unmap_memory       = intel_agp_unmap_memory,
2140 #endif
2141 };
2142
2143 static const struct agp_bridge_driver intel_i965_driver = {
2144         .owner                  = THIS_MODULE,
2145         .aperture_sizes         = intel_i830_sizes,
2146         .size_type              = FIXED_APER_SIZE,
2147         .num_aperture_sizes     = 4,
2148         .needs_scratch_page     = true,
2149         .configure              = intel_i915_configure,
2150         .fetch_size             = intel_i9xx_fetch_size,
2151         .cleanup                = intel_i915_cleanup,
2152         .tlb_flush              = intel_i810_tlbflush,
2153         .mask_memory            = intel_i965_mask_memory,
2154         .masks                  = intel_i810_masks,
2155         .agp_enable             = intel_i810_agp_enable,
2156         .cache_flush            = global_cache_flush,
2157         .create_gatt_table      = intel_i965_create_gatt_table,
2158         .free_gatt_table        = intel_i830_free_gatt_table,
2159         .insert_memory          = intel_i915_insert_entries,
2160         .remove_memory          = intel_i915_remove_entries,
2161         .alloc_by_type          = intel_i830_alloc_by_type,
2162         .free_by_type           = intel_i810_free_by_type,
2163         .agp_alloc_page         = agp_generic_alloc_page,
2164         .agp_alloc_pages        = agp_generic_alloc_pages,
2165         .agp_destroy_page       = agp_generic_destroy_page,
2166         .agp_destroy_pages      = agp_generic_destroy_pages,
2167         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2168         .chipset_flush          = intel_i915_chipset_flush,
2169 #ifdef USE_PCI_DMA_API
2170         .agp_map_page           = intel_agp_map_page,
2171         .agp_unmap_page         = intel_agp_unmap_page,
2172         .agp_map_memory         = intel_agp_map_memory,
2173         .agp_unmap_memory       = intel_agp_unmap_memory,
2174 #endif
2175 };
2176
2177 static const struct agp_bridge_driver intel_7505_driver = {
2178         .owner                  = THIS_MODULE,
2179         .aperture_sizes         = intel_8xx_sizes,
2180         .size_type              = U8_APER_SIZE,
2181         .num_aperture_sizes     = 7,
2182         .configure              = intel_7505_configure,
2183         .fetch_size             = intel_8xx_fetch_size,
2184         .cleanup                = intel_8xx_cleanup,
2185         .tlb_flush              = intel_8xx_tlbflush,
2186         .mask_memory            = agp_generic_mask_memory,
2187         .masks                  = intel_generic_masks,
2188         .agp_enable             = agp_generic_enable,
2189         .cache_flush            = global_cache_flush,
2190         .create_gatt_table      = agp_generic_create_gatt_table,
2191         .free_gatt_table        = agp_generic_free_gatt_table,
2192         .insert_memory          = agp_generic_insert_memory,
2193         .remove_memory          = agp_generic_remove_memory,
2194         .alloc_by_type          = agp_generic_alloc_by_type,
2195         .free_by_type           = agp_generic_free_by_type,
2196         .agp_alloc_page         = agp_generic_alloc_page,
2197         .agp_alloc_pages        = agp_generic_alloc_pages,
2198         .agp_destroy_page       = agp_generic_destroy_page,
2199         .agp_destroy_pages      = agp_generic_destroy_pages,
2200         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
2201 };
2202
2203 static const struct agp_bridge_driver intel_g33_driver = {
2204         .owner                  = THIS_MODULE,
2205         .aperture_sizes         = intel_i830_sizes,
2206         .size_type              = FIXED_APER_SIZE,
2207         .num_aperture_sizes     = 4,
2208         .needs_scratch_page     = true,
2209         .configure              = intel_i915_configure,
2210         .fetch_size             = intel_i9xx_fetch_size,
2211         .cleanup                = intel_i915_cleanup,
2212         .tlb_flush              = intel_i810_tlbflush,
2213         .mask_memory            = intel_i965_mask_memory,
2214         .masks                  = intel_i810_masks,
2215         .agp_enable             = intel_i810_agp_enable,
2216         .cache_flush            = global_cache_flush,
2217         .create_gatt_table      = intel_i915_create_gatt_table,
2218         .free_gatt_table        = intel_i830_free_gatt_table,
2219         .insert_memory          = intel_i915_insert_entries,
2220         .remove_memory          = intel_i915_remove_entries,
2221         .alloc_by_type          = intel_i830_alloc_by_type,
2222         .free_by_type           = intel_i810_free_by_type,
2223         .agp_alloc_page         = agp_generic_alloc_page,
2224         .agp_alloc_pages        = agp_generic_alloc_pages,
2225         .agp_destroy_page       = agp_generic_destroy_page,
2226         .agp_destroy_pages      = agp_generic_destroy_pages,
2227         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
2228         .chipset_flush          = intel_i915_chipset_flush,
2229 #ifdef USE_PCI_DMA_API
2230         .agp_map_page           = intel_agp_map_page,
2231         .agp_unmap_page         = intel_agp_unmap_page,
2232         .agp_map_memory         = intel_agp_map_memory,
2233         .agp_unmap_memory       = intel_agp_unmap_memory,
2234 #endif
2235 };
2236
2237 static int find_gmch(u16 device)
2238 {
2239         struct pci_dev *gmch_device;
2240
2241         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2242         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2243                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2244                                              device, gmch_device);
2245         }
2246
2247         if (!gmch_device)
2248                 return 0;
2249
2250         intel_private.pcidev = gmch_device;
2251         return 1;
2252 }
2253
2254 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
2255  * driver and gmch_driver must be non-null, and find_gmch will determine
2256  * which one should be used if a gmch_chip_id is present.
2257  */
2258 static const struct intel_driver_description {
2259         unsigned int chip_id;
2260         unsigned int gmch_chip_id;
2261         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2262         char *name;
2263         const struct agp_bridge_driver *driver;
2264         const struct agp_bridge_driver *gmch_driver;
2265 } intel_agp_chipsets[] = {
2266         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2267         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2268         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2269         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2270                 NULL, &intel_810_driver },
2271         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2272                 NULL, &intel_810_driver },
2273         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2274                 NULL, &intel_810_driver },
2275         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2276                 &intel_815_driver, &intel_810_driver },
2277         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2278         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2279         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2280                 &intel_830mp_driver, &intel_830_driver },
2281         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2282         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2283         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2284                 &intel_845_driver, &intel_830_driver },
2285         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2286         { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2287                 &intel_845_driver, &intel_830_driver },
2288         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2289         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2290                 &intel_845_driver, &intel_830_driver },
2291         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2292         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2293                 &intel_845_driver, &intel_830_driver },
2294         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2295         { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2296                 NULL, &intel_915_driver },
2297         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2298                 NULL, &intel_915_driver },
2299         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2300                 NULL, &intel_915_driver },
2301         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2302                 NULL, &intel_915_driver },
2303         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2304                 NULL, &intel_915_driver },
2305         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2306                 NULL, &intel_915_driver },
2307         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2308                 NULL, &intel_i965_driver },
2309         { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2310                 NULL, &intel_i965_driver },
2311         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2312                 NULL, &intel_i965_driver },
2313         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2314                 NULL, &intel_i965_driver },
2315         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2316                 NULL, &intel_i965_driver },
2317         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2318                 NULL, &intel_i965_driver },
2319         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2320         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2321         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2322                 NULL, &intel_g33_driver },
2323         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2324                 NULL, &intel_g33_driver },
2325         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2326                 NULL, &intel_g33_driver },
2327         { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2328                 NULL, &intel_g33_driver },
2329         { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2330                 NULL, &intel_g33_driver },
2331         { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2332             "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2333         { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2334             "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2335         { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2336             "Q45/Q43", NULL, &intel_i965_driver },
2337         { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2338             "G45/G43", NULL, &intel_i965_driver },
2339         { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2340             "G41", NULL, &intel_i965_driver },
2341         { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2342             "IGDNG/D", NULL, &intel_i965_driver },
2343         { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2344             "IGDNG/M", NULL, &intel_i965_driver },
2345         { 0, 0, 0, NULL, NULL, NULL }
2346 };
2347
2348 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2349                                      const struct pci_device_id *ent)
2350 {
2351         struct agp_bridge_data *bridge;
2352         u8 cap_ptr = 0;
2353         struct resource *r;
2354         int i;
2355
2356         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2357
2358         bridge = agp_alloc_bridge();
2359         if (!bridge)
2360                 return -ENOMEM;
2361
2362         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2363                 /* In case that multiple models of gfx chip may
2364                    stand on same host bridge type, this can be
2365                    sure we detect the right IGD. */
2366                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2367                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2368                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2369                                 bridge->driver =
2370                                         intel_agp_chipsets[i].gmch_driver;
2371                                 break;
2372                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2373                                 continue;
2374                         } else {
2375                                 bridge->driver = intel_agp_chipsets[i].driver;
2376                                 break;
2377                         }
2378                 }
2379         }
2380
2381         if (intel_agp_chipsets[i].name == NULL) {
2382                 if (cap_ptr)
2383                         dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2384                                  pdev->vendor, pdev->device);
2385                 agp_put_bridge(bridge);
2386                 return -ENODEV;
2387         }
2388
2389         if (bridge->driver == NULL) {
2390                 /* bridge has no AGP and no IGD detected */
2391                 if (cap_ptr)
2392                         dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2393                                  intel_agp_chipsets[i].gmch_chip_id);
2394                 agp_put_bridge(bridge);
2395                 return -ENODEV;
2396         }
2397
2398         bridge->dev = pdev;
2399         bridge->capndx = cap_ptr;
2400         bridge->dev_private_data = &intel_private;
2401
2402         dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2403
2404         /*
2405         * The following fixes the case where the BIOS has "forgotten" to
2406         * provide an address range for the GART.
2407         * 20030610 - hamish@zot.org
2408         */
2409         r = &pdev->resource[0];
2410         if (!r->start && r->end) {
2411                 if (pci_assign_resource(pdev, 0)) {
2412                         dev_err(&pdev->dev, "can't assign resource 0\n");
2413                         agp_put_bridge(bridge);
2414                         return -ENODEV;
2415                 }
2416         }
2417
2418         /*
2419         * If the device has not been properly setup, the following will catch
2420         * the problem and should stop the system from crashing.
2421         * 20030610 - hamish@zot.org
2422         */
2423         if (pci_enable_device(pdev)) {
2424                 dev_err(&pdev->dev, "can't enable PCI device\n");
2425                 agp_put_bridge(bridge);
2426                 return -ENODEV;
2427         }
2428
2429         /* Fill in the mode register */
2430         if (cap_ptr) {
2431                 pci_read_config_dword(pdev,
2432                                 bridge->capndx+PCI_AGP_STATUS,
2433                                 &bridge->mode);
2434         }
2435
2436         pci_set_drvdata(pdev, bridge);
2437         return agp_add_bridge(bridge);
2438 }
2439
2440 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2441 {
2442         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2443
2444         agp_remove_bridge(bridge);
2445
2446         if (intel_private.pcidev)
2447                 pci_dev_put(intel_private.pcidev);
2448
2449         agp_put_bridge(bridge);
2450 }
2451
2452 #ifdef CONFIG_PM
2453 static int agp_intel_resume(struct pci_dev *pdev)
2454 {
2455         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2456         int ret_val;
2457
2458         pci_restore_state(pdev);
2459
2460         /* We should restore our graphics device's config space,
2461          * as host bridge (00:00) resumes before graphics device (02:00),
2462          * then our access to its pci space can work right.
2463          */
2464         if (intel_private.pcidev)
2465                 pci_restore_state(intel_private.pcidev);
2466
2467         if (bridge->driver == &intel_generic_driver)
2468                 intel_configure();
2469         else if (bridge->driver == &intel_850_driver)
2470                 intel_850_configure();
2471         else if (bridge->driver == &intel_845_driver)
2472                 intel_845_configure();
2473         else if (bridge->driver == &intel_830mp_driver)
2474                 intel_830mp_configure();
2475         else if (bridge->driver == &intel_915_driver)
2476                 intel_i915_configure();
2477         else if (bridge->driver == &intel_830_driver)
2478                 intel_i830_configure();
2479         else if (bridge->driver == &intel_810_driver)
2480                 intel_i810_configure();
2481         else if (bridge->driver == &intel_i965_driver)
2482                 intel_i915_configure();
2483
2484         ret_val = agp_rebind_memory();
2485         if (ret_val != 0)
2486                 return ret_val;
2487
2488         return 0;
2489 }
2490 #endif
2491
2492 static struct pci_device_id agp_intel_pci_table[] = {
2493 #define ID(x)                                           \
2494         {                                               \
2495         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2496         .class_mask     = ~0,                           \
2497         .vendor         = PCI_VENDOR_ID_INTEL,          \
2498         .device         = x,                            \
2499         .subvendor      = PCI_ANY_ID,                   \
2500         .subdevice      = PCI_ANY_ID,                   \
2501         }
2502         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2503         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2504         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2505         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2506         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2507         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2508         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2509         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2510         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2511         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2512         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2513         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2514         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2515         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2516         ID(PCI_DEVICE_ID_INTEL_82854_HB),
2517         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2518         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2519         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2520         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2521         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2522         ID(PCI_DEVICE_ID_INTEL_7505_0),
2523         ID(PCI_DEVICE_ID_INTEL_7205_0),
2524         ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2525         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2526         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2527         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2528         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2529         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2530         ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2531         ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
2532         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2533         ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2534         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2535         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2536         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2537         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2538         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2539         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2540         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2541         ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2542         ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2543         ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2544         ID(PCI_DEVICE_ID_INTEL_G45_HB),
2545         ID(PCI_DEVICE_ID_INTEL_G41_HB),
2546         ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2547         ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2548         { }
2549 };
2550
2551 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2552
2553 static struct pci_driver agp_intel_pci_driver = {
2554         .name           = "agpgart-intel",
2555         .id_table       = agp_intel_pci_table,
2556         .probe          = agp_intel_probe,
2557         .remove         = __devexit_p(agp_intel_remove),
2558 #ifdef CONFIG_PM
2559         .resume         = agp_intel_resume,
2560 #endif
2561 };
2562
2563 static int __init agp_intel_init(void)
2564 {
2565         if (agp_off)
2566                 return -EINVAL;
2567         return pci_register_driver(&agp_intel_pci_driver);
2568 }
2569
2570 static void __exit agp_intel_cleanup(void)
2571 {
2572         pci_unregister_driver(&agp_intel_pci_driver);
2573 }
2574
2575 module_init(agp_intel_init);
2576 module_exit(agp_intel_cleanup);
2577
2578 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2579 MODULE_LICENSE("GPL and additional rights");