1 /* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com>
3 * This program is free software; you can redistribute it and/or
4 * modify it under the terms of the GNU General Public License
5 * as published by the Free Software Foundation; either version
6 * 2 of the License, or (at your option) any later version.
8 * This driver supports ATM cards based on the Efficient "Lanai"
9 * chipset such as the Speedstream 3010 and the ENI-25p. The
10 * Speedstream 3060 is currently not supported since we don't
11 * have the code to drive the on-board Alcatel DSL chipset (yet).
13 * Thanks to Efficient for supporting this project with hardware,
14 * documentation, and by answering my questions.
16 * Things not working yet:
18 * o We don't support the Speedstream 3060 yet - this card has
19 * an on-board DSL modem chip by Alcatel and the driver will
20 * need some extra code added to handle it
22 * o Note that due to limitations of the Lanai only one VCC can be
25 * o We don't currently parse the EEPROM at all. The code is all
26 * there as per the spec, but it doesn't actually work. I think
27 * there may be some issues with the docs. Anyway, do NOT
28 * enable it yet - bugs in that code may actually damage your
29 * hardware! Because of this you should hardware an ESI before
30 * trying to use this in a LANE or MPOA environment.
32 * o AAL0 is stubbed in but the actual rx/tx path isn't written yet:
33 * vcc_tx_aal0() needs to send or queue a SKB
34 * vcc_tx_unqueue_aal0() needs to attempt to send queued SKBs
35 * vcc_rx_aal0() needs to handle AAL0 interrupts
36 * This isn't too much work - I just wanted to get other things
39 * o lanai_change_qos() isn't written yet
41 * o There aren't any ioctl's yet -- I'd like to eventually support
42 * setting loopback and LED modes that way.
44 * o If the segmentation engine or DMA gets shut down we should restart
45 * card as per section 17.0i. (see lanai_reset)
47 * o setsockopt(SO_CIRANGE) isn't done (although despite what the
48 * API says it isn't exactly commonly implemented)
52 * v.1.00 -- 26-JUL-2003 -- PCI/DMA updates
53 * v.0.02 -- 11-JAN-2000 -- Endian fixes
54 * v.0.01 -- 30-NOV-1999 -- Initial release
57 #include <linux/module.h>
59 #include <linux/atmdev.h>
61 #include <asm/byteorder.h>
62 #include <linux/spinlock.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/init.h>
66 #include <linux/delay.h>
67 #include <linux/interrupt.h>
68 #include <linux/dma-mapping.h>
70 /* -------------------- TUNABLE PARAMATERS: */
73 * Maximum number of VCIs per card. Setting it lower could theoretically
74 * save some memory, but since we allocate our vcc list with get_free_pages,
75 * it's not really likely for most architectures
77 #define NUM_VCI (1024)
80 * Enable extra debugging
84 * Debug _all_ register operations with card, except the memory test.
85 * Also disables the timed poll to prevent extra chattiness. This
86 * isn't for normal use
91 * The programming guide specifies a full test of the on-board SRAM
92 * at initialization time. Undefine to remove this
94 #define FULL_MEMORY_TEST
97 * This is the number of (4 byte) service entries that we will
98 * try to allocate at startup. Note that we will end up with
99 * one PAGE_SIZE's worth regardless of what this is set to
101 #define SERVICE_ENTRIES (1024)
102 /* TODO: make above a module load-time option */
105 * We normally read the onboard EEPROM in order to discover our MAC
106 * address. Undefine to _not_ do this
108 /* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */
109 /* TODO: make above a module load-time option (also) */
112 * Depth of TX fifo (in 128 byte units; range 2-31)
113 * Smaller numbers are better for network latency
114 * Larger numbers are better for PCI latency
115 * I'm really sure where the best tradeoff is, but the BSD driver uses
116 * 7 and it seems to work ok.
118 #define TX_FIFO_DEPTH (7)
119 /* TODO: make above a module load-time option */
122 * How often (in jiffies) we will try to unstick stuck connections -
123 * shouldn't need to happen much
125 #define LANAI_POLL_PERIOD (10*HZ)
126 /* TODO: make above a module load-time option */
129 * When allocating an AAL5 receiving buffer, try to make it at least
130 * large enough to hold this many max_sdu sized PDUs
132 #define AAL5_RX_MULTIPLIER (3)
133 /* TODO: make above a module load-time option */
136 * Same for transmitting buffer
138 #define AAL5_TX_MULTIPLIER (3)
139 /* TODO: make above a module load-time option */
142 * When allocating an AAL0 transmiting buffer, how many cells should fit.
143 * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't
146 #define AAL0_TX_MULTIPLIER (40)
147 /* TODO: make above a module load-time option */
150 * How large should we make the AAL0 receiving buffer. Remember that this
151 * is shared between all AAL0 VC's
153 #define AAL0_RX_BUFFER_SIZE (PAGE_SIZE)
154 /* TODO: make above a module load-time option */
157 * Should we use Lanai's "powerdown" feature when no vcc's are bound?
159 /* #define USE_POWERDOWN */
160 /* TODO: make above a module load-time option (also) */
162 /* -------------------- DEBUGGING AIDS: */
164 #define DEV_LABEL "lanai"
168 #define DPRINTK(format, args...) \
169 printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
170 #define APRINTK(truth, format, args...) \
172 if (unlikely(!(truth))) \
173 printk(KERN_ERR DEV_LABEL ": " format, ##args); \
178 #define DPRINTK(format, args...)
179 #define APRINTK(truth, format, args...)
184 #define RWDEBUG(format, args...) \
185 printk(KERN_DEBUG DEV_LABEL ": " format, ##args)
186 #else /* !DEBUG_RW */
187 #define RWDEBUG(format, args...)
190 /* -------------------- DATA DEFINITIONS: */
192 #define LANAI_MAPPING_SIZE (0x40000)
193 #define LANAI_EEPROM_SIZE (128)
196 typedef void __iomem *bus_addr_t;
198 /* DMA buffer in host memory for TX, RX, or service list. */
199 struct lanai_buffer {
200 u32 *start; /* From get_free_pages */
201 u32 *end; /* One past last byte */
202 u32 *ptr; /* Pointer to current host location */
206 struct lanai_vcc_stats {
211 unsigned service_trash;
212 unsigned service_stream;
213 unsigned service_rxcrc;
220 struct lanai_dev; /* Forward declaration */
223 * This is the card-specific per-vcc data. Note that unlike some other
224 * drivers there is NOT a 1-to-1 correspondance between these and
225 * atm_vcc's - each one of these represents an actual 2-way vcc, but
226 * an atm_vcc can be 1-way and share with a 1-way vcc in the other
227 * direction. To make it weirder, there can even be 0-way vccs
228 * bound to us, waiting to do a change_qos
231 bus_addr_t vbase; /* Base of VCC's registers */
232 struct lanai_vcc_stats stats;
233 int nref; /* # of atm_vcc's who reference us */
236 struct lanai_buffer buf;
237 struct atm_vcc *atmvcc; /* atm_vcc who is receiver */
240 struct lanai_buffer buf;
241 struct atm_vcc *atmvcc; /* atm_vcc who is transmitter */
242 int endptr; /* last endptr from service entry */
243 struct sk_buff_head backlog;
244 void (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int);
249 lanai2 = PCI_DEVICE_ID_EF_ATM_LANAI2,
250 lanaihb = PCI_DEVICE_ID_EF_ATM_LANAIHB
253 struct lanai_dev_stats {
254 unsigned ovfl_trash; /* # of cells dropped - buffer overflow */
255 unsigned vci_trash; /* # of cells dropped - closed vci */
256 unsigned hec_err; /* # of cells dropped - bad HEC */
257 unsigned atm_ovfl; /* # of cells dropped - rx fifo overflow */
258 unsigned pcierr_parity_detect;
259 unsigned pcierr_serr_set;
260 unsigned pcierr_master_abort;
261 unsigned pcierr_m_target_abort;
262 unsigned pcierr_s_target_abort;
263 unsigned pcierr_master_parity;
264 unsigned service_notx;
265 unsigned service_norx;
266 unsigned service_rxnotaal5;
267 unsigned dma_reenable;
273 struct lanai_dev_stats stats;
274 struct lanai_buffer service;
275 struct lanai_vcc **vccs;
277 int nbound; /* number of bound vccs */
279 enum lanai_type type;
280 vci_t num_vci; /* Currently just NUM_VCI */
281 u8 eeprom[LANAI_EEPROM_SIZE];
282 u32 serialno, magicno;
284 DECLARE_BITMAP(backlog_vccs, NUM_VCI); /* VCCs with tx backlog */
285 DECLARE_BITMAP(transmit_ready, NUM_VCI); /* VCCs with transmit space */
286 struct timer_list timer;
288 struct lanai_buffer aal0buf; /* AAL0 RX buffers */
289 u32 conf1, conf2; /* CONFIG[12] registers */
290 u32 status; /* STATUS register */
291 spinlock_t endtxlock;
292 spinlock_t servicelock;
293 struct atm_vcc *cbrvcc;
296 /* TODO - look at race conditions with maintence of conf1/conf2 */
297 /* TODO - transmit locking: should we use _irq not _irqsave? */
298 /* TODO - organize above in some rational fashion (see <asm/cache.h>) */
302 * Each device has two bitmaps for each VCC (baclog_vccs and transmit_ready)
303 * This function iterates one of these, calling a given function for each
304 * vci with their bit set
306 static void vci_bitfield_iterate(struct lanai_dev *lanai,
307 const unsigned long *lp,
308 void (*func)(struct lanai_dev *,vci_t vci))
310 vci_t vci = find_first_bit(lp, NUM_VCI);
311 while (vci < NUM_VCI) {
313 vci = find_next_bit(lp, NUM_VCI, vci + 1);
317 /* -------------------- BUFFER UTILITIES: */
320 * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes -
321 * usually any page allocation will do. Just to be safe in case
322 * PAGE_SIZE is insanely tiny, though...
324 #define LANAI_PAGE_SIZE ((PAGE_SIZE >= 1024) ? PAGE_SIZE : 1024)
327 * Allocate a buffer in host RAM for service list, RX, or TX
328 * Returns buf->start==NULL if no memory
329 * Note that the size will be rounded up 2^n bytes, and
330 * if we can't allocate that we'll settle for something smaller
333 static void lanai_buf_allocate(struct lanai_buffer *buf,
334 size_t bytes, size_t minbytes, struct pci_dev *pci)
338 if (bytes > (128 * 1024)) /* max lanai buffer size */
340 for (size = LANAI_PAGE_SIZE; size < bytes; size *= 2)
342 if (minbytes < LANAI_PAGE_SIZE)
343 minbytes = LANAI_PAGE_SIZE;
346 * Technically we could use non-consistent mappings for
347 * everything, but the way the lanai uses DMA memory would
348 * make that a terrific pain. This is much simpler.
350 buf->start = pci_alloc_consistent(pci, size, &buf->dmaaddr);
351 if (buf->start != NULL) { /* Success */
352 /* Lanai requires 256-byte alignment of DMA bufs */
353 APRINTK((buf->dmaaddr & ~0xFFFFFF00) == 0,
354 "bad dmaaddr: 0x%lx\n",
355 (unsigned long) buf->dmaaddr);
356 buf->ptr = buf->start;
358 (&((unsigned char *) buf->start)[size]);
359 memset(buf->start, 0, size);
363 } while (size >= minbytes);
366 /* size of buffer in bytes */
367 static inline size_t lanai_buf_size(const struct lanai_buffer *buf)
369 return ((unsigned long) buf->end) - ((unsigned long) buf->start);
372 static void lanai_buf_deallocate(struct lanai_buffer *buf,
375 if (buf->start != NULL) {
376 pci_free_consistent(pci, lanai_buf_size(buf),
377 buf->start, buf->dmaaddr);
378 buf->start = buf->end = buf->ptr = NULL;
382 /* size of buffer as "card order" (0=1k .. 7=128k) */
383 static int lanai_buf_size_cardorder(const struct lanai_buffer *buf)
385 int order = get_order(lanai_buf_size(buf)) + (PAGE_SHIFT - 10);
387 /* This can only happen if PAGE_SIZE is gigantic, but just in case */
393 /* -------------------- PORT I/O UTILITIES: */
395 /* Registers (and their bit-fields) */
396 enum lanai_register {
397 Reset_Reg = 0x00, /* Reset; read for chip type; bits: */
398 #define RESET_GET_BOARD_REV(x) (((x)>> 0)&0x03) /* Board revision */
399 #define RESET_GET_BOARD_ID(x) (((x)>> 2)&0x03) /* Board ID */
400 #define BOARD_ID_LANAI256 (0) /* 25.6M adapter card */
401 Endian_Reg = 0x04, /* Endian setting */
402 IntStatus_Reg = 0x08, /* Interrupt status */
403 IntStatusMasked_Reg = 0x0C, /* Interrupt status (masked) */
404 IntAck_Reg = 0x10, /* Interrupt acknowledge */
405 IntAckMasked_Reg = 0x14, /* Interrupt acknowledge (masked) */
406 IntStatusSet_Reg = 0x18, /* Get status + enable/disable */
407 IntStatusSetMasked_Reg = 0x1C, /* Get status + en/di (masked) */
408 IntControlEna_Reg = 0x20, /* Interrupt control enable */
409 IntControlDis_Reg = 0x24, /* Interrupt control disable */
410 Status_Reg = 0x28, /* Status */
411 #define STATUS_PROMDATA (0x00000001) /* PROM_DATA pin */
412 #define STATUS_WAITING (0x00000002) /* Interrupt being delayed */
413 #define STATUS_SOOL (0x00000004) /* SOOL alarm */
414 #define STATUS_LOCD (0x00000008) /* LOCD alarm */
415 #define STATUS_LED (0x00000010) /* LED (HAPPI) output */
416 #define STATUS_GPIN (0x00000020) /* GPIN pin */
417 #define STATUS_BUTTBUSY (0x00000040) /* Butt register is pending */
418 Config1_Reg = 0x2C, /* Config word 1; bits: */
419 #define CONFIG1_PROMDATA (0x00000001) /* PROM_DATA pin */
420 #define CONFIG1_PROMCLK (0x00000002) /* PROM_CLK pin */
421 #define CONFIG1_SET_READMODE(x) ((x)*0x004) /* PCI BM reads; values: */
422 #define READMODE_PLAIN (0) /* Plain memory read */
423 #define READMODE_LINE (2) /* Memory read line */
424 #define READMODE_MULTIPLE (3) /* Memory read multiple */
425 #define CONFIG1_DMA_ENABLE (0x00000010) /* Turn on DMA */
426 #define CONFIG1_POWERDOWN (0x00000020) /* Turn off clocks */
427 #define CONFIG1_SET_LOOPMODE(x) ((x)*0x080) /* Clock&loop mode; values: */
428 #define LOOPMODE_NORMAL (0) /* Normal - no loop */
429 #define LOOPMODE_TIME (1)
430 #define LOOPMODE_DIAG (2)
431 #define LOOPMODE_LINE (3)
432 #define CONFIG1_MASK_LOOPMODE (0x00000180)
433 #define CONFIG1_SET_LEDMODE(x) ((x)*0x0200) /* Mode of LED; values: */
434 #define LEDMODE_NOT_SOOL (0) /* !SOOL */
435 #define LEDMODE_OFF (1) /* 0 */
436 #define LEDMODE_ON (2) /* 1 */
437 #define LEDMODE_NOT_LOCD (3) /* !LOCD */
438 #define LEDMORE_GPIN (4) /* GPIN */
439 #define LEDMODE_NOT_GPIN (7) /* !GPIN */
440 #define CONFIG1_MASK_LEDMODE (0x00000E00)
441 #define CONFIG1_GPOUT1 (0x00001000) /* Toggle for reset */
442 #define CONFIG1_GPOUT2 (0x00002000) /* Loopback PHY */
443 #define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */
444 Config2_Reg = 0x30, /* Config word 2; bits: */
445 #define CONFIG2_HOWMANY (0x00000001) /* >512 VCIs? */
446 #define CONFIG2_PTI7_MODE (0x00000002) /* Make PTI=7 RM, not OAM */
447 #define CONFIG2_VPI_CHK_DIS (0x00000004) /* Ignore RX VPI value */
448 #define CONFIG2_HEC_DROP (0x00000008) /* Drop cells w/ HEC errors */
449 #define CONFIG2_VCI0_NORMAL (0x00000010) /* Treat VCI=0 normally */
450 #define CONFIG2_CBR_ENABLE (0x00000020) /* Deal with CBR traffic */
451 #define CONFIG2_TRASH_ALL (0x00000040) /* Trashing incoming cells */
452 #define CONFIG2_TX_DISABLE (0x00000080) /* Trashing outgoing cells */
453 #define CONFIG2_SET_TRASH (0x00000100) /* Turn trashing on */
454 Statistics_Reg = 0x34, /* Statistics; bits: */
455 #define STATS_GET_FIFO_OVFL(x) (((x)>> 0)&0xFF) /* FIFO overflowed */
456 #define STATS_GET_HEC_ERR(x) (((x)>> 8)&0xFF) /* HEC was bad */
457 #define STATS_GET_BAD_VCI(x) (((x)>>16)&0xFF) /* VCI not open */
458 #define STATS_GET_BUF_OVFL(x) (((x)>>24)&0xFF) /* VCC buffer full */
459 ServiceStuff_Reg = 0x38, /* Service stuff; bits: */
460 #define SSTUFF_SET_SIZE(x) ((x)*0x20000000) /* size of service buffer */
461 #define SSTUFF_SET_ADDR(x) ((x)>>8) /* set address of buffer */
462 ServWrite_Reg = 0x3C, /* ServWrite Pointer */
463 ServRead_Reg = 0x40, /* ServRead Pointer */
464 TxDepth_Reg = 0x44, /* FIFO Transmit Depth */
465 Butt_Reg = 0x48, /* Butt register */
468 PingCount_Reg = 0x58, /* Ping count */
469 DMA_Addr_Reg = 0x5C /* DMA address */
472 static inline bus_addr_t reg_addr(const struct lanai_dev *lanai,
473 enum lanai_register reg)
475 return lanai->base + reg;
478 static inline u32 reg_read(const struct lanai_dev *lanai,
479 enum lanai_register reg)
482 t = readl(reg_addr(lanai, reg));
483 RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base,
488 static inline void reg_write(const struct lanai_dev *lanai, u32 val,
489 enum lanai_register reg)
491 RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base,
493 writel(val, reg_addr(lanai, reg));
496 static inline void conf1_write(const struct lanai_dev *lanai)
498 reg_write(lanai, lanai->conf1, Config1_Reg);
501 static inline void conf2_write(const struct lanai_dev *lanai)
503 reg_write(lanai, lanai->conf2, Config2_Reg);
506 /* Same as conf2_write(), but defers I/O if we're powered down */
507 static inline void conf2_write_if_powerup(const struct lanai_dev *lanai)
510 if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0))
512 #endif /* USE_POWERDOWN */
516 static inline void reset_board(const struct lanai_dev *lanai)
518 DPRINTK("about to reset board\n");
519 reg_write(lanai, 0, Reset_Reg);
521 * If we don't delay a little while here then we can end up
522 * leaving the card in a VERY weird state and lock up the
523 * PCI bus. This isn't documented anywhere but I've convinced
524 * myself after a lot of painful experimentation
529 /* -------------------- CARD SRAM UTILITIES: */
531 /* The SRAM is mapped into normal PCI memory space - the only catch is
532 * that it is only 16-bits wide but must be accessed as 32-bit. The
533 * 16 high bits will be zero. We don't hide this, since they get
534 * programmed mostly like discrete registers anyway
536 #define SRAM_START (0x20000)
537 #define SRAM_BYTES (0x20000) /* Again, half don't really exist */
539 static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset)
541 return lanai->base + SRAM_START + offset;
544 static inline u32 sram_read(const struct lanai_dev *lanai, int offset)
546 return readl(sram_addr(lanai, offset));
549 static inline void sram_write(const struct lanai_dev *lanai,
552 writel(val, sram_addr(lanai, offset));
555 static int __devinit sram_test_word(const struct lanai_dev *lanai,
556 int offset, u32 pattern)
559 sram_write(lanai, pattern, offset);
560 readback = sram_read(lanai, offset);
561 if (likely(readback == pattern))
563 printk(KERN_ERR DEV_LABEL
564 "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n",
565 lanai->number, offset,
566 (unsigned int) pattern, (unsigned int) readback);
570 static int __devinit sram_test_pass(const struct lanai_dev *lanai, u32 pattern)
572 int offset, result = 0;
573 for (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4)
574 result = sram_test_word(lanai, offset, pattern);
578 static int __devinit sram_test_and_clear(const struct lanai_dev *lanai)
580 #ifdef FULL_MEMORY_TEST
582 DPRINTK("testing SRAM\n");
583 if ((result = sram_test_pass(lanai, 0x5555)) != 0)
585 if ((result = sram_test_pass(lanai, 0xAAAA)) != 0)
588 DPRINTK("clearing SRAM\n");
589 return sram_test_pass(lanai, 0x0000);
592 /* -------------------- CARD-BASED VCC TABLE UTILITIES: */
595 enum lanai_vcc_offset {
596 vcc_rxaddr1 = 0x00, /* Location1, plus bits: */
597 #define RXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of RX buffer */
598 #define RXADDR1_SET_RMMODE(x) ((x)*0x00800) /* RM cell action; values: */
599 #define RMMODE_TRASH (0) /* discard */
600 #define RMMODE_PRESERVE (1) /* input as AAL0 */
601 #define RMMODE_PIPE (2) /* pipe to coscheduler */
602 #define RMMODE_PIPEALL (3) /* pipe non-RM too */
603 #define RXADDR1_OAM_PRESERVE (0x00002000) /* Input OAM cells as AAL0 */
604 #define RXADDR1_SET_MODE(x) ((x)*0x0004000) /* Reassembly mode */
605 #define RXMODE_TRASH (0) /* discard */
606 #define RXMODE_AAL0 (1) /* non-AAL5 mode */
607 #define RXMODE_AAL5 (2) /* AAL5, intr. each PDU */
608 #define RXMODE_AAL5_STREAM (3) /* AAL5 w/o per-PDU intr */
609 vcc_rxaddr2 = 0x04, /* Location2 */
610 vcc_rxcrc1 = 0x08, /* RX CRC claculation space */
612 vcc_rxwriteptr = 0x10, /* RX writeptr, plus bits: */
613 #define RXWRITEPTR_LASTEFCI (0x00002000) /* Last PDU had EFCI bit */
614 #define RXWRITEPTR_DROPPING (0x00004000) /* Had error, dropping */
615 #define RXWRITEPTR_TRASHING (0x00008000) /* Trashing */
616 vcc_rxbufstart = 0x14, /* RX bufstart, plus bits: */
617 #define RXBUFSTART_CLP (0x00004000)
618 #define RXBUFSTART_CI (0x00008000)
619 vcc_rxreadptr = 0x18, /* RX readptr */
620 vcc_txicg = 0x1C, /* TX ICG */
621 vcc_txaddr1 = 0x20, /* Location1, plus bits: */
622 #define TXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of TX buffer */
623 #define TXADDR1_ABR (0x00008000) /* use ABR (doesn't work) */
624 vcc_txaddr2 = 0x24, /* Location2 */
625 vcc_txcrc1 = 0x28, /* TX CRC claculation space */
627 vcc_txreadptr = 0x30, /* TX Readptr, plus bits: */
628 #define TXREADPTR_GET_PTR(x) ((x)&0x01FFF)
629 #define TXREADPTR_MASK_DELTA (0x0000E000) /* ? */
630 vcc_txendptr = 0x34, /* TX Endptr, plus bits: */
631 #define TXENDPTR_CLP (0x00002000)
632 #define TXENDPTR_MASK_PDUMODE (0x0000C000) /* PDU mode; values: */
633 #define PDUMODE_AAL0 (0*0x04000)
634 #define PDUMODE_AAL5 (2*0x04000)
635 #define PDUMODE_AAL5STREAM (3*0x04000)
636 vcc_txwriteptr = 0x38, /* TX Writeptr */
637 #define TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF)
638 vcc_txcbr_next = 0x3C /* # of next CBR VCI in ring */
639 #define TXCBR_NEXT_BOZO (0x00008000) /* "bozo bit" */
642 #define CARDVCC_SIZE (0x40)
644 static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai,
647 return sram_addr(lanai, vci * CARDVCC_SIZE);
650 static inline u32 cardvcc_read(const struct lanai_vcc *lvcc,
651 enum lanai_vcc_offset offset)
654 APRINTK(lvcc->vbase != NULL, "cardvcc_read: unbound vcc!\n");
655 val= readl(lvcc->vbase + offset);
656 RWDEBUG("VR vci=%04d 0x%02X = 0x%08X\n",
657 lvcc->vci, (int) offset, val);
661 static inline void cardvcc_write(const struct lanai_vcc *lvcc,
662 u32 val, enum lanai_vcc_offset offset)
664 APRINTK(lvcc->vbase != NULL, "cardvcc_write: unbound vcc!\n");
665 APRINTK((val & ~0xFFFF) == 0,
666 "cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\n",
667 (unsigned int) val, lvcc->vci, (unsigned int) offset);
668 RWDEBUG("VW vci=%04d 0x%02X > 0x%08X\n",
669 lvcc->vci, (unsigned int) offset, (unsigned int) val);
670 writel(val, lvcc->vbase + offset);
673 /* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */
675 /* How many bytes will an AAL5 PDU take to transmit - remember that:
676 * o we need to add 8 bytes for length, CPI, UU, and CRC
677 * o we need to round up to 48 bytes for cells
679 static inline int aal5_size(int size)
681 int cells = (size + 8 + 47) / 48;
685 /* How many bytes can we send if we have "space" space, assuming we have
688 static inline int aal5_spacefor(int space)
690 int cells = space / 48;
694 /* -------------------- FREE AN ATM SKB: */
696 static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb)
698 if (atmvcc->pop != NULL)
699 atmvcc->pop(atmvcc, skb);
701 dev_kfree_skb_any(skb);
704 /* -------------------- TURN VCCS ON AND OFF: */
706 static void host_vcc_start_rx(const struct lanai_vcc *lvcc)
709 if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) {
710 dma_addr_t dmaaddr = lvcc->rx.buf.dmaaddr;
711 cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1);
712 cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2);
713 cardvcc_write(lvcc, 0, vcc_rxwriteptr);
714 cardvcc_write(lvcc, 0, vcc_rxbufstart);
715 cardvcc_write(lvcc, 0, vcc_rxreadptr);
716 cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2);
717 addr1 = ((dmaaddr >> 8) & 0xFF) |
718 RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))|
719 RXADDR1_SET_RMMODE(RMMODE_TRASH) | /* ??? */
720 /* RXADDR1_OAM_PRESERVE | --- no OAM support yet */
721 RXADDR1_SET_MODE(RXMODE_AAL5);
723 addr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */
724 RXADDR1_OAM_PRESERVE | /* ??? */
725 RXADDR1_SET_MODE(RXMODE_AAL0);
726 /* This one must be last! */
727 cardvcc_write(lvcc, addr1, vcc_rxaddr1);
730 static void host_vcc_start_tx(const struct lanai_vcc *lvcc)
732 dma_addr_t dmaaddr = lvcc->tx.buf.dmaaddr;
733 cardvcc_write(lvcc, 0, vcc_txicg);
734 cardvcc_write(lvcc, 0xFFFF, vcc_txcrc1);
735 cardvcc_write(lvcc, 0xFFFF, vcc_txcrc2);
736 cardvcc_write(lvcc, 0, vcc_txreadptr);
737 cardvcc_write(lvcc, 0, vcc_txendptr);
738 cardvcc_write(lvcc, 0, vcc_txwriteptr);
740 (lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ?
741 TXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next);
742 cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2);
744 ((dmaaddr >> 8) & 0xFF) |
745 TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)),
749 /* Shutdown receiving on card */
750 static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc)
752 if (lvcc->vbase == NULL) /* We were never bound to a VCI */
754 /* 15.1.1 - set to trashing, wait one cell time (15us) */
756 RXADDR1_SET_RMMODE(RMMODE_TRASH) |
757 RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1);
759 /* 15.1.2 - clear rest of entries */
760 cardvcc_write(lvcc, 0, vcc_rxaddr2);
761 cardvcc_write(lvcc, 0, vcc_rxcrc1);
762 cardvcc_write(lvcc, 0, vcc_rxcrc2);
763 cardvcc_write(lvcc, 0, vcc_rxwriteptr);
764 cardvcc_write(lvcc, 0, vcc_rxbufstart);
765 cardvcc_write(lvcc, 0, vcc_rxreadptr);
768 /* Shutdown transmitting on card.
769 * Unfortunately the lanai needs us to wait until all the data
770 * drains out of the buffer before we can dealloc it, so this
771 * can take awhile -- up to 370ms for a full 128KB buffer
772 * assuming everone else is quiet. In theory the time is
773 * boundless if there's a CBR VCC holding things up.
775 static void lanai_shutdown_tx_vci(struct lanai_dev *lanai,
776 struct lanai_vcc *lvcc)
779 unsigned long flags, timeout;
780 int read, write, lastread = -1;
781 APRINTK(!in_interrupt(),
782 "lanai_shutdown_tx_vci called w/o process context!\n");
783 if (lvcc->vbase == NULL) /* We were never bound to a VCI */
785 /* 15.2.1 - wait for queue to drain */
786 while ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL)
787 lanai_free_skb(lvcc->tx.atmvcc, skb);
788 read_lock_irqsave(&vcc_sklist_lock, flags);
789 __clear_bit(lvcc->vci, lanai->backlog_vccs);
790 read_unlock_irqrestore(&vcc_sklist_lock, flags);
792 * We need to wait for the VCC to drain but don't wait forever. We
793 * give each 1K of buffer size 1/128th of a second to clear out.
794 * TODO: maybe disable CBR if we're about to timeout?
797 (((lanai_buf_size(&lvcc->tx.buf) / 1024) * HZ) >> 7);
798 write = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr));
800 read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
801 if (read == write && /* Is TX buffer empty? */
802 (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR ||
803 (cardvcc_read(lvcc, vcc_txcbr_next) &
804 TXCBR_NEXT_BOZO) == 0))
806 if (read != lastread) { /* Has there been any progress? */
810 if (unlikely(time_after(jiffies, timeout))) {
811 printk(KERN_ERR DEV_LABEL "(itf %d): Timed out on "
812 "backlog closing vci %d\n",
813 lvcc->tx.atmvcc->dev->number, lvcc->vci);
814 DPRINTK("read, write = %d, %d\n", read, write);
819 /* 15.2.2 - clear out all tx registers */
820 cardvcc_write(lvcc, 0, vcc_txreadptr);
821 cardvcc_write(lvcc, 0, vcc_txwriteptr);
822 cardvcc_write(lvcc, 0, vcc_txendptr);
823 cardvcc_write(lvcc, 0, vcc_txcrc1);
824 cardvcc_write(lvcc, 0, vcc_txcrc2);
825 cardvcc_write(lvcc, 0, vcc_txaddr2);
826 cardvcc_write(lvcc, 0, vcc_txaddr1);
829 /* -------------------- MANAGING AAL0 RX BUFFER: */
831 static inline int aal0_buffer_allocate(struct lanai_dev *lanai)
833 DPRINTK("aal0_buffer_allocate: allocating AAL0 RX buffer\n");
834 lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80,
836 return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0;
839 static inline void aal0_buffer_free(struct lanai_dev *lanai)
841 DPRINTK("aal0_buffer_allocate: freeing AAL0 RX buffer\n");
842 lanai_buf_deallocate(&lanai->aal0buf, lanai->pci);
845 /* -------------------- EEPROM UTILITIES: */
847 /* Offsets of data in the EEPROM */
848 #define EEPROM_COPYRIGHT (0)
849 #define EEPROM_COPYRIGHT_LEN (44)
850 #define EEPROM_CHECKSUM (62)
851 #define EEPROM_CHECKSUM_REV (63)
852 #define EEPROM_MAC (64)
853 #define EEPROM_MAC_REV (70)
854 #define EEPROM_SERIAL (112)
855 #define EEPROM_SERIAL_REV (116)
856 #define EEPROM_MAGIC (120)
857 #define EEPROM_MAGIC_REV (124)
859 #define EEPROM_MAGIC_VALUE (0x5AB478D2)
863 /* Stub functions to use if EEPROM reading is disabled */
864 static int __devinit eeprom_read(struct lanai_dev *lanai)
866 printk(KERN_INFO DEV_LABEL "(itf %d): *NOT* reading EEPROM\n",
868 memset(&lanai->eeprom[EEPROM_MAC], 0, 6);
872 static int __devinit eeprom_validate(struct lanai_dev *lanai)
875 lanai->magicno = EEPROM_MAGIC_VALUE;
879 #else /* READ_EEPROM */
881 static int __devinit eeprom_read(struct lanai_dev *lanai)
886 #define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \
888 #define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK)
889 #define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK)
890 #define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA)
891 #define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA)
892 #define pre_read() do { data_h(); clock_h(); udelay(5); } while (0)
893 #define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA)
894 #define send_stop() do { data_l(); udelay(5); clock_h(); udelay(5); \
895 data_h(); udelay(5); } while (0)
896 /* start with both clock and data high */
897 data_h(); clock_h(); udelay(5);
898 for (address = 0; address < LANAI_EEPROM_SIZE; address++) {
899 data = (address << 1) | 1; /* Command=read + address */
902 clock_l(); udelay(5);
903 for (i = 128; i != 0; i >>= 1) { /* write command out */
904 tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) |
905 (data & i) ? CONFIG1_PROMDATA : 0;
906 if (lanai->conf1 != tmp) {
908 udelay(5); /* Let new data settle */
910 clock_h(); udelay(5); clock_l(); udelay(5);
913 data_h(); clock_h(); udelay(5);
915 goto error; /* No ack seen */
916 clock_l(); udelay(5);
917 /* read back result */
918 for (data = 0, i = 7; i >= 0; i--) {
919 data_h(); clock_h(); udelay(5);
920 data = (data << 1) | !!read_pin();
921 clock_l(); udelay(5);
923 /* look again for ack */
924 data_h(); clock_h(); udelay(5);
926 goto error; /* Spurious ack */
927 clock_l(); udelay(5);
929 lanai->eeprom[address] = data;
930 DPRINTK("EEPROM 0x%04X %02X\n",
931 (unsigned int) address, (unsigned int) data);
935 clock_l(); udelay(5); /* finish read */
937 printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n",
938 lanai->number, address);
950 /* read a big-endian 4-byte value out of eeprom */
951 static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address)
953 return be32_to_cpup((const u32 *) &lanai->eeprom[address]);
956 /* Checksum/validate EEPROM contents */
957 static int __devinit eeprom_validate(struct lanai_dev *lanai)
961 const u8 *e = lanai->eeprom;
963 /* First, see if we can get an ASCIIZ string out of the copyright */
964 for (i = EEPROM_COPYRIGHT;
965 i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++)
966 if (e[i] < 0x20 || e[i] > 0x7E)
968 if ( i != EEPROM_COPYRIGHT &&
969 i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0')
970 DPRINTK("eeprom: copyright = \"%s\"\n",
971 (char *) &e[EEPROM_COPYRIGHT]);
973 DPRINTK("eeprom: copyright not found\n");
975 /* Validate checksum */
976 for (i = s = 0; i < EEPROM_CHECKSUM; i++)
979 if (s != e[EEPROM_CHECKSUM]) {
980 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad "
981 "(wanted 0x%02X, got 0x%02X)\n", lanai->number,
982 (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]);
986 if (s != e[EEPROM_CHECKSUM_REV]) {
987 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum "
988 "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number,
989 (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]);
992 /* Verify MAC address */
993 for (i = 0; i < 6; i++)
994 if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) {
995 printk(KERN_ERR DEV_LABEL
996 "(itf %d) : EEPROM MAC addresses don't match "
997 "(0x%02X, inverse 0x%02X)\n", lanai->number,
998 (unsigned int) e[EEPROM_MAC + i],
999 (unsigned int) e[EEPROM_MAC_REV + i]);
1002 DPRINTK("eeprom: MAC address = %02X:%02X:%02X:%02X:%02X:%02X\n",
1003 e[EEPROM_MAC + 0], e[EEPROM_MAC + 1], e[EEPROM_MAC + 2],
1004 e[EEPROM_MAC + 3], e[EEPROM_MAC + 4], e[EEPROM_MAC + 5]);
1005 /* Verify serial number */
1006 lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL);
1007 v = eeprom_be4(lanai, EEPROM_SERIAL_REV);
1008 if ((lanai->serialno ^ v) != 0xFFFFFFFF) {
1009 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers "
1010 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1011 (unsigned int) lanai->serialno, (unsigned int) v);
1014 DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno);
1015 /* Verify magic number */
1016 lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC);
1017 v = eeprom_be4(lanai, EEPROM_MAGIC_REV);
1018 if ((lanai->magicno ^ v) != 0xFFFFFFFF) {
1019 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers "
1020 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number,
1024 DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno);
1025 if (lanai->magicno != EEPROM_MAGIC_VALUE)
1026 printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM "
1027 "magic not what expected (got 0x%08X, not 0x%08X)\n",
1028 lanai->number, (unsigned int) lanai->magicno,
1029 (unsigned int) EEPROM_MAGIC_VALUE);
1033 #endif /* READ_EEPROM */
1035 static inline const u8 *eeprom_mac(const struct lanai_dev *lanai)
1037 return &lanai->eeprom[EEPROM_MAC];
1040 /* -------------------- INTERRUPT HANDLING UTILITIES: */
1042 /* Interrupt types */
1043 #define INT_STATS (0x00000002) /* Statistics counter overflow */
1044 #define INT_SOOL (0x00000004) /* SOOL changed state */
1045 #define INT_LOCD (0x00000008) /* LOCD changed state */
1046 #define INT_LED (0x00000010) /* LED (HAPPI) changed state */
1047 #define INT_GPIN (0x00000020) /* GPIN changed state */
1048 #define INT_PING (0x00000040) /* PING_COUNT fulfilled */
1049 #define INT_WAKE (0x00000080) /* Lanai wants bus */
1050 #define INT_CBR0 (0x00000100) /* CBR sched hit VCI 0 */
1051 #define INT_LOCK (0x00000200) /* Service list overflow */
1052 #define INT_MISMATCH (0x00000400) /* TX magic list mismatch */
1053 #define INT_AAL0_STR (0x00000800) /* Non-AAL5 buffer half filled */
1054 #define INT_AAL0 (0x00001000) /* Non-AAL5 data available */
1055 #define INT_SERVICE (0x00002000) /* Service list entries available */
1056 #define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */
1057 #define INT_TABORTBM (0x00008000) /* Abort rcv'd as bus master */
1058 #define INT_TIMEOUTBM (0x00010000) /* No response to bus master */
1059 #define INT_PCIPARITY (0x00020000) /* Parity error on PCI */
1061 /* Sets of the above */
1062 #define INT_ALL (0x0003FFFE) /* All interrupts */
1063 #define INT_STATUS (0x0000003C) /* Some status pin changed */
1064 #define INT_DMASHUT (0x00038000) /* DMA engine got shut down */
1065 #define INT_SEGSHUT (0x00000700) /* Segmentation got shut down */
1067 static inline u32 intr_pending(const struct lanai_dev *lanai)
1069 return reg_read(lanai, IntStatusMasked_Reg);
1072 static inline void intr_enable(const struct lanai_dev *lanai, u32 i)
1074 reg_write(lanai, i, IntControlEna_Reg);
1077 static inline void intr_disable(const struct lanai_dev *lanai, u32 i)
1079 reg_write(lanai, i, IntControlDis_Reg);
1082 /* -------------------- CARD/PCI STATUS: */
1084 static void status_message(int itf, const char *name, int status)
1086 static const char *onoff[2] = { "off to on", "on to off" };
1087 printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n",
1088 itf, name, onoff[!status]);
1091 static void lanai_check_status(struct lanai_dev *lanai)
1093 u32 new = reg_read(lanai, Status_Reg);
1094 u32 changes = new ^ lanai->status;
1095 lanai->status = new;
1096 #define e(flag, name) \
1097 if (changes & flag) \
1098 status_message(lanai->number, name, new & flag)
1099 e(STATUS_SOOL, "SOOL");
1100 e(STATUS_LOCD, "LOCD");
1101 e(STATUS_LED, "LED");
1102 e(STATUS_GPIN, "GPIN");
1106 static void pcistatus_got(int itf, const char *name)
1108 printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name);
1111 static void pcistatus_check(struct lanai_dev *lanai, int clearonly)
1115 result = pci_read_config_word(lanai->pci, PCI_STATUS, &s);
1116 if (result != PCIBIOS_SUCCESSFUL) {
1117 printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: "
1118 "%d\n", lanai->number, result);
1121 s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR |
1122 PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT |
1123 PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY;
1126 result = pci_write_config_word(lanai->pci, PCI_STATUS, s);
1127 if (result != PCIBIOS_SUCCESSFUL)
1128 printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: "
1129 "%d\n", lanai->number, result);
1132 #define e(flag, name, stat) \
1134 pcistatus_got(lanai->number, name); \
1135 ++lanai->stats.pcierr_##stat; \
1137 e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect);
1138 e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set);
1139 e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort);
1140 e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort);
1141 e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort);
1142 e(PCI_STATUS_PARITY, "master parity", master_parity);
1146 /* -------------------- VCC TX BUFFER UTILITIES: */
1148 /* space left in tx buffer in bytes */
1149 static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr)
1153 r -= ((unsigned long) lvcc->tx.buf.ptr) -
1154 ((unsigned long) lvcc->tx.buf.start);
1155 r -= 16; /* Leave "bubble" - if start==end it looks empty */
1157 r += lanai_buf_size(&lvcc->tx.buf);
1161 /* test if VCC is currently backlogged */
1162 static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc)
1164 return !skb_queue_empty(&lvcc->tx.backlog);
1167 /* Bit fields in the segmentation buffer descriptor */
1168 #define DESCRIPTOR_MAGIC (0xD0000000)
1169 #define DESCRIPTOR_AAL5 (0x00008000)
1170 #define DESCRIPTOR_AAL5_STREAM (0x00004000)
1171 #define DESCRIPTOR_CLP (0x00002000)
1173 /* Add 32-bit descriptor with its padding */
1174 static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc,
1178 APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0,
1179 "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr);
1180 lvcc->tx.buf.ptr += 4; /* Hope the values REALLY don't matter */
1181 pos = ((unsigned char *) lvcc->tx.buf.ptr) -
1182 (unsigned char *) lvcc->tx.buf.start;
1183 APRINTK((pos & ~0x0001FFF0) == 0,
1184 "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, "
1185 "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
1186 lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
1187 pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1);
1188 APRINTK((pos & ~0x0001FFF0) == 0,
1189 "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, "
1190 "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci,
1191 lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end);
1192 lvcc->tx.buf.ptr[-1] =
1193 cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 |
1194 ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ?
1195 DESCRIPTOR_CLP : 0) | flags | pos >> 4);
1196 if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
1197 lvcc->tx.buf.ptr = lvcc->tx.buf.start;
1200 /* Add 32-bit AAL5 trailer and leave room for its CRC */
1201 static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc,
1202 int len, int cpi, int uu)
1204 APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8,
1205 "vcc_tx_add_aal5_trailer: bad ptr=%p\n", lvcc->tx.buf.ptr);
1206 lvcc->tx.buf.ptr += 2;
1207 lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len);
1208 if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end)
1209 lvcc->tx.buf.ptr = lvcc->tx.buf.start;
1212 static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc,
1213 const unsigned char *src, int n)
1217 e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
1218 m = e - (unsigned char *) lvcc->tx.buf.end;
1221 memcpy(lvcc->tx.buf.ptr, src, n - m);
1223 memcpy(lvcc->tx.buf.start, src + n - m, m);
1224 e = ((unsigned char *) lvcc->tx.buf.start) + m;
1226 lvcc->tx.buf.ptr = (u32 *) e;
1229 static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n)
1235 e = ((unsigned char *) lvcc->tx.buf.ptr) + n;
1236 m = e - (unsigned char *) lvcc->tx.buf.end;
1239 memset(lvcc->tx.buf.ptr, 0, n - m);
1241 memset(lvcc->tx.buf.start, 0, m);
1242 e = ((unsigned char *) lvcc->tx.buf.start) + m;
1244 lvcc->tx.buf.ptr = (u32 *) e;
1247 /* Update "butt" register to specify new WritePtr */
1248 static inline void lanai_endtx(struct lanai_dev *lanai,
1249 const struct lanai_vcc *lvcc)
1251 int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) -
1252 (unsigned char *) lvcc->tx.buf.start;
1253 APRINTK((ptr & ~0x0001FFF0) == 0,
1254 "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n",
1255 ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr,
1259 * Since the "butt register" is a shared resounce on the card we
1260 * serialize all accesses to it through this spinlock. This is
1261 * mostly just paranoia sicne the register is rarely "busy" anyway
1262 * but is needed for correctness.
1264 spin_lock(&lanai->endtxlock);
1266 * We need to check if the "butt busy" bit is set before
1267 * updating the butt register. In theory this should
1268 * never happen because the ATM card is plenty fast at
1269 * updating the register. Still, we should make sure
1271 for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) {
1272 if (unlikely(i > 50)) {
1273 printk(KERN_ERR DEV_LABEL "(itf %d): butt register "
1274 "always busy!\n", lanai->number);
1280 * Before we tall the card to start work we need to be sure 100% of
1281 * the info in the service buffer has been written before we tell
1285 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg);
1286 spin_unlock(&lanai->endtxlock);
1290 * Add one AAL5 PDU to lvcc's transmit buffer. Caller garauntees there's
1291 * space available. "pdusize" is the number of bytes the PDU will take
1293 static void lanai_send_one_aal5(struct lanai_dev *lanai,
1294 struct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize)
1297 APRINTK(pdusize == aal5_size(skb->len),
1298 "lanai_send_one_aal5: wrong size packet (%d != %d)\n",
1299 pdusize, aal5_size(skb->len));
1300 vcc_tx_add_aal5_descriptor(lvcc, 0, pdusize);
1301 pad = pdusize - skb->len - 8;
1302 APRINTK(pad >= 0, "pad is negative (%d)\n", pad);
1303 APRINTK(pad < 48, "pad is too big (%d)\n", pad);
1304 vcc_tx_memcpy(lvcc, skb->data, skb->len);
1305 vcc_tx_memzero(lvcc, pad);
1306 vcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0);
1307 lanai_endtx(lanai, lvcc);
1308 lanai_free_skb(lvcc->tx.atmvcc, skb);
1309 atomic_inc(&lvcc->tx.atmvcc->stats->tx);
1312 /* Try to fill the buffer - don't call unless there is backlog */
1313 static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai,
1314 struct lanai_vcc *lvcc, int endptr)
1317 struct sk_buff *skb;
1318 int space = vcc_tx_space(lvcc, endptr);
1319 APRINTK(vcc_is_backlogged(lvcc),
1320 "vcc_tx_unqueue() called with empty backlog (vci=%d)\n",
1322 while (space >= 64) {
1323 skb = skb_dequeue(&lvcc->tx.backlog);
1326 n = aal5_size(skb->len);
1327 if (n + 16 > space) {
1328 /* No room for this packet - put it back on queue */
1329 skb_queue_head(&lvcc->tx.backlog, skb);
1332 lanai_send_one_aal5(lanai, lvcc, skb, n);
1335 if (!vcc_is_backlogged(lvcc)) {
1337 __clear_bit(lvcc->vci, lanai->backlog_vccs);
1341 /* Given an skb that we want to transmit either send it now or queue */
1342 static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1343 struct sk_buff *skb)
1346 if (vcc_is_backlogged(lvcc)) /* Already backlogged */
1348 space = vcc_tx_space(lvcc,
1349 TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)));
1350 n = aal5_size(skb->len);
1351 APRINTK(n + 16 >= 64, "vcc_tx_aal5: n too small (%d)\n", n);
1352 if (space < n + 16) { /* No space for this PDU */
1353 __set_bit(lvcc->vci, lanai->backlog_vccs);
1355 skb_queue_tail(&lvcc->tx.backlog, skb);
1358 lanai_send_one_aal5(lanai, lvcc, skb, n);
1361 static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai,
1362 struct lanai_vcc *lvcc, int endptr)
1364 printk(KERN_INFO DEV_LABEL
1365 ": vcc_tx_unqueue_aal0: not implemented\n");
1368 static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1369 struct sk_buff *skb)
1371 printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n");
1372 /* Remember to increment lvcc->tx.atmvcc->stats->tx */
1373 lanai_free_skb(lvcc->tx.atmvcc, skb);
1376 /* -------------------- VCC RX BUFFER UTILITIES: */
1378 /* unlike the _tx_ cousins, this doesn't update ptr */
1379 static inline void vcc_rx_memcpy(unsigned char *dest,
1380 const struct lanai_vcc *lvcc, int n)
1382 int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n -
1383 ((const unsigned char *) (lvcc->rx.buf.end));
1386 memcpy(dest, lvcc->rx.buf.ptr, n - m);
1387 memcpy(dest + n - m, lvcc->rx.buf.start, m);
1388 /* Make sure that these copies don't get reordered */
1392 /* Receive AAL5 data on a VCC with a particular endptr */
1393 static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr)
1396 struct sk_buff *skb;
1398 u32 *end = &lvcc->rx.buf.start[endptr * 4];
1399 int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr);
1401 n += lanai_buf_size(&lvcc->rx.buf);
1402 APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15),
1403 "vcc_rx_aal5: n out of range (%d/%Zu)\n",
1404 n, lanai_buf_size(&lvcc->rx.buf));
1405 /* Recover the second-to-last word to get true pdu length */
1406 if ((x = &end[-2]) < lvcc->rx.buf.start)
1407 x = &lvcc->rx.buf.end[-2];
1409 * Before we actually read from the buffer, make sure the memory
1410 * changes have arrived
1413 size = be32_to_cpup(x) & 0xffff;
1414 if (unlikely(n != aal5_size(size))) {
1415 /* Make sure size matches padding */
1416 printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length "
1417 "on vci=%d - size=%d n=%d\n",
1418 lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n);
1419 lvcc->stats.x.aal5.rx_badlen++;
1422 skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC);
1423 if (unlikely(skb == NULL)) {
1424 lvcc->stats.rx_nomem++;
1428 vcc_rx_memcpy(skb->data, lvcc, size);
1429 ATM_SKB(skb)->vcc = lvcc->rx.atmvcc;
1430 __net_timestamp(skb);
1431 lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb);
1432 atomic_inc(&lvcc->rx.atmvcc->stats->rx);
1434 lvcc->rx.buf.ptr = end;
1435 cardvcc_write(lvcc, endptr, vcc_rxreadptr);
1438 static void vcc_rx_aal0(struct lanai_dev *lanai)
1440 printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n");
1441 /* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */
1442 /* Remember to increment lvcc->rx.atmvcc->stats->rx */
1445 /* -------------------- MANAGING HOST-BASED VCC TABLE: */
1447 /* Decide whether to use vmalloc or get_zeroed_page for VCC table */
1448 #if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE
1449 #define VCCTABLE_GETFREEPAGE
1451 #include <linux/vmalloc.h>
1454 static int __devinit vcc_table_allocate(struct lanai_dev *lanai)
1456 #ifdef VCCTABLE_GETFREEPAGE
1457 APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE,
1458 "vcc table > PAGE_SIZE!");
1459 lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL);
1460 return (lanai->vccs == NULL) ? -ENOMEM : 0;
1462 int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *);
1463 lanai->vccs = (struct lanai_vcc **) vmalloc(bytes);
1464 if (unlikely(lanai->vccs == NULL))
1466 memset(lanai->vccs, 0, bytes);
1471 static inline void vcc_table_deallocate(const struct lanai_dev *lanai)
1473 #ifdef VCCTABLE_GETFREEPAGE
1474 free_page((unsigned long) lanai->vccs);
1480 /* Allocate a fresh lanai_vcc, with the appropriate things cleared */
1481 static inline struct lanai_vcc *new_lanai_vcc(void)
1483 struct lanai_vcc *lvcc;
1484 lvcc = kzalloc(sizeof(*lvcc), GFP_KERNEL);
1485 if (likely(lvcc != NULL)) {
1486 skb_queue_head_init(&lvcc->tx.backlog);
1494 static int lanai_get_sized_buffer(struct lanai_dev *lanai,
1495 struct lanai_buffer *buf, int max_sdu, int multiplier,
1499 if (unlikely(max_sdu < 1))
1501 max_sdu = aal5_size(max_sdu);
1502 size = (max_sdu + 16) * multiplier + 16;
1503 lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci);
1504 if (unlikely(buf->start == NULL))
1506 if (unlikely(lanai_buf_size(buf) < size))
1507 printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes "
1508 "for %s buffer, got only %Zu\n", lanai->number, size,
1509 name, lanai_buf_size(buf));
1510 DPRINTK("Allocated %Zu byte %s buffer\n", lanai_buf_size(buf), name);
1514 /* Setup a RX buffer for a currently unbound AAL5 vci */
1515 static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai,
1516 struct lanai_vcc *lvcc, const struct atm_qos *qos)
1518 return lanai_get_sized_buffer(lanai, &lvcc->rx.buf,
1519 qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, "RX");
1522 /* Setup a TX buffer for a currently unbound AAL5 vci */
1523 static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc,
1524 const struct atm_qos *qos)
1526 int max_sdu, multiplier;
1527 if (qos->aal == ATM_AAL0) {
1528 lvcc->tx.unqueue = vcc_tx_unqueue_aal0;
1529 max_sdu = ATM_CELL_SIZE - 1;
1530 multiplier = AAL0_TX_MULTIPLIER;
1532 lvcc->tx.unqueue = vcc_tx_unqueue_aal5;
1533 max_sdu = qos->txtp.max_sdu;
1534 multiplier = AAL5_TX_MULTIPLIER;
1536 return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu,
1540 static inline void host_vcc_bind(struct lanai_dev *lanai,
1541 struct lanai_vcc *lvcc, vci_t vci)
1543 if (lvcc->vbase != NULL)
1544 return; /* We already were bound in the other direction */
1545 DPRINTK("Binding vci %d\n", vci);
1546 #ifdef USE_POWERDOWN
1547 if (lanai->nbound++ == 0) {
1548 DPRINTK("Coming out of powerdown\n");
1549 lanai->conf1 &= ~CONFIG1_POWERDOWN;
1554 lvcc->vbase = cardvcc_addr(lanai, vci);
1555 lanai->vccs[lvcc->vci = vci] = lvcc;
1558 static inline void host_vcc_unbind(struct lanai_dev *lanai,
1559 struct lanai_vcc *lvcc)
1561 if (lvcc->vbase == NULL)
1562 return; /* This vcc was never bound */
1563 DPRINTK("Unbinding vci %d\n", lvcc->vci);
1565 lanai->vccs[lvcc->vci] = NULL;
1566 #ifdef USE_POWERDOWN
1567 if (--lanai->nbound == 0) {
1568 DPRINTK("Going into powerdown\n");
1569 lanai->conf1 |= CONFIG1_POWERDOWN;
1575 /* -------------------- RESET CARD: */
1577 static void lanai_reset(struct lanai_dev *lanai)
1579 printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* reseting - not "
1580 "implemented\n", lanai->number);
1582 /* The following is just a hack until we write the real
1583 * resetter - at least ack whatever interrupt sent us
1586 reg_write(lanai, INT_ALL, IntAck_Reg);
1587 lanai->stats.card_reset++;
1590 /* -------------------- SERVICE LIST UTILITIES: */
1593 * Allocate service buffer and tell card about it
1595 static int __devinit service_buffer_allocate(struct lanai_dev *lanai)
1597 lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8,
1599 if (unlikely(lanai->service.start == NULL))
1601 DPRINTK("allocated service buffer at 0x%08lX, size %Zu(%d)\n",
1602 (unsigned long) lanai->service.start,
1603 lanai_buf_size(&lanai->service),
1604 lanai_buf_size_cardorder(&lanai->service));
1605 /* Clear ServWrite register to be safe */
1606 reg_write(lanai, 0, ServWrite_Reg);
1607 /* ServiceStuff register contains size and address of buffer */
1609 SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) |
1610 SSTUFF_SET_ADDR(lanai->service.dmaaddr),
1615 static inline void service_buffer_deallocate(struct lanai_dev *lanai)
1617 lanai_buf_deallocate(&lanai->service, lanai->pci);
1620 /* Bitfields in service list */
1621 #define SERVICE_TX (0x80000000) /* Was from transmission */
1622 #define SERVICE_TRASH (0x40000000) /* RXed PDU was trashed */
1623 #define SERVICE_CRCERR (0x20000000) /* RXed PDU had CRC error */
1624 #define SERVICE_CI (0x10000000) /* RXed PDU had CI set */
1625 #define SERVICE_CLP (0x08000000) /* RXed PDU had CLP set */
1626 #define SERVICE_STREAM (0x04000000) /* RX Stream mode */
1627 #define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF)
1628 #define SERVICE_GET_END(x) ((x)&0x1FFF)
1630 /* Handle one thing from the service list - returns true if it marked a
1631 * VCC ready for xmit
1633 static int handle_service(struct lanai_dev *lanai, u32 s)
1635 vci_t vci = SERVICE_GET_VCI(s);
1636 struct lanai_vcc *lvcc;
1637 read_lock(&vcc_sklist_lock);
1638 lvcc = lanai->vccs[vci];
1639 if (unlikely(lvcc == NULL)) {
1640 read_unlock(&vcc_sklist_lock);
1641 DPRINTK("(itf %d) got service entry 0x%X for nonexistent "
1642 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1644 lanai->stats.service_notx++;
1646 lanai->stats.service_norx++;
1649 if (s & SERVICE_TX) { /* segmentation interrupt */
1650 if (unlikely(lvcc->tx.atmvcc == NULL)) {
1651 read_unlock(&vcc_sklist_lock);
1652 DPRINTK("(itf %d) got service entry 0x%X for non-TX "
1653 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1654 lanai->stats.service_notx++;
1657 __set_bit(vci, lanai->transmit_ready);
1658 lvcc->tx.endptr = SERVICE_GET_END(s);
1659 read_unlock(&vcc_sklist_lock);
1662 if (unlikely(lvcc->rx.atmvcc == NULL)) {
1663 read_unlock(&vcc_sklist_lock);
1664 DPRINTK("(itf %d) got service entry 0x%X for non-RX "
1665 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1666 lanai->stats.service_norx++;
1669 if (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) {
1670 read_unlock(&vcc_sklist_lock);
1671 DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 "
1672 "vcc %d\n", lanai->number, (unsigned int) s, vci);
1673 lanai->stats.service_rxnotaal5++;
1674 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1677 if (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) {
1678 vcc_rx_aal5(lvcc, SERVICE_GET_END(s));
1679 read_unlock(&vcc_sklist_lock);
1682 if (s & SERVICE_TRASH) {
1684 read_unlock(&vcc_sklist_lock);
1685 DPRINTK("got trashed rx pdu on vci %d\n", vci);
1686 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1687 lvcc->stats.x.aal5.service_trash++;
1688 bytes = (SERVICE_GET_END(s) * 16) -
1689 (((unsigned long) lvcc->rx.buf.ptr) -
1690 ((unsigned long) lvcc->rx.buf.start)) + 47;
1692 bytes += lanai_buf_size(&lvcc->rx.buf);
1693 lanai->stats.ovfl_trash += (bytes / 48);
1696 if (s & SERVICE_STREAM) {
1697 read_unlock(&vcc_sklist_lock);
1698 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1699 lvcc->stats.x.aal5.service_stream++;
1700 printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream "
1701 "PDU on VCI %d!\n", lanai->number, vci);
1705 DPRINTK("got rx crc error on vci %d\n", vci);
1706 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err);
1707 lvcc->stats.x.aal5.service_rxcrc++;
1708 lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4];
1709 cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr);
1710 read_unlock(&vcc_sklist_lock);
1714 /* Try transmitting on all VCIs that we marked ready to serve */
1715 static void iter_transmit(struct lanai_dev *lanai, vci_t vci)
1717 struct lanai_vcc *lvcc = lanai->vccs[vci];
1718 if (vcc_is_backlogged(lvcc))
1719 lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr);
1722 /* Run service queue -- called from interrupt context or with
1723 * interrupts otherwise disabled and with the lanai->servicelock
1726 static void run_service(struct lanai_dev *lanai)
1729 u32 wreg = reg_read(lanai, ServWrite_Reg);
1730 const u32 *end = lanai->service.start + wreg;
1731 while (lanai->service.ptr != end) {
1732 ntx += handle_service(lanai,
1733 le32_to_cpup(lanai->service.ptr++));
1734 if (lanai->service.ptr >= lanai->service.end)
1735 lanai->service.ptr = lanai->service.start;
1737 reg_write(lanai, wreg, ServRead_Reg);
1739 read_lock(&vcc_sklist_lock);
1740 vci_bitfield_iterate(lanai, lanai->transmit_ready,
1742 bitmap_zero(lanai->transmit_ready, NUM_VCI);
1743 read_unlock(&vcc_sklist_lock);
1747 /* -------------------- GATHER STATISTICS: */
1749 static void get_statistics(struct lanai_dev *lanai)
1751 u32 statreg = reg_read(lanai, Statistics_Reg);
1752 lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg);
1753 lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg);
1754 lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg);
1755 lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg);
1758 /* -------------------- POLLING TIMER: */
1761 /* Try to undequeue 1 backlogged vcc */
1762 static void iter_dequeue(struct lanai_dev *lanai, vci_t vci)
1764 struct lanai_vcc *lvcc = lanai->vccs[vci];
1766 if (lvcc == NULL || lvcc->tx.atmvcc == NULL ||
1767 !vcc_is_backlogged(lvcc)) {
1768 __clear_bit(vci, lanai->backlog_vccs);
1771 endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr));
1772 lvcc->tx.unqueue(lanai, lvcc, endptr);
1774 #endif /* !DEBUG_RW */
1776 static void lanai_timed_poll(unsigned long arg)
1778 struct lanai_dev *lanai = (struct lanai_dev *) arg;
1780 unsigned long flags;
1781 #ifdef USE_POWERDOWN
1782 if (lanai->conf1 & CONFIG1_POWERDOWN)
1784 #endif /* USE_POWERDOWN */
1785 local_irq_save(flags);
1786 /* If we can grab the spinlock, check if any services need to be run */
1787 if (spin_trylock(&lanai->servicelock)) {
1789 spin_unlock(&lanai->servicelock);
1791 /* ...and see if any backlogged VCs can make progress */
1792 /* unfortunately linux has no read_trylock() currently */
1793 read_lock(&vcc_sklist_lock);
1794 vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue);
1795 read_unlock(&vcc_sklist_lock);
1796 local_irq_restore(flags);
1798 get_statistics(lanai);
1799 #endif /* !DEBUG_RW */
1800 mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD);
1803 static inline void lanai_timed_poll_start(struct lanai_dev *lanai)
1805 init_timer(&lanai->timer);
1806 lanai->timer.expires = jiffies + LANAI_POLL_PERIOD;
1807 lanai->timer.data = (unsigned long) lanai;
1808 lanai->timer.function = lanai_timed_poll;
1809 add_timer(&lanai->timer);
1812 static inline void lanai_timed_poll_stop(struct lanai_dev *lanai)
1814 del_timer_sync(&lanai->timer);
1817 /* -------------------- INTERRUPT SERVICE: */
1819 static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason)
1822 if (reason & INT_SERVICE) {
1824 spin_lock(&lanai->servicelock);
1826 spin_unlock(&lanai->servicelock);
1828 if (reason & (INT_AAL0_STR | INT_AAL0)) {
1829 ack |= reason & (INT_AAL0_STR | INT_AAL0);
1832 /* The rest of the interrupts are pretty rare */
1835 if (reason & INT_STATS) {
1836 reason &= ~INT_STATS; /* No need to ack */
1837 get_statistics(lanai);
1839 if (reason & INT_STATUS) {
1840 ack |= reason & INT_STATUS;
1841 lanai_check_status(lanai);
1843 if (unlikely(reason & INT_DMASHUT)) {
1844 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA "
1845 "shutdown, reason=0x%08X, address=0x%08X\n",
1846 lanai->number, (unsigned int) (reason & INT_DMASHUT),
1847 (unsigned int) reg_read(lanai, DMA_Addr_Reg));
1848 if (reason & INT_TABORTBM) {
1852 ack |= (reason & INT_DMASHUT);
1853 printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n",
1856 lanai->stats.dma_reenable++;
1857 pcistatus_check(lanai, 0);
1859 if (unlikely(reason & INT_TABORTSENT)) {
1860 ack |= (reason & INT_TABORTSENT);
1861 printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n",
1863 pcistatus_check(lanai, 0);
1865 if (unlikely(reason & INT_SEGSHUT)) {
1866 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
1867 "segmentation shutdown, reason=0x%08X\n", lanai->number,
1868 (unsigned int) (reason & INT_SEGSHUT));
1872 if (unlikely(reason & (INT_PING | INT_WAKE))) {
1873 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - "
1874 "unexpected interrupt 0x%08X, resetting\n",
1876 (unsigned int) (reason & (INT_PING | INT_WAKE)));
1881 if (unlikely(ack != reason)) {
1882 DPRINTK("unacked ints: 0x%08X\n",
1883 (unsigned int) (reason & ~ack));
1889 reg_write(lanai, ack, IntAck_Reg);
1892 static irqreturn_t lanai_int(int irq, void *devid)
1894 struct lanai_dev *lanai = devid;
1897 #ifdef USE_POWERDOWN
1899 * If we're powered down we shouldn't be generating any interrupts -
1900 * so assume that this is a shared interrupt line and it's for someone
1903 if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN))
1907 reason = intr_pending(lanai);
1909 return IRQ_NONE; /* Must be for someone else */
1912 if (unlikely(reason == 0xFFFFFFFF))
1913 break; /* Maybe we've been unplugged? */
1914 lanai_int_1(lanai, reason);
1915 reason = intr_pending(lanai);
1916 } while (reason != 0);
1921 /* TODO - it would be nice if we could use the "delayed interrupt" system
1925 /* -------------------- CHECK BOARD ID/REV: */
1928 * The board id and revision are stored both in the reset register and
1929 * in the PCI configuration space - the documentation says to check
1930 * each of them. If revp!=NULL we store the revision there
1932 static int check_board_id_and_rev(const char *name, u32 val, int *revp)
1934 DPRINTK("%s says board_id=%d, board_rev=%d\n", name,
1935 (int) RESET_GET_BOARD_ID(val),
1936 (int) RESET_GET_BOARD_REV(val));
1937 if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) {
1938 printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a "
1939 "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val));
1943 *revp = RESET_GET_BOARD_REV(val);
1947 /* -------------------- PCI INITIALIZATION/SHUTDOWN: */
1949 static int __devinit lanai_pci_start(struct lanai_dev *lanai)
1951 struct pci_dev *pci = lanai->pci;
1955 if (pci_enable_device(pci) != 0) {
1956 printk(KERN_ERR DEV_LABEL "(itf %d): can't enable "
1957 "PCI device", lanai->number);
1960 pci_set_master(pci);
1961 if (pci_set_dma_mask(pci, DMA_32BIT_MASK) != 0) {
1962 printk(KERN_WARNING DEV_LABEL
1963 "(itf %d): No suitable DMA available.\n", lanai->number);
1966 if (pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK) != 0) {
1967 printk(KERN_WARNING DEV_LABEL
1968 "(itf %d): No suitable DMA available.\n", lanai->number);
1971 result = pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &w);
1972 if (result != PCIBIOS_SUCCESSFUL) {
1973 printk(KERN_ERR DEV_LABEL "(itf %d): can't read "
1974 "PCI_SUBSYSTEM_ID: %d\n", lanai->number, result);
1977 result = check_board_id_and_rev("PCI", w, NULL);
1980 /* Set latency timer to zero as per lanai docs */
1981 result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0);
1982 if (result != PCIBIOS_SUCCESSFUL) {
1983 printk(KERN_ERR DEV_LABEL "(itf %d): can't write "
1984 "PCI_LATENCY_TIMER: %d\n", lanai->number, result);
1987 pcistatus_check(lanai, 1);
1988 pcistatus_check(lanai, 0);
1992 /* -------------------- VPI/VCI ALLOCATION: */
1995 * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll
1996 * get a CBRZERO interrupt), and we can use it only if noone is receiving
1997 * AAL0 traffic (since they will use the same queue) - according to the
1998 * docs we shouldn't even use it for AAL0 traffic
2000 static inline int vci0_is_ok(struct lanai_dev *lanai,
2001 const struct atm_qos *qos)
2003 if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0)
2005 if (qos->rxtp.traffic_class != ATM_NONE) {
2006 if (lanai->naal0 != 0)
2008 lanai->conf2 |= CONFIG2_VCI0_NORMAL;
2009 conf2_write_if_powerup(lanai);
2014 /* return true if vci is currently unused, or if requested qos is
2017 static int vci_is_ok(struct lanai_dev *lanai, vci_t vci,
2018 const struct atm_vcc *atmvcc)
2020 const struct atm_qos *qos = &atmvcc->qos;
2021 const struct lanai_vcc *lvcc = lanai->vccs[vci];
2022 if (vci == 0 && !vci0_is_ok(lanai, qos))
2024 if (unlikely(lvcc != NULL)) {
2025 if (qos->rxtp.traffic_class != ATM_NONE &&
2026 lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc)
2028 if (qos->txtp.traffic_class != ATM_NONE &&
2029 lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc)
2031 if (qos->txtp.traffic_class == ATM_CBR &&
2032 lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc)
2035 if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 &&
2036 qos->rxtp.traffic_class != ATM_NONE) {
2037 const struct lanai_vcc *vci0 = lanai->vccs[0];
2038 if (vci0 != NULL && vci0->rx.atmvcc != NULL)
2040 lanai->conf2 &= ~CONFIG2_VCI0_NORMAL;
2041 conf2_write_if_powerup(lanai);
2046 static int lanai_normalize_ci(struct lanai_dev *lanai,
2047 const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip)
2060 for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci;
2062 if (vci_is_ok(lanai, *vcip, atmvcc))
2066 if (*vcip >= lanai->num_vci || *vcip < 0 ||
2067 !vci_is_ok(lanai, *vcip, atmvcc))
2073 /* -------------------- MANAGE CBR: */
2076 * CBR ICG is stored as a fixed-point number with 4 fractional bits.
2077 * Note that storing a number greater than 2046.0 will result in
2080 #define CBRICG_FRAC_BITS (4)
2081 #define CBRICG_MAX (2046 << CBRICG_FRAC_BITS)
2084 * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1)
2085 * where MAXPCR is (according to the docs) 25600000/(54*8),
2086 * which is equal to (3125<<9)/27.
2088 * Solving for ICG, we get:
2089 * ICG = MAXPCR/PCR - 1
2090 * ICG = (3125<<9)/(27*PCR) - 1
2091 * ICG = ((3125<<9) - (27*PCR)) / (27*PCR)
2093 * The end result is supposed to be a fixed-point number with FRAC_BITS
2094 * bits of a fractional part, so we keep everything in the numerator
2095 * shifted by that much as we compute
2098 static int pcr_to_cbricg(const struct atm_qos *qos)
2100 int rounddown = 0; /* 1 = Round PCR down, i.e. round ICG _up_ */
2101 int x, icg, pcr = atm_pcr_goal(&qos->txtp);
2102 if (pcr == 0) /* Use maximum bandwidth */
2109 icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS);
2113 if (icg > CBRICG_MAX)
2115 DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n",
2116 pcr, rounddown ? 'Y' : 'N', icg);
2120 static inline void lanai_cbr_setup(struct lanai_dev *lanai)
2122 reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg);
2123 reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg);
2124 lanai->conf2 |= CONFIG2_CBR_ENABLE;
2128 static inline void lanai_cbr_shutdown(struct lanai_dev *lanai)
2130 lanai->conf2 &= ~CONFIG2_CBR_ENABLE;
2134 /* -------------------- OPERATIONS: */
2136 /* setup a newly detected device */
2137 static int __devinit lanai_dev_open(struct atm_dev *atmdev)
2139 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2140 unsigned long raw_base;
2143 DPRINTK("In lanai_dev_open()\n");
2144 /* Basic device fields */
2145 lanai->number = atmdev->number;
2146 lanai->num_vci = NUM_VCI;
2147 bitmap_zero(lanai->backlog_vccs, NUM_VCI);
2148 bitmap_zero(lanai->transmit_ready, NUM_VCI);
2150 #ifdef USE_POWERDOWN
2153 lanai->cbrvcc = NULL;
2154 memset(&lanai->stats, 0, sizeof lanai->stats);
2155 spin_lock_init(&lanai->endtxlock);
2156 spin_lock_init(&lanai->servicelock);
2157 atmdev->ci_range.vpi_bits = 0;
2158 atmdev->ci_range.vci_bits = 0;
2159 while (1 << atmdev->ci_range.vci_bits < lanai->num_vci)
2160 atmdev->ci_range.vci_bits++;
2161 atmdev->link_rate = ATM_25_PCR;
2163 /* 3.2: PCI initialization */
2164 if ((result = lanai_pci_start(lanai)) != 0)
2166 raw_base = lanai->pci->resource[0].start;
2167 lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE);
2168 if (lanai->base == NULL) {
2169 printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n");
2172 /* 3.3: Reset lanai and PHY */
2174 lanai->conf1 = reg_read(lanai, Config1_Reg);
2175 lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN |
2176 CONFIG1_MASK_LEDMODE);
2177 lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL);
2178 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2183 * 3.4: Turn on endian mode for big-endian hardware
2184 * We don't actually want to do this - the actual bit fields
2185 * in the endian register are not documented anywhere.
2186 * Instead we do the bit-flipping ourselves on big-endian
2189 * 3.5: get the board ID/rev by reading the reset register
2191 result = check_board_id_and_rev("register",
2192 reg_read(lanai, Reset_Reg), &lanai->board_rev);
2196 /* 3.6: read EEPROM */
2197 if ((result = eeprom_read(lanai)) != 0)
2199 if ((result = eeprom_validate(lanai)) != 0)
2202 /* 3.7: re-reset PHY, do loopback tests, setup PHY */
2203 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg);
2206 /* TODO - loopback tests */
2207 lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE);
2210 /* 3.8/3.9: test and initialize card SRAM */
2211 if ((result = sram_test_and_clear(lanai)) != 0)
2214 /* 3.10: initialize lanai registers */
2215 lanai->conf1 |= CONFIG1_DMA_ENABLE;
2217 if ((result = service_buffer_allocate(lanai)) != 0)
2219 if ((result = vcc_table_allocate(lanai)) != 0)
2221 lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) |
2222 CONFIG2_HEC_DROP | /* ??? */ CONFIG2_PTI7_MODE;
2224 reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg);
2225 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */
2226 if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED,
2227 DEV_LABEL, lanai)) != 0) {
2228 printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n");
2229 goto error_vcctable;
2231 mb(); /* Make sure that all that made it */
2232 intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE));
2233 /* 3.11: initialize loop mode (i.e. turn looping off) */
2234 lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) |
2235 CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) |
2236 CONFIG1_GPOUT2 | CONFIG1_GPOUT3;
2238 lanai->status = reg_read(lanai, Status_Reg);
2239 /* We're now done initializing this card */
2240 #ifdef USE_POWERDOWN
2241 lanai->conf1 |= CONFIG1_POWERDOWN;
2244 memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN);
2245 lanai_timed_poll_start(lanai);
2246 printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%u "
2247 "(%02X-%02X-%02X-%02X-%02X-%02X)\n", lanai->number,
2248 (int) lanai->pci->revision, (unsigned long) lanai->base,
2250 atmdev->esi[0], atmdev->esi[1], atmdev->esi[2],
2251 atmdev->esi[3], atmdev->esi[4], atmdev->esi[5]);
2252 printk(KERN_NOTICE DEV_LABEL "(itf %d): LANAI%s, serialno=%u(0x%X), "
2253 "board_rev=%d\n", lanai->number,
2254 lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno,
2255 (unsigned int) lanai->serialno, lanai->board_rev);
2259 vcc_table_deallocate(lanai);
2261 service_buffer_deallocate(lanai);
2264 #ifdef USE_POWERDOWN
2265 lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN;
2268 iounmap(lanai->base);
2270 pci_disable_device(lanai->pci);
2275 /* called when device is being shutdown, and all vcc's are gone - higher
2276 * levels will deallocate the atm device for us
2278 static void lanai_dev_close(struct atm_dev *atmdev)
2280 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2281 printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n",
2283 lanai_timed_poll_stop(lanai);
2284 #ifdef USE_POWERDOWN
2285 lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN;
2288 intr_disable(lanai, INT_ALL);
2289 free_irq(lanai->pci->irq, lanai);
2291 #ifdef USE_POWERDOWN
2292 lanai->conf1 |= CONFIG1_POWERDOWN;
2295 pci_disable_device(lanai->pci);
2296 vcc_table_deallocate(lanai);
2297 service_buffer_deallocate(lanai);
2298 iounmap(lanai->base);
2303 static void lanai_close(struct atm_vcc *atmvcc)
2305 struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
2306 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2309 clear_bit(ATM_VF_READY, &atmvcc->flags);
2310 clear_bit(ATM_VF_PARTIAL, &atmvcc->flags);
2311 if (lvcc->rx.atmvcc == atmvcc) {
2312 lanai_shutdown_rx_vci(lvcc);
2313 if (atmvcc->qos.aal == ATM_AAL0) {
2314 if (--lanai->naal0 <= 0)
2315 aal0_buffer_free(lanai);
2317 lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci);
2318 lvcc->rx.atmvcc = NULL;
2320 if (lvcc->tx.atmvcc == atmvcc) {
2321 if (atmvcc == lanai->cbrvcc) {
2322 if (lvcc->vbase != NULL)
2323 lanai_cbr_shutdown(lanai);
2324 lanai->cbrvcc = NULL;
2326 lanai_shutdown_tx_vci(lanai, lvcc);
2327 lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci);
2328 lvcc->tx.atmvcc = NULL;
2330 if (--lvcc->nref == 0) {
2331 host_vcc_unbind(lanai, lvcc);
2334 atmvcc->dev_data = NULL;
2335 clear_bit(ATM_VF_ADDR, &atmvcc->flags);
2338 /* open a vcc on the card to vpi/vci */
2339 static int lanai_open(struct atm_vcc *atmvcc)
2341 struct lanai_dev *lanai;
2342 struct lanai_vcc *lvcc;
2344 int vci = atmvcc->vci;
2345 short vpi = atmvcc->vpi;
2346 /* we don't support partial open - it's not really useful anyway */
2347 if ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) ||
2348 (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC))
2350 lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2351 result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci);
2352 if (unlikely(result != 0))
2354 set_bit(ATM_VF_ADDR, &atmvcc->flags);
2355 if (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5)
2357 DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number,
2359 lvcc = lanai->vccs[vci];
2361 lvcc = new_lanai_vcc();
2362 if (unlikely(lvcc == NULL))
2364 atmvcc->dev_data = lvcc;
2367 if (atmvcc->qos.rxtp.traffic_class != ATM_NONE) {
2368 APRINTK(lvcc->rx.atmvcc == NULL, "rx.atmvcc!=NULL, vci=%d\n",
2370 if (atmvcc->qos.aal == ATM_AAL0) {
2371 if (lanai->naal0 == 0)
2372 result = aal0_buffer_allocate(lanai);
2374 result = lanai_setup_rx_vci_aal5(
2375 lanai, lvcc, &atmvcc->qos);
2376 if (unlikely(result != 0))
2378 lvcc->rx.atmvcc = atmvcc;
2379 lvcc->stats.rx_nomem = 0;
2380 lvcc->stats.x.aal5.rx_badlen = 0;
2381 lvcc->stats.x.aal5.service_trash = 0;
2382 lvcc->stats.x.aal5.service_stream = 0;
2383 lvcc->stats.x.aal5.service_rxcrc = 0;
2384 if (atmvcc->qos.aal == ATM_AAL0)
2387 if (atmvcc->qos.txtp.traffic_class != ATM_NONE) {
2388 APRINTK(lvcc->tx.atmvcc == NULL, "tx.atmvcc!=NULL, vci=%d\n",
2390 result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos);
2391 if (unlikely(result != 0))
2393 lvcc->tx.atmvcc = atmvcc;
2394 if (atmvcc->qos.txtp.traffic_class == ATM_CBR) {
2395 APRINTK(lanai->cbrvcc == NULL,
2396 "cbrvcc!=NULL, vci=%d\n", vci);
2397 lanai->cbrvcc = atmvcc;
2400 host_vcc_bind(lanai, lvcc, vci);
2402 * Make sure everything made it to RAM before we tell the card about
2406 if (atmvcc == lvcc->rx.atmvcc)
2407 host_vcc_start_rx(lvcc);
2408 if (atmvcc == lvcc->tx.atmvcc) {
2409 host_vcc_start_tx(lvcc);
2410 if (lanai->cbrvcc == atmvcc)
2411 lanai_cbr_setup(lanai);
2413 set_bit(ATM_VF_READY, &atmvcc->flags);
2416 lanai_close(atmvcc);
2421 static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb)
2423 struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data;
2424 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data;
2425 unsigned long flags;
2426 if (unlikely(lvcc == NULL || lvcc->vbase == NULL ||
2427 lvcc->tx.atmvcc != atmvcc))
2430 if (unlikely(skb == NULL)) {
2431 DPRINTK("lanai_send: skb==NULL for vci=%d\n", atmvcc->vci);
2434 if (unlikely(lanai == NULL)) {
2435 DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci);
2439 ATM_SKB(skb)->vcc = atmvcc;
2440 switch (atmvcc->qos.aal) {
2442 read_lock_irqsave(&vcc_sklist_lock, flags);
2443 vcc_tx_aal5(lanai, lvcc, skb);
2444 read_unlock_irqrestore(&vcc_sklist_lock, flags);
2447 if (unlikely(skb->len != ATM_CELL_SIZE-1))
2449 /* NOTE - this next line is technically invalid - we haven't unshared skb */
2450 cpu_to_be32s((u32 *) skb->data);
2451 read_lock_irqsave(&vcc_sklist_lock, flags);
2452 vcc_tx_aal0(lanai, lvcc, skb);
2453 read_unlock_irqrestore(&vcc_sklist_lock, flags);
2456 DPRINTK("lanai_send: bad aal=%d on vci=%d\n", (int) atmvcc->qos.aal,
2459 lanai_free_skb(atmvcc, skb);
2463 static int lanai_change_qos(struct atm_vcc *atmvcc,
2464 /*const*/ struct atm_qos *qos, int flags)
2466 return -EBUSY; /* TODO: need to write this */
2469 #ifndef CONFIG_PROC_FS
2470 #define lanai_proc_read NULL
2472 static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page)
2474 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data;
2476 struct lanai_vcc *lvcc;
2478 return sprintf(page, DEV_LABEL "(itf %d): chip=LANAI%s, "
2479 "serial=%u, magic=0x%08X, num_vci=%d\n",
2480 atmdev->number, lanai->type==lanai2 ? "2" : "HB",
2481 (unsigned int) lanai->serialno,
2482 (unsigned int) lanai->magicno, lanai->num_vci);
2484 return sprintf(page, "revision: board=%d, pci_if=%d\n",
2485 lanai->board_rev, (int) lanai->pci->revision);
2487 return sprintf(page, "EEPROM ESI: "
2488 "%02X:%02X:%02X:%02X:%02X:%02X\n",
2489 lanai->eeprom[EEPROM_MAC + 0],
2490 lanai->eeprom[EEPROM_MAC + 1],
2491 lanai->eeprom[EEPROM_MAC + 2],
2492 lanai->eeprom[EEPROM_MAC + 3],
2493 lanai->eeprom[EEPROM_MAC + 4],
2494 lanai->eeprom[EEPROM_MAC + 5]);
2496 return sprintf(page, "status: SOOL=%d, LOCD=%d, LED=%d, "
2497 "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0,
2498 (lanai->status & STATUS_LOCD) ? 1 : 0,
2499 (lanai->status & STATUS_LED) ? 1 : 0,
2500 (lanai->status & STATUS_GPIN) ? 1 : 0);
2502 return sprintf(page, "global buffer sizes: service=%Zu, "
2503 "aal0_rx=%Zu\n", lanai_buf_size(&lanai->service),
2504 lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0);
2506 get_statistics(lanai);
2507 return sprintf(page, "cells in error: overflow=%u, "
2508 "closed_vci=%u, bad_HEC=%u, rx_fifo=%u\n",
2509 lanai->stats.ovfl_trash, lanai->stats.vci_trash,
2510 lanai->stats.hec_err, lanai->stats.atm_ovfl);
2513 return sprintf(page, "PCI errors: parity_detect=%u, "
2514 "master_abort=%u, master_target_abort=%u,\n",
2515 lanai->stats.pcierr_parity_detect,
2516 lanai->stats.pcierr_serr_set,
2517 lanai->stats.pcierr_m_target_abort);
2519 return sprintf(page, " slave_target_abort=%u, "
2520 "master_parity=%u\n", lanai->stats.pcierr_s_target_abort,
2521 lanai->stats.pcierr_master_parity);
2523 return sprintf(page, " no_tx=%u, "
2524 "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx,
2525 lanai->stats.service_notx,
2526 lanai->stats.service_rxnotaal5);
2528 return sprintf(page, "resets: dma=%u, card=%u\n",
2529 lanai->stats.dma_reenable, lanai->stats.card_reset);
2530 /* At this point, "left" should be the VCI we're looking for */
2531 read_lock(&vcc_sklist_lock);
2533 if (left >= NUM_VCI) {
2537 if ((lvcc = lanai->vccs[left]) != NULL)
2541 /* Note that we re-use "left" here since we're done with it */
2542 left = sprintf(page, "VCI %4d: nref=%d, rx_nomem=%u", (vci_t) left,
2543 lvcc->nref, lvcc->stats.rx_nomem);
2544 if (lvcc->rx.atmvcc != NULL) {
2545 left += sprintf(&page[left], ",\n rx_AAL=%d",
2546 lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0);
2547 if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5)
2548 left += sprintf(&page[left], ", rx_buf_size=%Zu, "
2549 "rx_bad_len=%u,\n rx_service_trash=%u, "
2550 "rx_service_stream=%u, rx_bad_crc=%u",
2551 lanai_buf_size(&lvcc->rx.buf),
2552 lvcc->stats.x.aal5.rx_badlen,
2553 lvcc->stats.x.aal5.service_trash,
2554 lvcc->stats.x.aal5.service_stream,
2555 lvcc->stats.x.aal5.service_rxcrc);
2557 if (lvcc->tx.atmvcc != NULL)
2558 left += sprintf(&page[left], ",\n tx_AAL=%d, "
2559 "tx_buf_size=%Zu, tx_qos=%cBR, tx_backlogged=%c",
2560 lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0,
2561 lanai_buf_size(&lvcc->tx.buf),
2562 lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U',
2563 vcc_is_backlogged(lvcc) ? 'Y' : 'N');
2564 page[left++] = '\n';
2567 read_unlock(&vcc_sklist_lock);
2570 #endif /* CONFIG_PROC_FS */
2572 /* -------------------- HOOKS: */
2574 static const struct atmdev_ops ops = {
2575 .dev_close = lanai_dev_close,
2577 .close = lanai_close,
2583 .change_qos = lanai_change_qos,
2584 .proc_read = lanai_proc_read,
2585 .owner = THIS_MODULE
2588 /* initialize one probed card */
2589 static int __devinit lanai_init_one(struct pci_dev *pci,
2590 const struct pci_device_id *ident)
2592 struct lanai_dev *lanai;
2593 struct atm_dev *atmdev;
2596 lanai = kmalloc(sizeof(*lanai), GFP_KERNEL);
2597 if (lanai == NULL) {
2598 printk(KERN_ERR DEV_LABEL
2599 ": couldn't allocate dev_data structure!\n");
2603 atmdev = atm_dev_register(DEV_LABEL, &ops, -1, NULL);
2604 if (atmdev == NULL) {
2605 printk(KERN_ERR DEV_LABEL
2606 ": couldn't register atm device!\n");
2611 atmdev->dev_data = lanai;
2613 lanai->type = (enum lanai_type) ident->device;
2615 result = lanai_dev_open(atmdev);
2617 DPRINTK("lanai_start() failed, err=%d\n", -result);
2618 atm_dev_deregister(atmdev);
2624 static struct pci_device_id lanai_pci_tbl[] = {
2625 { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) },
2626 { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) },
2627 { 0, } /* terminal entry */
2629 MODULE_DEVICE_TABLE(pci, lanai_pci_tbl);
2631 static struct pci_driver lanai_driver = {
2633 .id_table = lanai_pci_tbl,
2634 .probe = lanai_init_one,
2637 static int __init lanai_module_init(void)
2641 x = pci_register_driver(&lanai_driver);
2643 printk(KERN_ERR DEV_LABEL ": no adapter found\n");
2647 static void __exit lanai_module_exit(void)
2649 /* We'll only get called when all the interfaces are already
2650 * gone, so there isn't much to do
2652 DPRINTK("cleanup_module()\n");
2653 pci_unregister_driver(&lanai_driver);
2656 module_init(lanai_module_init);
2657 module_exit(lanai_module_exit);
2659 MODULE_AUTHOR("Mitchell Blank Jr <mitch@sfgoth.com>");
2660 MODULE_DESCRIPTION("Efficient Networks Speedstream 3010 driver");
2661 MODULE_LICENSE("GPL");
git.openpandora.org / pandora-kernel.git / blob