2 * sata_sx4.c - Promise SATA
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware documentation available under NDA.
37 The SX4 (PDC20621) chip features a single Host DMA (HDMA) copy
38 engine, DIMM memory, and four ATA engines (one per SATA port).
39 Data is copied to/from DIMM memory by the HDMA engine, before
40 handing off to one (or more) of the ATA engines. The ATA
41 engines operate solely on DIMM memory.
43 The SX4 behaves like a PATA chip, with no SATA controls or
44 knowledge whatsoever, leading to the presumption that
45 PATA<->SATA bridges exist on SX4 boards, external to the
48 The chip is quite capable, supporting an XOR engine and linked
49 hardware commands (permits a string to transactions to be
50 submitted and waited-on as a single unit), and an optional
53 The limiting factor is largely software. This Linux driver was
54 written to multiplex the single HDMA engine to copy disk
55 transactions into a fixed DIMM memory space, from where an ATA
56 engine takes over. As a result, each WRITE looks like this:
58 submit HDMA packet to hardware
59 hardware copies data from system memory to DIMM
60 hardware raises interrupt
62 submit ATA packet to hardware
63 hardware executes ATA WRITE command, w/ data in DIMM
64 hardware raises interrupt
66 and each READ looks like this:
68 submit ATA packet to hardware
69 hardware executes ATA READ command, w/ data in DIMM
70 hardware raises interrupt
72 submit HDMA packet to hardware
73 hardware copies data from DIMM to system memory
74 hardware raises interrupt
76 This is a very slow, lock-step way of doing things that can
77 certainly be improved by motivated kernel hackers.
81 #include <linux/kernel.h>
82 #include <linux/module.h>
83 #include <linux/pci.h>
84 #include <linux/slab.h>
85 #include <linux/blkdev.h>
86 #include <linux/delay.h>
87 #include <linux/interrupt.h>
88 #include <linux/device.h>
89 #include <scsi/scsi_host.h>
90 #include <scsi/scsi_cmnd.h>
91 #include <linux/libata.h>
92 #include "sata_promise.h"
94 #define DRV_NAME "sata_sx4"
95 #define DRV_VERSION "0.12"
102 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
104 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
105 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
106 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
107 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
109 PDC_CTLSTAT = 0x60, /* IDEn control / status */
111 PDC_20621_SEQCTL = 0x400,
112 PDC_20621_SEQMASK = 0x480,
113 PDC_20621_GENERAL_CTL = 0x484,
114 PDC_20621_PAGE_SIZE = (32 * 1024),
116 /* chosen, not constant, values; we design our own DIMM mem map */
117 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
118 PDC_20621_DIMM_BASE = 0x00200000,
119 PDC_20621_DIMM_DATA = (64 * 1024),
120 PDC_DIMM_DATA_STEP = (256 * 1024),
121 PDC_DIMM_WINDOW_STEP = (8 * 1024),
122 PDC_DIMM_HOST_PRD = (6 * 1024),
123 PDC_DIMM_HOST_PKT = (128 * 0),
124 PDC_DIMM_HPKT_PRD = (128 * 1),
125 PDC_DIMM_ATA_PKT = (128 * 2),
126 PDC_DIMM_APKT_PRD = (128 * 3),
127 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
128 PDC_PAGE_WINDOW = 0x40,
129 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
130 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
131 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
133 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
135 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
138 board_20621 = 0, /* FastTrak S150 SX4 */
140 PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
141 PDC_RESET = (1 << 11), /* HDMA/ATA reset */
142 PDC_DMA_ENABLE = (1 << 7), /* DMA start/stop */
145 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
147 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
148 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
149 PDC_I2C_CONTROL = 0x48,
150 PDC_I2C_ADDR_DATA = 0x4C,
151 PDC_DIMM0_CONTROL = 0x80,
152 PDC_DIMM1_CONTROL = 0x84,
153 PDC_SDRAM_CONTROL = 0x88,
154 PDC_I2C_WRITE = 0, /* master -> slave */
155 PDC_I2C_READ = (1 << 6), /* master <- slave */
156 PDC_I2C_START = (1 << 7), /* start I2C proto */
157 PDC_I2C_MASK_INT = (1 << 5), /* mask I2C interrupt */
158 PDC_I2C_COMPLETE = (1 << 16), /* I2C normal compl. */
159 PDC_I2C_NO_ACK = (1 << 20), /* slave no-ack addr */
160 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
161 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
162 PDC_DIMM_SPD_ROW_NUM = 3,
163 PDC_DIMM_SPD_COLUMN_NUM = 4,
164 PDC_DIMM_SPD_MODULE_ROW = 5,
165 PDC_DIMM_SPD_TYPE = 11,
166 PDC_DIMM_SPD_FRESH_RATE = 12,
167 PDC_DIMM_SPD_BANK_NUM = 17,
168 PDC_DIMM_SPD_CAS_LATENCY = 18,
169 PDC_DIMM_SPD_ATTRIBUTE = 21,
170 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
171 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
172 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
173 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
174 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
175 PDC_CTL_STATUS = 0x08,
176 PDC_DIMM_WINDOW_CTLR = 0x0C,
177 PDC_TIME_CONTROL = 0x3C,
178 PDC_TIME_PERIOD = 0x40,
179 PDC_TIME_COUNTER = 0x44,
180 PDC_GENERAL_CTLR = 0x484,
181 PCI_PLL_INIT = 0x8A531824,
182 PCI_X_TCOUNT = 0xEE1E5CFF,
184 /* PDC_TIME_CONTROL bits */
185 PDC_TIMER_BUZZER = (1 << 10),
186 PDC_TIMER_MODE_PERIODIC = 0, /* bits 9:8 == 00 */
187 PDC_TIMER_MODE_ONCE = (1 << 8), /* bits 9:8 == 01 */
188 PDC_TIMER_ENABLE = (1 << 7),
189 PDC_TIMER_MASK_INT = (1 << 5),
190 PDC_TIMER_SEQ_MASK = 0x1f, /* SEQ ID for timer */
191 PDC_TIMER_DEFAULT = PDC_TIMER_MODE_ONCE |
196 #define ECC_ERASE_BUF_SZ (128 * 1024)
198 struct pdc_port_priv {
199 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
204 struct pdc_host_priv {
205 unsigned int doing_hdma;
206 unsigned int hdma_prod;
207 unsigned int hdma_cons;
209 struct ata_queued_cmd *qc;
211 unsigned long pkt_ofs;
216 static int pdc_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
217 static void pdc_error_handler(struct ata_port *ap);
218 static void pdc_freeze(struct ata_port *ap);
219 static void pdc_thaw(struct ata_port *ap);
220 static int pdc_port_start(struct ata_port *ap);
221 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
222 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
223 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
224 static unsigned int pdc20621_dimm_init(struct ata_host *host);
225 static int pdc20621_detect_dimm(struct ata_host *host);
226 static unsigned int pdc20621_i2c_read(struct ata_host *host,
227 u32 device, u32 subaddr, u32 *pdata);
228 static int pdc20621_prog_dimm0(struct ata_host *host);
229 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
230 #ifdef ATA_VERBOSE_DEBUG
231 static void pdc20621_get_from_dimm(struct ata_host *host,
232 void *psource, u32 offset, u32 size);
234 static void pdc20621_put_to_dimm(struct ata_host *host,
235 void *psource, u32 offset, u32 size);
236 static void pdc20621_irq_clear(struct ata_port *ap);
237 static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc);
238 static int pdc_softreset(struct ata_link *link, unsigned int *class,
239 unsigned long deadline);
240 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
241 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
244 static struct scsi_host_template pdc_sata_sht = {
245 ATA_BASE_SHT(DRV_NAME),
246 .sg_tablesize = LIBATA_MAX_PRD,
247 .dma_boundary = ATA_DMA_BOUNDARY,
250 /* TODO: inherit from base port_ops after converting to new EH */
251 static struct ata_port_operations pdc_20621_ops = {
252 .inherits = &ata_sff_port_ops,
254 .check_atapi_dma = pdc_check_atapi_dma,
255 .qc_prep = pdc20621_qc_prep,
256 .qc_issue = pdc20621_qc_issue,
258 .freeze = pdc_freeze,
260 .softreset = pdc_softreset,
261 .error_handler = pdc_error_handler,
262 .lost_interrupt = ATA_OP_NULL,
263 .post_internal_cmd = pdc_post_internal_cmd,
265 .port_start = pdc_port_start,
267 .sff_tf_load = pdc_tf_load_mmio,
268 .sff_exec_command = pdc_exec_command_mmio,
269 .sff_irq_clear = pdc20621_irq_clear,
272 static const struct ata_port_info pdc_port_info[] = {
275 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_ATAPI |
276 ATA_FLAG_PIO_POLLING,
277 .pio_mask = ATA_PIO4,
278 .mwdma_mask = ATA_MWDMA2,
279 .udma_mask = ATA_UDMA6,
280 .port_ops = &pdc_20621_ops,
285 static const struct pci_device_id pdc_sata_pci_tbl[] = {
286 { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
288 { } /* terminate list */
291 static struct pci_driver pdc_sata_pci_driver = {
293 .id_table = pdc_sata_pci_tbl,
294 .probe = pdc_sata_init_one,
295 .remove = ata_pci_remove_one,
299 static int pdc_port_start(struct ata_port *ap)
301 struct device *dev = ap->host->dev;
302 struct pdc_port_priv *pp;
304 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
308 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
312 ap->private_data = pp;
317 static inline void pdc20621_ata_sg(u8 *buf, unsigned int portno,
318 unsigned int total_len)
321 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
322 __le32 *buf32 = (__le32 *) buf;
324 /* output ATA packet S/G table */
325 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
326 (PDC_DIMM_DATA_STEP * portno);
327 VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
328 buf32[dw] = cpu_to_le32(addr);
329 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
331 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
332 PDC_20621_DIMM_BASE +
333 (PDC_DIMM_WINDOW_STEP * portno) +
335 buf32[dw], buf32[dw + 1]);
338 static inline void pdc20621_host_sg(u8 *buf, unsigned int portno,
339 unsigned int total_len)
342 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
343 __le32 *buf32 = (__le32 *) buf;
345 /* output Host DMA packet S/G table */
346 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
347 (PDC_DIMM_DATA_STEP * portno);
349 buf32[dw] = cpu_to_le32(addr);
350 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
352 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
353 PDC_20621_DIMM_BASE +
354 (PDC_DIMM_WINDOW_STEP * portno) +
356 buf32[dw], buf32[dw + 1]);
359 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
360 unsigned int devno, u8 *buf,
364 __le32 *buf32 = (__le32 *) buf;
367 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
368 (PDC_DIMM_WINDOW_STEP * portno) +
370 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
372 i = PDC_DIMM_ATA_PKT;
377 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
378 buf[i++] = PDC_PKT_READ;
379 else if (tf->protocol == ATA_PROT_NODATA)
380 buf[i++] = PDC_PKT_NODATA;
383 buf[i++] = 0; /* reserved */
384 buf[i++] = portno + 1; /* seq. id */
385 buf[i++] = 0xff; /* delay seq. id */
387 /* dimm dma S/G, and next-pkt */
389 if (tf->protocol == ATA_PROT_NODATA)
392 buf32[dw] = cpu_to_le32(dimm_sg);
397 dev_reg = ATA_DEVICE_OBS;
399 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
402 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
405 /* device control register */
406 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
412 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
417 __le32 *buf32 = (__le32 *) buf;
419 unsigned int host_sg = PDC_20621_DIMM_BASE +
420 (PDC_DIMM_WINDOW_STEP * portno) +
422 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
423 (PDC_DIMM_WINDOW_STEP * portno) +
425 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
426 VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
428 dw = PDC_DIMM_HOST_PKT >> 2;
431 * Set up Host DMA packet
433 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
437 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
438 tmp |= (0xff << 24); /* delay seq. id */
439 buf32[dw + 0] = cpu_to_le32(tmp);
440 buf32[dw + 1] = cpu_to_le32(host_sg);
441 buf32[dw + 2] = cpu_to_le32(dimm_sg);
444 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
445 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
453 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
455 struct scatterlist *sg;
456 struct ata_port *ap = qc->ap;
457 struct pdc_port_priv *pp = ap->private_data;
458 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
459 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
460 unsigned int portno = ap->port_no;
461 unsigned int i, si, idx, total_len = 0, sgt_len;
462 __le32 *buf = (__le32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
464 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
466 VPRINTK("ata%u: ENTER\n", ap->print_id);
468 /* hard-code chip #0 */
469 mmio += PDC_CHIP0_OFS;
475 for_each_sg(qc->sg, sg, qc->n_elem, si) {
476 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
477 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
478 total_len += sg_dma_len(sg);
480 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
484 * Build ATA, host DMA packets
486 pdc20621_host_sg(&pp->dimm_buf[0], portno, total_len);
487 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
489 pdc20621_ata_sg(&pp->dimm_buf[0], portno, total_len);
490 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
492 if (qc->tf.flags & ATA_TFLAG_LBA48)
493 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
495 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
497 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
499 /* copy three S/G tables and two packets to DIMM MMIO window */
500 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
501 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
502 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
504 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
506 /* force host FIFO dump */
507 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
509 readl(dimm_mmio); /* MMIO PCI posting flush */
511 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
514 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
516 struct ata_port *ap = qc->ap;
517 struct pdc_port_priv *pp = ap->private_data;
518 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
519 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
520 unsigned int portno = ap->port_no;
523 VPRINTK("ata%u: ENTER\n", ap->print_id);
525 /* hard-code chip #0 */
526 mmio += PDC_CHIP0_OFS;
528 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
530 if (qc->tf.flags & ATA_TFLAG_LBA48)
531 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
533 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
535 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
537 /* copy three S/G tables and two packets to DIMM MMIO window */
538 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
539 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
541 /* force host FIFO dump */
542 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
544 readl(dimm_mmio); /* MMIO PCI posting flush */
546 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
549 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
551 switch (qc->tf.protocol) {
553 pdc20621_dma_prep(qc);
555 case ATA_PROT_NODATA:
556 pdc20621_nodata_prep(qc);
563 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
567 struct ata_port *ap = qc->ap;
568 struct ata_host *host = ap->host;
569 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
571 /* hard-code chip #0 */
572 mmio += PDC_CHIP0_OFS;
574 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
575 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
577 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
578 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
581 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
585 struct ata_port *ap = qc->ap;
586 struct pdc_host_priv *pp = ap->host->private_data;
587 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
589 if (!pp->doing_hdma) {
590 __pdc20621_push_hdma(qc, seq, pkt_ofs);
595 pp->hdma[idx].qc = qc;
596 pp->hdma[idx].seq = seq;
597 pp->hdma[idx].pkt_ofs = pkt_ofs;
601 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
603 struct ata_port *ap = qc->ap;
604 struct pdc_host_priv *pp = ap->host->private_data;
605 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
607 /* if nothing on queue, we're done */
608 if (pp->hdma_prod == pp->hdma_cons) {
613 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
614 pp->hdma[idx].pkt_ofs);
618 #ifdef ATA_VERBOSE_DEBUG
619 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
621 struct ata_port *ap = qc->ap;
622 unsigned int port_no = ap->port_no;
623 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
625 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
626 dimm_mmio += PDC_DIMM_HOST_PKT;
628 printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
629 printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
630 printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
631 printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
634 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
635 #endif /* ATA_VERBOSE_DEBUG */
637 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
639 struct ata_port *ap = qc->ap;
640 struct ata_host *host = ap->host;
641 unsigned int port_no = ap->port_no;
642 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
643 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
644 u8 seq = (u8) (port_no + 1);
645 unsigned int port_ofs;
647 /* hard-code chip #0 */
648 mmio += PDC_CHIP0_OFS;
650 VPRINTK("ata%u: ENTER\n", ap->print_id);
652 wmb(); /* flush PRD, pkt writes */
654 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
656 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
657 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
660 pdc20621_dump_hdma(qc);
661 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
662 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
663 port_ofs + PDC_DIMM_HOST_PKT,
664 port_ofs + PDC_DIMM_HOST_PKT,
667 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
668 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
670 writel(port_ofs + PDC_DIMM_ATA_PKT,
671 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
672 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
673 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
674 port_ofs + PDC_DIMM_ATA_PKT,
675 port_ofs + PDC_DIMM_ATA_PKT,
680 static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc)
682 switch (qc->tf.protocol) {
683 case ATA_PROT_NODATA:
684 if (qc->tf.flags & ATA_TFLAG_POLLING)
688 pdc20621_packet_start(qc);
699 return ata_sff_qc_issue(qc);
702 static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
703 struct ata_queued_cmd *qc,
704 unsigned int doing_hdma,
707 unsigned int port_no = ap->port_no;
708 unsigned int port_ofs =
709 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
711 unsigned int handled = 0;
715 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
716 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
718 /* step two - DMA from DIMM to host */
720 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->print_id,
721 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
722 /* get drive status; clear intr; complete txn */
723 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
725 pdc20621_pop_hdma(qc);
728 /* step one - exec ATA command */
730 u8 seq = (u8) (port_no + 1 + 4);
731 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->print_id,
732 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
734 /* submit hdma pkt */
735 pdc20621_dump_hdma(qc);
736 pdc20621_push_hdma(qc, seq,
737 port_ofs + PDC_DIMM_HOST_PKT);
741 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
743 /* step one - DMA from host to DIMM */
745 u8 seq = (u8) (port_no + 1);
746 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->print_id,
747 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
750 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
751 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
752 writel(port_ofs + PDC_DIMM_ATA_PKT,
753 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
754 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
757 /* step two - execute ATA command */
759 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->print_id,
760 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
761 /* get drive status; clear intr; complete txn */
762 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
764 pdc20621_pop_hdma(qc);
768 /* command completion, but no data xfer */
769 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
771 status = ata_sff_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
772 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
773 qc->err_mask |= ac_err_mask(status);
778 ap->stats.idle_irq++;
784 static void pdc20621_irq_clear(struct ata_port *ap)
786 ioread8(ap->ioaddr.status_addr);
789 static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
791 struct ata_host *host = dev_instance;
794 unsigned int i, tmp, port_no;
795 unsigned int handled = 0;
796 void __iomem *mmio_base;
800 if (!host || !host->iomap[PDC_MMIO_BAR]) {
801 VPRINTK("QUICK EXIT\n");
805 mmio_base = host->iomap[PDC_MMIO_BAR];
807 /* reading should also clear interrupts */
808 mmio_base += PDC_CHIP0_OFS;
809 mask = readl(mmio_base + PDC_20621_SEQMASK);
810 VPRINTK("mask == 0x%x\n", mask);
812 if (mask == 0xffffffff) {
813 VPRINTK("QUICK EXIT 2\n");
816 mask &= 0xffff; /* only 16 tags possible */
818 VPRINTK("QUICK EXIT 3\n");
822 spin_lock(&host->lock);
824 for (i = 1; i < 9; i++) {
828 if (port_no >= host->n_ports)
831 ap = host->ports[port_no];
832 tmp = mask & (1 << i);
833 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
835 struct ata_queued_cmd *qc;
837 qc = ata_qc_from_tag(ap, ap->link.active_tag);
838 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
839 handled += pdc20621_host_intr(ap, qc, (i > 4),
844 spin_unlock(&host->lock);
846 VPRINTK("mask == 0x%x\n", mask);
850 return IRQ_RETVAL(handled);
853 static void pdc_freeze(struct ata_port *ap)
855 void __iomem *mmio = ap->ioaddr.cmd_addr;
858 /* FIXME: if all 4 ATA engines are stopped, also stop HDMA engine */
860 tmp = readl(mmio + PDC_CTLSTAT);
862 tmp &= ~PDC_DMA_ENABLE;
863 writel(tmp, mmio + PDC_CTLSTAT);
864 readl(mmio + PDC_CTLSTAT); /* flush */
867 static void pdc_thaw(struct ata_port *ap)
869 void __iomem *mmio = ap->ioaddr.cmd_addr;
872 /* FIXME: start HDMA engine, if zero ATA engines running */
875 ioread8(ap->ioaddr.status_addr);
877 /* turn IRQ back on */
878 tmp = readl(mmio + PDC_CTLSTAT);
879 tmp &= ~PDC_MASK_INT;
880 writel(tmp, mmio + PDC_CTLSTAT);
881 readl(mmio + PDC_CTLSTAT); /* flush */
884 static void pdc_reset_port(struct ata_port *ap)
886 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
890 /* FIXME: handle HDMA copy engine */
892 for (i = 11; i > 0; i--) {
905 readl(mmio); /* flush */
908 static int pdc_softreset(struct ata_link *link, unsigned int *class,
909 unsigned long deadline)
911 pdc_reset_port(link->ap);
912 return ata_sff_softreset(link, class, deadline);
915 static void pdc_error_handler(struct ata_port *ap)
917 if (!(ap->pflags & ATA_PFLAG_FROZEN))
920 ata_sff_error_handler(ap);
923 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
925 struct ata_port *ap = qc->ap;
927 /* make DMA engine forget about the failed command */
928 if (qc->flags & ATA_QCFLAG_FAILED)
932 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
934 u8 *scsicmd = qc->scsicmd->cmnd;
935 int pio = 1; /* atapi dma off by default */
937 /* Whitelist commands that may use DMA. */
938 switch (scsicmd[0]) {
945 case 0xad: /* READ_DVD_STRUCTURE */
946 case 0xbe: /* READ_CD */
949 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
950 if (scsicmd[0] == WRITE_10) {
956 if (lba >= 0xFFFF4FA2)
962 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
964 WARN_ON(tf->protocol == ATA_PROT_DMA ||
965 tf->protocol == ATAPI_PROT_DMA);
966 ata_sff_tf_load(ap, tf);
970 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
972 WARN_ON(tf->protocol == ATA_PROT_DMA ||
973 tf->protocol == ATAPI_PROT_DMA);
974 ata_sff_exec_command(ap, tf);
978 static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
980 port->cmd_addr = base;
981 port->data_addr = base;
983 port->error_addr = base + 0x4;
984 port->nsect_addr = base + 0x8;
985 port->lbal_addr = base + 0xc;
986 port->lbam_addr = base + 0x10;
987 port->lbah_addr = base + 0x14;
988 port->device_addr = base + 0x18;
990 port->status_addr = base + 0x1c;
991 port->altstatus_addr =
992 port->ctl_addr = base + 0x38;
996 #ifdef ATA_VERBOSE_DEBUG
997 static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
998 u32 offset, u32 size)
1004 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1005 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1007 /* hard-code chip #0 */
1008 mmio += PDC_CHIP0_OFS;
1011 window_size = 0x2000 * 4; /* 32K byte uchar size */
1012 idx = (u16) (offset / window_size);
1014 writel(0x01, mmio + PDC_GENERAL_CTLR);
1015 readl(mmio + PDC_GENERAL_CTLR);
1016 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1017 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1019 offset -= (idx * window_size);
1021 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
1022 (long) (window_size - offset);
1023 memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
1028 for (; (long) size >= (long) window_size ;) {
1029 writel(0x01, mmio + PDC_GENERAL_CTLR);
1030 readl(mmio + PDC_GENERAL_CTLR);
1031 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1032 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1033 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1035 psource += window_size;
1036 size -= window_size;
1041 writel(0x01, mmio + PDC_GENERAL_CTLR);
1042 readl(mmio + PDC_GENERAL_CTLR);
1043 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1044 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1045 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
1052 static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
1053 u32 offset, u32 size)
1059 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1060 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1062 /* hard-code chip #0 */
1063 mmio += PDC_CHIP0_OFS;
1066 window_size = 0x2000 * 4; /* 32K byte uchar size */
1067 idx = (u16) (offset / window_size);
1069 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1070 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1071 offset -= (idx * window_size);
1073 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1074 (long) (window_size - offset);
1075 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1076 writel(0x01, mmio + PDC_GENERAL_CTLR);
1077 readl(mmio + PDC_GENERAL_CTLR);
1081 for (; (long) size >= (long) window_size ;) {
1082 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1083 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1084 memcpy_toio(dimm_mmio, psource, window_size / 4);
1085 writel(0x01, mmio + PDC_GENERAL_CTLR);
1086 readl(mmio + PDC_GENERAL_CTLR);
1087 psource += window_size;
1088 size -= window_size;
1093 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1094 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1095 memcpy_toio(dimm_mmio, psource, size / 4);
1096 writel(0x01, mmio + PDC_GENERAL_CTLR);
1097 readl(mmio + PDC_GENERAL_CTLR);
1102 static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
1103 u32 subaddr, u32 *pdata)
1105 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1110 /* hard-code chip #0 */
1111 mmio += PDC_CHIP0_OFS;
1113 i2creg |= device << 24;
1114 i2creg |= subaddr << 16;
1116 /* Set the device and subaddress */
1117 writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1118 readl(mmio + PDC_I2C_ADDR_DATA);
1120 /* Write Control to perform read operation, mask int */
1121 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1122 mmio + PDC_I2C_CONTROL);
1124 for (count = 0; count <= 1000; count ++) {
1125 status = readl(mmio + PDC_I2C_CONTROL);
1126 if (status & PDC_I2C_COMPLETE) {
1127 status = readl(mmio + PDC_I2C_ADDR_DATA);
1129 } else if (count == 1000)
1133 *pdata = (status >> 8) & 0x000000ff;
1138 static int pdc20621_detect_dimm(struct ata_host *host)
1141 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1142 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1148 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1158 static int pdc20621_prog_dimm0(struct ata_host *host)
1164 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1165 static const struct {
1168 } pdc_i2c_read_data [] = {
1169 { PDC_DIMM_SPD_TYPE, 11 },
1170 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1171 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1172 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1173 { PDC_DIMM_SPD_ROW_NUM, 3 },
1174 { PDC_DIMM_SPD_BANK_NUM, 17 },
1175 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1176 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1177 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1178 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1179 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1180 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1183 /* hard-code chip #0 */
1184 mmio += PDC_CHIP0_OFS;
1186 for (i = 0; i < ARRAY_SIZE(pdc_i2c_read_data); i++)
1187 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1188 pdc_i2c_read_data[i].reg,
1189 &spd0[pdc_i2c_read_data[i].ofs]);
1191 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1192 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1193 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1194 data |= (((((spd0[29] > spd0[28])
1195 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1196 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1198 if (spd0[18] & 0x08)
1199 data |= ((0x03) << 14);
1200 else if (spd0[18] & 0x04)
1201 data |= ((0x02) << 14);
1202 else if (spd0[18] & 0x01)
1203 data |= ((0x01) << 14);
1208 Calculate the size of bDIMMSize (power of 2) and
1209 merge the DIMM size by program start/end address.
1212 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1213 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1214 data |= (((size / 16) - 1) << 16);
1217 writel(data, mmio + PDC_DIMM0_CONTROL);
1218 readl(mmio + PDC_DIMM0_CONTROL);
1223 static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
1227 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1229 /* hard-code chip #0 */
1230 mmio += PDC_CHIP0_OFS;
1233 Set To Default : DIMM Module Global Control Register (0x022259F1)
1234 DIMM Arbitration Disable (bit 20)
1235 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1236 Refresh Enable (bit 17)
1240 writel(data, mmio + PDC_SDRAM_CONTROL);
1241 readl(mmio + PDC_SDRAM_CONTROL);
1243 /* Turn on for ECC */
1244 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1245 PDC_DIMM_SPD_TYPE, &spd0);
1247 data |= (0x01 << 16);
1248 writel(data, mmio + PDC_SDRAM_CONTROL);
1249 readl(mmio + PDC_SDRAM_CONTROL);
1250 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1253 /* DIMM Initialization Select/Enable (bit 18/19) */
1256 writel(data, mmio + PDC_SDRAM_CONTROL);
1259 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
1260 data = readl(mmio + PDC_SDRAM_CONTROL);
1261 if (!(data & (1<<19))) {
1271 static unsigned int pdc20621_dimm_init(struct ata_host *host)
1273 int speed, size, length;
1274 u32 addr, spd0, pci_status;
1275 u32 time_period = 0;
1280 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1282 /* hard-code chip #0 */
1283 mmio += PDC_CHIP0_OFS;
1285 /* Initialize PLL based upon PCI Bus Frequency */
1287 /* Initialize Time Period Register */
1288 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1289 time_period = readl(mmio + PDC_TIME_PERIOD);
1290 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1293 writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1294 readl(mmio + PDC_TIME_CONTROL);
1296 /* Wait 3 seconds */
1300 When timer is enabled, counter is decreased every internal
1304 tcount = readl(mmio + PDC_TIME_COUNTER);
1305 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1308 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1309 register should be >= (0xffffffff - 3x10^8).
1311 if (tcount >= PCI_X_TCOUNT) {
1312 ticks = (time_period - tcount);
1313 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1315 clock = (ticks / 300000);
1316 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1318 clock = (clock * 33);
1319 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1321 /* PLL F Param (bit 22:16) */
1322 fparam = (1400000 / clock) - 2;
1323 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1325 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1326 pci_status = (0x8a001824 | (fparam << 16));
1328 pci_status = PCI_PLL_INIT;
1330 /* Initialize PLL. */
1331 VPRINTK("pci_status: 0x%x\n", pci_status);
1332 writel(pci_status, mmio + PDC_CTL_STATUS);
1333 readl(mmio + PDC_CTL_STATUS);
1336 Read SPD of DIMM by I2C interface,
1337 and program the DIMM Module Controller.
1339 if (!(speed = pdc20621_detect_dimm(host))) {
1340 printk(KERN_ERR "Detect Local DIMM Fail\n");
1341 return 1; /* DIMM error */
1343 VPRINTK("Local DIMM Speed = %d\n", speed);
1345 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1346 size = pdc20621_prog_dimm0(host);
1347 VPRINTK("Local DIMM Size = %dMB\n", size);
1349 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1350 if (pdc20621_prog_dimm_global(host)) {
1351 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1355 #ifdef ATA_VERBOSE_DEBUG
1357 u8 test_parttern1[40] =
1358 {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1359 'N','o','t',' ','Y','e','t',' ',
1360 'D','e','f','i','n','e','d',' ',
1362 '9','8','0','3','1','6','1','2',0,0};
1363 u8 test_parttern2[40] = {0};
1365 pdc20621_put_to_dimm(host, test_parttern2, 0x10040, 40);
1366 pdc20621_put_to_dimm(host, test_parttern2, 0x40, 40);
1368 pdc20621_put_to_dimm(host, test_parttern1, 0x10040, 40);
1369 pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
1370 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1371 test_parttern2[1], &(test_parttern2[2]));
1372 pdc20621_get_from_dimm(host, test_parttern2, 0x10040,
1374 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1375 test_parttern2[1], &(test_parttern2[2]));
1377 pdc20621_put_to_dimm(host, test_parttern1, 0x40, 40);
1378 pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
1379 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1380 test_parttern2[1], &(test_parttern2[2]));
1384 /* ECC initiliazation. */
1386 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1387 PDC_DIMM_SPD_TYPE, &spd0);
1390 VPRINTK("Start ECC initialization\n");
1392 length = size * 1024 * 1024;
1393 buf = kzalloc(ECC_ERASE_BUF_SZ, GFP_KERNEL);
1394 while (addr < length) {
1395 pdc20621_put_to_dimm(host, buf, addr,
1397 addr += ECC_ERASE_BUF_SZ;
1400 VPRINTK("Finish ECC initialization\n");
1406 static void pdc_20621_init(struct ata_host *host)
1409 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1411 /* hard-code chip #0 */
1412 mmio += PDC_CHIP0_OFS;
1415 * Select page 0x40 for our 32k DIMM window
1417 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1418 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1419 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1424 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1426 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1427 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1431 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1433 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1434 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1437 static int pdc_sata_init_one(struct pci_dev *pdev,
1438 const struct pci_device_id *ent)
1440 const struct ata_port_info *ppi[] =
1441 { &pdc_port_info[ent->driver_data], NULL };
1442 struct ata_host *host;
1443 struct pdc_host_priv *hpriv;
1446 ata_print_version_once(&pdev->dev, DRV_VERSION);
1449 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1450 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1451 if (!host || !hpriv)
1454 host->private_data = hpriv;
1456 /* acquire resources and fill host */
1457 rc = pcim_enable_device(pdev);
1461 rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1464 pcim_pin_device(pdev);
1467 host->iomap = pcim_iomap_table(pdev);
1469 for (i = 0; i < 4; i++) {
1470 struct ata_port *ap = host->ports[i];
1471 void __iomem *base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1472 unsigned int offset = 0x200 + i * 0x80;
1474 pdc_sata_setup_port(&ap->ioaddr, base + offset);
1476 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1477 ata_port_pbar_desc(ap, PDC_DIMM_BAR, -1, "dimm");
1478 ata_port_pbar_desc(ap, PDC_MMIO_BAR, offset, "port");
1481 /* configure and activate */
1482 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1485 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1489 if (pdc20621_dimm_init(host))
1491 pdc_20621_init(host);
1493 pci_set_master(pdev);
1494 return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1495 IRQF_SHARED, &pdc_sata_sht);
1498 module_pci_driver(pdc_sata_pci_driver);
1500 MODULE_AUTHOR("Jeff Garzik");
1501 MODULE_DESCRIPTION("Promise SATA low-level driver");
1502 MODULE_LICENSE("GPL");
1503 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1504 MODULE_VERSION(DRV_VERSION);