2 * sata_mv.c - Marvell SATA support
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 * --> Errata workaround for NCQ device errors.
30 * --> More errata workarounds for PCI-X.
32 * --> Complete a full errata audit for all chipsets to identify others.
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
40 * --> Develop a low-power-consumption strategy, and implement it.
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
55 #include <linux/kernel.h>
56 #include <linux/module.h>
57 #include <linux/pci.h>
58 #include <linux/init.h>
59 #include <linux/blkdev.h>
60 #include <linux/delay.h>
61 #include <linux/interrupt.h>
62 #include <linux/dmapool.h>
63 #include <linux/dma-mapping.h>
64 #include <linux/device.h>
65 #include <linux/platform_device.h>
66 #include <linux/ata_platform.h>
67 #include <linux/mbus.h>
68 #include <linux/bitops.h>
69 #include <scsi/scsi_host.h>
70 #include <scsi/scsi_cmnd.h>
71 #include <scsi/scsi_device.h>
72 #include <linux/libata.h>
74 #define DRV_NAME "sata_mv"
75 #define DRV_VERSION "1.21"
78 /* BAR's are enumerated in terms of pci_resource_start() terms */
79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
80 MV_IO_BAR = 2, /* offset 0x18: IO space */
81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
94 MV_SATAHC0_REG_BASE = 0x20000,
95 MV_FLASH_CTL_OFS = 0x1046c,
96 MV_GPIO_PORT_CTL_OFS = 0x104f0,
97 MV_RESET_CFG_OFS = 0x180d8,
99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
108 * CRPB needs alignment on a 256B boundary. Size == 256B
109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
117 MV_PORT_HC_SHIFT = 2,
118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
126 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
127 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
128 ATA_FLAG_PIO_POLLING,
130 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
132 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
133 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
134 ATA_FLAG_NCQ | ATA_FLAG_AN,
136 CRQB_FLAG_READ = (1 << 0),
138 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
139 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
140 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
141 CRQB_CMD_ADDR_SHIFT = 8,
142 CRQB_CMD_CS = (0x2 << 11),
143 CRQB_CMD_LAST = (1 << 15),
145 CRPB_FLAG_STATUS_SHIFT = 8,
146 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
147 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
149 EPRD_FLAG_END_OF_TBL = (1 << 31),
151 /* PCI interface registers */
153 PCI_COMMAND_OFS = 0xc00,
154 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
156 PCI_MAIN_CMD_STS_OFS = 0xd30,
157 STOP_PCI_MASTER = (1 << 2),
158 PCI_MASTER_EMPTY = (1 << 3),
159 GLOB_SFT_RST = (1 << 4),
161 MV_PCI_MODE_OFS = 0xd00,
162 MV_PCI_MODE_MASK = 0x30,
164 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
165 MV_PCI_DISC_TIMER = 0xd04,
166 MV_PCI_MSI_TRIGGER = 0xc38,
167 MV_PCI_SERR_MASK = 0xc28,
168 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
169 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
170 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
171 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
172 MV_PCI_ERR_COMMAND = 0x1d50,
174 PCI_IRQ_CAUSE_OFS = 0x1d58,
175 PCI_IRQ_MASK_OFS = 0x1d5c,
176 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
178 PCIE_IRQ_CAUSE_OFS = 0x1900,
179 PCIE_IRQ_MASK_OFS = 0x1910,
180 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
182 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
183 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
184 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
185 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
186 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
187 ERR_IRQ = (1 << 0), /* shift by port # */
188 DONE_IRQ = (1 << 1), /* shift by port # */
189 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
190 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
192 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
193 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
194 PORTS_0_3_COAL_DONE = (1 << 8),
195 PORTS_4_7_COAL_DONE = (1 << 17),
196 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
197 GPIO_INT = (1 << 22),
198 SELF_INT = (1 << 23),
199 TWSI_INT = (1 << 24),
200 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
201 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
202 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
204 /* SATAHC registers */
207 HC_IRQ_CAUSE_OFS = 0x14,
208 DMA_IRQ = (1 << 0), /* shift by port # */
209 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
210 DEV_IRQ = (1 << 8), /* shift by port # */
212 /* Shadow block registers */
214 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
217 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
218 SATA_ACTIVE_OFS = 0x350,
219 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
220 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
223 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
228 SATA_IFCTL_OFS = 0x344,
229 SATA_TESTCTL_OFS = 0x348,
230 SATA_IFSTAT_OFS = 0x34c,
231 VENDOR_UNIQUE_FIS_OFS = 0x35c,
234 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
235 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
238 MV5_LTMODE_OFS = 0x30,
239 MV5_PHY_CTL_OFS = 0x0C,
240 SATA_INTERFACE_CFG_OFS = 0x050,
242 MV_M2_PREAMP_MASK = 0x7e0,
246 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
247 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
248 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
249 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
250 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
251 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
252 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
254 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
255 EDMA_ERR_IRQ_MASK_OFS = 0xc,
256 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
257 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
258 EDMA_ERR_DEV = (1 << 2), /* device error */
259 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
260 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
261 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
262 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
263 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
264 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
265 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
266 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
267 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
268 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
269 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
271 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
272 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
273 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
274 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
275 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
277 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
279 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
280 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
281 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
282 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
283 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
284 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
286 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
288 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
289 EDMA_ERR_OVERRUN_5 = (1 << 5),
290 EDMA_ERR_UNDERRUN_5 = (1 << 6),
292 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
293 EDMA_ERR_LNK_CTRL_RX_1 |
294 EDMA_ERR_LNK_CTRL_RX_3 |
295 EDMA_ERR_LNK_CTRL_TX,
297 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
307 EDMA_ERR_LNK_CTRL_RX_2 |
308 EDMA_ERR_LNK_DATA_RX |
309 EDMA_ERR_LNK_DATA_TX |
310 EDMA_ERR_TRANS_PROTO,
312 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
317 EDMA_ERR_UNDERRUN_5 |
318 EDMA_ERR_SELF_DIS_5 |
324 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
325 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
327 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
328 EDMA_REQ_Q_PTR_SHIFT = 5,
330 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
331 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
332 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
333 EDMA_RSP_Q_PTR_SHIFT = 3,
335 EDMA_CMD_OFS = 0x28, /* EDMA command register */
336 EDMA_EN = (1 << 0), /* enable EDMA */
337 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
338 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
340 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
341 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
342 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
344 EDMA_IORDY_TMOUT_OFS = 0x34,
345 EDMA_ARB_CFG_OFS = 0x38,
347 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
349 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
351 /* Host private flags (hp_flags) */
352 MV_HP_FLAG_MSI = (1 << 0),
353 MV_HP_ERRATA_50XXB0 = (1 << 1),
354 MV_HP_ERRATA_50XXB2 = (1 << 2),
355 MV_HP_ERRATA_60X1B2 = (1 << 3),
356 MV_HP_ERRATA_60X1C0 = (1 << 4),
357 MV_HP_ERRATA_XX42A0 = (1 << 5),
358 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
359 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
360 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
361 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
362 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
363 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
365 /* Port private flags (pp_flags) */
366 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
367 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
368 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
369 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
372 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
373 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
374 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
375 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
376 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
378 #define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
379 #define WINDOW_BASE(i) (0x20034 + ((i) << 4))
382 /* DMA boundary 0xffff is required by the s/g splitting
383 * we need on /length/ in mv_fill-sg().
385 MV_DMA_BOUNDARY = 0xffffU,
387 /* mask of register bits containing lower 32 bits
388 * of EDMA request queue DMA address
390 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
392 /* ditto, for response queue */
393 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
407 /* Command ReQuest Block: 32B */
423 /* Command ResPonse Block: 8B */
430 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
438 struct mv_port_priv {
439 struct mv_crqb *crqb;
441 struct mv_crpb *crpb;
443 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
444 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
446 unsigned int req_idx;
447 unsigned int resp_idx;
450 unsigned int delayed_eh_pmp_map;
453 struct mv_port_signal {
458 struct mv_host_priv {
461 struct mv_port_signal signal[8];
462 const struct mv_hw_ops *ops;
465 void __iomem *main_irq_cause_addr;
466 void __iomem *main_irq_mask_addr;
471 * These consistent DMA memory pools give us guaranteed
472 * alignment for hardware-accessed data structures,
473 * and less memory waste in accomplishing the alignment.
475 struct dma_pool *crqb_pool;
476 struct dma_pool *crpb_pool;
477 struct dma_pool *sg_tbl_pool;
481 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
483 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
484 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
486 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
488 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
489 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
492 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
493 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
494 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
495 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
496 static int mv_port_start(struct ata_port *ap);
497 static void mv_port_stop(struct ata_port *ap);
498 static int mv_qc_defer(struct ata_queued_cmd *qc);
499 static void mv_qc_prep(struct ata_queued_cmd *qc);
500 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
501 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
502 static int mv_hardreset(struct ata_link *link, unsigned int *class,
503 unsigned long deadline);
504 static void mv_eh_freeze(struct ata_port *ap);
505 static void mv_eh_thaw(struct ata_port *ap);
506 static void mv6_dev_config(struct ata_device *dev);
508 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
510 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
511 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
513 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
515 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
516 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
518 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
520 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
521 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
523 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
525 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
526 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
528 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
530 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
531 void __iomem *mmio, unsigned int n_hc);
532 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
534 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
535 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
536 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
537 unsigned int port_no);
538 static int mv_stop_edma(struct ata_port *ap);
539 static int mv_stop_edma_engine(void __iomem *port_mmio);
540 static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
542 static void mv_pmp_select(struct ata_port *ap, int pmp);
543 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
544 unsigned long deadline);
545 static int mv_softreset(struct ata_link *link, unsigned int *class,
546 unsigned long deadline);
547 static void mv_pmp_error_handler(struct ata_port *ap);
548 static void mv_process_crpb_entries(struct ata_port *ap,
549 struct mv_port_priv *pp);
551 /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
552 * because we have to allow room for worst case splitting of
553 * PRDs for 64K boundaries in mv_fill_sg().
555 static struct scsi_host_template mv5_sht = {
556 ATA_BASE_SHT(DRV_NAME),
557 .sg_tablesize = MV_MAX_SG_CT / 2,
558 .dma_boundary = MV_DMA_BOUNDARY,
561 static struct scsi_host_template mv6_sht = {
562 ATA_NCQ_SHT(DRV_NAME),
563 .can_queue = MV_MAX_Q_DEPTH - 1,
564 .sg_tablesize = MV_MAX_SG_CT / 2,
565 .dma_boundary = MV_DMA_BOUNDARY,
568 static struct ata_port_operations mv5_ops = {
569 .inherits = &ata_sff_port_ops,
571 .qc_defer = mv_qc_defer,
572 .qc_prep = mv_qc_prep,
573 .qc_issue = mv_qc_issue,
575 .freeze = mv_eh_freeze,
577 .hardreset = mv_hardreset,
578 .error_handler = ata_std_error_handler, /* avoid SFF EH */
579 .post_internal_cmd = ATA_OP_NULL,
581 .scr_read = mv5_scr_read,
582 .scr_write = mv5_scr_write,
584 .port_start = mv_port_start,
585 .port_stop = mv_port_stop,
588 static struct ata_port_operations mv6_ops = {
589 .inherits = &mv5_ops,
590 .dev_config = mv6_dev_config,
591 .scr_read = mv_scr_read,
592 .scr_write = mv_scr_write,
594 .pmp_hardreset = mv_pmp_hardreset,
595 .pmp_softreset = mv_softreset,
596 .softreset = mv_softreset,
597 .error_handler = mv_pmp_error_handler,
600 static struct ata_port_operations mv_iie_ops = {
601 .inherits = &mv6_ops,
602 .dev_config = ATA_OP_NULL,
603 .qc_prep = mv_qc_prep_iie,
606 static const struct ata_port_info mv_port_info[] = {
608 .flags = MV_COMMON_FLAGS,
609 .pio_mask = 0x1f, /* pio0-4 */
610 .udma_mask = ATA_UDMA6,
611 .port_ops = &mv5_ops,
614 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
615 .pio_mask = 0x1f, /* pio0-4 */
616 .udma_mask = ATA_UDMA6,
617 .port_ops = &mv5_ops,
620 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
621 .pio_mask = 0x1f, /* pio0-4 */
622 .udma_mask = ATA_UDMA6,
623 .port_ops = &mv5_ops,
626 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
627 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
629 .pio_mask = 0x1f, /* pio0-4 */
630 .udma_mask = ATA_UDMA6,
631 .port_ops = &mv6_ops,
634 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
635 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
636 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
637 .pio_mask = 0x1f, /* pio0-4 */
638 .udma_mask = ATA_UDMA6,
639 .port_ops = &mv6_ops,
642 .flags = MV_GENIIE_FLAGS,
643 .pio_mask = 0x1f, /* pio0-4 */
644 .udma_mask = ATA_UDMA6,
645 .port_ops = &mv_iie_ops,
648 .flags = MV_GENIIE_FLAGS,
649 .pio_mask = 0x1f, /* pio0-4 */
650 .udma_mask = ATA_UDMA6,
651 .port_ops = &mv_iie_ops,
654 .flags = MV_GENIIE_FLAGS,
655 .pio_mask = 0x1f, /* pio0-4 */
656 .udma_mask = ATA_UDMA6,
657 .port_ops = &mv_iie_ops,
661 static const struct pci_device_id mv_pci_tbl[] = {
662 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
663 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
665 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
666 /* RocketRAID 1740/174x have different identifiers */
667 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
668 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
670 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
671 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
673 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
674 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
676 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
679 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
681 /* Marvell 7042 support */
682 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
684 /* Highpoint RocketRAID PCIe series */
685 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
686 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
688 { } /* terminate list */
691 static const struct mv_hw_ops mv5xxx_ops = {
692 .phy_errata = mv5_phy_errata,
693 .enable_leds = mv5_enable_leds,
694 .read_preamp = mv5_read_preamp,
695 .reset_hc = mv5_reset_hc,
696 .reset_flash = mv5_reset_flash,
697 .reset_bus = mv5_reset_bus,
700 static const struct mv_hw_ops mv6xxx_ops = {
701 .phy_errata = mv6_phy_errata,
702 .enable_leds = mv6_enable_leds,
703 .read_preamp = mv6_read_preamp,
704 .reset_hc = mv6_reset_hc,
705 .reset_flash = mv6_reset_flash,
706 .reset_bus = mv_reset_pci_bus,
709 static const struct mv_hw_ops mv_soc_ops = {
710 .phy_errata = mv6_phy_errata,
711 .enable_leds = mv_soc_enable_leds,
712 .read_preamp = mv_soc_read_preamp,
713 .reset_hc = mv_soc_reset_hc,
714 .reset_flash = mv_soc_reset_flash,
715 .reset_bus = mv_soc_reset_bus,
722 static inline void writelfl(unsigned long data, void __iomem *addr)
725 (void) readl(addr); /* flush to avoid PCI posted write */
728 static inline unsigned int mv_hc_from_port(unsigned int port)
730 return port >> MV_PORT_HC_SHIFT;
733 static inline unsigned int mv_hardport_from_port(unsigned int port)
735 return port & MV_PORT_MASK;
739 * Consolidate some rather tricky bit shift calculations.
740 * This is hot-path stuff, so not a function.
741 * Simple code, with two return values, so macro rather than inline.
743 * port is the sole input, in range 0..7.
744 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
745 * hardport is the other output, in range 0..3.
747 * Note that port and hardport may be the same variable in some cases.
749 #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
751 shift = mv_hc_from_port(port) * HC_SHIFT; \
752 hardport = mv_hardport_from_port(port); \
753 shift += hardport * 2; \
756 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
758 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
761 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
764 return mv_hc_base(base, mv_hc_from_port(port));
767 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
769 return mv_hc_base_from_port(base, port) +
770 MV_SATAHC_ARBTR_REG_SZ +
771 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
774 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
776 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
777 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
779 return hc_mmio + ofs;
782 static inline void __iomem *mv_host_base(struct ata_host *host)
784 struct mv_host_priv *hpriv = host->private_data;
788 static inline void __iomem *mv_ap_base(struct ata_port *ap)
790 return mv_port_base(mv_host_base(ap->host), ap->port_no);
793 static inline int mv_get_hc_count(unsigned long port_flags)
795 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
798 static void mv_set_edma_ptrs(void __iomem *port_mmio,
799 struct mv_host_priv *hpriv,
800 struct mv_port_priv *pp)
805 * initialize request queue
807 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
808 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
810 WARN_ON(pp->crqb_dma & 0x3ff);
811 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
812 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
813 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
815 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
816 writelfl((pp->crqb_dma & 0xffffffff) | index,
817 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
819 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
822 * initialize response queue
824 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
825 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
827 WARN_ON(pp->crpb_dma & 0xff);
828 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
830 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
831 writelfl((pp->crpb_dma & 0xffffffff) | index,
832 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
834 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
836 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
837 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
840 static void mv_set_main_irq_mask(struct ata_host *host,
841 u32 disable_bits, u32 enable_bits)
843 struct mv_host_priv *hpriv = host->private_data;
844 u32 old_mask, new_mask;
846 old_mask = hpriv->main_irq_mask;
847 new_mask = (old_mask & ~disable_bits) | enable_bits;
848 if (new_mask != old_mask) {
849 hpriv->main_irq_mask = new_mask;
850 writelfl(new_mask, hpriv->main_irq_mask_addr);
854 static void mv_enable_port_irqs(struct ata_port *ap,
855 unsigned int port_bits)
857 unsigned int shift, hardport, port = ap->port_no;
858 u32 disable_bits, enable_bits;
860 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
862 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
863 enable_bits = port_bits << shift;
864 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
868 * mv_start_dma - Enable eDMA engine
869 * @base: port base address
870 * @pp: port private data
872 * Verify the local cache of the eDMA state is accurate with a
876 * Inherited from caller.
878 static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
879 struct mv_port_priv *pp, u8 protocol)
881 int want_ncq = (protocol == ATA_PROT_NCQ);
883 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
884 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
885 if (want_ncq != using_ncq)
888 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
889 struct mv_host_priv *hpriv = ap->host->private_data;
890 int hardport = mv_hardport_from_port(ap->port_no);
891 void __iomem *hc_mmio = mv_hc_base_from_port(
892 mv_host_base(ap->host), hardport);
893 u32 hc_irq_cause, ipending;
895 /* clear EDMA event indicators, if any */
896 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
898 /* clear EDMA interrupt indicator, if any */
899 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
900 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
901 if (hc_irq_cause & ipending) {
902 writelfl(hc_irq_cause & ~ipending,
903 hc_mmio + HC_IRQ_CAUSE_OFS);
906 mv_edma_cfg(ap, want_ncq);
908 /* clear FIS IRQ Cause */
909 if (IS_GEN_IIE(hpriv))
910 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
912 mv_set_edma_ptrs(port_mmio, hpriv, pp);
913 mv_enable_port_irqs(ap, DONE_IRQ|ERR_IRQ);
915 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
916 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
920 static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
922 void __iomem *port_mmio = mv_ap_base(ap);
923 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
924 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
928 * Wait for the EDMA engine to finish transactions in progress.
929 * No idea what a good "timeout" value might be, but measurements
930 * indicate that it often requires hundreds of microseconds
931 * with two drives in-use. So we use the 15msec value above
932 * as a rough guess at what even more drives might require.
934 for (i = 0; i < timeout; ++i) {
935 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
936 if ((edma_stat & empty_idle) == empty_idle)
940 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
944 * mv_stop_edma_engine - Disable eDMA engine
945 * @port_mmio: io base address
948 * Inherited from caller.
950 static int mv_stop_edma_engine(void __iomem *port_mmio)
954 /* Disable eDMA. The disable bit auto clears. */
955 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
957 /* Wait for the chip to confirm eDMA is off. */
958 for (i = 10000; i > 0; i--) {
959 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
960 if (!(reg & EDMA_EN))
967 static int mv_stop_edma(struct ata_port *ap)
969 void __iomem *port_mmio = mv_ap_base(ap);
970 struct mv_port_priv *pp = ap->private_data;
972 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
974 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
975 mv_wait_for_edma_empty_idle(ap);
976 if (mv_stop_edma_engine(port_mmio)) {
977 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
984 static void mv_dump_mem(void __iomem *start, unsigned bytes)
987 for (b = 0; b < bytes; ) {
988 DPRINTK("%p: ", start + b);
989 for (w = 0; b < bytes && w < 4; w++) {
990 printk("%08x ", readl(start + b));
998 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1003 for (b = 0; b < bytes; ) {
1004 DPRINTK("%02x: ", b);
1005 for (w = 0; b < bytes && w < 4; w++) {
1006 (void) pci_read_config_dword(pdev, b, &dw);
1007 printk("%08x ", dw);
1014 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1015 struct pci_dev *pdev)
1018 void __iomem *hc_base = mv_hc_base(mmio_base,
1019 port >> MV_PORT_HC_SHIFT);
1020 void __iomem *port_base;
1021 int start_port, num_ports, p, start_hc, num_hcs, hc;
1024 start_hc = start_port = 0;
1025 num_ports = 8; /* shld be benign for 4 port devs */
1028 start_hc = port >> MV_PORT_HC_SHIFT;
1030 num_ports = num_hcs = 1;
1032 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
1033 num_ports > 1 ? num_ports - 1 : start_port);
1036 DPRINTK("PCI config space regs:\n");
1037 mv_dump_pci_cfg(pdev, 0x68);
1039 DPRINTK("PCI regs:\n");
1040 mv_dump_mem(mmio_base+0xc00, 0x3c);
1041 mv_dump_mem(mmio_base+0xd00, 0x34);
1042 mv_dump_mem(mmio_base+0xf00, 0x4);
1043 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1044 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
1045 hc_base = mv_hc_base(mmio_base, hc);
1046 DPRINTK("HC regs (HC %i):\n", hc);
1047 mv_dump_mem(hc_base, 0x1c);
1049 for (p = start_port; p < start_port + num_ports; p++) {
1050 port_base = mv_port_base(mmio_base, p);
1051 DPRINTK("EDMA regs (port %i):\n", p);
1052 mv_dump_mem(port_base, 0x54);
1053 DPRINTK("SATA regs (port %i):\n", p);
1054 mv_dump_mem(port_base+0x300, 0x60);
1059 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1063 switch (sc_reg_in) {
1067 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1070 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1079 static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
1081 unsigned int ofs = mv_scr_offset(sc_reg_in);
1083 if (ofs != 0xffffffffU) {
1084 *val = readl(mv_ap_base(ap) + ofs);
1090 static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1092 unsigned int ofs = mv_scr_offset(sc_reg_in);
1094 if (ofs != 0xffffffffU) {
1095 writelfl(val, mv_ap_base(ap) + ofs);
1101 static void mv6_dev_config(struct ata_device *adev)
1104 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1106 * Gen-II does not support NCQ over a port multiplier
1107 * (no FIS-based switching).
1109 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1110 * See mv_qc_prep() for more info.
1112 if (adev->flags & ATA_DFLAG_NCQ) {
1113 if (sata_pmp_attached(adev->link->ap)) {
1114 adev->flags &= ~ATA_DFLAG_NCQ;
1115 ata_dev_printk(adev, KERN_INFO,
1116 "NCQ disabled for command-based switching\n");
1117 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1118 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1119 ata_dev_printk(adev, KERN_INFO,
1120 "max_sectors limited to %u for NCQ\n",
1126 static int mv_qc_defer(struct ata_queued_cmd *qc)
1128 struct ata_link *link = qc->dev->link;
1129 struct ata_port *ap = link->ap;
1130 struct mv_port_priv *pp = ap->private_data;
1133 * Don't allow new commands if we're in a delayed EH state
1134 * for NCQ and/or FIS-based switching.
1136 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1137 return ATA_DEFER_PORT;
1139 * If the port is completely idle, then allow the new qc.
1141 if (ap->nr_active_links == 0)
1144 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1146 * The port is operating in host queuing mode (EDMA).
1147 * It can accomodate a new qc if the qc protocol
1148 * is compatible with the current host queue mode.
1150 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1152 * The host queue (EDMA) is in NCQ mode.
1153 * If the new qc is also an NCQ command,
1154 * then allow the new qc.
1156 if (qc->tf.protocol == ATA_PROT_NCQ)
1160 * The host queue (EDMA) is in non-NCQ, DMA mode.
1161 * If the new qc is also a non-NCQ, DMA command,
1162 * then allow the new qc.
1164 if (qc->tf.protocol == ATA_PROT_DMA)
1168 return ATA_DEFER_PORT;
1171 static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
1173 u32 new_fiscfg, old_fiscfg;
1174 u32 new_ltmode, old_ltmode;
1175 u32 new_haltcond, old_haltcond;
1177 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1178 old_ltmode = readl(port_mmio + LTMODE_OFS);
1179 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1181 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1182 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1183 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1186 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1187 new_ltmode = old_ltmode | LTMODE_BIT8;
1189 new_haltcond &= ~EDMA_ERR_DEV;
1191 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
1194 if (new_fiscfg != old_fiscfg)
1195 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
1196 if (new_ltmode != old_ltmode)
1197 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
1198 if (new_haltcond != old_haltcond)
1199 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
1202 static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1204 struct mv_host_priv *hpriv = ap->host->private_data;
1207 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1208 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1210 new = old | (1 << 22);
1212 new = old & ~(1 << 22);
1214 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1217 static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
1220 struct mv_port_priv *pp = ap->private_data;
1221 struct mv_host_priv *hpriv = ap->host->private_data;
1222 void __iomem *port_mmio = mv_ap_base(ap);
1224 /* set up non-NCQ EDMA configuration */
1225 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
1226 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
1228 if (IS_GEN_I(hpriv))
1229 cfg |= (1 << 8); /* enab config burst size mask */
1231 else if (IS_GEN_II(hpriv)) {
1232 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
1233 mv_60x1_errata_sata25(ap, want_ncq);
1235 } else if (IS_GEN_IIE(hpriv)) {
1236 int want_fbs = sata_pmp_attached(ap);
1238 * Possible future enhancement:
1240 * The chip can use FBS with non-NCQ, if we allow it,
1241 * But first we need to have the error handling in place
1242 * for this mode (datasheet section 7.3.15.4.2.3).
1243 * So disallow non-NCQ FBS for now.
1245 want_fbs &= want_ncq;
1247 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1250 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1251 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1254 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1255 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1257 cfg |= (1 << 18); /* enab early completion */
1258 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1259 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
1263 cfg |= EDMA_CFG_NCQ;
1264 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1266 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1268 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1271 static void mv_port_free_dma_mem(struct ata_port *ap)
1273 struct mv_host_priv *hpriv = ap->host->private_data;
1274 struct mv_port_priv *pp = ap->private_data;
1278 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1282 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1286 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1287 * For later hardware, we have one unique sg_tbl per NCQ tag.
1289 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1290 if (pp->sg_tbl[tag]) {
1291 if (tag == 0 || !IS_GEN_I(hpriv))
1292 dma_pool_free(hpriv->sg_tbl_pool,
1294 pp->sg_tbl_dma[tag]);
1295 pp->sg_tbl[tag] = NULL;
1301 * mv_port_start - Port specific init/start routine.
1302 * @ap: ATA channel to manipulate
1304 * Allocate and point to DMA memory, init port private memory,
1308 * Inherited from caller.
1310 static int mv_port_start(struct ata_port *ap)
1312 struct device *dev = ap->host->dev;
1313 struct mv_host_priv *hpriv = ap->host->private_data;
1314 struct mv_port_priv *pp;
1317 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1320 ap->private_data = pp;
1322 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1325 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
1327 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1329 goto out_port_free_dma_mem;
1330 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
1333 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1334 * For later hardware, we need one unique sg_tbl per NCQ tag.
1336 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1337 if (tag == 0 || !IS_GEN_I(hpriv)) {
1338 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1339 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1340 if (!pp->sg_tbl[tag])
1341 goto out_port_free_dma_mem;
1343 pp->sg_tbl[tag] = pp->sg_tbl[0];
1344 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1349 out_port_free_dma_mem:
1350 mv_port_free_dma_mem(ap);
1355 * mv_port_stop - Port specific cleanup/stop routine.
1356 * @ap: ATA channel to manipulate
1358 * Stop DMA, cleanup port memory.
1361 * This routine uses the host lock to protect the DMA stop.
1363 static void mv_port_stop(struct ata_port *ap)
1366 mv_enable_port_irqs(ap, 0);
1367 mv_port_free_dma_mem(ap);
1371 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1372 * @qc: queued command whose SG list to source from
1374 * Populate the SG list and mark the last entry.
1377 * Inherited from caller.
1379 static void mv_fill_sg(struct ata_queued_cmd *qc)
1381 struct mv_port_priv *pp = qc->ap->private_data;
1382 struct scatterlist *sg;
1383 struct mv_sg *mv_sg, *last_sg = NULL;
1386 mv_sg = pp->sg_tbl[qc->tag];
1387 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1388 dma_addr_t addr = sg_dma_address(sg);
1389 u32 sg_len = sg_dma_len(sg);
1392 u32 offset = addr & 0xffff;
1395 if ((offset + sg_len > 0x10000))
1396 len = 0x10000 - offset;
1398 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1399 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1400 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
1410 if (likely(last_sg))
1411 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1414 static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1416 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1417 (last ? CRQB_CMD_LAST : 0);
1418 *cmdw = cpu_to_le16(tmp);
1422 * mv_qc_prep - Host specific command preparation.
1423 * @qc: queued command to prepare
1425 * This routine simply redirects to the general purpose routine
1426 * if command is not DMA. Else, it handles prep of the CRQB
1427 * (command request block), does some sanity checking, and calls
1428 * the SG load routine.
1431 * Inherited from caller.
1433 static void mv_qc_prep(struct ata_queued_cmd *qc)
1435 struct ata_port *ap = qc->ap;
1436 struct mv_port_priv *pp = ap->private_data;
1438 struct ata_taskfile *tf;
1442 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1443 (qc->tf.protocol != ATA_PROT_NCQ))
1446 /* Fill in command request block
1448 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1449 flags |= CRQB_FLAG_READ;
1450 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1451 flags |= qc->tag << CRQB_TAG_SHIFT;
1452 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1454 /* get current queue index from software */
1455 in_index = pp->req_idx;
1457 pp->crqb[in_index].sg_addr =
1458 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1459 pp->crqb[in_index].sg_addr_hi =
1460 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1461 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1463 cw = &pp->crqb[in_index].ata_cmd[0];
1466 /* Sadly, the CRQB cannot accomodate all registers--there are
1467 * only 11 bytes...so we must pick and choose required
1468 * registers based on the command. So, we drop feature and
1469 * hob_feature for [RW] DMA commands, but they are needed for
1470 * NCQ. NCQ will drop hob_nsect.
1472 switch (tf->command) {
1474 case ATA_CMD_READ_EXT:
1476 case ATA_CMD_WRITE_EXT:
1477 case ATA_CMD_WRITE_FUA_EXT:
1478 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1480 case ATA_CMD_FPDMA_READ:
1481 case ATA_CMD_FPDMA_WRITE:
1482 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1483 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1486 /* The only other commands EDMA supports in non-queued and
1487 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1488 * of which are defined/used by Linux. If we get here, this
1489 * driver needs work.
1491 * FIXME: modify libata to give qc_prep a return value and
1492 * return error here.
1494 BUG_ON(tf->command);
1497 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1498 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1499 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1500 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1501 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1502 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1503 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1504 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1505 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1507 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1513 * mv_qc_prep_iie - Host specific command preparation.
1514 * @qc: queued command to prepare
1516 * This routine simply redirects to the general purpose routine
1517 * if command is not DMA. Else, it handles prep of the CRQB
1518 * (command request block), does some sanity checking, and calls
1519 * the SG load routine.
1522 * Inherited from caller.
1524 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1526 struct ata_port *ap = qc->ap;
1527 struct mv_port_priv *pp = ap->private_data;
1528 struct mv_crqb_iie *crqb;
1529 struct ata_taskfile *tf;
1533 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1534 (qc->tf.protocol != ATA_PROT_NCQ))
1537 /* Fill in Gen IIE command request block */
1538 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1539 flags |= CRQB_FLAG_READ;
1541 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1542 flags |= qc->tag << CRQB_TAG_SHIFT;
1543 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
1544 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
1546 /* get current queue index from software */
1547 in_index = pp->req_idx;
1549 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1550 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1551 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
1552 crqb->flags = cpu_to_le32(flags);
1555 crqb->ata_cmd[0] = cpu_to_le32(
1556 (tf->command << 16) |
1559 crqb->ata_cmd[1] = cpu_to_le32(
1565 crqb->ata_cmd[2] = cpu_to_le32(
1566 (tf->hob_lbal << 0) |
1567 (tf->hob_lbam << 8) |
1568 (tf->hob_lbah << 16) |
1569 (tf->hob_feature << 24)
1571 crqb->ata_cmd[3] = cpu_to_le32(
1573 (tf->hob_nsect << 8)
1576 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1582 * mv_qc_issue - Initiate a command to the host
1583 * @qc: queued command to start
1585 * This routine simply redirects to the general purpose routine
1586 * if command is not DMA. Else, it sanity checks our local
1587 * caches of the request producer/consumer indices then enables
1588 * DMA and bumps the request producer index.
1591 * Inherited from caller.
1593 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1595 struct ata_port *ap = qc->ap;
1596 void __iomem *port_mmio = mv_ap_base(ap);
1597 struct mv_port_priv *pp = ap->private_data;
1600 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1601 (qc->tf.protocol != ATA_PROT_NCQ)) {
1603 * We're about to send a non-EDMA capable command to the
1604 * port. Turn off EDMA so there won't be problems accessing
1605 * shadow block, etc registers.
1608 mv_enable_port_irqs(ap, ERR_IRQ);
1609 mv_pmp_select(ap, qc->dev->link->pmp);
1610 return ata_sff_qc_issue(qc);
1613 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
1615 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1616 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1618 /* and write the request in pointer to kick the EDMA to life */
1619 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1620 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1625 static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1627 struct mv_port_priv *pp = ap->private_data;
1628 struct ata_queued_cmd *qc;
1630 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1632 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1633 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1638 static void mv_pmp_error_handler(struct ata_port *ap)
1640 unsigned int pmp, pmp_map;
1641 struct mv_port_priv *pp = ap->private_data;
1643 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1645 * Perform NCQ error analysis on failed PMPs
1646 * before we freeze the port entirely.
1648 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1650 pmp_map = pp->delayed_eh_pmp_map;
1651 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1652 for (pmp = 0; pmp_map != 0; pmp++) {
1653 unsigned int this_pmp = (1 << pmp);
1654 if (pmp_map & this_pmp) {
1655 struct ata_link *link = &ap->pmp_link[pmp];
1656 pmp_map &= ~this_pmp;
1657 ata_eh_analyze_ncq_error(link);
1660 ata_port_freeze(ap);
1662 sata_pmp_error_handler(ap);
1665 static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1667 void __iomem *port_mmio = mv_ap_base(ap);
1669 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1672 static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1674 struct ata_eh_info *ehi;
1678 * Initialize EH info for PMPs which saw device errors
1680 ehi = &ap->link.eh_info;
1681 for (pmp = 0; pmp_map != 0; pmp++) {
1682 unsigned int this_pmp = (1 << pmp);
1683 if (pmp_map & this_pmp) {
1684 struct ata_link *link = &ap->pmp_link[pmp];
1686 pmp_map &= ~this_pmp;
1687 ehi = &link->eh_info;
1688 ata_ehi_clear_desc(ehi);
1689 ata_ehi_push_desc(ehi, "dev err");
1690 ehi->err_mask |= AC_ERR_DEV;
1691 ehi->action |= ATA_EH_RESET;
1692 ata_link_abort(link);
1697 static int mv_req_q_empty(struct ata_port *ap)
1699 void __iomem *port_mmio = mv_ap_base(ap);
1700 u32 in_ptr, out_ptr;
1702 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1703 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1704 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1705 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1706 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1709 static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1711 struct mv_port_priv *pp = ap->private_data;
1713 unsigned int old_map, new_map;
1716 * Device error during FBS+NCQ operation:
1718 * Set a port flag to prevent further I/O being enqueued.
1719 * Leave the EDMA running to drain outstanding commands from this port.
1720 * Perform the post-mortem/EH only when all responses are complete.
1721 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1723 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1724 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1725 pp->delayed_eh_pmp_map = 0;
1727 old_map = pp->delayed_eh_pmp_map;
1728 new_map = old_map | mv_get_err_pmp_map(ap);
1730 if (old_map != new_map) {
1731 pp->delayed_eh_pmp_map = new_map;
1732 mv_pmp_eh_prep(ap, new_map & ~old_map);
1734 failed_links = hweight16(new_map);
1736 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1737 "failed_links=%d nr_active_links=%d\n",
1738 __func__, pp->delayed_eh_pmp_map,
1739 ap->qc_active, failed_links,
1740 ap->nr_active_links);
1742 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
1743 mv_process_crpb_entries(ap, pp);
1746 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1747 return 1; /* handled */
1749 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1750 return 1; /* handled */
1753 static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1756 * Possible future enhancement:
1758 * FBS+non-NCQ operation is not yet implemented.
1759 * See related notes in mv_edma_cfg().
1761 * Device error during FBS+non-NCQ operation:
1763 * We need to snapshot the shadow registers for each failed command.
1764 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1766 return 0; /* not handled */
1769 static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1771 struct mv_port_priv *pp = ap->private_data;
1773 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1774 return 0; /* EDMA was not active: not handled */
1775 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1776 return 0; /* FBS was not active: not handled */
1778 if (!(edma_err_cause & EDMA_ERR_DEV))
1779 return 0; /* non DEV error: not handled */
1780 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1781 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1782 return 0; /* other problems: not handled */
1784 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1786 * EDMA should NOT have self-disabled for this case.
1787 * If it did, then something is wrong elsewhere,
1788 * and we cannot handle it here.
1790 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1791 ata_port_printk(ap, KERN_WARNING,
1792 "%s: err_cause=0x%x pp_flags=0x%x\n",
1793 __func__, edma_err_cause, pp->pp_flags);
1794 return 0; /* not handled */
1796 return mv_handle_fbs_ncq_dev_err(ap);
1799 * EDMA should have self-disabled for this case.
1800 * If it did not, then something is wrong elsewhere,
1801 * and we cannot handle it here.
1803 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1804 ata_port_printk(ap, KERN_WARNING,
1805 "%s: err_cause=0x%x pp_flags=0x%x\n",
1806 __func__, edma_err_cause, pp->pp_flags);
1807 return 0; /* not handled */
1809 return mv_handle_fbs_non_ncq_dev_err(ap);
1811 return 0; /* not handled */
1814 static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
1816 struct ata_eh_info *ehi = &ap->link.eh_info;
1817 char *when = "idle";
1819 ata_ehi_clear_desc(ehi);
1820 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1822 } else if (edma_was_enabled) {
1823 when = "EDMA enabled";
1825 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1826 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1829 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
1830 ehi->err_mask |= AC_ERR_OTHER;
1831 ehi->action |= ATA_EH_RESET;
1832 ata_port_freeze(ap);
1836 * mv_err_intr - Handle error interrupts on the port
1837 * @ap: ATA channel to manipulate
1838 * @qc: affected command (non-NCQ), or NULL
1840 * Most cases require a full reset of the chip's state machine,
1841 * which also performs a COMRESET.
1842 * Also, if the port disabled DMA, update our cached copy to match.
1845 * Inherited from caller.
1847 static void mv_err_intr(struct ata_port *ap)
1849 void __iomem *port_mmio = mv_ap_base(ap);
1850 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1852 struct mv_port_priv *pp = ap->private_data;
1853 struct mv_host_priv *hpriv = ap->host->private_data;
1854 unsigned int action = 0, err_mask = 0;
1855 struct ata_eh_info *ehi = &ap->link.eh_info;
1856 struct ata_queued_cmd *qc;
1860 * Read and clear the SError and err_cause bits.
1861 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1862 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
1864 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1865 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1867 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1868 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1869 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1870 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1872 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1874 if (edma_err_cause & EDMA_ERR_DEV) {
1876 * Device errors during FIS-based switching operation
1877 * require special handling.
1879 if (mv_handle_dev_err(ap, edma_err_cause))
1883 qc = mv_get_active_qc(ap);
1884 ata_ehi_clear_desc(ehi);
1885 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1886 edma_err_cause, pp->pp_flags);
1888 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1889 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
1890 if (fis_cause & SATA_FIS_IRQ_AN) {
1891 u32 ec = edma_err_cause &
1892 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1893 sata_async_notification(ap);
1895 return; /* Just an AN; no need for the nukes */
1896 ata_ehi_push_desc(ehi, "SDB notify");
1900 * All generations share these EDMA error cause bits:
1902 if (edma_err_cause & EDMA_ERR_DEV) {
1903 err_mask |= AC_ERR_DEV;
1904 action |= ATA_EH_RESET;
1905 ata_ehi_push_desc(ehi, "dev error");
1907 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
1908 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
1909 EDMA_ERR_INTRL_PAR)) {
1910 err_mask |= AC_ERR_ATA_BUS;
1911 action |= ATA_EH_RESET;
1912 ata_ehi_push_desc(ehi, "parity error");
1914 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1915 ata_ehi_hotplugged(ehi);
1916 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
1917 "dev disconnect" : "dev connect");
1918 action |= ATA_EH_RESET;
1922 * Gen-I has a different SELF_DIS bit,
1923 * different FREEZE bits, and no SERR bit:
1925 if (IS_GEN_I(hpriv)) {
1926 eh_freeze_mask = EDMA_EH_FREEZE_5;
1927 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
1928 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1929 ata_ehi_push_desc(ehi, "EDMA self-disable");
1932 eh_freeze_mask = EDMA_EH_FREEZE;
1933 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1934 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1935 ata_ehi_push_desc(ehi, "EDMA self-disable");
1937 if (edma_err_cause & EDMA_ERR_SERR) {
1938 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1939 err_mask |= AC_ERR_ATA_BUS;
1940 action |= ATA_EH_RESET;
1945 err_mask = AC_ERR_OTHER;
1946 action |= ATA_EH_RESET;
1949 ehi->serror |= serr;
1950 ehi->action |= action;
1953 qc->err_mask |= err_mask;
1955 ehi->err_mask |= err_mask;
1957 if (err_mask == AC_ERR_DEV) {
1959 * Cannot do ata_port_freeze() here,
1960 * because it would kill PIO access,
1961 * which is needed for further diagnosis.
1965 } else if (edma_err_cause & eh_freeze_mask) {
1967 * Note to self: ata_port_freeze() calls ata_port_abort()
1969 ata_port_freeze(ap);
1976 ata_link_abort(qc->dev->link);
1982 static void mv_process_crpb_response(struct ata_port *ap,
1983 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1985 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1989 u16 edma_status = le16_to_cpu(response->flags);
1991 * edma_status from a response queue entry:
1992 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1993 * MSB is saved ATA status from command completion.
1996 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1999 * Error will be seen/handled by mv_err_intr().
2000 * So do nothing at all here.
2005 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2006 if (!ac_err_mask(ata_status))
2007 ata_qc_complete(qc);
2008 /* else: leave it for mv_err_intr() */
2010 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2015 static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
2017 void __iomem *port_mmio = mv_ap_base(ap);
2018 struct mv_host_priv *hpriv = ap->host->private_data;
2020 bool work_done = false;
2021 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
2023 /* Get the hardware queue position index */
2024 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2025 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2027 /* Process new responses from since the last time we looked */
2028 while (in_index != pp->resp_idx) {
2030 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
2032 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2034 if (IS_GEN_I(hpriv)) {
2035 /* 50xx: no NCQ, only one command active at a time */
2036 tag = ap->link.active_tag;
2038 /* Gen II/IIE: get command tag from CRPB entry */
2039 tag = le16_to_cpu(response->id) & 0x1f;
2041 mv_process_crpb_response(ap, response, tag, ncq_enabled);
2045 /* Update the software queue position index in hardware */
2047 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
2048 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
2049 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
2052 static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2054 struct mv_port_priv *pp;
2055 int edma_was_enabled;
2057 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2058 mv_unexpected_intr(ap, 0);
2062 * Grab a snapshot of the EDMA_EN flag setting,
2063 * so that we have a consistent view for this port,
2064 * even if something we call of our routines changes it.
2066 pp = ap->private_data;
2067 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2069 * Process completed CRPB response(s) before other events.
2071 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2072 mv_process_crpb_entries(ap, pp);
2073 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2074 mv_handle_fbs_ncq_dev_err(ap);
2077 * Handle chip-reported errors, or continue on to handle PIO.
2079 if (unlikely(port_cause & ERR_IRQ)) {
2081 } else if (!edma_was_enabled) {
2082 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2084 ata_sff_host_intr(ap, qc);
2086 mv_unexpected_intr(ap, edma_was_enabled);
2091 * mv_host_intr - Handle all interrupts on the given host controller
2092 * @host: host specific structure
2093 * @main_irq_cause: Main interrupt cause register for the chip.
2096 * Inherited from caller.
2098 static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
2100 struct mv_host_priv *hpriv = host->private_data;
2101 void __iomem *mmio = hpriv->base, *hc_mmio;
2102 unsigned int handled = 0, port;
2104 for (port = 0; port < hpriv->n_ports; port++) {
2105 struct ata_port *ap = host->ports[port];
2106 unsigned int p, shift, hardport, port_cause;
2108 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
2110 * Each hc within the host has its own hc_irq_cause register,
2111 * where the interrupting ports bits get ack'd.
2113 if (hardport == 0) { /* first port on this hc ? */
2114 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2115 u32 port_mask, ack_irqs;
2117 * Skip this entire hc if nothing pending for any ports
2120 port += MV_PORTS_PER_HC - 1;
2124 * We don't need/want to read the hc_irq_cause register,
2125 * because doing so hurts performance, and
2126 * main_irq_cause already gives us everything we need.
2128 * But we do have to *write* to the hc_irq_cause to ack
2129 * the ports that we are handling this time through.
2131 * This requires that we create a bitmap for those
2132 * ports which interrupted us, and use that bitmap
2133 * to ack (only) those ports via hc_irq_cause.
2136 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2137 if ((port + p) >= hpriv->n_ports)
2139 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2140 if (hc_cause & port_mask)
2141 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2143 hc_mmio = mv_hc_base_from_port(mmio, port);
2144 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
2148 * Handle interrupts signalled for this port:
2150 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2152 mv_port_intr(ap, port_cause);
2157 static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
2159 struct mv_host_priv *hpriv = host->private_data;
2160 struct ata_port *ap;
2161 struct ata_queued_cmd *qc;
2162 struct ata_eh_info *ehi;
2163 unsigned int i, err_mask, printed = 0;
2166 err_cause = readl(mmio + hpriv->irq_cause_ofs);
2168 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2171 DPRINTK("All regs @ PCI error\n");
2172 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2174 writelfl(0, mmio + hpriv->irq_cause_ofs);
2176 for (i = 0; i < host->n_ports; i++) {
2177 ap = host->ports[i];
2178 if (!ata_link_offline(&ap->link)) {
2179 ehi = &ap->link.eh_info;
2180 ata_ehi_clear_desc(ehi);
2182 ata_ehi_push_desc(ehi,
2183 "PCI err cause 0x%08x", err_cause);
2184 err_mask = AC_ERR_HOST_BUS;
2185 ehi->action = ATA_EH_RESET;
2186 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2188 qc->err_mask |= err_mask;
2190 ehi->err_mask |= err_mask;
2192 ata_port_freeze(ap);
2195 return 1; /* handled */
2199 * mv_interrupt - Main interrupt event handler
2201 * @dev_instance: private data; in this case the host structure
2203 * Read the read only register to determine if any host
2204 * controllers have pending interrupts. If so, call lower level
2205 * routine to handle. Also check for PCI errors which are only
2209 * This routine holds the host lock while processing pending
2212 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
2214 struct ata_host *host = dev_instance;
2215 struct mv_host_priv *hpriv = host->private_data;
2216 unsigned int handled = 0;
2217 u32 main_irq_cause, pending_irqs;
2219 spin_lock(&host->lock);
2220 main_irq_cause = readl(hpriv->main_irq_cause_addr);
2221 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
2223 * Deal with cases where we either have nothing pending, or have read
2224 * a bogus register value which can indicate HW removal or PCI fault.
2226 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2227 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
2228 handled = mv_pci_error(host, hpriv->base);
2230 handled = mv_host_intr(host, pending_irqs);
2232 spin_unlock(&host->lock);
2233 return IRQ_RETVAL(handled);
2236 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2240 switch (sc_reg_in) {
2244 ofs = sc_reg_in * sizeof(u32);
2253 static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
2255 struct mv_host_priv *hpriv = ap->host->private_data;
2256 void __iomem *mmio = hpriv->base;
2257 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2258 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2260 if (ofs != 0xffffffffU) {
2261 *val = readl(addr + ofs);
2267 static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
2269 struct mv_host_priv *hpriv = ap->host->private_data;
2270 void __iomem *mmio = hpriv->base;
2271 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
2272 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2274 if (ofs != 0xffffffffU) {
2275 writelfl(val, addr + ofs);
2281 static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
2283 struct pci_dev *pdev = to_pci_dev(host->dev);
2286 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
2289 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2291 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2294 mv_reset_pci_bus(host, mmio);
2297 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2299 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
2302 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
2305 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2308 tmp = readl(phy_mmio + MV5_PHY_MODE);
2310 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2311 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
2314 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2318 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
2320 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2322 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2324 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2327 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2330 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2331 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2333 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2336 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
2338 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
2340 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
2343 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
2346 tmp = readl(phy_mmio + MV5_PHY_MODE);
2348 tmp |= hpriv->signal[port].pre;
2349 tmp |= hpriv->signal[port].amps;
2350 writel(tmp, phy_mmio + MV5_PHY_MODE);
2355 #define ZERO(reg) writel(0, port_mmio + (reg))
2356 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2359 void __iomem *port_mmio = mv_port_base(mmio, port);
2361 mv_reset_channel(hpriv, mmio, port);
2363 ZERO(0x028); /* command */
2364 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2365 ZERO(0x004); /* timer */
2366 ZERO(0x008); /* irq err cause */
2367 ZERO(0x00c); /* irq err mask */
2368 ZERO(0x010); /* rq bah */
2369 ZERO(0x014); /* rq inp */
2370 ZERO(0x018); /* rq outp */
2371 ZERO(0x01c); /* respq bah */
2372 ZERO(0x024); /* respq outp */
2373 ZERO(0x020); /* respq inp */
2374 ZERO(0x02c); /* test control */
2375 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2379 #define ZERO(reg) writel(0, hc_mmio + (reg))
2380 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2383 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2391 tmp = readl(hc_mmio + 0x20);
2394 writel(tmp, hc_mmio + 0x20);
2398 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2401 unsigned int hc, port;
2403 for (hc = 0; hc < n_hc; hc++) {
2404 for (port = 0; port < MV_PORTS_PER_HC; port++)
2405 mv5_reset_hc_port(hpriv, mmio,
2406 (hc * MV_PORTS_PER_HC) + port);
2408 mv5_reset_one_hc(hpriv, mmio, hc);
2415 #define ZERO(reg) writel(0, mmio + (reg))
2416 static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
2418 struct mv_host_priv *hpriv = host->private_data;
2421 tmp = readl(mmio + MV_PCI_MODE_OFS);
2423 writel(tmp, mmio + MV_PCI_MODE_OFS);
2425 ZERO(MV_PCI_DISC_TIMER);
2426 ZERO(MV_PCI_MSI_TRIGGER);
2427 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
2428 ZERO(MV_PCI_SERR_MASK);
2429 ZERO(hpriv->irq_cause_ofs);
2430 ZERO(hpriv->irq_mask_ofs);
2431 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2432 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2433 ZERO(MV_PCI_ERR_ATTRIBUTE);
2434 ZERO(MV_PCI_ERR_COMMAND);
2438 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2442 mv5_reset_flash(hpriv, mmio);
2444 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
2446 tmp |= (1 << 5) | (1 << 6);
2447 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
2451 * mv6_reset_hc - Perform the 6xxx global soft reset
2452 * @mmio: base address of the HBA
2454 * This routine only applies to 6xxx parts.
2457 * Inherited from caller.
2459 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2462 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2466 /* Following procedure defined in PCI "main command and status
2470 writel(t | STOP_PCI_MASTER, reg);
2472 for (i = 0; i < 1000; i++) {
2475 if (PCI_MASTER_EMPTY & t)
2478 if (!(PCI_MASTER_EMPTY & t)) {
2479 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2487 writel(t | GLOB_SFT_RST, reg);
2490 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2492 if (!(GLOB_SFT_RST & t)) {
2493 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2498 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2501 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2504 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2506 if (GLOB_SFT_RST & t) {
2507 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2514 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
2517 void __iomem *port_mmio;
2520 tmp = readl(mmio + MV_RESET_CFG_OFS);
2521 if ((tmp & (1 << 0)) == 0) {
2522 hpriv->signal[idx].amps = 0x7 << 8;
2523 hpriv->signal[idx].pre = 0x1 << 5;
2527 port_mmio = mv_port_base(mmio, idx);
2528 tmp = readl(port_mmio + PHY_MODE2);
2530 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2531 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2534 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
2536 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
2539 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2542 void __iomem *port_mmio = mv_port_base(mmio, port);
2544 u32 hp_flags = hpriv->hp_flags;
2546 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2548 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2551 if (fix_phy_mode2) {
2552 m2 = readl(port_mmio + PHY_MODE2);
2555 writel(m2, port_mmio + PHY_MODE2);
2559 m2 = readl(port_mmio + PHY_MODE2);
2560 m2 &= ~((1 << 16) | (1 << 31));
2561 writel(m2, port_mmio + PHY_MODE2);
2566 /* who knows what this magic does */
2567 tmp = readl(port_mmio + PHY_MODE3);
2570 writel(tmp, port_mmio + PHY_MODE3);
2572 if (fix_phy_mode4) {
2575 m4 = readl(port_mmio + PHY_MODE4);
2577 if (hp_flags & MV_HP_ERRATA_60X1B2)
2578 tmp = readl(port_mmio + PHY_MODE3);
2580 /* workaround for errata FEr SATA#10 (part 1) */
2581 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2583 writel(m4, port_mmio + PHY_MODE4);
2585 if (hp_flags & MV_HP_ERRATA_60X1B2)
2586 writel(tmp, port_mmio + PHY_MODE3);
2589 /* Revert values of pre-emphasis and signal amps to the saved ones */
2590 m2 = readl(port_mmio + PHY_MODE2);
2592 m2 &= ~MV_M2_PREAMP_MASK;
2593 m2 |= hpriv->signal[port].amps;
2594 m2 |= hpriv->signal[port].pre;
2597 /* according to mvSata 3.6.1, some IIE values are fixed */
2598 if (IS_GEN_IIE(hpriv)) {
2603 writel(m2, port_mmio + PHY_MODE2);
2606 /* TODO: use the generic LED interface to configure the SATA Presence */
2607 /* & Acitivy LEDs on the board */
2608 static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2614 static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2617 void __iomem *port_mmio;
2620 port_mmio = mv_port_base(mmio, idx);
2621 tmp = readl(port_mmio + PHY_MODE2);
2623 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2624 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2628 #define ZERO(reg) writel(0, port_mmio + (reg))
2629 static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2630 void __iomem *mmio, unsigned int port)
2632 void __iomem *port_mmio = mv_port_base(mmio, port);
2634 mv_reset_channel(hpriv, mmio, port);
2636 ZERO(0x028); /* command */
2637 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2638 ZERO(0x004); /* timer */
2639 ZERO(0x008); /* irq err cause */
2640 ZERO(0x00c); /* irq err mask */
2641 ZERO(0x010); /* rq bah */
2642 ZERO(0x014); /* rq inp */
2643 ZERO(0x018); /* rq outp */
2644 ZERO(0x01c); /* respq bah */
2645 ZERO(0x024); /* respq outp */
2646 ZERO(0x020); /* respq inp */
2647 ZERO(0x02c); /* test control */
2648 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
2653 #define ZERO(reg) writel(0, hc_mmio + (reg))
2654 static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2657 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2667 static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2668 void __iomem *mmio, unsigned int n_hc)
2672 for (port = 0; port < hpriv->n_ports; port++)
2673 mv_soc_reset_hc_port(hpriv, mmio, port);
2675 mv_soc_reset_one_hc(hpriv, mmio);
2680 static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2686 static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2691 static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
2693 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
2695 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
2697 ifcfg |= (1 << 7); /* enable gen2i speed */
2698 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
2701 static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
2702 unsigned int port_no)
2704 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2707 * The datasheet warns against setting EDMA_RESET when EDMA is active
2708 * (but doesn't say what the problem might be). So we first try
2709 * to disable the EDMA engine before doing the EDMA_RESET operation.
2711 mv_stop_edma_engine(port_mmio);
2712 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2714 if (!IS_GEN_I(hpriv)) {
2715 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2716 mv_setup_ifcfg(port_mmio, 1);
2719 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
2720 * link, and physical layers. It resets all SATA interface registers
2721 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
2723 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
2724 udelay(25); /* allow reset propagation */
2725 writelfl(0, port_mmio + EDMA_CMD_OFS);
2727 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2729 if (IS_GEN_I(hpriv))
2733 static void mv_pmp_select(struct ata_port *ap, int pmp)
2735 if (sata_pmp_supported(ap)) {
2736 void __iomem *port_mmio = mv_ap_base(ap);
2737 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2738 int old = reg & 0xf;
2741 reg = (reg & ~0xf) | pmp;
2742 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2747 static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2748 unsigned long deadline)
2750 mv_pmp_select(link->ap, sata_srst_pmp(link));
2751 return sata_std_hardreset(link, class, deadline);
2754 static int mv_softreset(struct ata_link *link, unsigned int *class,
2755 unsigned long deadline)
2757 mv_pmp_select(link->ap, sata_srst_pmp(link));
2758 return ata_sff_softreset(link, class, deadline);
2761 static int mv_hardreset(struct ata_link *link, unsigned int *class,
2762 unsigned long deadline)
2764 struct ata_port *ap = link->ap;
2765 struct mv_host_priv *hpriv = ap->host->private_data;
2766 struct mv_port_priv *pp = ap->private_data;
2767 void __iomem *mmio = hpriv->base;
2768 int rc, attempts = 0, extra = 0;
2772 mv_reset_channel(hpriv, mmio, ap->port_no);
2773 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2775 /* Workaround for errata FEr SATA#10 (part 2) */
2777 const unsigned long *timing =
2778 sata_ehc_deb_timing(&link->eh_context);
2780 rc = sata_link_hardreset(link, timing, deadline + extra,
2782 rc = online ? -EAGAIN : rc;
2785 sata_scr_read(link, SCR_STATUS, &sstatus);
2786 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2787 /* Force 1.5gb/s link speed and try again */
2788 mv_setup_ifcfg(mv_ap_base(ap), 0);
2789 if (time_after(jiffies + HZ, deadline))
2790 extra = HZ; /* only extend it once, max */
2792 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
2797 static void mv_eh_freeze(struct ata_port *ap)
2800 mv_enable_port_irqs(ap, 0);
2803 static void mv_eh_thaw(struct ata_port *ap)
2805 struct mv_host_priv *hpriv = ap->host->private_data;
2806 unsigned int port = ap->port_no;
2807 unsigned int hardport = mv_hardport_from_port(port);
2808 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
2809 void __iomem *port_mmio = mv_ap_base(ap);
2812 /* clear EDMA errors on this port */
2813 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2815 /* clear pending irq events */
2816 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
2817 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2818 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
2820 mv_enable_port_irqs(ap, ERR_IRQ);
2824 * mv_port_init - Perform some early initialization on a single port.
2825 * @port: libata data structure storing shadow register addresses
2826 * @port_mmio: base address of the port
2828 * Initialize shadow register mmio addresses, clear outstanding
2829 * interrupts on the port, and unmask interrupts for the future
2830 * start of the port.
2833 * Inherited from caller.
2835 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2837 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
2840 /* PIO related setup
2842 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2844 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2845 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2846 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2847 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2848 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2849 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2851 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2852 /* special case: control/altstatus doesn't have ATA_REG_ address */
2853 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2856 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
2858 /* Clear any currently outstanding port interrupt conditions */
2859 serr_ofs = mv_scr_offset(SCR_ERROR);
2860 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2861 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2863 /* unmask all non-transient EDMA error interrupts */
2864 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2866 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2867 readl(port_mmio + EDMA_CFG_OFS),
2868 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2869 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2872 static unsigned int mv_in_pcix_mode(struct ata_host *host)
2874 struct mv_host_priv *hpriv = host->private_data;
2875 void __iomem *mmio = hpriv->base;
2878 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
2879 return 0; /* not PCI-X capable */
2880 reg = readl(mmio + MV_PCI_MODE_OFS);
2881 if ((reg & MV_PCI_MODE_MASK) == 0)
2882 return 0; /* conventional PCI mode */
2883 return 1; /* chip is in PCI-X mode */
2886 static int mv_pci_cut_through_okay(struct ata_host *host)
2888 struct mv_host_priv *hpriv = host->private_data;
2889 void __iomem *mmio = hpriv->base;
2892 if (!mv_in_pcix_mode(host)) {
2893 reg = readl(mmio + PCI_COMMAND_OFS);
2894 if (reg & PCI_COMMAND_MRDTRIG)
2895 return 0; /* not okay */
2897 return 1; /* okay */
2900 static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
2902 struct pci_dev *pdev = to_pci_dev(host->dev);
2903 struct mv_host_priv *hpriv = host->private_data;
2904 u32 hp_flags = hpriv->hp_flags;
2906 switch (board_idx) {
2908 hpriv->ops = &mv5xxx_ops;
2909 hp_flags |= MV_HP_GEN_I;
2911 switch (pdev->revision) {
2913 hp_flags |= MV_HP_ERRATA_50XXB0;
2916 hp_flags |= MV_HP_ERRATA_50XXB2;
2919 dev_printk(KERN_WARNING, &pdev->dev,
2920 "Applying 50XXB2 workarounds to unknown rev\n");
2921 hp_flags |= MV_HP_ERRATA_50XXB2;
2928 hpriv->ops = &mv5xxx_ops;
2929 hp_flags |= MV_HP_GEN_I;
2931 switch (pdev->revision) {
2933 hp_flags |= MV_HP_ERRATA_50XXB0;
2936 hp_flags |= MV_HP_ERRATA_50XXB2;
2939 dev_printk(KERN_WARNING, &pdev->dev,
2940 "Applying B2 workarounds to unknown rev\n");
2941 hp_flags |= MV_HP_ERRATA_50XXB2;
2948 hpriv->ops = &mv6xxx_ops;
2949 hp_flags |= MV_HP_GEN_II;
2951 switch (pdev->revision) {
2953 hp_flags |= MV_HP_ERRATA_60X1B2;
2956 hp_flags |= MV_HP_ERRATA_60X1C0;
2959 dev_printk(KERN_WARNING, &pdev->dev,
2960 "Applying B2 workarounds to unknown rev\n");
2961 hp_flags |= MV_HP_ERRATA_60X1B2;
2967 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
2968 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2969 (pdev->device == 0x2300 || pdev->device == 0x2310))
2972 * Highpoint RocketRAID PCIe 23xx series cards:
2974 * Unconfigured drives are treated as "Legacy"
2975 * by the BIOS, and it overwrites sector 8 with
2976 * a "Lgcy" metadata block prior to Linux boot.
2978 * Configured drives (RAID or JBOD) leave sector 8
2979 * alone, but instead overwrite a high numbered
2980 * sector for the RAID metadata. This sector can
2981 * be determined exactly, by truncating the physical
2982 * drive capacity to a nice even GB value.
2984 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2986 * Warn the user, lest they think we're just buggy.
2988 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2989 " BIOS CORRUPTS DATA on all attached drives,"
2990 " regardless of if/how they are configured."
2992 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2993 " use sectors 8-9 on \"Legacy\" drives,"
2994 " and avoid the final two gigabytes on"
2995 " all RocketRAID BIOS initialized drives.\n");
2999 hpriv->ops = &mv6xxx_ops;
3000 hp_flags |= MV_HP_GEN_IIE;
3001 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3002 hp_flags |= MV_HP_CUT_THROUGH;
3004 switch (pdev->revision) {
3006 hp_flags |= MV_HP_ERRATA_XX42A0;
3009 hp_flags |= MV_HP_ERRATA_60X1C0;
3012 dev_printk(KERN_WARNING, &pdev->dev,
3013 "Applying 60X1C0 workarounds to unknown rev\n");
3014 hp_flags |= MV_HP_ERRATA_60X1C0;
3019 hpriv->ops = &mv_soc_ops;
3020 hp_flags |= MV_HP_FLAG_SOC | MV_HP_ERRATA_60X1C0;
3024 dev_printk(KERN_ERR, host->dev,
3025 "BUG: invalid board index %u\n", board_idx);
3029 hpriv->hp_flags = hp_flags;
3030 if (hp_flags & MV_HP_PCIE) {
3031 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3032 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3033 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3035 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3036 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3037 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3044 * mv_init_host - Perform some early initialization of the host.
3045 * @host: ATA host to initialize
3046 * @board_idx: controller index
3048 * If possible, do an early global reset of the host. Then do
3049 * our port init and clear/unmask all/relevant host interrupts.
3052 * Inherited from caller.
3054 static int mv_init_host(struct ata_host *host, unsigned int board_idx)
3056 int rc = 0, n_hc, port, hc;
3057 struct mv_host_priv *hpriv = host->private_data;
3058 void __iomem *mmio = hpriv->base;
3060 rc = mv_chip_id(host, board_idx);
3064 if (IS_SOC(hpriv)) {
3065 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3066 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
3068 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3069 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
3072 /* global interrupt mask: 0 == mask everything */
3073 mv_set_main_irq_mask(host, ~0, 0);
3075 n_hc = mv_get_hc_count(host->ports[0]->flags);
3077 for (port = 0; port < host->n_ports; port++)
3078 hpriv->ops->read_preamp(hpriv, port, mmio);
3080 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
3084 hpriv->ops->reset_flash(hpriv, mmio);
3085 hpriv->ops->reset_bus(host, mmio);
3086 hpriv->ops->enable_leds(hpriv, mmio);
3088 for (port = 0; port < host->n_ports; port++) {
3089 struct ata_port *ap = host->ports[port];
3090 void __iomem *port_mmio = mv_port_base(mmio, port);
3092 mv_port_init(&ap->ioaddr, port_mmio);
3095 if (!IS_SOC(hpriv)) {
3096 unsigned int offset = port_mmio - mmio;
3097 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3098 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3103 for (hc = 0; hc < n_hc; hc++) {
3104 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3106 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3107 "(before clear)=0x%08x\n", hc,
3108 readl(hc_mmio + HC_CFG_OFS),
3109 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3111 /* Clear any currently outstanding hc interrupt conditions */
3112 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
3115 if (!IS_SOC(hpriv)) {
3116 /* Clear any currently outstanding host interrupt conditions */
3117 writelfl(0, mmio + hpriv->irq_cause_ofs);
3119 /* and unmask interrupt generation for host regs */
3120 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
3123 * enable only global host interrupts for now.
3124 * The per-port interrupts get done later as ports are set up.
3126 mv_set_main_irq_mask(host, 0, PCI_ERR);
3132 static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3134 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3136 if (!hpriv->crqb_pool)
3139 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3141 if (!hpriv->crpb_pool)
3144 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3146 if (!hpriv->sg_tbl_pool)
3152 static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3153 struct mbus_dram_target_info *dram)
3157 for (i = 0; i < 4; i++) {
3158 writel(0, hpriv->base + WINDOW_CTRL(i));
3159 writel(0, hpriv->base + WINDOW_BASE(i));
3162 for (i = 0; i < dram->num_cs; i++) {
3163 struct mbus_dram_window *cs = dram->cs + i;
3165 writel(((cs->size - 1) & 0xffff0000) |
3166 (cs->mbus_attr << 8) |
3167 (dram->mbus_dram_target_id << 4) | 1,
3168 hpriv->base + WINDOW_CTRL(i));
3169 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3174 * mv_platform_probe - handle a positive probe of an soc Marvell
3176 * @pdev: platform device found
3179 * Inherited from caller.
3181 static int mv_platform_probe(struct platform_device *pdev)
3183 static int printed_version;
3184 const struct mv_sata_platform_data *mv_platform_data;
3185 const struct ata_port_info *ppi[] =
3186 { &mv_port_info[chip_soc], NULL };
3187 struct ata_host *host;
3188 struct mv_host_priv *hpriv;
3189 struct resource *res;
3192 if (!printed_version++)
3193 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3196 * Simple resource validation ..
3198 if (unlikely(pdev->num_resources != 2)) {
3199 dev_err(&pdev->dev, "invalid number of resources\n");
3204 * Get the register base first
3206 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3211 mv_platform_data = pdev->dev.platform_data;
3212 n_ports = mv_platform_data->n_ports;
3214 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3215 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3217 if (!host || !hpriv)
3219 host->private_data = hpriv;
3220 hpriv->n_ports = n_ports;
3223 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3224 res->end - res->start + 1);
3225 hpriv->base -= MV_SATAHC0_REG_BASE;
3228 * (Re-)program MBUS remapping windows if we are asked to.
3230 if (mv_platform_data->dram != NULL)
3231 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3233 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3237 /* initialize adapter */
3238 rc = mv_init_host(host, chip_soc);
3242 dev_printk(KERN_INFO, &pdev->dev,
3243 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3246 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3247 IRQF_SHARED, &mv6_sht);
3252 * mv_platform_remove - unplug a platform interface
3253 * @pdev: platform device
3255 * A platform bus SATA device has been unplugged. Perform the needed
3256 * cleanup. Also called on module unload for any active devices.
3258 static int __devexit mv_platform_remove(struct platform_device *pdev)
3260 struct device *dev = &pdev->dev;
3261 struct ata_host *host = dev_get_drvdata(dev);
3263 ata_host_detach(host);
3267 static struct platform_driver mv_platform_driver = {
3268 .probe = mv_platform_probe,
3269 .remove = __devexit_p(mv_platform_remove),
3272 .owner = THIS_MODULE,
3278 static int mv_pci_init_one(struct pci_dev *pdev,
3279 const struct pci_device_id *ent);
3282 static struct pci_driver mv_pci_driver = {
3284 .id_table = mv_pci_tbl,
3285 .probe = mv_pci_init_one,
3286 .remove = ata_pci_remove_one,
3292 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3295 /* move to PCI layer or libata core? */
3296 static int pci_go_64(struct pci_dev *pdev)
3300 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3301 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3303 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3305 dev_printk(KERN_ERR, &pdev->dev,
3306 "64-bit DMA enable failed\n");
3311 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3313 dev_printk(KERN_ERR, &pdev->dev,
3314 "32-bit DMA enable failed\n");
3317 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3319 dev_printk(KERN_ERR, &pdev->dev,
3320 "32-bit consistent DMA enable failed\n");
3329 * mv_print_info - Dump key info to kernel log for perusal.
3330 * @host: ATA host to print info about
3332 * FIXME: complete this.
3335 * Inherited from caller.
3337 static void mv_print_info(struct ata_host *host)
3339 struct pci_dev *pdev = to_pci_dev(host->dev);
3340 struct mv_host_priv *hpriv = host->private_data;
3342 const char *scc_s, *gen;
3344 /* Use this to determine the HW stepping of the chip so we know
3345 * what errata to workaround
3347 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3350 else if (scc == 0x01)
3355 if (IS_GEN_I(hpriv))
3357 else if (IS_GEN_II(hpriv))
3359 else if (IS_GEN_IIE(hpriv))
3364 dev_printk(KERN_INFO, &pdev->dev,
3365 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3366 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
3367 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3371 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
3372 * @pdev: PCI device found
3373 * @ent: PCI device ID entry for the matched host
3376 * Inherited from caller.
3378 static int mv_pci_init_one(struct pci_dev *pdev,
3379 const struct pci_device_id *ent)
3381 static int printed_version;
3382 unsigned int board_idx = (unsigned int)ent->driver_data;
3383 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3384 struct ata_host *host;
3385 struct mv_host_priv *hpriv;
3388 if (!printed_version++)
3389 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
3392 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3394 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3395 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3396 if (!host || !hpriv)
3398 host->private_data = hpriv;
3399 hpriv->n_ports = n_ports;
3401 /* acquire resources */
3402 rc = pcim_enable_device(pdev);
3406 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3408 pcim_pin_device(pdev);
3411 host->iomap = pcim_iomap_table(pdev);
3412 hpriv->base = host->iomap[MV_PRIMARY_BAR];
3414 rc = pci_go_64(pdev);
3418 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3422 /* initialize adapter */
3423 rc = mv_init_host(host, board_idx);
3427 /* Enable interrupts */
3428 if (msi && pci_enable_msi(pdev))
3431 mv_dump_pci_cfg(pdev, 0x68);
3432 mv_print_info(host);
3434 pci_set_master(pdev);
3435 pci_try_set_mwi(pdev);
3436 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
3437 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
3441 static int mv_platform_probe(struct platform_device *pdev);
3442 static int __devexit mv_platform_remove(struct platform_device *pdev);
3444 static int __init mv_init(void)
3448 rc = pci_register_driver(&mv_pci_driver);
3452 rc = platform_driver_register(&mv_platform_driver);
3456 pci_unregister_driver(&mv_pci_driver);
3461 static void __exit mv_exit(void)
3464 pci_unregister_driver(&mv_pci_driver);
3466 platform_driver_unregister(&mv_platform_driver);
3469 MODULE_AUTHOR("Brett Russ");
3470 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3471 MODULE_LICENSE("GPL");
3472 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3473 MODULE_VERSION(DRV_VERSION);
3474 MODULE_ALIAS("platform:" DRV_NAME);
3477 module_param(msi, int, 0444);
3478 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
3481 module_init(mv_init);
3482 module_exit(mv_exit);