2 * drivers/ata/sata_dwc_460ex.c
4 * Synopsys DesignWare Cores (DWC) SATA host driver
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
21 #ifdef CONFIG_SATA_DWC_DEBUG
25 #ifdef CONFIG_SATA_DWC_VDEBUG
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/device.h>
34 #include <linux/of_platform.h>
35 #include <linux/platform_device.h>
36 #include <linux/libata.h>
37 #include <linux/slab.h>
40 #include <scsi/scsi_host.h>
41 #include <scsi/scsi_cmnd.h>
43 /* These two are defined in "libata.h" */
46 #define DRV_NAME "sata-dwc"
47 #define DRV_VERSION "1.2"
49 /* SATA DMA driver Globals */
50 #define DMA_NUM_CHANS 1
51 #define DMA_NUM_CHAN_REGS 8
53 /* SATA DMA Register definitions */
54 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/
57 u32 low; /* Low bits 0-31 */
58 u32 high; /* High bits 32-63 */
61 /* DMA Per Channel registers */
62 struct dma_chan_regs {
63 struct dmareg sar; /* Source Address */
64 struct dmareg dar; /* Destination address */
65 struct dmareg llp; /* Linked List Pointer */
66 struct dmareg ctl; /* Control */
67 struct dmareg sstat; /* Source Status not implemented in core */
68 struct dmareg dstat; /* Destination Status not implemented in core*/
69 struct dmareg sstatar; /* Source Status Address not impl in core */
70 struct dmareg dstatar; /* Destination Status Address not implemente */
71 struct dmareg cfg; /* Config */
72 struct dmareg sgr; /* Source Gather */
73 struct dmareg dsr; /* Destination Scatter */
76 /* Generic Interrupt Registers */
77 struct dma_interrupt_regs {
78 struct dmareg tfr; /* Transfer Interrupt */
79 struct dmareg block; /* Block Interrupt */
80 struct dmareg srctran; /* Source Transfer Interrupt */
81 struct dmareg dsttran; /* Dest Transfer Interrupt */
82 struct dmareg error; /* Error */
86 struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
87 struct dma_interrupt_regs interrupt_raw; /* Raw Interrupt */
88 struct dma_interrupt_regs interrupt_status; /* Interrupt Status */
89 struct dma_interrupt_regs interrupt_mask; /* Interrupt Mask */
90 struct dma_interrupt_regs interrupt_clear; /* Interrupt Clear */
91 struct dmareg statusInt; /* Interrupt combined*/
92 struct dmareg rq_srcreg; /* Src Trans Req */
93 struct dmareg rq_dstreg; /* Dst Trans Req */
94 struct dmareg rq_sgl_srcreg; /* Sngl Src Trans Req*/
95 struct dmareg rq_sgl_dstreg; /* Sngl Dst Trans Req*/
96 struct dmareg rq_lst_srcreg; /* Last Src Trans Req*/
97 struct dmareg rq_lst_dstreg; /* Last Dst Trans Req*/
98 struct dmareg dma_cfg; /* DMA Config */
99 struct dmareg dma_chan_en; /* DMA Channel Enable*/
100 struct dmareg dma_id; /* DMA ID */
101 struct dmareg dma_test; /* DMA Test */
102 struct dmareg res1; /* reserved */
103 struct dmareg res2; /* reserved */
106 * Param 6 = dma_param[0], Param 5 = dma_param[1],
107 * Param 4 = dma_param[2] ...
109 struct dmareg dma_params[6];
112 /* Data structure for linked list item */
114 u32 sar; /* Source Address */
115 u32 dar; /* Destination address */
116 u32 llp; /* Linked List Pointer */
117 struct dmareg ctl; /* Control */
118 struct dmareg dstat; /* Destination Status */
122 SATA_DWC_DMAC_LLI_SZ = (sizeof(struct lli)),
123 SATA_DWC_DMAC_LLI_NUM = 256,
124 SATA_DWC_DMAC_LLI_TBL_SZ = (SATA_DWC_DMAC_LLI_SZ * \
125 SATA_DWC_DMAC_LLI_NUM),
126 SATA_DWC_DMAC_TWIDTH_BYTES = 4,
127 SATA_DWC_DMAC_CTRL_TSIZE_MAX = (0x00000800 * \
128 SATA_DWC_DMAC_TWIDTH_BYTES),
131 /* DMA Register Operation Bits */
133 DMA_EN = 0x00000001, /* Enable AHB DMA */
134 DMA_CTL_LLP_SRCEN = 0x10000000, /* Blk chain enable Src */
135 DMA_CTL_LLP_DSTEN = 0x08000000, /* Blk chain enable Dst */
138 #define DMA_CTL_BLK_TS(size) ((size) & 0x000000FFF) /* Blk Transfer size */
139 #define DMA_CHANNEL(ch) (0x00000001 << (ch)) /* Select channel */
141 #define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
142 ((0x000000001 << (ch)) << 8))
143 /* Disable channel */
144 #define DMA_DISABLE_CHAN(ch) (0x00000000 | ((0x000000001 << (ch)) << 8))
145 /* Transfer Type & Flow Controller */
146 #define DMA_CTL_TTFC(type) (((type) & 0x7) << 20)
147 #define DMA_CTL_SMS(num) (((num) & 0x3) << 25) /* Src Master Select */
148 #define DMA_CTL_DMS(num) (((num) & 0x3) << 23)/* Dst Master Select */
149 /* Src Burst Transaction Length */
150 #define DMA_CTL_SRC_MSIZE(size) (((size) & 0x7) << 14)
151 /* Dst Burst Transaction Length */
152 #define DMA_CTL_DST_MSIZE(size) (((size) & 0x7) << 11)
153 /* Source Transfer Width */
154 #define DMA_CTL_SRC_TRWID(size) (((size) & 0x7) << 4)
155 /* Destination Transfer Width */
156 #define DMA_CTL_DST_TRWID(size) (((size) & 0x7) << 1)
158 /* Assign HW handshaking interface (x) to destination / source peripheral */
159 #define DMA_CFG_HW_HS_DEST(int_num) (((int_num) & 0xF) << 11)
160 #define DMA_CFG_HW_HS_SRC(int_num) (((int_num) & 0xF) << 7)
161 #define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master))
164 * This define is used to set block chaining disabled in the control low
165 * register. It is already in little endian format so it can be &'d dirctly.
166 * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
169 DMA_CTL_LLP_DISABLE_LE32 = 0xffffffe7,
170 DMA_CTL_TTFC_P2M_DMAC = 0x00000002, /* Per to mem, DMAC cntr */
171 DMA_CTL_TTFC_M2P_PER = 0x00000003, /* Mem to per, peripheral cntr */
172 DMA_CTL_SINC_INC = 0x00000000, /* Source Address Increment */
173 DMA_CTL_SINC_DEC = 0x00000200,
174 DMA_CTL_SINC_NOCHANGE = 0x00000400,
175 DMA_CTL_DINC_INC = 0x00000000, /* Destination Address Increment */
176 DMA_CTL_DINC_DEC = 0x00000080,
177 DMA_CTL_DINC_NOCHANGE = 0x00000100,
178 DMA_CTL_INT_EN = 0x00000001, /* Interrupt Enable */
180 /* Channel Configuration Register high bits */
181 DMA_CFG_FCMOD_REQ = 0x00000001, /* Flow Control - request based */
182 DMA_CFG_PROTCTL = (0x00000003 << 2),/* Protection Control */
184 /* Channel Configuration Register low bits */
185 DMA_CFG_RELD_DST = 0x80000000, /* Reload Dest / Src Addr */
186 DMA_CFG_RELD_SRC = 0x40000000,
187 DMA_CFG_HS_SELSRC = 0x00000800, /* Software handshake Src/ Dest */
188 DMA_CFG_HS_SELDST = 0x00000400,
189 DMA_CFG_FIFOEMPTY = (0x00000001 << 9), /* FIFO Empty bit */
191 /* Channel Linked List Pointer Register */
192 DMA_LLP_AHBMASTER1 = 0, /* List Master Select */
193 DMA_LLP_AHBMASTER2 = 1,
195 SATA_DWC_MAX_PORTS = 1,
197 SATA_DWC_SCR_OFFSET = 0x24,
198 SATA_DWC_REG_OFFSET = 0x64,
201 /* DWC SATA Registers */
202 struct sata_dwc_regs {
203 u32 fptagr; /* 1st party DMA tag */
204 u32 fpbor; /* 1st party DMA buffer offset */
205 u32 fptcr; /* 1st party DMA Xfr count */
206 u32 dmacr; /* DMA Control */
207 u32 dbtsr; /* DMA Burst Transac size */
208 u32 intpr; /* Interrupt Pending */
209 u32 intmr; /* Interrupt Mask */
210 u32 errmr; /* Error Mask */
211 u32 llcr; /* Link Layer Control */
212 u32 phycr; /* PHY Control */
213 u32 physr; /* PHY Status */
214 u32 rxbistpd; /* Recvd BIST pattern def register */
215 u32 rxbistpd1; /* Recvd BIST data dword1 */
216 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
217 u32 txbistpd; /* Trans BIST pattern def register */
218 u32 txbistpd1; /* Trans BIST data dword1 */
219 u32 txbistpd2; /* Trans BIST data dword2 */
220 u32 bistcr; /* BIST Control Register */
221 u32 bistfctr; /* BIST FIS Count Register */
222 u32 bistsr; /* BIST Status Register */
223 u32 bistdecr; /* BIST Dword Error count register */
224 u32 res[15]; /* Reserved locations */
225 u32 testr; /* Test Register */
226 u32 versionr; /* Version Register */
227 u32 idr; /* ID Register */
228 u32 unimpl[192]; /* Unimplemented */
229 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
233 SCR_SCONTROL_DET_ENABLE = 0x00000001,
234 SCR_SSTATUS_DET_PRESENT = 0x00000001,
235 SCR_SERROR_DIAG_X = 0x04000000,
236 /* DWC SATA Register Operations */
237 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
238 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
239 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
240 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
241 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
242 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
243 SATA_DWC_INTPR_DMAT = 0x00000001,
244 SATA_DWC_INTPR_NEWFP = 0x00000002,
245 SATA_DWC_INTPR_PMABRT = 0x00000004,
246 SATA_DWC_INTPR_ERR = 0x00000008,
247 SATA_DWC_INTPR_NEWBIST = 0x00000010,
248 SATA_DWC_INTPR_IPF = 0x10000000,
249 SATA_DWC_INTMR_DMATM = 0x00000001,
250 SATA_DWC_INTMR_NEWFPM = 0x00000002,
251 SATA_DWC_INTMR_PMABRTM = 0x00000004,
252 SATA_DWC_INTMR_ERRM = 0x00000008,
253 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
254 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
255 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
256 SATA_DWC_LLCR_RPDEN = 0x00000004,
257 /* This is all error bits, zero's are reserved fields. */
258 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
261 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
262 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
263 SATA_DWC_DMACR_TMOD_TXCHEN)
264 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
265 SATA_DWC_DMACR_TMOD_TXCHEN)
266 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
267 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
269 struct sata_dwc_device {
270 struct device *dev; /* generic device struct */
271 struct ata_probe_ent *pe; /* ptr to probe-ent */
272 struct ata_host *host;
274 struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */
278 #define SATA_DWC_QCMD_MAX 32
280 struct sata_dwc_device_port {
281 struct sata_dwc_device *hsdev;
282 int cmd_issued[SATA_DWC_QCMD_MAX];
283 struct lli *llit[SATA_DWC_QCMD_MAX]; /* DMA LLI table */
284 dma_addr_t llit_dma[SATA_DWC_QCMD_MAX];
285 u32 dma_chan[SATA_DWC_QCMD_MAX];
286 int dma_pending[SATA_DWC_QCMD_MAX];
290 * Commonly used DWC SATA driver Macros
292 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\
293 (host)->private_data)
294 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\
295 (ap)->host->private_data)
296 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\
298 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\
299 (qc)->ap->host->private_data)
300 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\
304 SATA_DWC_CMD_ISSUED_NOT = 0,
305 SATA_DWC_CMD_ISSUED_PEND = 1,
306 SATA_DWC_CMD_ISSUED_EXEC = 2,
307 SATA_DWC_CMD_ISSUED_NODATA = 3,
309 SATA_DWC_DMA_PENDING_NONE = 0,
310 SATA_DWC_DMA_PENDING_TX = 1,
311 SATA_DWC_DMA_PENDING_RX = 2,
314 struct sata_dwc_host_priv {
315 void __iomem *scr_addr_sstatus;
316 u32 sata_dwc_sactive_issued ;
317 u32 sata_dwc_sactive_queued ;
318 u32 dma_interrupt_count;
319 struct ahb_dma_regs *sata_dma_regs;
320 struct device *dwc_dev;
322 struct sata_dwc_host_priv host_pvt;
326 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
327 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
329 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
330 static void sata_dwc_port_stop(struct ata_port *ap);
331 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
332 static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq);
333 static void dma_dwc_exit(struct sata_dwc_device *hsdev);
334 static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
335 struct lli *lli, dma_addr_t dma_lli,
336 void __iomem *addr, int dir);
337 static void dma_dwc_xfer_start(int dma_ch);
339 static void sata_dwc_tf_dump(struct ata_taskfile *tf)
341 dev_vdbg(host_pvt.dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags:"
342 "0x%lx device: %x\n", tf->command, ata_get_cmd_descript\
343 (tf->protocol), tf->flags, tf->device);
344 dev_vdbg(host_pvt.dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x "
345 "lbam: 0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
347 dev_vdbg(host_pvt.dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x "
348 "hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
349 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
354 * Function: get_burst_length_encode
355 * arguments: datalength: length in bytes of data
356 * returns value to be programmed in register corrresponding to data length
357 * This value is effectively the log(base 2) of the length
359 static int get_burst_length_encode(int datalength)
361 int items = datalength >> 2; /* div by 4 to get lword count */
381 static void clear_chan_interrupts(int c)
383 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.tfr.low),
385 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.block.low),
387 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.srctran.low),
389 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.dsttran.low),
391 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.error.low),
396 * Function: dma_request_channel
398 * returns channel number if available else -1
399 * This function assigns the next available DMA channel from the list to the
402 static int dma_request_channel(void)
406 for (i = 0; i < DMA_NUM_CHANS; i++) {
407 if (!(in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) &\
411 dev_err(host_pvt.dwc_dev, "%s NO channel chan_en: 0x%08x\n", __func__,
412 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)));
417 * Function: dma_dwc_interrupt
418 * arguments: irq, dev_id, pt_regs
419 * returns channel number if available else -1
420 * Interrupt Handler for DW AHB SATA DMA
422 static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance)
425 u32 tfr_reg, err_reg;
427 struct sata_dwc_device *hsdev =
428 (struct sata_dwc_device *)hsdev_instance;
429 struct ata_host *host = (struct ata_host *)hsdev->host;
431 struct sata_dwc_device_port *hsdevp;
433 unsigned int port = 0;
435 spin_lock_irqsave(&host->lock, flags);
436 ap = host->ports[port];
437 hsdevp = HSDEVP_FROM_AP(ap);
438 tag = ap->link.active_tag;
440 tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\
442 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\
445 dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
446 tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
448 for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
449 /* Check for end-of-transfer interrupt. */
450 if (tfr_reg & DMA_CHANNEL(chan)) {
452 * Each DMA command produces 2 interrupts. Only
453 * complete the command after both interrupts have been
454 * seen. (See sata_dwc_isr())
456 host_pvt.dma_interrupt_count++;
457 sata_dwc_clear_dmacr(hsdevp, tag);
459 if (hsdevp->dma_pending[tag] ==
460 SATA_DWC_DMA_PENDING_NONE) {
461 dev_err(ap->dev, "DMA not pending eot=0x%08x "
462 "err=0x%08x tag=0x%02x pending=%d\n",
463 tfr_reg, err_reg, tag,
464 hsdevp->dma_pending[tag]);
467 if ((host_pvt.dma_interrupt_count % 2) == 0)
468 sata_dwc_dma_xfer_complete(ap, 1);
470 /* Clear the interrupt */
471 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
476 /* Check for error interrupt. */
477 if (err_reg & DMA_CHANNEL(chan)) {
478 /* TODO Need error handler ! */
479 dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
482 /* Clear the interrupt. */
483 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
488 spin_unlock_irqrestore(&host->lock, flags);
493 * Function: dma_request_interrupts
496 * This function registers ISR for a particular DMA channel interrupt
498 static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
503 for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
504 /* Unmask error interrupt */
505 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low,
506 DMA_ENABLE_CHAN(chan));
508 /* Unmask end-of-transfer interrupt */
509 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low,
510 DMA_ENABLE_CHAN(chan));
513 retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
515 dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n",
520 /* Mark this interrupt as requested */
521 hsdev->irq_dma = irq;
526 * Function: map_sg_to_lli
527 * The Synopsis driver has a comment proposing that better performance
528 * is possible by only enabling interrupts on the last item in the linked list.
529 * However, it seems that could be a problem if an error happened on one of the
530 * first items. The transfer would halt, but no error interrupt would occur.
531 * Currently this function sets interrupts enabled for each linked list item:
534 static int map_sg_to_lli(struct scatterlist *sg, int num_elems,
535 struct lli *lli, dma_addr_t dma_lli,
536 void __iomem *dmadr_addr, int dir)
543 dev_dbg(host_pvt.dwc_dev, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x"
544 " dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli,
547 bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
549 for (i = 0; i < num_elems; i++, sg++) {
553 addr = (u32) sg_dma_address(sg);
554 sg_len = sg_dma_len(sg);
556 dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len"
557 "=%d\n", __func__, i, addr, sg_len);
560 if (idx >= SATA_DWC_DMAC_LLI_NUM) {
561 /* The LLI table is not large enough. */
562 dev_err(host_pvt.dwc_dev, "LLI table overrun "
566 len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
567 SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
569 offset = addr & 0xffff;
570 if ((offset + sg_len) > 0x10000)
571 len = 0x10000 - offset;
574 * Make sure a LLI block is not created that will span
575 * 8K max FIS boundary. If the block spans such a FIS
576 * boundary, there is a chance that a DMA burst will
577 * cross that boundary -- this results in an error in
578 * the host controller.
580 if (fis_len + len > 8192) {
581 dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len="
582 "%d(0x%x) len=%d(0x%x)\n", fis_len,
584 len = 8192 - fis_len;
593 * Set DMA addresses and lower half of control register
594 * based on direction.
596 if (dir == DMA_FROM_DEVICE) {
597 lli[idx].dar = cpu_to_le32(addr);
598 lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
600 lli[idx].ctl.low = cpu_to_le32(
601 DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
604 DMA_CTL_SRC_MSIZE(bl) |
605 DMA_CTL_DST_MSIZE(bl) |
606 DMA_CTL_SINC_NOCHANGE |
607 DMA_CTL_SRC_TRWID(2) |
608 DMA_CTL_DST_TRWID(2) |
612 } else { /* DMA_TO_DEVICE */
613 lli[idx].sar = cpu_to_le32(addr);
614 lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
616 lli[idx].ctl.low = cpu_to_le32(
617 DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
620 DMA_CTL_SRC_MSIZE(bl) |
621 DMA_CTL_DST_MSIZE(bl) |
622 DMA_CTL_DINC_NOCHANGE |
623 DMA_CTL_SRC_TRWID(2) |
624 DMA_CTL_DST_TRWID(2) |
630 dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: "
631 "0x%08x val: 0x%08x\n", __func__,
632 len, DMA_CTL_BLK_TS(len / 4));
634 /* Program the LLI CTL high register */
635 lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\
638 /* Program the next pointer. The next pointer must be
639 * the physical address, not the virtual address.
641 next_llp = (dma_lli + ((idx + 1) * sizeof(struct \
644 /* The last 2 bits encode the list master select. */
645 next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
647 lli[idx].llp = cpu_to_le32(next_llp);
655 * The last next ptr has to be zero and the last control low register
656 * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
657 * and destination enable) set back to 0 (disabled.) This is what tells
658 * the core that this is the last item in the linked list.
661 lli[idx-1].llp = 0x00000000;
662 lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
664 /* Flush cache to memory */
665 dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
673 * Function: dma_dwc_xfer_start
674 * arguments: Channel number
676 * Enables the DMA channel
678 static void dma_dwc_xfer_start(int dma_ch)
680 /* Enable the DMA channel */
681 out_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low),
682 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) |
683 DMA_ENABLE_CHAN(dma_ch));
686 static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
687 struct lli *lli, dma_addr_t dma_lli,
688 void __iomem *addr, int dir)
692 /* Acquire DMA channel */
693 dma_ch = dma_request_channel();
695 dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n",
700 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
701 num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir);
703 dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli:"
704 " 0x%0xlx addr: %p lli count: %d\n", __func__, sg, num_elems,
705 lli, (u32)dma_lli, addr, num_lli);
707 clear_chan_interrupts(dma_ch);
709 /* Program the CFG register. */
710 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.high),
711 DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ);
712 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.low), 0);
714 /* Program the address of the linked list */
715 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].llp.low),
716 DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2));
718 /* Program the CTL register with src enable / dst enable */
719 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].ctl.low),
720 DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN);
725 * Function: dma_dwc_exit
728 * This function exits the SATA DMA driver
730 static void dma_dwc_exit(struct sata_dwc_device *hsdev)
732 dev_dbg(host_pvt.dwc_dev, "%s:\n", __func__);
733 if (host_pvt.sata_dma_regs)
734 iounmap(host_pvt.sata_dma_regs);
737 free_irq(hsdev->irq_dma, hsdev);
741 * Function: dma_dwc_init
744 * This function initializes the SATA DMA driver
746 static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq)
750 err = dma_request_interrupts(hsdev, irq);
752 dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns"
753 " %d\n", __func__, err);
758 out_le32(&(host_pvt.sata_dma_regs->dma_cfg.low), DMA_EN);
760 dev_notice(host_pvt.dwc_dev, "DMA initialized\n");
761 dev_dbg(host_pvt.dwc_dev, "SATA DMA registers=0x%p\n", host_pvt.\
772 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
774 if (scr > SCR_NOTIFICATION) {
775 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
780 *val = in_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4));
781 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
782 __func__, link->ap->print_id, scr, *val);
787 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
789 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
790 __func__, link->ap->print_id, scr, val);
791 if (scr > SCR_NOTIFICATION) {
792 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
796 out_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4), val);
801 static u32 core_scr_read(unsigned int scr)
803 return in_le32((void __iomem *)(host_pvt.scr_addr_sstatus) +\
807 static void core_scr_write(unsigned int scr, u32 val)
809 out_le32((void __iomem *)(host_pvt.scr_addr_sstatus) + (scr * 4),
813 static void clear_serror(void)
816 val = core_scr_read(SCR_ERROR);
817 core_scr_write(SCR_ERROR, val);
821 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
823 out_le32(&hsdev->sata_dwc_regs->intpr,
824 in_le32(&hsdev->sata_dwc_regs->intpr));
827 static u32 qcmd_tag_to_mask(u8 tag)
829 return 0x00000001 << (tag & 0x1f);
833 static void sata_dwc_error_intr(struct ata_port *ap,
834 struct sata_dwc_device *hsdev, uint intpr)
836 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
837 struct ata_eh_info *ehi = &ap->link.eh_info;
838 unsigned int err_mask = 0, action = 0;
839 struct ata_queued_cmd *qc;
844 ata_ehi_clear_desc(ehi);
846 serror = core_scr_read(SCR_ERROR);
847 status = ap->ops->sff_check_status(ap);
849 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error.\
851 tag = ap->link.active_tag;
853 dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x "
854 "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n",
855 __func__, serror, intpr, status, host_pvt.dma_interrupt_count,
856 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg);
858 /* Clear error register and interrupt bit */
860 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
862 /* This is the only error happening now. TODO check for exact error */
864 err_mask |= AC_ERR_HOST_BUS;
865 action |= ATA_EH_RESET;
867 /* Pass this on to EH */
868 ehi->serror |= serror;
869 ehi->action |= action;
871 qc = ata_qc_from_tag(ap, tag);
873 qc->err_mask |= err_mask;
875 ehi->err_mask |= err_mask;
881 * Function : sata_dwc_isr
882 * arguments : irq, void *dev_instance, struct pt_regs *regs
883 * Return value : irqreturn_t - status of IRQ
884 * This Interrupt handler called via port ops registered function.
885 * .irq_handler = sata_dwc_isr
887 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
889 struct ata_host *host = (struct ata_host *)dev_instance;
890 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
892 struct ata_queued_cmd *qc;
895 int handled, num_processed, port = 0;
896 uint intpr, sactive, sactive2, tag_mask;
897 struct sata_dwc_device_port *hsdevp;
898 host_pvt.sata_dwc_sactive_issued = 0;
900 spin_lock_irqsave(&host->lock, flags);
902 /* Read the interrupt register */
903 intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
905 ap = host->ports[port];
906 hsdevp = HSDEVP_FROM_AP(ap);
908 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
909 ap->link.active_tag);
911 /* Check for error interrupt */
912 if (intpr & SATA_DWC_INTPR_ERR) {
913 sata_dwc_error_intr(ap, hsdev, intpr);
918 /* Check for DMA SETUP FIS (FP DMA) interrupt */
919 if (intpr & SATA_DWC_INTPR_NEWFP) {
920 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
922 tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
923 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
924 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
925 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
927 host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
929 qc = ata_qc_from_tag(ap, tag);
931 * Start FP DMA for NCQ command. At this point the tag is the
932 * active tag. It is the tag that matches the command about to
935 qc->ap->link.active_tag = tag;
936 sata_dwc_bmdma_start_by_tag(qc, tag);
941 sactive = core_scr_read(SCR_ACTIVE);
942 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
944 /* If no sactive issued and tag_mask is zero then this is not NCQ */
945 if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
946 if (ap->link.active_tag == ATA_TAG_POISON)
949 tag = ap->link.active_tag;
950 qc = ata_qc_from_tag(ap, tag);
952 /* DEV interrupt w/ no active qc? */
953 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
954 dev_err(ap->dev, "%s interrupt with no active qc "
955 "qc=%p\n", __func__, qc);
956 ap->ops->sff_check_status(ap);
960 status = ap->ops->sff_check_status(ap);
962 qc->ap->link.active_tag = tag;
963 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
965 if (status & ATA_ERR) {
966 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
967 sata_dwc_qc_complete(ap, qc, 1);
972 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
973 __func__, ata_get_cmd_descript(qc->tf.protocol));
975 if (ata_is_dma(qc->tf.protocol)) {
977 * Each DMA transaction produces 2 interrupts. The DMAC
978 * transfer complete interrupt and the SATA controller
979 * operation done interrupt. The command should be
980 * completed only after both interrupts are seen.
982 host_pvt.dma_interrupt_count++;
983 if (hsdevp->dma_pending[tag] == \
984 SATA_DWC_DMA_PENDING_NONE) {
985 dev_err(ap->dev, "%s: DMA not pending "
986 "intpr=0x%08x status=0x%08x pending"
987 "=%d\n", __func__, intpr, status,
988 hsdevp->dma_pending[tag]);
991 if ((host_pvt.dma_interrupt_count % 2) == 0)
992 sata_dwc_dma_xfer_complete(ap, 1);
993 } else if (ata_is_pio(qc->tf.protocol)) {
994 ata_sff_hsm_move(ap, qc, status, 0);
998 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1007 * This is a NCQ command. At this point we need to figure out for which
1008 * tags we have gotten a completion interrupt. One interrupt may serve
1009 * as completion for more than one operation when commands are queued
1010 * (NCQ). We need to process each completed command.
1013 /* process completed commands */
1014 sactive = core_scr_read(SCR_ACTIVE);
1015 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
1017 if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
1019 dev_dbg(ap->dev, "%s NCQ:sactive=0x%08x sactive_issued=0x%08x"
1020 "tag_mask=0x%08x\n", __func__, sactive,
1021 host_pvt.sata_dwc_sactive_issued, tag_mask);
1024 if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
1025 (host_pvt.sata_dwc_sactive_issued)) {
1026 dev_warn(ap->dev, "Bad tag mask? sactive=0x%08x "
1027 "(host_pvt.sata_dwc_sactive_issued)=0x%08x tag_mask"
1028 "=0x%08x\n", sactive, host_pvt.sata_dwc_sactive_issued,
1032 /* read just to clear ... not bad if currently still busy */
1033 status = ap->ops->sff_check_status(ap);
1034 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
1040 while (!(tag_mask & 0x00000001)) {
1045 tag_mask &= (~0x00000001);
1046 qc = ata_qc_from_tag(ap, tag);
1048 /* To be picked up by completion functions */
1049 qc->ap->link.active_tag = tag;
1050 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1052 /* Let libata/scsi layers handle error */
1053 if (status & ATA_ERR) {
1054 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
1056 sata_dwc_qc_complete(ap, qc, 1);
1061 /* Process completed command */
1062 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
1063 ata_get_cmd_descript(qc->tf.protocol));
1064 if (ata_is_dma(qc->tf.protocol)) {
1065 host_pvt.dma_interrupt_count++;
1066 if (hsdevp->dma_pending[tag] == \
1067 SATA_DWC_DMA_PENDING_NONE)
1068 dev_warn(ap->dev, "%s: DMA not pending?\n",
1070 if ((host_pvt.dma_interrupt_count % 2) == 0)
1071 sata_dwc_dma_xfer_complete(ap, 1);
1073 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1079 ap->stats.idle_irq++;
1080 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
1082 } /* while tag_mask */
1085 * Check to see if any commands completed while we were processing our
1086 * initial set of completed commands (read status clears interrupts,
1087 * so we might miss a completed command interrupt if one came in while
1088 * we were processing --we read status as part of processing a completed
1091 sactive2 = core_scr_read(SCR_ACTIVE);
1092 if (sactive2 != sactive) {
1093 dev_dbg(ap->dev, "More completed - sactive=0x%x sactive2"
1094 "=0x%x\n", sactive, sactive2);
1099 spin_unlock_irqrestore(&host->lock, flags);
1100 return IRQ_RETVAL(handled);
1103 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
1105 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
1107 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
1108 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1109 SATA_DWC_DMACR_RX_CLEAR(
1110 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1111 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
1112 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1113 SATA_DWC_DMACR_TX_CLEAR(
1114 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1117 * This should not happen, it indicates the driver is out of
1118 * sync. If it does happen, clear dmacr anyway.
1120 dev_err(host_pvt.dwc_dev, "%s DMA protocol RX and"
1121 "TX DMA not pending tag=0x%02x pending=%d"
1122 " dmacr: 0x%08x\n", __func__, tag,
1123 hsdevp->dma_pending[tag],
1124 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1125 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1126 SATA_DWC_DMACR_TXRXCH_CLEAR);
1130 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
1132 struct ata_queued_cmd *qc;
1133 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1134 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1137 tag = ap->link.active_tag;
1138 qc = ata_qc_from_tag(ap, tag);
1140 dev_err(ap->dev, "failed to get qc");
1146 dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s "
1147 "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command,
1148 ata_get_cmd_descript(qc->dma_dir),
1149 ata_get_cmd_descript(qc->tf.protocol),
1150 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1154 if (ata_is_dma(qc->tf.protocol)) {
1155 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
1156 dev_err(ap->dev, "%s DMA protocol RX and TX DMA not "
1157 "pending dmacr: 0x%08x\n", __func__,
1158 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1161 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
1162 sata_dwc_qc_complete(ap, qc, check_status);
1163 ap->link.active_tag = ATA_TAG_POISON;
1165 sata_dwc_qc_complete(ap, qc, check_status);
1169 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
1175 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1176 host_pvt.sata_dwc_sactive_queued = 0;
1177 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
1179 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
1180 dev_err(ap->dev, "TX DMA PENDING\n");
1181 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
1182 dev_err(ap->dev, "RX DMA PENDING\n");
1183 dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u:"
1184 " protocol=%d\n", qc->tf.command, status, ap->print_id,
1187 /* clear active bit */
1188 mask = (~(qcmd_tag_to_mask(tag)));
1189 host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
1191 host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
1193 ata_qc_complete(qc);
1197 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
1199 /* Enable selective interrupts by setting the interrupt maskregister*/
1200 out_le32(&hsdev->sata_dwc_regs->intmr,
1201 SATA_DWC_INTMR_ERRM |
1202 SATA_DWC_INTMR_NEWFPM |
1203 SATA_DWC_INTMR_PMABRTM |
1204 SATA_DWC_INTMR_DMATM);
1206 * Unmask the error bits that should trigger an error interrupt by
1207 * setting the error mask register.
1209 out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
1211 dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
1212 __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
1213 in_le32(&hsdev->sata_dwc_regs->errmr));
1216 static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
1218 port->cmd_addr = (void *)base + 0x00;
1219 port->data_addr = (void *)base + 0x00;
1221 port->error_addr = (void *)base + 0x04;
1222 port->feature_addr = (void *)base + 0x04;
1224 port->nsect_addr = (void *)base + 0x08;
1226 port->lbal_addr = (void *)base + 0x0c;
1227 port->lbam_addr = (void *)base + 0x10;
1228 port->lbah_addr = (void *)base + 0x14;
1230 port->device_addr = (void *)base + 0x18;
1231 port->command_addr = (void *)base + 0x1c;
1232 port->status_addr = (void *)base + 0x1c;
1234 port->altstatus_addr = (void *)base + 0x20;
1235 port->ctl_addr = (void *)base + 0x20;
1239 * Function : sata_dwc_port_start
1240 * arguments : struct ata_ioports *port
1241 * Return value : returns 0 if success, error code otherwise
1242 * This function allocates the scatter gather LLI table for AHB DMA
1244 static int sata_dwc_port_start(struct ata_port *ap)
1247 struct sata_dwc_device *hsdev;
1248 struct sata_dwc_device_port *hsdevp = NULL;
1249 struct device *pdev;
1252 hsdev = HSDEV_FROM_AP(ap);
1254 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
1256 hsdev->host = ap->host;
1257 pdev = ap->host->dev;
1259 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
1264 /* Allocate Port Struct */
1265 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
1267 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
1271 hsdevp->hsdev = hsdev;
1273 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
1274 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
1276 ap->bmdma_prd = 0; /* set these so libata doesn't use them */
1277 ap->bmdma_prd_dma = 0;
1280 * DMA - Assign scatter gather LLI table. We can't use the libata
1281 * version since it's PRD is IDE PCI specific.
1283 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1284 hsdevp->llit[i] = dma_alloc_coherent(pdev,
1285 SATA_DWC_DMAC_LLI_TBL_SZ,
1286 &(hsdevp->llit_dma[i]),
1288 if (!hsdevp->llit[i]) {
1289 dev_err(ap->dev, "%s: dma_alloc_coherent failed\n",
1296 if (ap->port_no == 0) {
1297 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
1299 out_le32(&hsdev->sata_dwc_regs->dmacr,
1300 SATA_DWC_DMACR_TXRXCH_CLEAR);
1302 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
1304 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1305 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1306 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
1309 /* Clear any error bits before libata starts issuing commands */
1311 ap->private_data = hsdevp;
1315 sata_dwc_port_stop(ap);
1316 dev_dbg(ap->dev, "%s: fail\n", __func__);
1318 dev_dbg(ap->dev, "%s: done\n", __func__);
1324 static void sata_dwc_port_stop(struct ata_port *ap)
1327 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1328 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1330 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
1332 if (hsdevp && hsdev) {
1333 /* deallocate LLI table */
1334 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1335 dma_free_coherent(ap->host->dev,
1336 SATA_DWC_DMAC_LLI_TBL_SZ,
1337 hsdevp->llit[i], hsdevp->llit_dma[i]);
1342 ap->private_data = NULL;
1346 * Function : sata_dwc_exec_command_by_tag
1347 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
1348 * Return value : None
1349 * This function keeps track of individual command tag ids and calls
1350 * ata_exec_command in libata
1352 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
1353 struct ata_taskfile *tf,
1354 u8 tag, u32 cmd_issued)
1356 unsigned long flags;
1357 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1359 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
1360 ata_get_cmd_descript(tf->command), tag);
1362 spin_lock_irqsave(&ap->host->lock, flags);
1363 hsdevp->cmd_issued[tag] = cmd_issued;
1364 spin_unlock_irqrestore(&ap->host->lock, flags);
1366 * Clear SError before executing a new command.
1367 * sata_dwc_scr_write and read can not be used here. Clearing the PM
1368 * managed SError register for the disk needs to be done before the
1369 * task file is loaded.
1372 ata_sff_exec_command(ap, tf);
1375 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1377 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1378 SATA_DWC_CMD_ISSUED_PEND);
1381 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1385 if (ata_is_ncq(qc->tf.protocol)) {
1386 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1387 __func__, qc->ap->link.sactive, tag);
1391 sata_dwc_bmdma_setup_by_tag(qc, tag);
1394 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1398 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1399 struct ata_port *ap = qc->ap;
1400 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1401 int dir = qc->dma_dir;
1402 dma_chan = hsdevp->dma_chan[tag];
1404 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1406 if (dir == DMA_TO_DEVICE)
1407 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1409 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1411 dev_err(ap->dev, "%s: Command not pending cmd_issued=%d "
1412 "(tag=%d) DMA NOT started\n", __func__,
1413 hsdevp->cmd_issued[tag], tag);
1417 dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s "
1418 "start_dma? %x\n", __func__, qc, tag, qc->tf.command,
1419 ata_get_cmd_descript(qc->dma_dir), start_dma);
1420 sata_dwc_tf_dump(&(qc->tf));
1423 reg = core_scr_read(SCR_ERROR);
1424 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1425 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1429 if (dir == DMA_TO_DEVICE)
1430 out_le32(&hsdev->sata_dwc_regs->dmacr,
1431 SATA_DWC_DMACR_TXCHEN);
1433 out_le32(&hsdev->sata_dwc_regs->dmacr,
1434 SATA_DWC_DMACR_RXCHEN);
1436 /* Enable AHB DMA transfer on the specified channel */
1437 dma_dwc_xfer_start(dma_chan);
1441 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1445 if (ata_is_ncq(qc->tf.protocol)) {
1446 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1447 __func__, qc->ap->link.sactive, tag);
1451 dev_dbg(qc->ap->dev, "%s\n", __func__);
1452 sata_dwc_bmdma_start_by_tag(qc, tag);
1456 * Function : sata_dwc_qc_prep_by_tag
1457 * arguments : ata_queued_cmd *qc, u8 tag
1458 * Return value : None
1459 * qc_prep for a particular queued command based on tag
1461 static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
1463 struct scatterlist *sg = qc->sg;
1464 struct ata_port *ap = qc->ap;
1466 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1467 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1469 dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
1470 __func__, ap->port_no, ata_get_cmd_descript(qc->dma_dir),
1473 dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag],
1474 hsdevp->llit_dma[tag],
1475 (void *__iomem)(&hsdev->sata_dwc_regs->\
1476 dmadr), qc->dma_dir);
1478 dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n",
1479 __func__, dma_chan);
1482 hsdevp->dma_chan[tag] = dma_chan;
1485 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1489 struct ata_port *ap = qc->ap;
1492 if (qc->tag > 0 || ap->link.sactive > 1)
1493 dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d "
1494 "prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1495 __func__, ap->print_id, qc->tf.command,
1496 ata_get_cmd_descript(qc->tf.command),
1497 qc->tag, ata_get_cmd_descript(qc->tf.protocol),
1498 ap->link.active_tag, ap->link.sactive);
1501 if (!ata_is_ncq(qc->tf.protocol))
1503 sata_dwc_qc_prep_by_tag(qc, tag);
1505 if (ata_is_ncq(qc->tf.protocol)) {
1506 sactive = core_scr_read(SCR_ACTIVE);
1507 sactive |= (0x00000001 << tag);
1508 core_scr_write(SCR_ACTIVE, sactive);
1510 dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x "
1511 "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive,
1514 ap->ops->sff_tf_load(ap, &qc->tf);
1515 sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
1516 SATA_DWC_CMD_ISSUED_PEND);
1518 ata_sff_qc_issue(qc);
1524 * Function : sata_dwc_qc_prep
1525 * arguments : ata_queued_cmd *qc
1526 * Return value : None
1527 * qc_prep for a particular queued command
1530 static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
1532 if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
1537 dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
1538 __func__, qc->tag, qc->ap->link.active_tag);
1544 static void sata_dwc_error_handler(struct ata_port *ap)
1546 ap->link.flags |= ATA_LFLAG_NO_HRST;
1547 ata_sff_error_handler(ap);
1551 * scsi mid-layer and libata interface structures
1553 static struct scsi_host_template sata_dwc_sht = {
1554 ATA_NCQ_SHT(DRV_NAME),
1556 * test-only: Currently this driver doesn't handle NCQ
1557 * correctly. We enable NCQ but set the queue depth to a
1558 * max of 1. This will get fixed in in a future release.
1560 .sg_tablesize = LIBATA_MAX_PRD,
1561 .can_queue = ATA_DEF_QUEUE, /* ATA_MAX_QUEUE */
1562 .dma_boundary = ATA_DMA_BOUNDARY,
1565 static struct ata_port_operations sata_dwc_ops = {
1566 .inherits = &ata_sff_port_ops,
1568 .error_handler = sata_dwc_error_handler,
1570 .qc_prep = sata_dwc_qc_prep,
1571 .qc_issue = sata_dwc_qc_issue,
1573 .scr_read = sata_dwc_scr_read,
1574 .scr_write = sata_dwc_scr_write,
1576 .port_start = sata_dwc_port_start,
1577 .port_stop = sata_dwc_port_stop,
1579 .bmdma_setup = sata_dwc_bmdma_setup,
1580 .bmdma_start = sata_dwc_bmdma_start,
1583 static const struct ata_port_info sata_dwc_port_info[] = {
1585 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
1586 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
1587 .pio_mask = ATA_PIO4,
1588 .udma_mask = ATA_UDMA6,
1589 .port_ops = &sata_dwc_ops,
1593 static int sata_dwc_probe(struct platform_device *ofdev,
1594 const struct of_device_id *match)
1596 struct sata_dwc_device *hsdev;
1598 char *ver = (char *)&versionr;
1602 struct ata_host *host;
1603 struct ata_port_info pi = sata_dwc_port_info[0];
1604 const struct ata_port_info *ppi[] = { &pi, NULL };
1606 /* Allocate DWC SATA device */
1607 hsdev = kmalloc(sizeof(*hsdev), GFP_KERNEL);
1608 if (hsdev == NULL) {
1609 dev_err(&ofdev->dev, "kmalloc failed for hsdev\n");
1613 memset(hsdev, 0, sizeof(*hsdev));
1615 /* Ioremap SATA registers */
1616 base = of_iomap(ofdev->dev.of_node, 0);
1618 dev_err(&ofdev->dev, "ioremap failed for SATA register"
1623 hsdev->reg_base = base;
1624 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1626 /* Synopsys DWC SATA specific Registers */
1627 hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
1629 /* Allocate and fill host */
1630 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1632 dev_err(&ofdev->dev, "ata_host_alloc_pinfo failed\n");
1637 host->private_data = hsdev;
1640 host->ports[0]->ioaddr.cmd_addr = base;
1641 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1642 host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
1643 sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
1645 /* Read the ID and Version Registers */
1646 idr = in_le32(&hsdev->sata_dwc_regs->idr);
1647 versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
1648 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1649 idr, ver[0], ver[1], ver[2]);
1651 /* Get SATA DMA interrupt number */
1652 irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
1653 if (irq == NO_IRQ) {
1654 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1659 /* Get physical SATA DMA register base address */
1660 host_pvt.sata_dma_regs = of_iomap(ofdev->dev.of_node, 1);
1661 if (!(host_pvt.sata_dma_regs)) {
1662 dev_err(&ofdev->dev, "ioremap failed for AHBDMA register"
1668 /* Save dev for later use in dev_xxx() routines */
1669 host_pvt.dwc_dev = &ofdev->dev;
1671 /* Initialize AHB DMAC */
1672 dma_dwc_init(hsdev, irq);
1674 /* Enable SATA Interrupts */
1675 sata_dwc_enable_interrupts(hsdev);
1677 /* Get SATA interrupt number */
1678 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1679 if (irq == NO_IRQ) {
1680 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1686 * Now, register with libATA core, this will also initiate the
1687 * device discovery process, invoking our port_start() handler &
1688 * error_handler() to execute a dummy Softreset EH session
1690 rc = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1693 dev_err(&ofdev->dev, "failed to activate host");
1695 dev_set_drvdata(&ofdev->dev, host);
1699 /* Free SATA DMA resources */
1700 dma_dwc_exit(hsdev);
1707 static int sata_dwc_remove(struct platform_device *ofdev)
1709 struct device *dev = &ofdev->dev;
1710 struct ata_host *host = dev_get_drvdata(dev);
1711 struct sata_dwc_device *hsdev = host->private_data;
1713 ata_host_detach(host);
1714 dev_set_drvdata(dev, NULL);
1716 /* Free SATA DMA resources */
1717 dma_dwc_exit(hsdev);
1719 iounmap(hsdev->reg_base);
1722 dev_dbg(&ofdev->dev, "done\n");
1726 static const struct of_device_id sata_dwc_match[] = {
1727 { .compatible = "amcc,sata-460ex", },
1730 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1732 static struct of_platform_driver sata_dwc_driver = {
1735 .owner = THIS_MODULE,
1736 .of_match_table = sata_dwc_match,
1738 .probe = sata_dwc_probe,
1739 .remove = sata_dwc_remove,
1742 static int __init sata_dwc_init(void)
1744 return of_register_platform_driver(&sata_dwc_driver);
1747 static void __exit sata_dwc_exit(void)
1749 of_unregister_platform_driver(&sata_dwc_driver);
1752 module_init(sata_dwc_init);
1753 module_exit(sata_dwc_exit);
1755 MODULE_LICENSE("GPL");
1756 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1757 MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver");
1758 MODULE_VERSION(DRV_VERSION);