2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
22 * Hardware information only available under NDA.
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/blkdev.h>
30 #include <linux/delay.h>
31 #include <linux/device.h>
32 #include <scsi/scsi.h>
33 #include <scsi/scsi_host.h>
34 #include <scsi/scsi_cmnd.h>
35 #include <linux/libata.h>
37 #define DRV_NAME "pata_pdc2027x"
38 #define DRV_VERSION "1.0"
42 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
44 #define PDPRINTK(fmt, args...)
53 PDC_100_MHZ = 100000000,
54 PDC_133_MHZ = 133333333,
58 PDC_GLOBAL_CTL = 0x1108,
61 PDC_BYTE_COUNT = 0x1120,
65 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
66 static void pdc2027x_error_handler(struct ata_port *ap);
67 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
69 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
70 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
71 static int pdc2027x_cable_detect(struct ata_port *ap);
72 static int pdc2027x_set_mode(struct ata_port *ap, struct ata_device **r_failed);
75 * ATA Timing Tables based on 133MHz controller clock.
76 * These tables are only used when the controller is in 133MHz clock.
77 * If the controller is in 100MHz clock, the ASIC hardware will
78 * set the timing registers automatically when "set feature" command
79 * is issued to the device. However, if the controller clock is 133MHz,
80 * the following tables must be used.
82 static struct pdc2027x_pio_timing {
83 u8 value0, value1, value2;
84 } pdc2027x_pio_timing_tbl [] = {
85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
92 static struct pdc2027x_mdma_timing {
94 } pdc2027x_mdma_timing_tbl [] = {
95 { 0xdf, 0x5f }, /* MDMA mode 0 */
96 { 0x6b, 0x27 }, /* MDMA mode 1 */
97 { 0x69, 0x25 }, /* MDMA mode 2 */
100 static struct pdc2027x_udma_timing {
101 u8 value0, value1, value2;
102 } pdc2027x_udma_timing_tbl [] = {
103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
112 static const struct pci_device_id pdc2027x_pci_tbl[] = {
113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
121 { } /* terminate list */
124 static struct pci_driver pdc2027x_pci_driver = {
126 .id_table = pdc2027x_pci_tbl,
127 .probe = pdc2027x_init_one,
128 .remove = ata_pci_remove_one,
131 static struct scsi_host_template pdc2027x_sht = {
132 .module = THIS_MODULE,
134 .ioctl = ata_scsi_ioctl,
135 .queuecommand = ata_scsi_queuecmd,
136 .can_queue = ATA_DEF_QUEUE,
137 .this_id = ATA_SHT_THIS_ID,
138 .sg_tablesize = LIBATA_MAX_PRD,
139 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
140 .emulated = ATA_SHT_EMULATED,
141 .use_clustering = ATA_SHT_USE_CLUSTERING,
142 .proc_name = DRV_NAME,
143 .dma_boundary = ATA_DMA_BOUNDARY,
144 .slave_configure = ata_scsi_slave_config,
145 .slave_destroy = ata_scsi_slave_destroy,
146 .bios_param = ata_std_bios_param,
149 static struct ata_port_operations pdc2027x_pata100_ops = {
150 .port_disable = ata_port_disable,
151 .mode_filter = ata_pci_default_filter,
153 .tf_load = ata_tf_load,
154 .tf_read = ata_tf_read,
155 .check_status = ata_check_status,
156 .exec_command = ata_exec_command,
157 .dev_select = ata_std_dev_select,
159 .check_atapi_dma = pdc2027x_check_atapi_dma,
160 .bmdma_setup = ata_bmdma_setup,
161 .bmdma_start = ata_bmdma_start,
162 .bmdma_stop = ata_bmdma_stop,
163 .bmdma_status = ata_bmdma_status,
164 .qc_prep = ata_qc_prep,
165 .qc_issue = ata_qc_issue_prot,
166 .data_xfer = ata_data_xfer,
168 .freeze = ata_bmdma_freeze,
169 .thaw = ata_bmdma_thaw,
170 .error_handler = pdc2027x_error_handler,
171 .post_internal_cmd = ata_bmdma_post_internal_cmd,
172 .cable_detect = pdc2027x_cable_detect,
174 .irq_clear = ata_bmdma_irq_clear,
175 .irq_on = ata_irq_on,
176 .irq_ack = ata_irq_ack,
178 .port_start = ata_port_start,
181 static struct ata_port_operations pdc2027x_pata133_ops = {
182 .port_disable = ata_port_disable,
183 .set_piomode = pdc2027x_set_piomode,
184 .set_dmamode = pdc2027x_set_dmamode,
185 .set_mode = pdc2027x_set_mode,
186 .mode_filter = pdc2027x_mode_filter,
188 .tf_load = ata_tf_load,
189 .tf_read = ata_tf_read,
190 .check_status = ata_check_status,
191 .exec_command = ata_exec_command,
192 .dev_select = ata_std_dev_select,
194 .check_atapi_dma = pdc2027x_check_atapi_dma,
195 .bmdma_setup = ata_bmdma_setup,
196 .bmdma_start = ata_bmdma_start,
197 .bmdma_stop = ata_bmdma_stop,
198 .bmdma_status = ata_bmdma_status,
199 .qc_prep = ata_qc_prep,
200 .qc_issue = ata_qc_issue_prot,
201 .data_xfer = ata_data_xfer,
203 .freeze = ata_bmdma_freeze,
204 .thaw = ata_bmdma_thaw,
205 .error_handler = pdc2027x_error_handler,
206 .post_internal_cmd = ata_bmdma_post_internal_cmd,
207 .cable_detect = pdc2027x_cable_detect,
209 .irq_clear = ata_bmdma_irq_clear,
210 .irq_on = ata_irq_on,
211 .irq_ack = ata_irq_ack,
213 .port_start = ata_port_start,
216 static struct ata_port_info pdc2027x_port_info[] = {
219 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
221 .pio_mask = 0x1f, /* pio0-4 */
222 .mwdma_mask = 0x07, /* mwdma0-2 */
223 .udma_mask = ATA_UDMA5, /* udma0-5 */
224 .port_ops = &pdc2027x_pata100_ops,
228 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
230 .pio_mask = 0x1f, /* pio0-4 */
231 .mwdma_mask = 0x07, /* mwdma0-2 */
232 .udma_mask = ATA_UDMA6, /* udma0-6 */
233 .port_ops = &pdc2027x_pata133_ops,
237 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
238 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
239 MODULE_LICENSE("GPL");
240 MODULE_VERSION(DRV_VERSION);
241 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
244 * port_mmio - Get the MMIO address of PDC2027x extended registers
246 * @offset: offset from mmio base
248 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
250 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
254 * dev_mmio - Get the MMIO address of PDC2027x extended registers
257 * @offset: offset from mmio base
259 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
261 u8 adj = (adev->devno) ? 0x08 : 0x00;
262 return port_mmio(ap, offset) + adj;
266 * pdc2027x_pata_cable_detect - Probe host controller cable detect info
267 * @ap: Port for which cable detect info is desired
269 * Read 80c cable indicator from Promise extended register.
270 * This register is latched when the system is reset.
273 * None (inherited from caller).
275 static int pdc2027x_cable_detect(struct ata_port *ap)
279 /* check cable detect results */
280 cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL));
281 if (cgcr & (1 << 26))
284 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
286 return ATA_CBL_PATA80;
288 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
289 return ATA_CBL_PATA40;
293 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
296 static inline int pdc2027x_port_enabled(struct ata_port *ap)
298 return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
302 * pdc2027x_prereset - prereset for PATA host controller
304 * @deadline: deadline jiffies for the operation
306 * Probeinit including cable detection.
309 * None (inherited from caller).
312 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
314 /* Check whether port enabled */
315 if (!pdc2027x_port_enabled(link->ap))
317 return ata_std_prereset(link, deadline);
321 * pdc2027x_error_handler - Perform reset on PATA port and classify
324 * Reset PATA phy and classify attached devices.
327 * None (inherited from caller).
330 static void pdc2027x_error_handler(struct ata_port *ap)
332 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
336 * pdc2720x_mode_filter - mode selection filter
338 * @mask: list of modes proposed
340 * Block UDMA on devices that cause trouble with this controller.
343 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
345 unsigned char model_num[ATA_ID_PROD_LEN + 1];
346 struct ata_device *pair = ata_dev_pair(adev);
348 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
349 return ata_pci_default_filter(adev, mask);
351 /* Check for slave of a Maxtor at UDMA6 */
352 ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
353 ATA_ID_PROD_LEN + 1);
354 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
355 if(strstr(model_num, "Maxtor") == 0 && pair->dma_mode == XFER_UDMA_6)
356 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
358 return ata_pci_default_filter(adev, mask);
362 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
363 * @ap: Port to configure
365 * @pio: PIO mode, 0 - 4
367 * Set PIO mode for device.
370 * None (inherited from caller).
373 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
375 unsigned int pio = adev->pio_mode - XFER_PIO_0;
378 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
382 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
387 /* Set the PIO timing registers using value table for 133MHz */
388 PDPRINTK("Set pio regs... \n");
390 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
392 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
393 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
394 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
396 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
398 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
399 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
401 PDPRINTK("Set pio regs done\n");
403 PDPRINTK("Set to pio mode[%u] \n", pio);
407 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
408 * @ap: Port to configure
410 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
412 * Set UDMA mode for device.
415 * None (inherited from caller).
417 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
419 unsigned int dma_mode = adev->dma_mode;
422 if ((dma_mode >= XFER_UDMA_0) &&
423 (dma_mode <= XFER_UDMA_6)) {
424 /* Set the UDMA timing registers with value table for 133MHz */
425 unsigned int udma_mode = dma_mode & 0x07;
427 if (dma_mode == XFER_UDMA_2) {
430 * If tHOLD is '1', the hardware will add half clock for data hold time.
431 * This code segment seems to be no effect. tHOLD will be overwritten below.
433 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
434 writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
437 PDPRINTK("Set udma regs... \n");
439 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
441 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
442 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
443 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
444 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
446 PDPRINTK("Set udma regs done\n");
448 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
450 } else if ((dma_mode >= XFER_MW_DMA_0) &&
451 (dma_mode <= XFER_MW_DMA_2)) {
452 /* Set the MDMA timing registers with value table for 133MHz */
453 unsigned int mdma_mode = dma_mode & 0x07;
455 PDPRINTK("Set mdma regs... \n");
456 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
459 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
460 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
462 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
463 PDPRINTK("Set mdma regs done\n");
465 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
467 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
472 * pdc2027x_set_mode - Set the timing registers back to correct values.
473 * @ap: Port to configure
474 * @r_failed: Returned device for failure
476 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
477 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
478 * This function overwrites the possibly incorrect values set by the hardware to be correct.
480 static int pdc2027x_set_mode(struct ata_port *ap, struct ata_device **r_failed)
482 struct ata_device *dev;
485 rc = ata_do_set_mode(ap, r_failed);
489 ata_link_for_each_dev(dev, &ap->link) {
490 if (ata_dev_enabled(dev)) {
492 pdc2027x_set_piomode(ap, dev);
495 * Enable prefetch if the device support PIO only.
497 if (dev->xfer_shift == ATA_SHIFT_PIO) {
498 u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1));
500 writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
502 PDPRINTK("Turn on prefetch\n");
504 pdc2027x_set_dmamode(ap, dev);
512 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
513 * @qc: Metadata associated with taskfile to check
516 * None (inherited from caller).
518 * RETURNS: 0 when ATAPI DMA can be used
521 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
523 struct scsi_cmnd *cmd = qc->scsicmd;
524 u8 *scsicmd = cmd->cmnd;
525 int rc = 1; /* atapi dma off by default */
528 * This workaround is from Promise's GPL driver.
529 * If ATAPI DMA is used for commands not in the
530 * following white list, say MODE_SENSE and REQUEST_SENSE,
531 * pdc2027x might hit the irq lost problem.
533 switch (scsicmd[0]) {
540 case 0xad: /* READ_DVD_STRUCTURE */
541 case 0xbe: /* READ_CD */
542 /* ATAPI DMA is ok */
553 * pdc_read_counter - Read the ctr counter
554 * @host: target ATA host
557 static long pdc_read_counter(struct ata_host *host)
559 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
562 u32 bccrl, bccrh, bccrlv, bccrhv;
565 bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
566 bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
569 /* Read the counter values again for verification */
570 bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
571 bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
574 counter = (bccrh << 15) | bccrl;
576 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
577 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
580 * The 30-bit decreasing counter are read by 2 pieces.
581 * Incorrect value may be read when both bccrh and bccrl are changing.
582 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
584 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
586 PDPRINTK("rereading counter\n");
594 * adjust_pll - Adjust the PLL input clock in Hz.
596 * @pdc_controller: controller specific information
597 * @host: target ATA host
598 * @pll_clock: The input of PLL in HZ
600 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
602 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
604 long pll_clock_khz = pll_clock / 1000;
605 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
606 long ratio = pout_required / pll_clock_khz;
610 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
611 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
616 PDPRINTK("pout_required is %ld\n", pout_required);
618 /* Show the current clock value of PLL control register
619 * (maybe already configured by the firmware)
621 pll_ctl = readw(mmio_base + PDC_PLL_CTL);
623 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
627 * Calculate the ratio of F, R and OD
628 * POUT = (F + 2) / (( R + 2) * NO)
630 if (ratio < 8600L) { /* 8.6x */
631 /* Using NO = 0x01, R = 0x0D */
633 } else if (ratio < 12900L) { /* 12.9x */
634 /* Using NO = 0x01, R = 0x08 */
636 } else if (ratio < 16100L) { /* 16.1x */
637 /* Using NO = 0x01, R = 0x06 */
639 } else if (ratio < 64000L) { /* 64x */
643 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
647 F = (ratio * (R+2)) / 1000 - 2;
649 if (unlikely(F < 0 || F > 127)) {
651 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
655 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
657 pll_ctl = (R << 8) | F;
659 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
661 writew(pll_ctl, mmio_base + PDC_PLL_CTL);
662 readw(mmio_base + PDC_PLL_CTL); /* flush */
664 /* Wait the PLL circuit to be stable */
669 * Show the current clock value of PLL control register
670 * (maybe configured by the firmware)
672 pll_ctl = readw(mmio_base + PDC_PLL_CTL);
674 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
681 * detect_pll_input_clock - Detect the PLL input clock in Hz.
682 * @host: target ATA host
683 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
684 * Half of the PCI clock.
686 static long pdc_detect_pll_input_clock(struct ata_host *host)
688 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
690 long start_count, end_count;
691 struct timeval start_time, end_time;
692 long pll_clock, usec_elapsed;
694 /* Start the test mode */
695 scr = readl(mmio_base + PDC_SYS_CTL);
696 PDPRINTK("scr[%X]\n", scr);
697 writel(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
698 readl(mmio_base + PDC_SYS_CTL); /* flush */
700 /* Read current counter value */
701 start_count = pdc_read_counter(host);
702 do_gettimeofday(&start_time);
704 /* Let the counter run for 100 ms. */
707 /* Read the counter values again */
708 end_count = pdc_read_counter(host);
709 do_gettimeofday(&end_time);
711 /* Stop the test mode */
712 scr = readl(mmio_base + PDC_SYS_CTL);
713 PDPRINTK("scr[%X]\n", scr);
714 writel(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
715 readl(mmio_base + PDC_SYS_CTL); /* flush */
717 /* calculate the input clock in Hz */
718 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
719 (end_time.tv_usec - start_time.tv_usec);
721 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
722 (100000000 / usec_elapsed);
724 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
725 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
731 * pdc_hardware_init - Initialize the hardware.
732 * @host: target ATA host
733 * @board_idx: board identifier
735 static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
740 * Detect PLL input clock rate.
741 * On some system, where PCI bus is running at non-standard clock rate.
742 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
743 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
745 pll_clock = pdc_detect_pll_input_clock(host);
747 if (pll_clock < 0) /* counter overflow? Try again. */
748 pll_clock = pdc_detect_pll_input_clock(host);
750 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
752 /* Adjust PLL control register */
753 pdc_adjust_pll(host, pll_clock, board_idx);
759 * pdc_ata_setup_port - setup the mmio address
760 * @port: ata ioports to setup
761 * @base: base address
763 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
766 port->data_addr = base;
768 port->error_addr = base + 0x05;
769 port->nsect_addr = base + 0x0a;
770 port->lbal_addr = base + 0x0f;
771 port->lbam_addr = base + 0x10;
772 port->lbah_addr = base + 0x15;
773 port->device_addr = base + 0x1a;
775 port->status_addr = base + 0x1f;
776 port->altstatus_addr =
777 port->ctl_addr = base + 0x81a;
781 * pdc2027x_init_one - PCI probe function
782 * Called when an instance of PCI adapter is inserted.
783 * This function checks whether the hardware is supported,
784 * initialize hardware and register an instance of ata_host to
785 * libata. (implements struct pci_driver.probe() )
787 * @pdev: instance of pci_dev found
788 * @ent: matching entry in the id_tbl[]
790 static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
792 static int printed_version;
793 unsigned int board_idx = (unsigned int) ent->driver_data;
794 const struct ata_port_info *ppi[] =
795 { &pdc2027x_port_info[board_idx], NULL };
796 struct ata_host *host;
797 void __iomem *mmio_base;
800 if (!printed_version++)
801 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
804 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
808 /* acquire resources and fill host */
809 rc = pcim_enable_device(pdev);
813 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
816 host->iomap = pcim_iomap_table(pdev);
818 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
822 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
826 mmio_base = host->iomap[PDC_MMIO_BAR];
828 pdc_ata_setup_port(&host->ports[0]->ioaddr, mmio_base + 0x17c0);
829 host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x1000;
830 pdc_ata_setup_port(&host->ports[1]->ioaddr, mmio_base + 0x15c0);
831 host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x1008;
833 //pci_enable_intx(pdev);
835 /* initialize adapter */
836 if (pdc_hardware_init(host, board_idx) != 0)
839 pci_set_master(pdev);
840 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
845 * pdc2027x_init - Called after this module is loaded into the kernel.
847 static int __init pdc2027x_init(void)
849 return pci_register_driver(&pdc2027x_pci_driver);
853 * pdc2027x_exit - Called before this module unloaded from the kernel
855 static void __exit pdc2027x_exit(void)
857 pci_unregister_driver(&pdc2027x_pci_driver);
860 module_init(pdc2027x_init);
861 module_exit(pdc2027x_exit);