2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
68 /* board IDs for specific chipsets in alphabetical order */
74 board_ahci_sb700, /* for SB700 and SB800 */
78 board_ahci_mcp_linux = board_ahci_mcp65,
79 board_ahci_mcp67 = board_ahci_mcp65,
80 board_ahci_mcp73 = board_ahci_mcp65,
81 board_ahci_mcp79 = board_ahci_mcp77,
84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
90 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
91 static int ahci_pci_device_resume(struct pci_dev *pdev);
94 static struct scsi_host_template ahci_sht = {
98 static struct ata_port_operations ahci_vt8251_ops = {
99 .inherits = &ahci_ops,
100 .hardreset = ahci_vt8251_hardreset,
103 static struct ata_port_operations ahci_p5wdh_ops = {
104 .inherits = &ahci_ops,
105 .hardreset = ahci_p5wdh_hardreset,
108 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
110 static const struct ata_port_info ahci_port_info[] = {
114 .flags = AHCI_FLAG_COMMON,
115 .pio_mask = ATA_PIO4,
116 .udma_mask = ATA_UDMA6,
117 .port_ops = &ahci_ops,
119 [board_ahci_ign_iferr] =
121 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
122 .flags = AHCI_FLAG_COMMON,
123 .pio_mask = ATA_PIO4,
124 .udma_mask = ATA_UDMA6,
125 .port_ops = &ahci_ops,
127 [board_ahci_noncq] = {
128 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
134 [board_ahci_nosntf] =
136 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
142 [board_ahci_yes_fbs] =
144 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
155 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_ops,
178 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
179 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
180 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_ops,
187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
188 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
189 AHCI_HFLAG_32BIT_ONLY),
190 .flags = AHCI_FLAG_COMMON,
191 .pio_mask = ATA_PIO4,
192 .udma_mask = ATA_UDMA6,
193 .port_ops = &ahci_pmp_retry_srst_ops,
195 [board_ahci_sb700] = /* for SB700 and SB800 */
197 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
198 .flags = AHCI_FLAG_COMMON,
199 .pio_mask = ATA_PIO4,
200 .udma_mask = ATA_UDMA6,
201 .port_ops = &ahci_pmp_retry_srst_ops,
203 [board_ahci_vt8251] =
205 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
206 .flags = AHCI_FLAG_COMMON,
207 .pio_mask = ATA_PIO4,
208 .udma_mask = ATA_UDMA6,
209 .port_ops = &ahci_vt8251_ops,
213 static const struct pci_device_id ahci_pci_tbl[] = {
215 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
216 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
217 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
218 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
219 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
220 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
221 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
223 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
224 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
225 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
227 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
228 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
229 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
230 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
234 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
235 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
239 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
240 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
241 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
242 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
243 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
244 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
245 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
246 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
247 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
248 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
249 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
250 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
251 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
252 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
253 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
254 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
256 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
257 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
259 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
260 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
261 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
262 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
263 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
264 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
265 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
266 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
267 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
268 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
269 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
270 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
271 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
272 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
274 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
275 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
277 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
278 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
279 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
280 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
281 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
282 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
283 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
285 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
286 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
287 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
288 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
289 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
290 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
291 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
293 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
294 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
295 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
298 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
299 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
301 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
302 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
303 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
304 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
305 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
306 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
307 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
308 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
309 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
310 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
311 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
312 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
313 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
314 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
315 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
316 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
317 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
319 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
320 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
321 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
324 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
325 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
326 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
327 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
328 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
329 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
330 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
333 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
334 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
335 /* AMD is using RAID class only for ahci controllers */
336 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
337 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
340 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
341 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
344 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
345 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
346 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
347 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
348 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
349 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
350 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
351 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
352 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
353 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
354 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
355 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
356 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
357 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
358 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
359 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
360 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
361 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
362 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
363 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
364 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
365 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
366 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
367 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
368 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
369 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
370 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
371 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
372 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
373 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
374 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
375 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
376 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
377 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
378 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
379 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
380 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
381 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
382 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
383 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
384 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
385 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
386 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
387 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
388 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
389 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
390 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
391 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
392 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
393 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
394 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
395 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
396 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
397 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
398 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
399 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
400 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
401 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
402 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
403 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
404 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
405 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
406 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
407 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
408 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
409 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
410 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
411 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
412 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
413 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
414 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
415 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
416 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
417 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
418 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
419 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
420 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
421 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
422 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
423 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
424 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
425 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
426 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
427 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
430 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
431 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
432 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
434 /* ST Microelectronics */
435 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
438 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
439 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
440 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
441 .class = PCI_CLASS_STORAGE_SATA_AHCI,
442 .class_mask = 0xffffff,
443 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
444 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
445 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
446 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
447 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
448 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
449 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
450 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
451 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
452 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
453 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
454 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
455 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
456 .driver_data = board_ahci_yes_fbs },
457 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
458 .driver_data = board_ahci_yes_fbs },
459 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
460 .driver_data = board_ahci_yes_fbs },
461 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
462 .driver_data = board_ahci_yes_fbs },
465 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
468 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
469 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
470 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
471 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
474 * Samsung SSDs found on some macbooks. NCQ times out.
475 * https://bugzilla.kernel.org/show_bug.cgi?id=60731
477 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_noncq },
480 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
482 /* Generic, PCI class code for AHCI */
483 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
484 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
486 { } /* terminate list */
490 static struct pci_driver ahci_pci_driver = {
492 .id_table = ahci_pci_tbl,
493 .probe = ahci_init_one,
494 .remove = ata_pci_remove_one,
496 .suspend = ahci_pci_device_suspend,
497 .resume = ahci_pci_device_resume,
501 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
502 static int marvell_enable;
504 static int marvell_enable = 1;
506 module_param(marvell_enable, int, 0644);
507 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
510 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
511 struct ahci_host_priv *hpriv)
513 unsigned int force_port_map = 0;
514 unsigned int mask_port_map = 0;
516 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
517 dev_info(&pdev->dev, "JMB361 has only one port\n");
522 * Temporary Marvell 6145 hack: PATA port presence
523 * is asserted through the standard AHCI port
524 * presence register, as bit 4 (counting from 0)
526 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
527 if (pdev->device == 0x6121)
532 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
535 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
539 static int ahci_pci_reset_controller(struct ata_host *host)
541 struct pci_dev *pdev = to_pci_dev(host->dev);
543 ahci_reset_controller(host);
545 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
546 struct ahci_host_priv *hpriv = host->private_data;
550 pci_read_config_word(pdev, 0x92, &tmp16);
551 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
552 tmp16 |= hpriv->port_map;
553 pci_write_config_word(pdev, 0x92, tmp16);
560 static void ahci_pci_init_controller(struct ata_host *host)
562 struct ahci_host_priv *hpriv = host->private_data;
563 struct pci_dev *pdev = to_pci_dev(host->dev);
564 void __iomem *port_mmio;
568 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
569 if (pdev->device == 0x6121)
573 port_mmio = __ahci_port_base(host, mv);
575 writel(0, port_mmio + PORT_IRQ_MASK);
578 tmp = readl(port_mmio + PORT_IRQ_STAT);
579 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
581 writel(tmp, port_mmio + PORT_IRQ_STAT);
584 ahci_init_controller(host);
587 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
588 unsigned long deadline)
590 struct ata_port *ap = link->ap;
596 ahci_stop_engine(ap);
598 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
599 deadline, &online, NULL);
601 ahci_start_engine(ap);
603 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
605 /* vt8251 doesn't clear BSY on signature FIS reception,
606 * request follow-up softreset.
608 return online ? -EAGAIN : rc;
611 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
612 unsigned long deadline)
614 struct ata_port *ap = link->ap;
615 struct ahci_port_priv *pp = ap->private_data;
616 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
617 struct ata_taskfile tf;
621 ahci_stop_engine(ap);
623 /* clear D2H reception area to properly wait for D2H FIS */
624 ata_tf_init(link->device, &tf);
626 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
628 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
629 deadline, &online, NULL);
631 ahci_start_engine(ap);
633 /* The pseudo configuration device on SIMG4726 attached to
634 * ASUS P5W-DH Deluxe doesn't send signature FIS after
635 * hardreset if no device is attached to the first downstream
636 * port && the pseudo device locks up on SRST w/ PMP==0. To
637 * work around this, wait for !BSY only briefly. If BSY isn't
638 * cleared, perform CLO and proceed to IDENTIFY (achieved by
639 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
641 * Wait for two seconds. Devices attached to downstream port
642 * which can't process the following IDENTIFY after this will
643 * have to be reset again. For most cases, this should
644 * suffice while making probing snappish enough.
647 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
650 ahci_kick_engine(ap);
656 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
658 struct ata_host *host = dev_get_drvdata(&pdev->dev);
659 struct ahci_host_priv *hpriv = host->private_data;
660 void __iomem *mmio = hpriv->mmio;
663 if (mesg.event & PM_EVENT_SUSPEND &&
664 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
666 "BIOS update required for suspend/resume\n");
670 if (mesg.event & PM_EVENT_SLEEP) {
671 /* AHCI spec rev1.1 section 8.3.3:
672 * Software must disable interrupts prior to requesting a
673 * transition of the HBA to D3 state.
675 ctl = readl(mmio + HOST_CTL);
677 writel(ctl, mmio + HOST_CTL);
678 readl(mmio + HOST_CTL); /* flush */
681 return ata_pci_device_suspend(pdev, mesg);
684 static int ahci_pci_device_resume(struct pci_dev *pdev)
686 struct ata_host *host = dev_get_drvdata(&pdev->dev);
689 rc = ata_pci_device_do_resume(pdev);
693 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
694 rc = ahci_pci_reset_controller(host);
698 ahci_pci_init_controller(host);
701 ata_host_resume(host);
707 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
712 * If the device fixup already set the dma_mask to some non-standard
713 * value, don't extend it here. This happens on STA2X11, for example.
715 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
719 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
720 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
722 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
725 "64-bit DMA enable failed\n");
730 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
732 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
735 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
738 "32-bit consistent DMA enable failed\n");
745 static void ahci_pci_print_info(struct ata_host *host)
747 struct pci_dev *pdev = to_pci_dev(host->dev);
751 pci_read_config_word(pdev, 0x0a, &cc);
752 if (cc == PCI_CLASS_STORAGE_IDE)
754 else if (cc == PCI_CLASS_STORAGE_SATA)
756 else if (cc == PCI_CLASS_STORAGE_RAID)
761 ahci_print_info(host, scc_s);
764 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
765 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
766 * support PMP and the 4726 either directly exports the device
767 * attached to the first downstream port or acts as a hardware storage
768 * controller and emulate a single ATA device (can be RAID 0/1 or some
769 * other configuration).
771 * When there's no device attached to the first downstream port of the
772 * 4726, "Config Disk" appears, which is a pseudo ATA device to
773 * configure the 4726. However, ATA emulation of the device is very
774 * lame. It doesn't send signature D2H Reg FIS after the initial
775 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
777 * The following function works around the problem by always using
778 * hardreset on the port and not depending on receiving signature FIS
779 * afterward. If signature FIS isn't received soon, ATA class is
780 * assumed without follow-up softreset.
782 static void ahci_p5wdh_workaround(struct ata_host *host)
784 static struct dmi_system_id sysids[] = {
786 .ident = "P5W DH Deluxe",
788 DMI_MATCH(DMI_SYS_VENDOR,
789 "ASUSTEK COMPUTER INC"),
790 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
795 struct pci_dev *pdev = to_pci_dev(host->dev);
797 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
798 dmi_check_system(sysids)) {
799 struct ata_port *ap = host->ports[1];
802 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
804 ap->ops = &ahci_p5wdh_ops;
805 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
809 /* only some SB600 ahci controllers can do 64bit DMA */
810 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
812 static const struct dmi_system_id sysids[] = {
814 * The oldest version known to be broken is 0901 and
815 * working is 1501 which was released on 2007-10-26.
816 * Enable 64bit DMA on 1501 and anything newer.
818 * Please read bko#9412 for more info.
821 .ident = "ASUS M2A-VM",
823 DMI_MATCH(DMI_BOARD_VENDOR,
824 "ASUSTeK Computer INC."),
825 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
827 .driver_data = "20071026", /* yyyymmdd */
830 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
833 * BIOS versions earlier than 1.5 had the Manufacturer DMI
834 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
835 * This spelling mistake was fixed in BIOS version 1.5, so
836 * 1.5 and later have the Manufacturer as
837 * "MICRO-STAR INTERNATIONAL CO.,LTD".
838 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
840 * BIOS versions earlier than 1.9 had a Board Product Name
841 * DMI field of "MS-7376". This was changed to be
842 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
843 * match on DMI_BOARD_NAME of "MS-7376".
846 .ident = "MSI K9A2 Platinum",
848 DMI_MATCH(DMI_BOARD_VENDOR,
850 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
854 * All BIOS versions for the Asus M3A support 64bit DMA.
855 * (all release versions from 0301 to 1206 were tested)
860 DMI_MATCH(DMI_BOARD_VENDOR,
861 "ASUSTeK Computer INC."),
862 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
867 const struct dmi_system_id *match;
868 int year, month, date;
871 match = dmi_first_match(sysids);
872 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
876 if (!match->driver_data)
879 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
880 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
882 if (strcmp(buf, match->driver_data) >= 0)
886 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
892 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
896 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
898 static const struct dmi_system_id broken_systems[] = {
900 .ident = "HP Compaq nx6310",
902 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
903 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
905 /* PCI slot number of the controller */
906 .driver_data = (void *)0x1FUL,
909 .ident = "HP Compaq 6720s",
911 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
912 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
914 /* PCI slot number of the controller */
915 .driver_data = (void *)0x1FUL,
918 { } /* terminate list */
920 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
923 unsigned long slot = (unsigned long)dmi->driver_data;
924 /* apply the quirk only to on-board controllers */
925 return slot == PCI_SLOT(pdev->devfn);
931 static bool ahci_broken_suspend(struct pci_dev *pdev)
933 static const struct dmi_system_id sysids[] = {
935 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
936 * to the harddisk doesn't become online after
937 * resuming from STR. Warn and fail suspend.
939 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
941 * Use dates instead of versions to match as HP is
942 * apparently recycling both product and version
945 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
950 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
951 DMI_MATCH(DMI_PRODUCT_NAME,
952 "HP Pavilion dv4 Notebook PC"),
954 .driver_data = "20090105", /* F.30 */
959 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
960 DMI_MATCH(DMI_PRODUCT_NAME,
961 "HP Pavilion dv5 Notebook PC"),
963 .driver_data = "20090506", /* F.16 */
968 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
969 DMI_MATCH(DMI_PRODUCT_NAME,
970 "HP Pavilion dv6 Notebook PC"),
972 .driver_data = "20090423", /* F.21 */
977 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
978 DMI_MATCH(DMI_PRODUCT_NAME,
979 "HP HDX18 Notebook PC"),
981 .driver_data = "20090430", /* F.23 */
984 * Acer eMachines G725 has the same problem. BIOS
985 * V1.03 is known to be broken. V3.04 is known to
986 * work. Between, there are V1.06, V2.06 and V3.03
987 * that we don't have much idea about. For now,
988 * blacklist anything older than V3.04.
990 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
995 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
996 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
998 .driver_data = "20091216", /* V3.04 */
1000 { } /* terminate list */
1002 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1003 int year, month, date;
1006 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1009 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1010 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1012 return strcmp(buf, dmi->driver_data) < 0;
1015 static bool ahci_broken_online(struct pci_dev *pdev)
1017 #define ENCODE_BUSDEVFN(bus, slot, func) \
1018 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1019 static const struct dmi_system_id sysids[] = {
1021 * There are several gigabyte boards which use
1022 * SIMG5723s configured as hardware RAID. Certain
1023 * 5723 firmware revisions shipped there keep the link
1024 * online but fail to answer properly to SRST or
1025 * IDENTIFY when no device is attached downstream
1026 * causing libata to retry quite a few times leading
1027 * to excessive detection delay.
1029 * As these firmwares respond to the second reset try
1030 * with invalid device signature, considering unknown
1031 * sig as offline works around the problem acceptably.
1034 .ident = "EP45-DQ6",
1036 DMI_MATCH(DMI_BOARD_VENDOR,
1037 "Gigabyte Technology Co., Ltd."),
1038 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1040 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1043 .ident = "EP45-DS5",
1045 DMI_MATCH(DMI_BOARD_VENDOR,
1046 "Gigabyte Technology Co., Ltd."),
1047 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1049 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1051 { } /* terminate list */
1053 #undef ENCODE_BUSDEVFN
1054 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1060 val = (unsigned long)dmi->driver_data;
1062 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1065 #ifdef CONFIG_ATA_ACPI
1066 static void ahci_gtf_filter_workaround(struct ata_host *host)
1068 static const struct dmi_system_id sysids[] = {
1070 * Aspire 3810T issues a bunch of SATA enable commands
1071 * via _GTF including an invalid one and one which is
1072 * rejected by the device. Among the successful ones
1073 * is FPDMA non-zero offset enable which when enabled
1074 * only on the drive side leads to NCQ command
1075 * failures. Filter it out.
1078 .ident = "Aspire 3810T",
1080 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1081 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1083 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1087 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1088 unsigned int filter;
1094 filter = (unsigned long)dmi->driver_data;
1095 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1096 filter, dmi->ident);
1098 for (i = 0; i < host->n_ports; i++) {
1099 struct ata_port *ap = host->ports[i];
1100 struct ata_link *link;
1101 struct ata_device *dev;
1103 ata_for_each_link(link, ap, EDGE)
1104 ata_for_each_dev(dev, link, ALL)
1105 dev->gtf_filter |= filter;
1109 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1113 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1115 unsigned int board_id = ent->driver_data;
1116 struct ata_port_info pi = ahci_port_info[board_id];
1117 const struct ata_port_info *ppi[] = { &pi, NULL };
1118 struct device *dev = &pdev->dev;
1119 struct ahci_host_priv *hpriv;
1120 struct ata_host *host;
1122 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1126 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1128 ata_print_version_once(&pdev->dev, DRV_VERSION);
1130 /* The AHCI driver can only drive the SATA ports, the PATA driver
1131 can drive them all so if both drivers are selected make sure
1132 AHCI stays out of the way */
1133 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1137 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1138 * ahci, use ata_generic instead.
1140 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1141 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1142 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1143 pdev->subsystem_device == 0xcb89)
1146 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1147 * At the moment, we can only use the AHCI mode. Let the users know
1148 * that for SAS drives they're out of luck.
1150 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1151 dev_info(&pdev->dev,
1152 "PDC42819 can only drive SATA devices with this driver\n");
1154 /* Both Connext and Enmotus devices use non-standard BARs */
1155 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1156 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1157 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1158 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1160 /* acquire resources */
1161 rc = pcim_enable_device(pdev);
1165 /* AHCI controllers often implement SFF compatible interface.
1166 * Grab all PCI BARs just in case.
1168 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1170 pcim_pin_device(pdev);
1174 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1175 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1178 /* ICH6s share the same PCI ID for both piix and ahci
1179 * modes. Enabling ahci mode while MAP indicates
1180 * combined mode is a bad idea. Yield to ata_piix.
1182 pci_read_config_byte(pdev, ICH_MAP, &map);
1184 dev_info(&pdev->dev,
1185 "controller is in combined mode, can't enable AHCI mode\n");
1190 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1193 hpriv->flags |= (unsigned long)pi.private_data;
1195 /* MCP65 revision A1 and A2 can't do MSI */
1196 if (board_id == board_ahci_mcp65 &&
1197 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1198 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1200 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1201 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1202 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1204 /* only some SB600s can do 64bit DMA */
1205 if (ahci_sb600_enable_64bit(pdev))
1206 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1208 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1211 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1213 /* save initial config */
1214 ahci_pci_save_initial_config(pdev, hpriv);
1217 if (hpriv->cap & HOST_CAP_NCQ) {
1218 pi.flags |= ATA_FLAG_NCQ;
1220 * Auto-activate optimization is supposed to be
1221 * supported on all AHCI controllers indicating NCQ
1222 * capability, but it seems to be broken on some
1223 * chipsets including NVIDIAs.
1225 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1226 pi.flags |= ATA_FLAG_FPDMA_AA;
1229 if (hpriv->cap & HOST_CAP_PMP)
1230 pi.flags |= ATA_FLAG_PMP;
1232 ahci_set_em_messages(hpriv, &pi);
1234 if (ahci_broken_system_poweroff(pdev)) {
1235 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1236 dev_info(&pdev->dev,
1237 "quirky BIOS, skipping spindown on poweroff\n");
1240 if (ahci_broken_suspend(pdev)) {
1241 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1242 dev_warn(&pdev->dev,
1243 "BIOS update required for suspend/resume\n");
1246 if (ahci_broken_online(pdev)) {
1247 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1248 dev_info(&pdev->dev,
1249 "online status unreliable, applying workaround\n");
1252 /* CAP.NP sometimes indicate the index of the last enabled
1253 * port, at other times, that of the last possible port, so
1254 * determining the maximum port number requires looking at
1255 * both CAP.NP and port_map.
1257 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1259 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1262 host->private_data = hpriv;
1264 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1265 host->flags |= ATA_HOST_PARALLEL_SCAN;
1267 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1269 if (pi.flags & ATA_FLAG_EM)
1270 ahci_reset_em(host);
1272 for (i = 0; i < host->n_ports; i++) {
1273 struct ata_port *ap = host->ports[i];
1275 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1276 ata_port_pbar_desc(ap, ahci_pci_bar,
1277 0x100 + ap->port_no * 0x80, "port");
1279 /* set enclosure management message type */
1280 if (ap->flags & ATA_FLAG_EM)
1281 ap->em_message_type = hpriv->em_msg_type;
1284 /* disabled/not-implemented port */
1285 if (!(hpriv->port_map & (1 << i)))
1286 ap->ops = &ata_dummy_port_ops;
1289 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1290 ahci_p5wdh_workaround(host);
1292 /* apply gtf filter quirk */
1293 ahci_gtf_filter_workaround(host);
1295 /* initialize adapter */
1296 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1300 rc = ahci_pci_reset_controller(host);
1304 ahci_pci_init_controller(host);
1305 ahci_pci_print_info(host);
1307 pci_set_master(pdev);
1308 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1312 static int __init ahci_init(void)
1314 return pci_register_driver(&ahci_pci_driver);
1317 static void __exit ahci_exit(void)
1319 pci_unregister_driver(&ahci_pci_driver);
1323 MODULE_AUTHOR("Jeff Garzik");
1324 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1325 MODULE_LICENSE("GPL");
1326 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1327 MODULE_VERSION(DRV_VERSION);
1329 module_init(ahci_init);
1330 module_exit(ahci_exit);