2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "ahci"
49 #define DRV_VERSION "2.1"
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
60 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_HDR_SZ = 0x80,
64 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
65 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
66 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
68 AHCI_IRQ_ON_SG = (1 << 31),
69 AHCI_CMD_ATAPI = (1 << 5),
70 AHCI_CMD_WRITE = (1 << 6),
71 AHCI_CMD_PREFETCH = (1 << 7),
72 AHCI_CMD_RESET = (1 << 8),
73 AHCI_CMD_CLR_BUSY = (1 << 10),
75 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
81 board_ahci_vt8251 = 2,
82 board_ahci_ign_iferr = 3,
84 /* global controller registers */
85 HOST_CAP = 0x00, /* host capabilities */
86 HOST_CTL = 0x04, /* global host control */
87 HOST_IRQ_STAT = 0x08, /* interrupt status */
88 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
89 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
92 HOST_RESET = (1 << 0), /* reset controller; self-clear */
93 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
94 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
97 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
98 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
99 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
100 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
101 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
103 /* registers for each SATA port */
104 PORT_LST_ADDR = 0x00, /* command list DMA addr */
105 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
106 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
107 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
108 PORT_IRQ_STAT = 0x10, /* interrupt status */
109 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
110 PORT_CMD = 0x18, /* port command */
111 PORT_TFDATA = 0x20, /* taskfile data */
112 PORT_SIG = 0x24, /* device TF signature */
113 PORT_CMD_ISSUE = 0x38, /* command issue */
114 PORT_SCR = 0x28, /* SATA phy register block */
115 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
116 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
117 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
118 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
120 /* PORT_IRQ_{STAT,MASK} bits */
121 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
122 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
123 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
124 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
125 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
126 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
127 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
128 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
130 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
131 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
132 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
133 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
134 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
135 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
136 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
137 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
138 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
140 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
145 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
147 PORT_IRQ_HBUS_DATA_ERR,
148 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
149 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
150 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
153 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
154 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
155 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
156 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
157 PORT_CMD_CLO = (1 << 3), /* Command list override */
158 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
159 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
160 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
162 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
163 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
164 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
165 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
168 AHCI_FLAG_NO_NCQ = (1 << 24),
169 AHCI_FLAG_IGN_IRQ_IF_ERR = (1 << 25), /* ignore IRQ_IF_ERR */
170 AHCI_FLAG_HONOR_PI = (1 << 26), /* honor PORTS_IMPL */
173 struct ahci_cmd_hdr {
188 struct ahci_host_priv {
189 u32 cap; /* cache of HOST_CAP register */
190 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
193 struct ahci_port_priv {
194 struct ahci_cmd_hdr *cmd_slot;
195 dma_addr_t cmd_slot_dma;
197 dma_addr_t cmd_tbl_dma;
199 dma_addr_t rx_fis_dma;
200 /* for NCQ spurious interrupt analysis */
201 unsigned int ncq_saw_d2h:1;
202 unsigned int ncq_saw_dmas:1;
203 unsigned int ncq_saw_sdb:1;
206 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
207 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
208 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
209 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
210 static irqreturn_t ahci_interrupt (int irq, void *dev_instance);
211 static void ahci_irq_clear(struct ata_port *ap);
212 static int ahci_port_start(struct ata_port *ap);
213 static void ahci_port_stop(struct ata_port *ap);
214 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
215 static void ahci_qc_prep(struct ata_queued_cmd *qc);
216 static u8 ahci_check_status(struct ata_port *ap);
217 static void ahci_freeze(struct ata_port *ap);
218 static void ahci_thaw(struct ata_port *ap);
219 static void ahci_error_handler(struct ata_port *ap);
220 static void ahci_vt8251_error_handler(struct ata_port *ap);
221 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
223 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
224 static int ahci_port_resume(struct ata_port *ap);
225 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
226 static int ahci_pci_device_resume(struct pci_dev *pdev);
229 static struct scsi_host_template ahci_sht = {
230 .module = THIS_MODULE,
232 .ioctl = ata_scsi_ioctl,
233 .queuecommand = ata_scsi_queuecmd,
234 .change_queue_depth = ata_scsi_change_queue_depth,
235 .can_queue = AHCI_MAX_CMDS - 1,
236 .this_id = ATA_SHT_THIS_ID,
237 .sg_tablesize = AHCI_MAX_SG,
238 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
239 .emulated = ATA_SHT_EMULATED,
240 .use_clustering = AHCI_USE_CLUSTERING,
241 .proc_name = DRV_NAME,
242 .dma_boundary = AHCI_DMA_BOUNDARY,
243 .slave_configure = ata_scsi_slave_config,
244 .slave_destroy = ata_scsi_slave_destroy,
245 .bios_param = ata_std_bios_param,
247 .suspend = ata_scsi_device_suspend,
248 .resume = ata_scsi_device_resume,
252 static const struct ata_port_operations ahci_ops = {
253 .port_disable = ata_port_disable,
255 .check_status = ahci_check_status,
256 .check_altstatus = ahci_check_status,
257 .dev_select = ata_noop_dev_select,
259 .tf_read = ahci_tf_read,
261 .qc_prep = ahci_qc_prep,
262 .qc_issue = ahci_qc_issue,
264 .irq_handler = ahci_interrupt,
265 .irq_clear = ahci_irq_clear,
266 .irq_on = ata_dummy_irq_on,
267 .irq_ack = ata_dummy_irq_ack,
269 .scr_read = ahci_scr_read,
270 .scr_write = ahci_scr_write,
272 .freeze = ahci_freeze,
275 .error_handler = ahci_error_handler,
276 .post_internal_cmd = ahci_post_internal_cmd,
279 .port_suspend = ahci_port_suspend,
280 .port_resume = ahci_port_resume,
283 .port_start = ahci_port_start,
284 .port_stop = ahci_port_stop,
287 static const struct ata_port_operations ahci_vt8251_ops = {
288 .port_disable = ata_port_disable,
290 .check_status = ahci_check_status,
291 .check_altstatus = ahci_check_status,
292 .dev_select = ata_noop_dev_select,
294 .tf_read = ahci_tf_read,
296 .qc_prep = ahci_qc_prep,
297 .qc_issue = ahci_qc_issue,
299 .irq_handler = ahci_interrupt,
300 .irq_clear = ahci_irq_clear,
301 .irq_on = ata_dummy_irq_on,
302 .irq_ack = ata_dummy_irq_ack,
304 .scr_read = ahci_scr_read,
305 .scr_write = ahci_scr_write,
307 .freeze = ahci_freeze,
310 .error_handler = ahci_vt8251_error_handler,
311 .post_internal_cmd = ahci_post_internal_cmd,
314 .port_suspend = ahci_port_suspend,
315 .port_resume = ahci_port_resume,
318 .port_start = ahci_port_start,
319 .port_stop = ahci_port_stop,
322 static const struct ata_port_info ahci_port_info[] = {
326 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
327 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
328 ATA_FLAG_SKIP_D2H_BSY,
329 .pio_mask = 0x1f, /* pio0-4 */
330 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
331 .port_ops = &ahci_ops,
336 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
337 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
338 ATA_FLAG_SKIP_D2H_BSY | AHCI_FLAG_HONOR_PI,
339 .pio_mask = 0x1f, /* pio0-4 */
340 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
341 .port_ops = &ahci_ops,
343 /* board_ahci_vt8251 */
346 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
347 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
348 ATA_FLAG_SKIP_D2H_BSY |
349 ATA_FLAG_HRST_TO_RESUME | AHCI_FLAG_NO_NCQ,
350 .pio_mask = 0x1f, /* pio0-4 */
351 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
352 .port_ops = &ahci_vt8251_ops,
354 /* board_ahci_ign_iferr */
357 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
358 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
359 ATA_FLAG_SKIP_D2H_BSY |
360 AHCI_FLAG_IGN_IRQ_IF_ERR,
361 .pio_mask = 0x1f, /* pio0-4 */
362 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
363 .port_ops = &ahci_ops,
367 static const struct pci_device_id ahci_pci_tbl[] = {
369 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
370 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
371 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
372 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
373 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
374 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
375 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
376 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
377 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
378 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
379 { PCI_VDEVICE(INTEL, 0x2821), board_ahci_pi }, /* ICH8 */
380 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_pi }, /* ICH8 */
381 { PCI_VDEVICE(INTEL, 0x2824), board_ahci_pi }, /* ICH8 */
382 { PCI_VDEVICE(INTEL, 0x2829), board_ahci_pi }, /* ICH8M */
383 { PCI_VDEVICE(INTEL, 0x282a), board_ahci_pi }, /* ICH8M */
384 { PCI_VDEVICE(INTEL, 0x2922), board_ahci_pi }, /* ICH9 */
385 { PCI_VDEVICE(INTEL, 0x2923), board_ahci_pi }, /* ICH9 */
386 { PCI_VDEVICE(INTEL, 0x2924), board_ahci_pi }, /* ICH9 */
387 { PCI_VDEVICE(INTEL, 0x2925), board_ahci_pi }, /* ICH9 */
388 { PCI_VDEVICE(INTEL, 0x2927), board_ahci_pi }, /* ICH9 */
389 { PCI_VDEVICE(INTEL, 0x2929), board_ahci_pi }, /* ICH9M */
390 { PCI_VDEVICE(INTEL, 0x292a), board_ahci_pi }, /* ICH9M */
391 { PCI_VDEVICE(INTEL, 0x292b), board_ahci_pi }, /* ICH9M */
392 { PCI_VDEVICE(INTEL, 0x292f), board_ahci_pi }, /* ICH9M */
393 { PCI_VDEVICE(INTEL, 0x294d), board_ahci_pi }, /* ICH9 */
394 { PCI_VDEVICE(INTEL, 0x294e), board_ahci_pi }, /* ICH9M */
396 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
397 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
398 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
401 { PCI_VDEVICE(ATI, 0x4380), board_ahci }, /* ATI SB600 non-raid */
402 { PCI_VDEVICE(ATI, 0x4381), board_ahci }, /* ATI SB600 raid */
405 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
408 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
409 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
410 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
411 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
412 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
413 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
414 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
415 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
416 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
417 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
418 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
419 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
420 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
421 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
422 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
423 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
424 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
425 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
426 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
430 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
431 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
432 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
434 /* Generic, PCI class code for AHCI */
435 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
436 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
438 { } /* terminate list */
442 static struct pci_driver ahci_pci_driver = {
444 .id_table = ahci_pci_tbl,
445 .probe = ahci_init_one,
446 .remove = ata_pci_remove_one,
448 .suspend = ahci_pci_device_suspend,
449 .resume = ahci_pci_device_resume,
454 static inline int ahci_nr_ports(u32 cap)
456 return (cap & 0x1f) + 1;
459 static inline void __iomem *ahci_port_base(void __iomem *base,
462 return base + 0x100 + (port * 0x80);
465 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
470 case SCR_STATUS: sc_reg = 0; break;
471 case SCR_CONTROL: sc_reg = 1; break;
472 case SCR_ERROR: sc_reg = 2; break;
473 case SCR_ACTIVE: sc_reg = 3; break;
478 return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
482 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
488 case SCR_STATUS: sc_reg = 0; break;
489 case SCR_CONTROL: sc_reg = 1; break;
490 case SCR_ERROR: sc_reg = 2; break;
491 case SCR_ACTIVE: sc_reg = 3; break;
496 writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
499 static void ahci_start_engine(void __iomem *port_mmio)
504 tmp = readl(port_mmio + PORT_CMD);
505 tmp |= PORT_CMD_START;
506 writel(tmp, port_mmio + PORT_CMD);
507 readl(port_mmio + PORT_CMD); /* flush */
510 static int ahci_stop_engine(void __iomem *port_mmio)
514 tmp = readl(port_mmio + PORT_CMD);
516 /* check if the HBA is idle */
517 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
520 /* setting HBA to idle */
521 tmp &= ~PORT_CMD_START;
522 writel(tmp, port_mmio + PORT_CMD);
524 /* wait for engine to stop. This could be as long as 500 msec */
525 tmp = ata_wait_register(port_mmio + PORT_CMD,
526 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
527 if (tmp & PORT_CMD_LIST_ON)
533 static void ahci_start_fis_rx(void __iomem *port_mmio, u32 cap,
534 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
538 /* set FIS registers */
539 if (cap & HOST_CAP_64)
540 writel((cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
541 writel(cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
543 if (cap & HOST_CAP_64)
544 writel((rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
545 writel(rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
547 /* enable FIS reception */
548 tmp = readl(port_mmio + PORT_CMD);
549 tmp |= PORT_CMD_FIS_RX;
550 writel(tmp, port_mmio + PORT_CMD);
553 readl(port_mmio + PORT_CMD);
556 static int ahci_stop_fis_rx(void __iomem *port_mmio)
560 /* disable FIS reception */
561 tmp = readl(port_mmio + PORT_CMD);
562 tmp &= ~PORT_CMD_FIS_RX;
563 writel(tmp, port_mmio + PORT_CMD);
565 /* wait for completion, spec says 500ms, give it 1000 */
566 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
567 PORT_CMD_FIS_ON, 10, 1000);
568 if (tmp & PORT_CMD_FIS_ON)
574 static void ahci_power_up(void __iomem *port_mmio, u32 cap)
578 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
581 if (cap & HOST_CAP_SSS) {
582 cmd |= PORT_CMD_SPIN_UP;
583 writel(cmd, port_mmio + PORT_CMD);
587 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
591 static void ahci_power_down(void __iomem *port_mmio, u32 cap)
595 if (!(cap & HOST_CAP_SSS))
598 /* put device into listen mode, first set PxSCTL.DET to 0 */
599 scontrol = readl(port_mmio + PORT_SCR_CTL);
601 writel(scontrol, port_mmio + PORT_SCR_CTL);
603 /* then set PxCMD.SUD to 0 */
604 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
605 cmd &= ~PORT_CMD_SPIN_UP;
606 writel(cmd, port_mmio + PORT_CMD);
610 static void ahci_init_port(void __iomem *port_mmio, u32 cap,
611 dma_addr_t cmd_slot_dma, dma_addr_t rx_fis_dma)
613 /* enable FIS reception */
614 ahci_start_fis_rx(port_mmio, cap, cmd_slot_dma, rx_fis_dma);
617 ahci_start_engine(port_mmio);
620 static int ahci_deinit_port(void __iomem *port_mmio, u32 cap, const char **emsg)
625 rc = ahci_stop_engine(port_mmio);
627 *emsg = "failed to stop engine";
631 /* disable FIS reception */
632 rc = ahci_stop_fis_rx(port_mmio);
634 *emsg = "failed stop FIS RX";
641 static int ahci_reset_controller(void __iomem *mmio, struct pci_dev *pdev)
643 u32 cap_save, impl_save, tmp;
645 cap_save = readl(mmio + HOST_CAP);
646 impl_save = readl(mmio + HOST_PORTS_IMPL);
648 /* global controller reset */
649 tmp = readl(mmio + HOST_CTL);
650 if ((tmp & HOST_RESET) == 0) {
651 writel(tmp | HOST_RESET, mmio + HOST_CTL);
652 readl(mmio + HOST_CTL); /* flush */
655 /* reset must complete within 1 second, or
656 * the hardware should be considered fried.
660 tmp = readl(mmio + HOST_CTL);
661 if (tmp & HOST_RESET) {
662 dev_printk(KERN_ERR, &pdev->dev,
663 "controller reset failed (0x%x)\n", tmp);
667 /* turn on AHCI mode */
668 writel(HOST_AHCI_EN, mmio + HOST_CTL);
669 (void) readl(mmio + HOST_CTL); /* flush */
671 /* These write-once registers are normally cleared on reset.
672 * Restore BIOS values... which we HOPE were present before
676 impl_save = (1 << ahci_nr_ports(cap_save)) - 1;
677 dev_printk(KERN_WARNING, &pdev->dev,
678 "PORTS_IMPL is zero, forcing 0x%x\n", impl_save);
680 writel(cap_save, mmio + HOST_CAP);
681 writel(impl_save, mmio + HOST_PORTS_IMPL);
682 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
684 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
688 pci_read_config_word(pdev, 0x92, &tmp16);
690 pci_write_config_word(pdev, 0x92, tmp16);
696 static void ahci_init_controller(void __iomem *mmio, struct pci_dev *pdev,
697 int n_ports, unsigned int port_flags,
698 struct ahci_host_priv *hpriv)
703 for (i = 0; i < n_ports; i++) {
704 void __iomem *port_mmio = ahci_port_base(mmio, i);
705 const char *emsg = NULL;
707 if ((port_flags & AHCI_FLAG_HONOR_PI) &&
708 !(hpriv->port_map & (1 << i)))
711 /* make sure port is not active */
712 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
714 dev_printk(KERN_WARNING, &pdev->dev,
715 "%s (%d)\n", emsg, rc);
718 tmp = readl(port_mmio + PORT_SCR_ERR);
719 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
720 writel(tmp, port_mmio + PORT_SCR_ERR);
723 tmp = readl(port_mmio + PORT_IRQ_STAT);
724 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
726 writel(tmp, port_mmio + PORT_IRQ_STAT);
728 writel(1 << i, mmio + HOST_IRQ_STAT);
731 tmp = readl(mmio + HOST_CTL);
732 VPRINTK("HOST_CTL 0x%x\n", tmp);
733 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
734 tmp = readl(mmio + HOST_CTL);
735 VPRINTK("HOST_CTL 0x%x\n", tmp);
738 static unsigned int ahci_dev_classify(struct ata_port *ap)
740 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
741 struct ata_taskfile tf;
744 tmp = readl(port_mmio + PORT_SIG);
745 tf.lbah = (tmp >> 24) & 0xff;
746 tf.lbam = (tmp >> 16) & 0xff;
747 tf.lbal = (tmp >> 8) & 0xff;
748 tf.nsect = (tmp) & 0xff;
750 return ata_dev_classify(&tf);
753 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
756 dma_addr_t cmd_tbl_dma;
758 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
760 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
761 pp->cmd_slot[tag].status = 0;
762 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
763 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
766 static int ahci_clo(struct ata_port *ap)
768 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
769 struct ahci_host_priv *hpriv = ap->host->private_data;
772 if (!(hpriv->cap & HOST_CAP_CLO))
775 tmp = readl(port_mmio + PORT_CMD);
777 writel(tmp, port_mmio + PORT_CMD);
779 tmp = ata_wait_register(port_mmio + PORT_CMD,
780 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
781 if (tmp & PORT_CMD_CLO)
787 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
789 struct ahci_port_priv *pp = ap->private_data;
790 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
791 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
792 const u32 cmd_fis_len = 5; /* five dwords */
793 const char *reason = NULL;
794 struct ata_taskfile tf;
801 if (ata_port_offline(ap)) {
802 DPRINTK("PHY reports no device\n");
803 *class = ATA_DEV_NONE;
807 /* prepare for SRST (AHCI-1.1 10.4.1) */
808 rc = ahci_stop_engine(port_mmio);
810 reason = "failed to stop engine";
814 /* check BUSY/DRQ, perform Command List Override if necessary */
815 if (ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ)) {
818 if (rc == -EOPNOTSUPP) {
819 reason = "port busy but CLO unavailable";
822 reason = "port busy but CLO failed";
828 ahci_start_engine(port_mmio);
830 ata_tf_init(ap->device, &tf);
833 /* issue the first D2H Register FIS */
834 ahci_fill_cmd_slot(pp, 0,
835 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
838 ata_tf_to_fis(&tf, fis, 0);
839 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
841 writel(1, port_mmio + PORT_CMD_ISSUE);
843 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
846 reason = "1st FIS failed";
850 /* spec says at least 5us, but be generous and sleep for 1ms */
853 /* issue the second D2H Register FIS */
854 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
857 ata_tf_to_fis(&tf, fis, 0);
858 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
860 writel(1, port_mmio + PORT_CMD_ISSUE);
861 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
863 /* spec mandates ">= 2ms" before checking status.
864 * We wait 150ms, because that was the magic delay used for
865 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
866 * between when the ATA command register is written, and then
867 * status is checked. Because waiting for "a while" before
868 * checking status is fine, post SRST, we perform this magic
869 * delay here as well.
873 *class = ATA_DEV_NONE;
874 if (ata_port_online(ap)) {
875 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
877 reason = "device not ready";
880 *class = ahci_dev_classify(ap);
883 DPRINTK("EXIT, class=%u\n", *class);
887 ahci_start_engine(port_mmio);
889 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
893 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
895 struct ahci_port_priv *pp = ap->private_data;
896 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
897 struct ata_taskfile tf;
898 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
899 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
904 ahci_stop_engine(port_mmio);
906 /* clear D2H reception area to properly wait for D2H FIS */
907 ata_tf_init(ap->device, &tf);
909 ata_tf_to_fis(&tf, d2h_fis, 0);
911 rc = sata_std_hardreset(ap, class);
913 ahci_start_engine(port_mmio);
915 if (rc == 0 && ata_port_online(ap))
916 *class = ahci_dev_classify(ap);
917 if (*class == ATA_DEV_UNKNOWN)
918 *class = ATA_DEV_NONE;
920 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
924 static int ahci_vt8251_hardreset(struct ata_port *ap, unsigned int *class)
926 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
927 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
932 ahci_stop_engine(port_mmio);
934 rc = sata_port_hardreset(ap, sata_ehc_deb_timing(&ap->eh_context));
936 /* vt8251 needs SError cleared for the port to operate */
937 ahci_scr_write(ap, SCR_ERROR, ahci_scr_read(ap, SCR_ERROR));
939 ahci_start_engine(port_mmio);
941 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
943 /* vt8251 doesn't clear BSY on signature FIS reception,
944 * request follow-up softreset.
946 return rc ?: -EAGAIN;
949 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
951 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
954 ata_std_postreset(ap, class);
956 /* Make sure port's ATAPI bit is set appropriately */
957 new_tmp = tmp = readl(port_mmio + PORT_CMD);
958 if (*class == ATA_DEV_ATAPI)
959 new_tmp |= PORT_CMD_ATAPI;
961 new_tmp &= ~PORT_CMD_ATAPI;
962 if (new_tmp != tmp) {
963 writel(new_tmp, port_mmio + PORT_CMD);
964 readl(port_mmio + PORT_CMD); /* flush */
968 static u8 ahci_check_status(struct ata_port *ap)
970 void __iomem *mmio = ap->ioaddr.cmd_addr;
972 return readl(mmio + PORT_TFDATA) & 0xFF;
975 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
977 struct ahci_port_priv *pp = ap->private_data;
978 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
980 ata_tf_from_fis(d2h_fis, tf);
983 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
985 struct scatterlist *sg;
986 struct ahci_sg *ahci_sg;
987 unsigned int n_sg = 0;
992 * Next, the S/G list.
994 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
995 ata_for_each_sg(sg, qc) {
996 dma_addr_t addr = sg_dma_address(sg);
997 u32 sg_len = sg_dma_len(sg);
999 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
1000 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
1001 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
1010 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1012 struct ata_port *ap = qc->ap;
1013 struct ahci_port_priv *pp = ap->private_data;
1014 int is_atapi = is_atapi_taskfile(&qc->tf);
1017 const u32 cmd_fis_len = 5; /* five dwords */
1018 unsigned int n_elem;
1021 * Fill in command table information. First, the header,
1022 * a SATA Register - Host to Device command FIS.
1024 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1026 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
1028 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1029 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1033 if (qc->flags & ATA_QCFLAG_DMAMAP)
1034 n_elem = ahci_fill_sg(qc, cmd_tbl);
1037 * Fill in command slot information.
1039 opts = cmd_fis_len | n_elem << 16;
1040 if (qc->tf.flags & ATA_TFLAG_WRITE)
1041 opts |= AHCI_CMD_WRITE;
1043 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1045 ahci_fill_cmd_slot(pp, qc->tag, opts);
1048 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1050 struct ahci_port_priv *pp = ap->private_data;
1051 struct ata_eh_info *ehi = &ap->eh_info;
1052 unsigned int err_mask = 0, action = 0;
1053 struct ata_queued_cmd *qc;
1056 ata_ehi_clear_desc(ehi);
1058 /* AHCI needs SError cleared; otherwise, it might lock up */
1059 serror = ahci_scr_read(ap, SCR_ERROR);
1060 ahci_scr_write(ap, SCR_ERROR, serror);
1062 /* analyze @irq_stat */
1063 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
1065 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1066 if (ap->flags & AHCI_FLAG_IGN_IRQ_IF_ERR)
1067 irq_stat &= ~PORT_IRQ_IF_ERR;
1069 if (irq_stat & PORT_IRQ_TF_ERR)
1070 err_mask |= AC_ERR_DEV;
1072 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1073 err_mask |= AC_ERR_HOST_BUS;
1074 action |= ATA_EH_SOFTRESET;
1077 if (irq_stat & PORT_IRQ_IF_ERR) {
1078 err_mask |= AC_ERR_ATA_BUS;
1079 action |= ATA_EH_SOFTRESET;
1080 ata_ehi_push_desc(ehi, ", interface fatal error");
1083 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1084 ata_ehi_hotplugged(ehi);
1085 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
1086 "connection status changed" : "PHY RDY changed");
1089 if (irq_stat & PORT_IRQ_UNK_FIS) {
1090 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1092 err_mask |= AC_ERR_HSM;
1093 action |= ATA_EH_SOFTRESET;
1094 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
1095 unk[0], unk[1], unk[2], unk[3]);
1098 /* okay, let's hand over to EH */
1099 ehi->serror |= serror;
1100 ehi->action |= action;
1102 qc = ata_qc_from_tag(ap, ap->active_tag);
1104 qc->err_mask |= err_mask;
1106 ehi->err_mask |= err_mask;
1108 if (irq_stat & PORT_IRQ_FREEZE)
1109 ata_port_freeze(ap);
1114 static void ahci_host_intr(struct ata_port *ap)
1116 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1117 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1118 struct ata_eh_info *ehi = &ap->eh_info;
1119 struct ahci_port_priv *pp = ap->private_data;
1120 u32 status, qc_active;
1121 int rc, known_irq = 0;
1123 status = readl(port_mmio + PORT_IRQ_STAT);
1124 writel(status, port_mmio + PORT_IRQ_STAT);
1126 if (unlikely(status & PORT_IRQ_ERROR)) {
1127 ahci_error_intr(ap, status);
1132 qc_active = readl(port_mmio + PORT_SCR_ACT);
1134 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1136 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
1140 ehi->err_mask |= AC_ERR_HSM;
1141 ehi->action |= ATA_EH_SOFTRESET;
1142 ata_port_freeze(ap);
1146 /* hmmm... a spurious interupt */
1148 /* if !NCQ, ignore. No modern ATA device has broken HSM
1149 * implementation for non-NCQ commands.
1154 if (status & PORT_IRQ_D2H_REG_FIS) {
1155 if (!pp->ncq_saw_d2h)
1156 ata_port_printk(ap, KERN_INFO,
1157 "D2H reg with I during NCQ, "
1158 "this message won't be printed again\n");
1159 pp->ncq_saw_d2h = 1;
1163 if (status & PORT_IRQ_DMAS_FIS) {
1164 if (!pp->ncq_saw_dmas)
1165 ata_port_printk(ap, KERN_INFO,
1166 "DMAS FIS during NCQ, "
1167 "this message won't be printed again\n");
1168 pp->ncq_saw_dmas = 1;
1172 if (status & PORT_IRQ_SDB_FIS) {
1173 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1175 if (le32_to_cpu(f[1])) {
1176 /* SDB FIS containing spurious completions
1177 * might be dangerous, whine and fail commands
1178 * with HSM violation. EH will turn off NCQ
1179 * after several such failures.
1181 ata_ehi_push_desc(ehi,
1182 "spurious completions during NCQ "
1183 "issue=0x%x SAct=0x%x FIS=%08x:%08x",
1184 readl(port_mmio + PORT_CMD_ISSUE),
1185 readl(port_mmio + PORT_SCR_ACT),
1186 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1187 ehi->err_mask |= AC_ERR_HSM;
1188 ehi->action |= ATA_EH_SOFTRESET;
1189 ata_port_freeze(ap);
1191 if (!pp->ncq_saw_sdb)
1192 ata_port_printk(ap, KERN_INFO,
1193 "spurious SDB FIS %08x:%08x during NCQ, "
1194 "this message won't be printed again\n",
1195 le32_to_cpu(f[0]), le32_to_cpu(f[1]));
1196 pp->ncq_saw_sdb = 1;
1202 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
1203 "(irq_stat 0x%x active_tag 0x%x sactive 0x%x)\n",
1204 status, ap->active_tag, ap->sactive);
1207 static void ahci_irq_clear(struct ata_port *ap)
1212 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1214 struct ata_host *host = dev_instance;
1215 struct ahci_host_priv *hpriv;
1216 unsigned int i, handled = 0;
1218 u32 irq_stat, irq_ack = 0;
1222 hpriv = host->private_data;
1223 mmio = host->iomap[AHCI_PCI_BAR];
1225 /* sigh. 0xffffffff is a valid return from h/w */
1226 irq_stat = readl(mmio + HOST_IRQ_STAT);
1227 irq_stat &= hpriv->port_map;
1231 spin_lock(&host->lock);
1233 for (i = 0; i < host->n_ports; i++) {
1234 struct ata_port *ap;
1236 if (!(irq_stat & (1 << i)))
1239 ap = host->ports[i];
1242 VPRINTK("port %u\n", i);
1244 VPRINTK("port %u (no irq)\n", i);
1245 if (ata_ratelimit())
1246 dev_printk(KERN_WARNING, host->dev,
1247 "interrupt on disabled port %u\n", i);
1250 irq_ack |= (1 << i);
1254 writel(irq_ack, mmio + HOST_IRQ_STAT);
1258 spin_unlock(&host->lock);
1262 return IRQ_RETVAL(handled);
1265 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1267 struct ata_port *ap = qc->ap;
1268 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
1270 if (qc->tf.protocol == ATA_PROT_NCQ)
1271 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1272 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1273 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1278 static void ahci_freeze(struct ata_port *ap)
1280 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1281 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1284 writel(0, port_mmio + PORT_IRQ_MASK);
1287 static void ahci_thaw(struct ata_port *ap)
1289 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1290 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1294 tmp = readl(port_mmio + PORT_IRQ_STAT);
1295 writel(tmp, port_mmio + PORT_IRQ_STAT);
1296 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1298 /* turn IRQ back on */
1299 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
1302 static void ahci_error_handler(struct ata_port *ap)
1304 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1305 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1307 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1308 /* restart engine */
1309 ahci_stop_engine(port_mmio);
1310 ahci_start_engine(port_mmio);
1313 /* perform recovery */
1314 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_hardreset,
1318 static void ahci_vt8251_error_handler(struct ata_port *ap)
1320 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1321 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1323 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1324 /* restart engine */
1325 ahci_stop_engine(port_mmio);
1326 ahci_start_engine(port_mmio);
1329 /* perform recovery */
1330 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1334 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1336 struct ata_port *ap = qc->ap;
1337 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1338 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1340 if (qc->flags & ATA_QCFLAG_FAILED)
1341 qc->err_mask |= AC_ERR_OTHER;
1344 /* make DMA engine forget about the failed command */
1345 ahci_stop_engine(port_mmio);
1346 ahci_start_engine(port_mmio);
1351 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1353 struct ahci_host_priv *hpriv = ap->host->private_data;
1354 struct ahci_port_priv *pp = ap->private_data;
1355 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1356 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1357 const char *emsg = NULL;
1360 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1362 ahci_power_down(port_mmio, hpriv->cap);
1364 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
1365 ahci_init_port(port_mmio, hpriv->cap,
1366 pp->cmd_slot_dma, pp->rx_fis_dma);
1372 static int ahci_port_resume(struct ata_port *ap)
1374 struct ahci_port_priv *pp = ap->private_data;
1375 struct ahci_host_priv *hpriv = ap->host->private_data;
1376 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1377 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1379 ahci_power_up(port_mmio, hpriv->cap);
1380 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1385 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1387 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1388 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1391 if (mesg.event == PM_EVENT_SUSPEND) {
1392 /* AHCI spec rev1.1 section 8.3.3:
1393 * Software must disable interrupts prior to requesting a
1394 * transition of the HBA to D3 state.
1396 ctl = readl(mmio + HOST_CTL);
1397 ctl &= ~HOST_IRQ_EN;
1398 writel(ctl, mmio + HOST_CTL);
1399 readl(mmio + HOST_CTL); /* flush */
1402 return ata_pci_device_suspend(pdev, mesg);
1405 static int ahci_pci_device_resume(struct pci_dev *pdev)
1407 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1408 struct ahci_host_priv *hpriv = host->private_data;
1409 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1412 rc = ata_pci_device_do_resume(pdev);
1416 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
1417 rc = ahci_reset_controller(mmio, pdev);
1421 ahci_init_controller(mmio, pdev, host->n_ports,
1422 host->ports[0]->flags, hpriv);
1425 ata_host_resume(host);
1431 static int ahci_port_start(struct ata_port *ap)
1433 struct device *dev = ap->host->dev;
1434 struct ahci_host_priv *hpriv = ap->host->private_data;
1435 struct ahci_port_priv *pp;
1436 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1437 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1442 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1446 rc = ata_pad_alloc(ap, dev);
1450 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1454 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1457 * First item in chunk of DMA memory: 32-slot command table,
1458 * 32 bytes each in size
1461 pp->cmd_slot_dma = mem_dma;
1463 mem += AHCI_CMD_SLOT_SZ;
1464 mem_dma += AHCI_CMD_SLOT_SZ;
1467 * Second item: Received-FIS area
1470 pp->rx_fis_dma = mem_dma;
1472 mem += AHCI_RX_FIS_SZ;
1473 mem_dma += AHCI_RX_FIS_SZ;
1476 * Third item: data area for storing a single command
1477 * and its scatter-gather table
1480 pp->cmd_tbl_dma = mem_dma;
1482 ap->private_data = pp;
1485 ahci_power_up(port_mmio, hpriv->cap);
1487 /* initialize port */
1488 ahci_init_port(port_mmio, hpriv->cap, pp->cmd_slot_dma, pp->rx_fis_dma);
1493 static void ahci_port_stop(struct ata_port *ap)
1495 struct ahci_host_priv *hpriv = ap->host->private_data;
1496 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1497 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1498 const char *emsg = NULL;
1501 /* de-initialize port */
1502 rc = ahci_deinit_port(port_mmio, hpriv->cap, &emsg);
1504 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
1507 static void ahci_setup_port(struct ata_ioports *port, void __iomem *base,
1508 unsigned int port_idx)
1510 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1511 base = ahci_port_base(base, port_idx);
1512 VPRINTK("base now==0x%lx\n", base);
1514 port->cmd_addr = base;
1515 port->scr_addr = base + PORT_SCR;
1520 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1522 struct ahci_host_priv *hpriv = probe_ent->private_data;
1523 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1524 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1525 unsigned int i, cap_n_ports, using_dac;
1528 rc = ahci_reset_controller(mmio, pdev);
1532 hpriv->cap = readl(mmio + HOST_CAP);
1533 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1534 cap_n_ports = ahci_nr_ports(hpriv->cap);
1536 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1537 hpriv->cap, hpriv->port_map, cap_n_ports);
1539 if (probe_ent->port_flags & AHCI_FLAG_HONOR_PI) {
1540 unsigned int n_ports = cap_n_ports;
1541 u32 port_map = hpriv->port_map;
1544 for (i = 0; i < AHCI_MAX_PORTS && n_ports; i++) {
1545 if (port_map & (1 << i)) {
1547 port_map &= ~(1 << i);
1550 probe_ent->dummy_port_mask |= 1 << i;
1553 if (n_ports || port_map)
1554 dev_printk(KERN_WARNING, &pdev->dev,
1555 "nr_ports (%u) and implemented port map "
1556 "(0x%x) don't match\n",
1557 cap_n_ports, hpriv->port_map);
1559 probe_ent->n_ports = max_port + 1;
1561 probe_ent->n_ports = cap_n_ports;
1563 using_dac = hpriv->cap & HOST_CAP_64;
1565 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1566 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1568 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1570 dev_printk(KERN_ERR, &pdev->dev,
1571 "64-bit DMA enable failed\n");
1576 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1578 dev_printk(KERN_ERR, &pdev->dev,
1579 "32-bit DMA enable failed\n");
1582 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1584 dev_printk(KERN_ERR, &pdev->dev,
1585 "32-bit consistent DMA enable failed\n");
1590 for (i = 0; i < probe_ent->n_ports; i++)
1591 ahci_setup_port(&probe_ent->port[i], mmio, i);
1593 ahci_init_controller(mmio, pdev, probe_ent->n_ports,
1594 probe_ent->port_flags, hpriv);
1596 pci_set_master(pdev);
1601 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1603 struct ahci_host_priv *hpriv = probe_ent->private_data;
1604 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1605 void __iomem *mmio = probe_ent->iomap[AHCI_PCI_BAR];
1606 u32 vers, cap, impl, speed;
1607 const char *speed_s;
1611 vers = readl(mmio + HOST_VERSION);
1613 impl = hpriv->port_map;
1615 speed = (cap >> 20) & 0xf;
1618 else if (speed == 2)
1623 pci_read_config_word(pdev, 0x0a, &cc);
1624 if (cc == PCI_CLASS_STORAGE_IDE)
1626 else if (cc == PCI_CLASS_STORAGE_SATA)
1628 else if (cc == PCI_CLASS_STORAGE_RAID)
1633 dev_printk(KERN_INFO, &pdev->dev,
1634 "AHCI %02x%02x.%02x%02x "
1635 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1638 (vers >> 24) & 0xff,
1639 (vers >> 16) & 0xff,
1643 ((cap >> 8) & 0x1f) + 1,
1649 dev_printk(KERN_INFO, &pdev->dev,
1655 cap & (1 << 31) ? "64bit " : "",
1656 cap & (1 << 30) ? "ncq " : "",
1657 cap & (1 << 28) ? "ilck " : "",
1658 cap & (1 << 27) ? "stag " : "",
1659 cap & (1 << 26) ? "pm " : "",
1660 cap & (1 << 25) ? "led " : "",
1662 cap & (1 << 24) ? "clo " : "",
1663 cap & (1 << 19) ? "nz " : "",
1664 cap & (1 << 18) ? "only " : "",
1665 cap & (1 << 17) ? "pmp " : "",
1666 cap & (1 << 15) ? "pio " : "",
1667 cap & (1 << 14) ? "slum " : "",
1668 cap & (1 << 13) ? "part " : ""
1672 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1674 static int printed_version;
1675 unsigned int board_idx = (unsigned int) ent->driver_data;
1676 struct device *dev = &pdev->dev;
1677 struct ata_probe_ent *probe_ent;
1678 struct ahci_host_priv *hpriv;
1683 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1685 if (!printed_version++)
1686 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1688 rc = pcim_enable_device(pdev);
1692 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1694 pcim_pin_device(pdev);
1698 if (pci_enable_msi(pdev))
1701 probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
1702 if (probe_ent == NULL)
1705 probe_ent->dev = pci_dev_to_dev(pdev);
1706 INIT_LIST_HEAD(&probe_ent->node);
1708 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1712 probe_ent->sht = ahci_port_info[board_idx].sht;
1713 probe_ent->port_flags = ahci_port_info[board_idx].flags;
1714 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1715 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1716 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1718 probe_ent->irq = pdev->irq;
1719 probe_ent->irq_flags = IRQF_SHARED;
1720 probe_ent->iomap = pcim_iomap_table(pdev);
1721 probe_ent->private_data = hpriv;
1723 /* initialize adapter */
1724 rc = ahci_host_init(probe_ent);
1728 if (!(probe_ent->port_flags & AHCI_FLAG_NO_NCQ) &&
1729 (hpriv->cap & HOST_CAP_NCQ))
1730 probe_ent->port_flags |= ATA_FLAG_NCQ;
1732 ahci_print_info(probe_ent);
1734 if (!ata_device_add(probe_ent))
1737 devm_kfree(dev, probe_ent);
1741 static int __init ahci_init(void)
1743 return pci_register_driver(&ahci_pci_driver);
1746 static void __exit ahci_exit(void)
1748 pci_unregister_driver(&ahci_pci_driver);
1752 MODULE_AUTHOR("Jeff Garzik");
1753 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1754 MODULE_LICENSE("GPL");
1755 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1756 MODULE_VERSION(DRV_VERSION);
1758 module_init(ahci_init);
1759 module_exit(ahci_exit);