board/technexion/pico-imx7d/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Technexion Ltd.
   4  *
   5  * Author: Richard Hu <richard.hu@technexion.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/imx-regs.h>
  12 #include <asm/arch/crm_regs.h>
  13 #include <asm/arch/mx7-pins.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <asm/arch-mx7/mx7-ddr.h>
  16 #include <asm/mach-imx/iomux-v3.h>
  17 #include <asm/gpio.h>
  18 #include <fsl_esdhc_imx.h>
  19 #include <spl.h>
  20
  21 #if defined(CONFIG_SPL_BUILD)
  22
  23 #ifdef CONFIG_SPL_OS_BOOT
  24 int spl_start_uboot(void)
  25 {
  26         /* Break into full U-Boot on 'c' */
  27         if (serial_tstc() && serial_getc() == 'c')
  28                 return 1;
  29
  30         return 0;
  31 }
  32 #endif
  33
  34 static struct ddrc ddrc_regs_val = {
  35         .mstr           = 0x01040001,
  36         .rfshtmg        = 0x00400046,
  37         .init1          = 0x00690000,
  38         .init0          = 0x00020083,
  39         .init3          = 0x09300004,
  40         .init4          = 0x04080000,
  41         .init5          = 0x00100004,
  42         .rankctl        = 0x0000033F,
  43         .dramtmg0       = 0x09081109,
  44         .dramtmg1       = 0x0007020d,
  45         .dramtmg2       = 0x03040407,
  46         .dramtmg3       = 0x00002006,
  47         .dramtmg4       = 0x04020205,
  48         .dramtmg5       = 0x03030202,
  49         .dramtmg8       = 0x00000803,
  50         .zqctl0         = 0x00800020,
  51         .dfitmg0        = 0x02098204,
  52         .dfitmg1        = 0x00030303,
  53         .dfiupd0        = 0x80400003,
  54         .dfiupd1        = 0x00100020,
  55         .dfiupd2        = 0x80100004,
  56         .addrmap4       = 0x00000F0F,
  57         .odtcfg         = 0x06000604,
  58         .odtmap         = 0x00000001,
  59         .rfshtmg        = 0x00400046,
  60         .dramtmg0       = 0x09081109,
  61         .addrmap0       = 0x0000001f,
  62         .addrmap1       = 0x00080808,
  63         .addrmap4       = 0x00000f0f,
  64         .addrmap5       = 0x07070707,
  65         .addrmap6       = 0x0f0f0707,
  66 };
  67
  68 static struct ddrc_mp ddrc_mp_val = {
  69         .pctrl_0        = 0x00000001,
  70 };
  71
  72 static struct ddr_phy ddr_phy_regs_val = {
  73         .phy_con0       = 0x17420f40,
  74         .phy_con1       = 0x10210100,
  75         .phy_con4       = 0x00060807,
  76         .mdll_con0      = 0x1010007e,
  77         .drvds_con0     = 0x00000d6e,
  78         .cmd_sdll_con0  = 0x00000010,
  79         .offset_lp_con0 = 0x0000000f,
  80         .offset_rd_con0 = 0x08080808,
  81         .offset_wr_con0 = 0x08080808,
  82 };
  83
  84 static struct mx7_calibration calib_param = {
  85         .num_val        = 5,
  86         .values         = {
  87                 0x0E407304,
  88                 0x0E447304,
  89                 0x0E447306,
  90                 0x0E447304,
  91                 0x0E447304,
  92         },
  93 };
  94
  95 static void gpr_init(void)
  96 {
  97         struct iomuxc_gpr_base_regs *gpr_regs =
  98                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  99         writel(0x4F400005, &gpr_regs->gpr[1]);
 100 }
 101
 102 static bool is_1g(void)
 103 {
 104         gpio_direction_input(IMX_GPIO_NR(1, 12));
 105         return !gpio_get_value(IMX_GPIO_NR(1, 12));
 106 }
 107
 108 static void ddr_init(void)
 109 {
 110         if (is_1g())
 111                 ddrc_regs_val.addrmap6  = 0x0f070707;
 112
 113         mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
 114                      &calib_param);
 115 }
 116
 117 void board_init_f(ulong dummy)
 118 {
 119         arch_cpu_init();
 120         gpr_init();
 121         board_early_init_f();
 122         timer_init();
 123         preloader_console_init();
 124         ddr_init();
 125         memset(__bss_start, 0, __bss_end - __bss_start);
 126         board_init_r(NULL, 0);
 127 }
 128
 129 void reset_cpu(ulong addr)
 130 {
 131 }
 132
 133 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
 134         PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
 135
 136 static iomux_v3_cfg_t const usdhc3_pads[] = {
 137         MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142         MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 143         MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 144         MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145         MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148 };
 149
 150 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 151         {USDHC3_BASE_ADDR},
 152 };
 153
 154 int board_mmc_getcd(struct mmc *mmc)
 155 {
 156         /* Assume uSDHC3 emmc is always present */
 157         return 1;
 158 }
 159
 160 int board_mmc_init(bd_t *bis)
 161 {
 162         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 163         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 164         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 165 }
 166 #endif