board/sks-kinkel/sksimx6/sksimx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
   4  */
   5
   6 #include <common.h>
   7 #include <net.h>
   8 #include <asm/arch/clock.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/iomux.h>
  11 #include <asm/arch/mx6-pins.h>
  12 #include <linux/errno.h>
  13 #include <asm/gpio.h>
  14 #include <asm/mach-imx/iomux-v3.h>
  15 #include <asm/mach-imx/video.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc_imx.h>
  18 #include <asm/arch/crm_regs.h>
  19 #include <asm/io.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <spl.h>
  22 #include <netdev.h>
  23 #include <miiphy.h>
  24 #include <micrel.h>
  25
  26 #include <common.h>
  27 #include <malloc.h>
  28 #include <fuse.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  33         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  34         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  35
  36 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  37         PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |               \
  38         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  39
  40 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  42         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  43
  44 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  45                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  46
  47 static iomux_v3_cfg_t const uart1_pads[] = {
  48         IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  49         IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  50 };
  51
  52 static iomux_v3_cfg_t const gpios_pads[] = {
  53         IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  54 };
  55
  56 static iomux_v3_cfg_t const usdhc2_pads[] = {
  57         IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  58         IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  59         IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60         IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61         IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  62         IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  63         IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
  64 };
  65
  66 static iomux_v3_cfg_t const enet_pads[] = {
  67         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  77         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  79         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
  80                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
  81         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  82                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  84                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85         IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86 };
  87
  88 iomux_v3_cfg_t const enet_pads1[] = {
  89         /* pin 35 - 1 (PHY_AD2) on reset */
  90         IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91         /* pin 32 - 1 - (MODE0) all */
  92         IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         /* pin 31 - 1 - (MODE1) all */
  94         IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         /* pin 28 - 1 - (MODE2) all */
  96         IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97         /* pin 27 - 1 - (MODE3) all */
  98         IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
  99         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 100         IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 101         /* pin 42 PHY nRST */
 102         IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 103 };
 104
 105 static int mx6_rgmii_rework(struct phy_device *phydev)
 106 {
 107
 108         /* min rx data delay */
 109         ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
 110                                    0x0);
 111         /* min tx data delay */
 112         ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
 113                                    0x0);
 114         /* max rx/tx clock delay, min rx/tx control */
 115         ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
 116                                    0xf0f0);
 117
 118         return 0;
 119 }
 120
 121 int board_phy_config(struct phy_device *phydev)
 122 {
 123         mx6_rgmii_rework(phydev);
 124
 125         if (phydev->drv->config)
 126                 return phydev->drv->config(phydev);
 127
 128         return 0;
 129 }
 130
 131 #define ENET_NRST IMX_GPIO_NR(1, 25)
 132
 133 void setup_iomux_enet(void)
 134 {
 135         SETUP_IOMUX_PADS(enet_pads);
 136
 137 }
 138
 139 int board_eth_init(bd_t *bis)
 140 {
 141         uint32_t base = IMX_FEC_BASE;
 142         struct mii_dev *bus = NULL;
 143         struct phy_device *phydev = NULL;
 144         int ret;
 145
 146         setup_iomux_enet();
 147
 148         bus = fec_get_miibus(base, -1);
 149         if (!bus)
 150                 return -EINVAL;
 151         /* scan phy */
 152         phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
 153                                         PHY_INTERFACE_MODE_RGMII);
 154
 155         if (!phydev) {
 156                 ret = -EINVAL;
 157                 goto free_bus;
 158         }
 159         ret  = fec_probe(bis, -1, base, bus, phydev);
 160         if (ret)
 161                 goto free_phydev;
 162
 163         return 0;
 164
 165 free_phydev:
 166         free(phydev);
 167 free_bus:
 168         free(bus);
 169         return ret;
 170 }
 171
 172 int board_early_init_f(void)
 173 {
 174         SETUP_IOMUX_PADS(uart1_pads);
 175
 176         return 0;
 177 }
 178
 179 int board_init(void)
 180 {
 181         /* Address of boot parameters */
 182         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 183
 184         /* Take in reset the ATMega processor */
 185         SETUP_IOMUX_PADS(gpios_pads);
 186         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 187
 188         return 0;
 189 }
 190
 191 int dram_init(void)
 192 {
 193         gd->ram_size = imx_ddr_size();
 194
 195         return 0;
 196 }
 197
 198 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 199         {USDHC2_BASE_ADDR, 0},
 200 };
 201
 202 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 0)
 203 int board_mmc_getcd(struct mmc *mmc)
 204 {
 205         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 206         int ret = 0;
 207
 208         if (cfg->esdhc_base == USDHC2_BASE_ADDR)
 209                 ret = 1;
 210
 211         return ret;
 212 }
 213
 214 int board_mmc_init(bd_t *bis)
 215 {
 216         int ret;
 217
 218         SETUP_IOMUX_PADS(usdhc2_pads);
 219         gpio_direction_input(USDHC2_CD_GPIO);
 220         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 221         usdhc_cfg[0].max_bus_width = 4;
 222
 223         ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 224         if (ret) {
 225                 printf("Warning: failed to initialize mmc dev \n");
 226                 return ret;
 227         }
 228
 229         return 0;
 230 }
 231
 232 #if defined(CONFIG_SPL_BUILD)
 233 #include <asm/arch/mx6-ddr.h>
 234
 235 /*
 236  * Driving strength:
 237  *   0x30 == 40 Ohm
 238  *   0x28 == 48 Ohm
 239  */
 240 #define IMX6SDL_DRIVE_STRENGTH  0x230
 241
 242
 243 /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
 244 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 245         .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
 246         .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
 247         .dram_cas = IMX6SDL_DRIVE_STRENGTH,
 248         .dram_ras = IMX6SDL_DRIVE_STRENGTH,
 249         .dram_reset = IMX6SDL_DRIVE_STRENGTH,
 250         .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
 251         .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
 252         .dram_sdba2 = 0x00000000,
 253         .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
 254         .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
 255         .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
 256         .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
 257         .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
 258         .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
 259         .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
 260         .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
 261         .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
 262         .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
 263         .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
 264         .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
 265         .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
 266         .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
 267         .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
 268         .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
 269         .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
 270         .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
 271 };
 272
 273 /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
 274 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 275         .grp_ddr_type = 0x000c0000,
 276         .grp_ddrmode_ctl = 0x00020000,
 277         .grp_ddrpke = 0x00000000,
 278         .grp_addds = IMX6SDL_DRIVE_STRENGTH,
 279         .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
 280         .grp_ddrmode = 0x00020000,
 281         .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
 282         .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
 283         .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
 284         .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
 285         .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
 286         .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
 287         .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
 288         .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
 289 };
 290
 291 /* MT41K128M16JT-125 */
 292 static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
 293         /* quad = 1066, duallite = 800 */
 294         .mem_speed = 1066,
 295         .density = 2,
 296         .width = 16,
 297         .banks = 8,
 298         .rowaddr = 14,
 299         .coladdr = 10,
 300         .pagesz = 2,
 301         .trcd = 1375,
 302         .trcmin = 4875,
 303         .trasmin = 3500,
 304         .SRT = 0,
 305 };
 306
 307 static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
 308         .p0_mpwldectrl0 = 0x0043004E,
 309         .p0_mpwldectrl1 = 0x003D003F,
 310         .p1_mpwldectrl0 = 0x00230021,
 311         .p1_mpwldectrl1 = 0x0028003E,
 312         .p0_mpdgctrl0 = 0x42580250,
 313         .p0_mpdgctrl1 = 0x0238023C,
 314         .p1_mpdgctrl0 = 0x422C0238,
 315         .p1_mpdgctrl1 = 0x02180228,
 316         .p0_mprddlctl = 0x44464A46,
 317         .p1_mprddlctl = 0x44464A42,
 318         .p0_mpwrdlctl = 0x36343236,
 319         .p1_mpwrdlctl = 0x36343230,
 320 };
 321
 322 /* DDR 64bit 1GB */
 323 static struct mx6_ddr_sysinfo mem_qdl = {
 324         .dsize = 2,
 325         .cs1_mirror = 0,
 326         /* config for full 4GB range so that get_mem_size() works */
 327         .cs_density = 32,
 328         .ncs = 1,
 329         .bi_on = 1,
 330         .rtt_nom = 1,
 331         .rtt_wr = 1,
 332         .ralat = 5,
 333         .walat = 0,
 334         .mif3_mode = 3,
 335         .rst_to_cke = 0x23,
 336         .sde_to_rst = 0x10,
 337         .refsel = 1,    /* Refresh cycles at 32KHz */
 338         .refr = 7,      /* 8 refresh commands per refresh cycle */
 339 };
 340
 341 static void ccgr_init(void)
 342 {
 343         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 344
 345         /* set the default clock gate to save power */
 346         writel(0x00C03F3F, &ccm->CCGR0);
 347         writel(0x0030FC03, &ccm->CCGR1);
 348         writel(0x0FFFC000, &ccm->CCGR2);
 349         writel(0x3FF00000, &ccm->CCGR3);
 350         writel(0x00FFF300, &ccm->CCGR4);
 351         writel(0xFFFFFFFF, &ccm->CCGR5);
 352         writel(0x000003FF, &ccm->CCGR6);
 353 }
 354
 355 static void spl_dram_init(void)
 356 {
 357         if (is_cpu_type(MXC_CPU_MX6DL)) {
 358                 mt41k128m16jt_125.mem_speed = 800;
 359                 mem_qdl.rtt_nom = 1;
 360                 mem_qdl.rtt_wr = 1;
 361
 362                 mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 363                 mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
 364         } else {
 365                 printf("Wrong CPU for this board\n");
 366                 return;
 367         }
 368
 369         udelay(100);
 370
 371 #ifdef CONFIG_MX6_DDRCAL
 372
 373         /* Perform DDR DRAM calibration */
 374         mmdc_do_write_level_calibration(&mem_qdl);
 375         mmdc_do_dqs_calibration(&mem_qdl);
 376 #endif
 377 }
 378
 379 static void check_bootcfg(void)
 380 {
 381         u32 val5, val6;
 382
 383         fuse_sense(0, 5, &val5);
 384         fuse_sense(0, 6, &val6);
 385         /* Check if boot from MMC */
 386         if (val6 & 0x10) {
 387                 puts("BT_FUSE_SEL already fused, will do nothing\n");
 388                 return;
 389         }
 390         fuse_prog(0, 5, 0x00000840);
 391         /* BT_FUSE_SEL */
 392         fuse_prog(0, 6, 0x00000010);
 393
 394         do_reset(NULL, 0, 0, NULL);
 395 }
 396
 397 void board_init_f(ulong dummy)
 398 {
 399         ccgr_init();
 400
 401         /* setup AIPS and disable watchdog */
 402         arch_cpu_init();
 403
 404         gpr_init();
 405
 406         /* iomux */
 407         board_early_init_f();
 408
 409         /* setup GP timer */
 410         timer_init();
 411
 412         /* UART clocks enabled and gd valid - init serial console */
 413         preloader_console_init();
 414
 415         /* DDR initialization */
 416         spl_dram_init();
 417
 418         /* Set fuses for new boards and reboot if not set */
 419         check_bootcfg();
 420
 421         /* Clear the BSS. */
 422         memset(__bss_start, 0, __bss_end - __bss_start);
 423
 424         /* load/boot image from boot device */
 425         board_init_r(NULL, 0);
 426 }
 427 #endif