board/renesas/stout/stout_spl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * board/renesas/stout/stout_spl.c
   4  *
   5  * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <malloc.h>
  11 #include <dm/platform_data/serial_sh.h>
  12 #include <asm/processor.h>
  13 #include <asm/mach-types.h>
  14 #include <asm/io.h>
  15 #include <linux/errno.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/gpio.h>
  18 #include <asm/arch/rmobile.h>
  19 #include <asm/arch/rcar-mstp.h>
  20
  21 #include <spl.h>
  22
  23 #define TMU0_MSTP125    BIT(25)
  24 #define SCIFA0_MSTP204  BIT(4)
  25 #define QSPI_MSTP917    BIT(17)
  26
  27 #define SD2CKCR         0xE615026C
  28 #define SD_97500KHZ     0x7
  29
  30 struct reg_config {
  31         u16     off;
  32         u32     val;
  33 };
  34
  35 static void dbsc_wait(u16 reg)
  36 {
  37         static const u32 dbsc3_0_base = DBSC3_0_BASE;
  38         static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
  39
  40         while (!(readl(dbsc3_0_base + reg) & BIT(0)))
  41                 ;
  42
  43         while (!(readl(dbsc3_1_base + reg) & BIT(0)))
  44                 ;
  45 }
  46
  47 static void spl_init_sys(void)
  48 {
  49         u32 r0 = 0;
  50
  51         writel(0xa5a5a500, 0xe6020004);
  52         writel(0xa5a5a500, 0xe6030004);
  53
  54         asm volatile(
  55                 /* ICIALLU - Invalidate I$ to PoU */
  56                 "mcr    15, 0, %0, cr7, cr5, 0  \n"
  57                 /* BPIALL - Invalidate branch predictors */
  58                 "mcr    15, 0, %0, cr7, cr5, 6  \n"
  59                 /* Set SCTLR[IZ] */
  60                 "mrc    15, 0, %0, cr1, cr0, 0  \n"
  61                 "orr    %0, #0x1800             \n"
  62                 "mcr    15, 0, %0, cr1, cr0, 0  \n"
  63                 "isb    sy                      \n"
  64                 :"=r"(r0));
  65 }
  66
  67 static void spl_init_pfc(void)
  68 {
  69         static const struct reg_config pfc_with_unlock[] = {
  70                 { 0x0090, 0x00140300 },
  71                 { 0x0094, 0x09500000 },
  72                 { 0x0098, 0xc0000084 },
  73                 { 0x0020, 0x01a33492 },
  74                 { 0x0024, 0x10000000 },
  75                 { 0x0028, 0x08449252 },
  76                 { 0x002c, 0x2925b322 },
  77                 { 0x0030, 0x0c311249 },
  78                 { 0x0034, 0x10124000 },
  79                 { 0x0038, 0x00001295 },
  80                 { 0x003c, 0x50890000 },
  81                 { 0x0040, 0x0eaa56aa },
  82                 { 0x0044, 0x55550000 },
  83                 { 0x0048, 0x00000005 },
  84                 { 0x004c, 0x54800000 },
  85                 { 0x0050, 0x3736db55 },
  86                 { 0x0054, 0x29148da3 },
  87                 { 0x0058, 0x48c446e1 },
  88                 { 0x005c, 0x2a3a54dc },
  89                 { 0x0160, 0x00000023 },
  90                 { 0x0004, 0xfca0ffff },
  91                 { 0x0008, 0x3fbffbf0 },
  92                 { 0x000c, 0x3ffdffff },
  93                 { 0x0010, 0x00ffffff },
  94                 { 0x0014, 0xfc3ffff3 },
  95                 { 0x0018, 0xe4fdfff7 },
  96         };
  97
  98         static const struct reg_config pfc_without_unlock[] = {
  99                 { 0x0104, 0xffffbfff },
 100                 { 0x0108, 0xb1ffffe1 },
 101                 { 0x010c, 0xffffffff },
 102                 { 0x0110, 0xffffffff },
 103                 { 0x0114, 0xe047beab },
 104                 { 0x0118, 0x00000203 },
 105         };
 106
 107         static const u32 pfc_base = 0xe6060000;
 108
 109         unsigned int i;
 110
 111         for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) {
 112                 writel(~pfc_with_unlock[i].val, pfc_base);
 113                 writel(pfc_with_unlock[i].val,
 114                        pfc_base | pfc_with_unlock[i].off);
 115         }
 116
 117         for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++)
 118                 writel(pfc_without_unlock[i].val,
 119                        pfc_base | pfc_without_unlock[i].off);
 120 }
 121
 122 static void spl_init_gpio(void)
 123 {
 124         static const u16 gpio_offs[] = {
 125                 0x1000, 0x3000, 0x4000, 0x5000
 126         };
 127
 128         static const struct reg_config gpio_set[] = {
 129                 { 0x4000, 0x00c00000 },
 130                 { 0x5000, 0x63020000 },
 131         };
 132
 133         static const struct reg_config gpio_clr[] = {
 134                 { 0x1000, 0x00000000 },
 135                 { 0x3000, 0x00000000 },
 136                 { 0x4000, 0x00c00000 },
 137                 { 0x5000, 0xe3020000 },
 138         };
 139
 140         static const u32 gpio_base = 0xe6050000;
 141
 142         unsigned int i;
 143
 144         for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
 145                 writel(0, gpio_base | 0x20 | gpio_offs[i]);
 146
 147         for (i = 0; i < ARRAY_SIZE(gpio_offs); i++)
 148                 writel(0, gpio_base | 0x00 | gpio_offs[i]);
 149
 150         for (i = 0; i < ARRAY_SIZE(gpio_set); i++)
 151                 writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off);
 152
 153         for (i = 0; i < ARRAY_SIZE(gpio_clr); i++)
 154                 writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off);
 155 }
 156
 157 static void spl_init_lbsc(void)
 158 {
 159         static const struct reg_config lbsc_config[] = {
 160                 { 0x00, 0x00000020 },
 161                 { 0x08, 0x00002020 },
 162                 { 0x30, 0x02150326 },
 163                 { 0x38, 0x077f077f },
 164         };
 165
 166         static const u16 lbsc_offs[] = {
 167                 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180
 168         };
 169
 170         static const u32 lbsc_base = 0xfec00200;
 171
 172         unsigned int i;
 173
 174         for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) {
 175                 writel(lbsc_config[i].val,
 176                        lbsc_base | lbsc_config[i].off);
 177                 writel(lbsc_config[i].val,
 178                        lbsc_base | (lbsc_config[i].off + 4));
 179         }
 180
 181         for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++)
 182                 writel(0, lbsc_base | lbsc_offs[i]);
 183 }
 184
 185 static void spl_init_dbsc(void)
 186 {
 187         static const struct reg_config dbsc_config1[] = {
 188                 { 0x0280, 0x0000a55a },
 189                 { 0x0018, 0x21000000 },
 190                 { 0x0018, 0x11000000 },
 191                 { 0x0018, 0x10000000 },
 192                 { 0x0290, 0x00000001 },
 193                 { 0x02a0, 0x80000000 },
 194                 { 0x0290, 0x00000004 },
 195         };
 196
 197         static const struct reg_config dbsc_config2[] = {
 198                 { 0x0290, 0x00000006 },
 199                 { 0x02a0, 0x0001c000 },
 200         };
 201
 202         static const struct reg_config dbsc_config3r0d0[] = {
 203                 { 0x0290, 0x0000000f },
 204                 { 0x02a0, 0x00181885 },
 205                 { 0x0290, 0x00000070 },
 206                 { 0x02a0, 0x7c000887 },
 207                 { 0x0290, 0x00000080 },
 208                 { 0x02a0, 0x7c000887 },
 209                 { 0x0290, 0x00000090 },
 210                 { 0x02a0, 0x7c000887 },
 211                 { 0x0290, 0x000000a0 },
 212                 { 0x02a0, 0x7c000887 },
 213                 { 0x0290, 0x000000b0 },
 214                 { 0x02a0, 0x7c000880 },
 215                 { 0x0290, 0x000000c0 },
 216                 { 0x02a0, 0x7c000880 },
 217                 { 0x0290, 0x000000d0 },
 218                 { 0x02a0, 0x7c000880 },
 219                 { 0x0290, 0x000000e0 },
 220                 { 0x02a0, 0x7c000880 },
 221         };
 222
 223         static const struct reg_config dbsc_config3r0d1[] = {
 224                 { 0x0290, 0x0000000f },
 225                 { 0x02a0, 0x00181885 },
 226                 { 0x0290, 0x00000070 },
 227                 { 0x02a0, 0x7c000887 },
 228                 { 0x0290, 0x00000080 },
 229                 { 0x02a0, 0x7c000887 },
 230                 { 0x0290, 0x00000090 },
 231                 { 0x02a0, 0x7c000887 },
 232                 { 0x0290, 0x000000a0 },
 233                 { 0x02a0, 0x7c000887 },
 234         };
 235
 236         static const struct reg_config dbsc_config3r2[] = {
 237                 { 0x0290, 0x0000000f },
 238                 { 0x02a0, 0x00181224 },
 239         };
 240
 241         static const struct reg_config dbsc_config4[] = {
 242                 { 0x0290, 0x00000010 },
 243                 { 0x02a0, 0xf004649b },
 244                 { 0x0290, 0x00000061 },
 245                 { 0x02a0, 0x0000006d },
 246                 { 0x0290, 0x00000001 },
 247                 { 0x02a0, 0x00000073 },
 248                 { 0x0020, 0x00000007 },
 249                 { 0x0024, 0x0f030a02 },
 250                 { 0x0030, 0x00000001 },
 251                 { 0x00b0, 0x00000000 },
 252                 { 0x0040, 0x0000000b },
 253                 { 0x0044, 0x00000008 },
 254                 { 0x0048, 0x00000000 },
 255                 { 0x0050, 0x0000000b },
 256                 { 0x0054, 0x000c000b },
 257                 { 0x0058, 0x00000027 },
 258                 { 0x005c, 0x0000001c },
 259                 { 0x0060, 0x00000006 },
 260                 { 0x0064, 0x00000020 },
 261                 { 0x0068, 0x00000008 },
 262                 { 0x006c, 0x0000000c },
 263                 { 0x0070, 0x00000009 },
 264                 { 0x0074, 0x00000012 },
 265                 { 0x0078, 0x000000d0 },
 266                 { 0x007c, 0x00140005 },
 267                 { 0x0080, 0x00050004 },
 268                 { 0x0084, 0x70233005 },
 269                 { 0x0088, 0x000c0000 },
 270                 { 0x008c, 0x00000200 },
 271                 { 0x0090, 0x00000040 },
 272                 { 0x0100, 0x00000001 },
 273                 { 0x00c0, 0x00020001 },
 274                 { 0x00c8, 0x20042004 },
 275                 { 0x0380, 0x00020002 },
 276                 { 0x0390, 0x0000001f },
 277         };
 278
 279         static const struct reg_config dbsc_config5[] = {
 280                 { 0x0244, 0x00000011 },
 281                 { 0x0290, 0x00000003 },
 282                 { 0x02a0, 0x0300c4e1 },
 283                 { 0x0290, 0x00000023 },
 284                 { 0x02a0, 0x00fcdb60 },
 285                 { 0x0290, 0x00000011 },
 286                 { 0x02a0, 0x1000040b },
 287                 { 0x0290, 0x00000012 },
 288                 { 0x02a0, 0x9d9cbb66 },
 289                 { 0x0290, 0x00000013 },
 290                 { 0x02a0, 0x1a868400 },
 291                 { 0x0290, 0x00000014 },
 292                 { 0x02a0, 0x300214d8 },
 293                 { 0x0290, 0x00000015 },
 294                 { 0x02a0, 0x00000d70 },
 295                 { 0x0290, 0x00000016 },
 296                 { 0x02a0, 0x00000006 },
 297                 { 0x0290, 0x00000017 },
 298                 { 0x02a0, 0x00000018 },
 299                 { 0x0290, 0x0000001a },
 300                 { 0x02a0, 0x910035c7 },
 301                 { 0x0290, 0x00000004 },
 302         };
 303
 304         static const struct reg_config dbsc_config6[] = {
 305                 { 0x0290, 0x00000001 },
 306                 { 0x02a0, 0x00000181 },
 307                 { 0x0018, 0x11000000 },
 308                 { 0x0290, 0x00000004 },
 309         };
 310
 311         static const struct reg_config dbsc_config7[] = {
 312                 { 0x0290, 0x00000001 },
 313                 { 0x02a0, 0x0000fe01 },
 314                 { 0x0304, 0x00000000 },
 315                 { 0x00f4, 0x01004c20 },
 316                 { 0x00f8, 0x014000aa },
 317                 { 0x00e0, 0x00000140 },
 318                 { 0x00e4, 0x00081860 },
 319                 { 0x00e8, 0x00010000 },
 320                 { 0x0290, 0x00000004 },
 321         };
 322
 323         static const struct reg_config dbsc_config8[] = {
 324                 { 0x0014, 0x00000001 },
 325                 { 0x0010, 0x00000001 },
 326                 { 0x0280, 0x00000000 },
 327         };
 328
 329         static const u32 dbsc3_0_base = DBSC3_0_BASE;
 330         static const u32 dbsc3_1_base = DBSC3_0_BASE + 0x10000;
 331         static const u32 prr_base = 0xff000044;
 332         const u16 prr_rev = readl(prr_base) & 0x7fff;
 333         unsigned int i;
 334
 335         for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) {
 336                 writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off);
 337                 writel(dbsc_config1[i].val, dbsc3_1_base | dbsc_config1[i].off);
 338         }
 339
 340         dbsc_wait(0x2a0);
 341
 342         for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) {
 343                 writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off);
 344                 writel(dbsc_config2[i].val, dbsc3_1_base | dbsc_config2[i].off);
 345         }
 346
 347         if (prr_rev == 0x4500) {
 348                 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d0); i++) {
 349                         writel(dbsc_config3r0d0[i].val,
 350                                 dbsc3_0_base | dbsc_config3r0d0[i].off);
 351                 }
 352                 for (i = 0; i < ARRAY_SIZE(dbsc_config3r0d1); i++) {
 353                         writel(dbsc_config3r0d1[i].val,
 354                                 dbsc3_1_base | dbsc_config3r0d1[i].off);
 355                 }
 356         } else if (prr_rev != 0x4510) {
 357                 for (i = 0; i < ARRAY_SIZE(dbsc_config3r2); i++) {
 358                         writel(dbsc_config3r2[i].val,
 359                                 dbsc3_0_base | dbsc_config3r2[i].off);
 360                         writel(dbsc_config3r2[i].val,
 361                                 dbsc3_1_base | dbsc_config3r2[i].off);
 362                 }
 363         }
 364
 365         for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) {
 366                 writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off);
 367                 writel(dbsc_config4[i].val, dbsc3_1_base | dbsc_config4[i].off);
 368         }
 369
 370         dbsc_wait(0x240);
 371
 372         for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) {
 373                 writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off);
 374                 writel(dbsc_config5[i].val, dbsc3_1_base | dbsc_config5[i].off);
 375         }
 376
 377         dbsc_wait(0x2a0);
 378
 379         for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) {
 380                 writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off);
 381                 writel(dbsc_config6[i].val, dbsc3_1_base | dbsc_config6[i].off);
 382         }
 383
 384         dbsc_wait(0x2a0);
 385
 386         for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) {
 387                 writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off);
 388                 writel(dbsc_config7[i].val, dbsc3_1_base | dbsc_config7[i].off);
 389         }
 390
 391         dbsc_wait(0x2a0);
 392
 393         for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) {
 394                 writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off);
 395                 writel(dbsc_config8[i].val, dbsc3_1_base | dbsc_config8[i].off);
 396         }
 397
 398 }
 399
 400 static void spl_init_qspi(void)
 401 {
 402         mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
 403
 404         static const u32 qspi_base = 0xe6b10000;
 405
 406         writeb(0x08, qspi_base + 0x00);
 407         writeb(0x00, qspi_base + 0x01);
 408         writeb(0x06, qspi_base + 0x02);
 409         writeb(0x01, qspi_base + 0x0a);
 410         writeb(0x00, qspi_base + 0x0b);
 411         writeb(0x00, qspi_base + 0x0c);
 412         writeb(0x00, qspi_base + 0x0d);
 413         writeb(0x00, qspi_base + 0x0e);
 414
 415         writew(0xe080, qspi_base + 0x10);
 416
 417         writeb(0xc0, qspi_base + 0x18);
 418         writeb(0x00, qspi_base + 0x18);
 419         writeb(0x00, qspi_base + 0x08);
 420         writeb(0x48, qspi_base + 0x00);
 421 }
 422
 423 void board_init_f(ulong dummy)
 424 {
 425         mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
 426         mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIFA0_MSTP204);
 427
 428         /*
 429          * SD0 clock is set to 97.5MHz by default.
 430          * Set SD2 to the 97.5MHz as well.
 431          */
 432         writel(SD_97500KHZ, SD2CKCR);
 433
 434         spl_init_sys();
 435         spl_init_pfc();
 436         spl_init_gpio();
 437         spl_init_lbsc();
 438         spl_init_dbsc();
 439         spl_init_qspi();
 440 }
 441
 442 void spl_board_init(void)
 443 {
 444         /* UART clocks enabled and gd valid - init serial console */
 445         preloader_console_init();
 446 }
 447
 448 void board_boot_order(u32 *spl_boot_list)
 449 {
 450         const u32 jtag_magic = 0x1337c0de;
 451         const u32 load_magic = 0xb33fc0de;
 452
 453         /*
 454          * If JTAG probe sets special word at 0xe6300020, then it must
 455          * put U-Boot into RAM and SPL will start it from RAM.
 456          */
 457         if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) {
 458                 printf("JTAG boot detected!\n");
 459
 460                 while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic)
 461                         ;
 462
 463                 spl_boot_list[0] = BOOT_DEVICE_RAM;
 464                 spl_boot_list[1] = BOOT_DEVICE_NONE;
 465
 466                 return;
 467         }
 468
 469         /* Boot from SPI NOR with YMODEM UART fallback. */
 470         spl_boot_list[0] = BOOT_DEVICE_SPI;
 471         spl_boot_list[1] = BOOT_DEVICE_UART;
 472         spl_boot_list[2] = BOOT_DEVICE_NONE;
 473 }
 474
 475 void reset_cpu(ulong addr)
 476 {
 477 }