1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Renesas Solutions Corp.
13 #include <asm/processor.h>
17 #include <spi_flash.h>
21 puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
26 static void init_gpio(void)
28 struct gpio_regs *gpio = GPIO_BASE;
29 struct sermux_regs *sermux = SERMUX_BASE;
32 writew(0x0000, &gpio->pacr); /* GETHER */
33 writew(0x0001, &gpio->pbcr); /* INTC */
34 writew(0x0000, &gpio->pccr); /* PWMU, INTC */
35 writew(0xeaff, &gpio->pecr); /* GPIO */
36 writew(0x0000, &gpio->pfcr); /* WDT */
37 writew(0x0000, &gpio->phcr); /* SPI1 */
38 writew(0x0000, &gpio->picr); /* SDHI */
39 writew(0x0003, &gpio->pkcr); /* SerMux */
40 writew(0x0000, &gpio->plcr); /* SerMux */
41 writew(0x0000, &gpio->pmcr); /* RIIC */
42 writew(0x0000, &gpio->pncr); /* USB, SGPIO */
43 writew(0x0000, &gpio->pocr); /* SGPIO */
44 writew(0xd555, &gpio->pqcr); /* GPIO */
45 writew(0x0000, &gpio->prcr); /* RIIC */
46 writew(0x0000, &gpio->pscr); /* RIIC */
47 writeb(0x00, &gpio->pudr);
48 writew(0x5555, &gpio->pucr); /* Debug LED */
49 writew(0x0000, &gpio->pvcr); /* RSPI */
50 writew(0x0000, &gpio->pwcr); /* EVC */
51 writew(0x0000, &gpio->pxcr); /* LBSC */
52 writew(0x0000, &gpio->pycr); /* LBSC */
53 writew(0x0000, &gpio->pzcr); /* eMMC */
54 writew(0xfe00, &gpio->psel0);
55 writew(0xff00, &gpio->psel3);
56 writew(0x771f, &gpio->psel4);
57 writew(0x00ff, &gpio->psel6);
58 writew(0xfc00, &gpio->psel7);
60 writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
63 static void init_usb_phy(void)
65 struct usb_common_regs *common0 = USB0_COMMON_BASE;
66 struct usb_common_regs *common1 = USB1_COMMON_BASE;
67 struct usb0_phy_regs *phy = USB0_PHY_BASE;
68 struct usb1_port_regs *port = USB1_PORT_BASE;
69 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
71 writew(0x0100, &phy->reset); /* set reset */
72 /* port0 = USB0, port1 = USB1 */
73 writew(0x0002, &phy->portsel);
74 writel(0x0001, &port->port1sel); /* port1 = Host */
75 writew(0x0111, &phy->reset); /* clear reset */
77 writew(0x4000, &common0->suspmode);
78 writew(0x4000, &common1->suspmode);
80 #if defined(__LITTLE_ENDIAN)
81 writel(0x00000000, &align->ehcidatac);
82 writel(0x00000000, &align->ohcidatac);
86 static void init_gether_mdio(void)
88 struct gpio_regs *gpio = GPIO_BASE;
90 writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
91 writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
94 static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
96 struct ether_mac_regs *ether;
100 string_to_enetaddr(mac_string, mac);
103 ether = GETHER0_MAC_BASE;
105 ether = GETHER1_MAC_BASE;
107 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
108 writel(val, ðer->mahr);
109 val = (mac[4] << 8) | mac[5];
110 writel(val, ðer->malr);
113 /*****************************************************************
114 * This PMB must be set on this timing. The lowlevel_init is run on
115 * Area 0(phys 0x00000000), so we have to map it.
117 * The new PMB table is following:
118 * ent virt phys v sz c wt
119 * 0 0xa0000000 0x40000000 1 128M 0 1
120 * 1 0xa8000000 0x48000000 1 128M 0 1
121 * 2 0xb0000000 0x50000000 1 128M 0 1
122 * 3 0xb8000000 0x58000000 1 128M 0 1
123 * 4 0x80000000 0x40000000 1 128M 1 1
124 * 5 0x88000000 0x48000000 1 128M 1 1
125 * 6 0x90000000 0x50000000 1 128M 1 1
126 * 7 0x98000000 0x58000000 1 128M 1 1
128 static void set_pmb_on_board_init(void)
130 struct mmu_regs *mmu = MMU_BASE;
133 writel(0x00000004, &mmu->mmucr);
135 /* delete PMB for SPIBOOT */
136 writel(0, PMB_ADDR_BASE(0));
137 writel(0, PMB_DATA_BASE(0));
139 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
140 /* ppn ub v s1 s0 c wt */
141 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
142 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
143 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
144 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
145 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
146 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
147 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
148 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
149 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
150 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
151 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
152 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
158 set_pmb_on_board_init();
166 int board_mmc_init(bd_t *bis)
168 struct gpio_regs *gpio = GPIO_BASE;
170 writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
171 writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
173 writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
176 return mmcif_mmc_init();
179 static int get_sh_eth_mac_raw(unsigned char *buf, int size)
181 #ifdef CONFIG_DEPRECATED
182 struct spi_flash *spi;
185 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
187 printf("%s: spi_flash probe failed.\n", __func__);
191 ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
193 printf("%s: spi_flash read failed.\n", __func__);
203 static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
205 memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
206 SH7752EVB_ETHERNET_MAC_SIZE);
207 mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
212 static void init_ethernet_mac(void)
221 printf("%s: malloc failed.\n", __func__);
224 get_sh_eth_mac_raw(buf, 256);
226 /* Gigabit Ethernet */
227 for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
228 get_sh_eth_mac(i, mac_string, buf);
230 env_set("ethaddr", mac_string);
232 sprintf(env_string, "eth%daddr", i);
233 env_set(env_string, mac_string);
235 set_mac_to_sh_giga_eth_register(i, mac_string);
241 int board_late_init(void)
248 #ifdef CONFIG_DEPRECATED
249 int do_write_mac(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
252 char mac_string[256];
253 struct spi_flash *spi;
259 printf("%s: malloc failed.\n", __func__);
263 get_sh_eth_mac_raw(buf, 256);
265 /* print current MAC address */
266 for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
267 get_sh_eth_mac(i, mac_string, buf);
268 printf("GETHERC ch%d = %s\n", i, mac_string);
275 memset(mac_string, 0xff, sizeof(mac_string));
276 sprintf(mac_string, "%s\t%s",
279 /* write MAC data to SPI rom */
280 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
282 printf("%s: spi_flash probe failed.\n", __func__);
286 ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
287 SH7752EVB_SPI_SECTOR_SIZE);
289 printf("%s: spi_flash erase failed.\n", __func__);
293 ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
294 sizeof(mac_string), mac_string);
296 printf("%s: spi_flash write failed.\n", __func__);
302 puts("The writing of the MAC address to SPI ROM was completed.\n");
308 write_mac, 3, 1, do_write_mac,
309 "write MAC address for GETHERC",
310 "[GETHERC ch0] [GETHERC ch1]\n"