3 * Texas Instruments, <www.ti.com>
4 * Jian Zhang <jzhang@ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
8 * Steve Sakoman <steve@sakoman.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/bits.h>
35 #include <asm/arch/gpio.h>
36 #include <asm/arch/mux.h>
37 #include <asm/arch/sys_proto.h>
38 #include <asm/arch/sys_info.h>
39 #include <asm/arch/clocks.h>
40 #include <asm/arch/mem.h>
43 #define CORE_DPLL_PARAM_M2 0x09
44 #define CORE_DPLL_PARAM_M 0x360
45 #define CORE_DPLL_PARAM_N 0xC
47 /* Used to index into DPLL parameter tables */
55 typedef struct dpll_param dpll_param;
57 /* Following functions are exported from lowlevel_init.S */
58 extern dpll_param *get_mpu_dpll_param();
59 extern dpll_param *get_iva_dpll_param();
60 extern dpll_param *get_core_dpll_param();
61 extern dpll_param *get_per_dpll_param();
63 #define __raw_readl(a) (*(volatile unsigned int *)(a))
64 #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
65 #define __raw_readw(a) (*(volatile unsigned short *)(a))
66 #define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
68 static char *rev_s[CPU_3XX_MAX_REV] = {
78 /*******************************************************
80 * Description: spinning delay to use before udelay works
81 ******************************************************/
82 static inline void delay(unsigned long loops)
84 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
85 "bne 1b":"=r" (loops):"0"(loops));
88 void udelay (unsigned long usecs) {
92 /*****************************************
94 * Description: Early hardware init.
95 *****************************************/
101 /*************************************************************
102 * get_device_type(): tell if GP/HS/EMU/TST
103 *************************************************************/
104 u32 get_device_type(void)
107 mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
111 /************************************************
112 * get_sysboot_value(void) - return SYS_BOOT[4:0]
113 ************************************************/
114 u32 get_sysboot_value(void)
117 mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
121 /*************************************************************
122 * Routine: get_mem_type(void) - returns the kind of memory connected
123 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
124 *************************************************************/
125 u32 get_mem_type(void)
127 u32 mem_type = get_sysboot_value();
170 /******************************************
171 * get_cpu_type(void) - extract cpu info
172 ******************************************/
173 u32 get_cpu_type(void)
175 return __raw_readl(CONTROL_OMAP_STATUS);
178 /******************************************
179 * get_cpu_id(void) - extract cpu id
180 * returns 0 for ES1.0, cpuid otherwise
181 ******************************************/
187 * On ES1.0 the IDCODE register is not exposed on L4
188 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
190 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
191 if ((cpuid & 0xf) == 0x0) {
194 /* Decode the IDs on > ES1.0 */
195 cpuid = __raw_readl(CONTROL_IDCODE);
201 /******************************************
202 * get_cpu_family(void) - extract cpu info
203 ******************************************/
204 u32 get_cpu_family(void)
208 u32 cpuid = get_cpu_id();
213 hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
215 case HAWKEYE_OMAP34XX:
216 cpu_family = CPU_OMAP34XX;
219 cpu_family = CPU_AM35XX;
221 case HAWKEYE_OMAP36XX:
222 cpu_family = CPU_OMAP36XX;
225 cpu_family = CPU_OMAP34XX;
231 /******************************************
232 * get_cpu_rev(void) - extract version info
233 ******************************************/
234 u32 get_cpu_rev(void)
236 u32 cpuid = get_cpu_id();
241 return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
244 /******************************************
245 * Print CPU information
246 ******************************************/
247 int print_cpuinfo (void)
249 char *cpu_family_s, *cpu_s, *sec_s;
251 switch (get_cpu_family()) {
253 cpu_family_s = "OMAP";
254 switch (get_cpu_type()) {
274 switch (get_cpu_type()) {
287 cpu_family_s = "OMAP";
288 switch (get_cpu_type()) {
298 cpu_family_s = "OMAP";
302 switch (get_device_type()) {
319 printf("%s%s-%s ES%s\n",
320 cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]);
325 /******************************************
326 * cpu_is_3410(void) - returns true for 3410
327 ******************************************/
328 u32 cpu_is_3410(void)
331 if (get_cpu_rev() < CPU_3430_ES2) {
334 /* read scalability status and return 1 for 3410*/
335 status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
336 /* Check whether MPU frequency is set to 266 MHz which
337 * is nominal for 3410. If yes return true else false
339 if (((status >> 8) & 0x3) == 0x2)
346 /*****************************************************************
347 * Routine: get_board_revision
348 * Description: Returns the board revision
349 *****************************************************************/
350 int get_board_revision(void)
354 if (!omap_request_gpio(112) &&
355 !omap_request_gpio(113) &&
356 !omap_request_gpio(115)) {
358 omap_set_gpio_direction(112, 1);
359 omap_set_gpio_direction(113, 1);
360 omap_set_gpio_direction(115, 1);
362 revision = omap_get_gpio_datain(115) << 2 |
363 omap_get_gpio_datain(113) << 1 |
364 omap_get_gpio_datain(112);
370 printf("Error: unable to acquire board revision GPIOs\n");
377 /*****************************************************************
378 * sr32 - clear & set a value in a bit range for a 32 bit address
379 *****************************************************************/
380 void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
385 tmp = __raw_readl(addr) & ~(msk << start_bit);
386 tmp |= value << start_bit;
387 __raw_writel(tmp, addr);
390 /*********************************************************************
391 * wait_on_value() - common routine to allow waiting for changes in
393 *********************************************************************/
394 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
399 val = __raw_readl(read_addr) & read_bit_mask;
400 if (val == match_value)
407 #ifdef CFG_3430SDRAM_DDR
408 /*********************************************************************
409 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
410 *********************************************************************/
411 void config_3430sdram_ddr(void)
413 /* reset sdrc controller */
414 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
415 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
416 __raw_writel(0, SDRC_SYSCONFIG);
418 /* setup sdrc to ball mux */
419 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
421 switch (get_board_revision()) {
422 case 0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
423 __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
424 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
425 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
426 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
427 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
428 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
429 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
430 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
431 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
433 case 1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
434 __raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
435 __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
436 __raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
437 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
438 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
439 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
440 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
441 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
442 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
445 __raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
446 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
447 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
448 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
449 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
450 __raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
451 __raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
452 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
453 __raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
456 __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
458 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
459 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
460 __raw_writel(CMD_NOP, SDRC_MANUAL_1);
464 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
465 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
467 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
468 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
470 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
471 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
474 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
475 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);
478 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
479 delay(0x2000); /* give time to lock */
481 #endif /* CFG_3430SDRAM_DDR */
483 /*************************************************************
484 * get_sys_clk_speed - determine reference oscillator speed
485 * based on known 32kHz clock and gptimer.
486 *************************************************************/
487 u32 get_osc_clk_speed(void)
489 u32 start, cstart, cend, cdiff, cdiv, val;
491 val = __raw_readl(PRM_CLKSRC_CTRL);
493 if (val & SYSCLKDIV_2)
499 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
500 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
502 /* Enable I and F Clocks for GPT1 */
503 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
504 __raw_writel(val, CM_ICLKEN_WKUP);
505 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
506 __raw_writel(val, CM_FCLKEN_WKUP);
508 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
509 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
510 /* enable 32kHz source */
511 /* enabled out of reset */
512 /* determine sys_clk via gauging */
514 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
515 while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
516 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
517 while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
518 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
519 cdiff = cend - cstart; /* get elapsed ticks */
522 /* based on number of ticks assign speed */
525 else if (cdiff > 15200)
527 else if (cdiff > 13000)
529 else if (cdiff > 9000)
531 else if (cdiff > 7600)
537 /******************************************************************************
538 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
539 * -- input oscillator clock frequency.
541 *****************************************************************************/
542 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
544 if (osc_clk == S38_4M)
546 else if (osc_clk == S26M)
548 else if (osc_clk == S19_2M)
550 else if (osc_clk == S13M)
552 else if (osc_clk == S12M)
556 /******************************************************************************
557 * prcm_init() - inits clocks for PRCM as defined in clocks.h
558 * -- called from SRAM, or Flash (using temp SRAM stack).
559 *****************************************************************************/
562 u32 osc_clk = 0, sys_clkin_sel;
563 dpll_param *dpll_param_p;
564 u32 clk_index, sil_index;
566 /* Gauge the input clock speed and find out the sys_clkin_sel
567 * value corresponding to the input clock.
569 osc_clk = get_osc_clk_speed();
570 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
572 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
574 /* If the input clock is greater than 19.2M always divide/2 */
575 if (sys_clkin_sel > 2) {
576 sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
577 clk_index = sys_clkin_sel / 2;
579 sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
580 clk_index = sys_clkin_sel;
583 sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
585 /* The DPLL tables are defined according to sysclk value and
586 * silicon revision. The clk_index value will be used to get
587 * the values for that input sysclk from the DPLL param table
588 * and sil_index will get the values for that SysClk for the
589 * appropriate silicon rev.
591 sil_index = get_cpu_rev() - 1;
593 /* Unlock MPU DPLL (slows things down, and needed later) */
594 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
595 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
597 /* Getting the base address of Core DPLL param table */
598 dpll_param_p = (dpll_param *) get_core_dpll_param();
599 /* Moving it to the right sysclk and ES rev base */
600 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
602 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
603 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
604 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
606 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
607 work. write another value and then default value. */
608 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
609 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
610 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
611 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
612 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
613 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
614 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
615 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
616 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
617 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
618 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
619 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
620 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
621 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
622 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
624 /* Getting the base address to PER DPLL param table */
625 dpll_param_p = (dpll_param *) get_per_dpll_param();
626 /* Moving it to the right sysclk base */
627 dpll_param_p = dpll_param_p + clk_index;
629 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
630 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
631 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
632 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
633 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
634 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
636 if (get_cpu_family() == CPU_OMAP36XX) {
637 sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */
638 sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */
639 sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */
641 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
642 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
643 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
646 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
647 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
648 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
650 /* Getting the base address to MPU DPLL param table */
651 dpll_param_p = (dpll_param *) get_mpu_dpll_param();
653 /* Moving it to the right sysclk and ES rev base */
654 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
656 /* MPU DPLL (unlocked already) */
657 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
658 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
659 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
660 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
661 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
662 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
664 /* Getting the base address to IVA DPLL param table */
665 dpll_param_p = (dpll_param *) get_iva_dpll_param();
666 /* Moving it to the right sysclk and ES rev base */
667 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
668 /* IVA DPLL (set to 12*20=240MHz) */
669 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
670 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
671 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
672 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
673 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
674 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
675 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
676 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
678 /* Set up GPTimers to sys_clk source only */
679 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
680 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
685 /*****************************************
686 * Routine: secure_unlock
687 * Description: Setup security registers for access
689 *****************************************/
690 void secure_unlock(void)
692 /* Permission values for registers -Full fledged permissions to all */
693 #define UNLOCK_1 0xFFFFFFFF
694 #define UNLOCK_2 0x00000000
695 #define UNLOCK_3 0x0000FFFF
696 /* Protection Module Register Target APE (PM_RT)*/
697 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
698 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
699 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
700 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
702 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
703 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
704 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
706 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
707 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
708 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
709 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
712 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
713 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
714 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
716 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
719 /**********************************************************
720 * Routine: try_unlock_sram()
721 * Description: If chip is GP type, unlock the SRAM for
723 ***********************************************************/
724 void try_unlock_memory(void)
728 /* if GP device unlock device SRAM for general use */
729 /* secure code breaks for Secure/Emulation device - HS/E/T*/
730 mode = get_device_type();
731 if (mode == GP_DEVICE)
736 /**********************************************************
738 * Description: Does early system init of muxing and clocks.
739 * - Called at time when only stack is available.
740 **********************************************************/
745 #ifdef CONFIG_3430_AS_3410
746 /* setup the scalability control register for
747 * 3430 to work in 3410 mode
749 __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
756 config_3430sdram_ddr();
759 /*******************************************************
760 * Routine: misc_init_r
761 ********************************************************/
762 int misc_init_r(void)
765 printf("Board revision: %d\n", get_board_revision());
769 /******************************************************
770 * Routine: wait_for_command_complete
771 * Description: Wait for posting to finish on watchdog
772 ******************************************************/
773 void wait_for_command_complete(unsigned int wd_base)
777 pending = __raw_readl(wd_base + WWPS);
781 /****************************************
782 * Routine: watchdog_init
783 * Description: Shut down watch dogs
784 *****************************************/
785 void watchdog_init(void)
787 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
788 * either taken care of by ROM (HS/EMU) or not accessible (GP).
789 * We need to take care of WD2-MPU or take a PRCM reset. WD3
790 * should not be running and does not generate a PRCM reset.
792 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
793 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
794 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
796 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
797 wait_for_command_complete(WD2_BASE);
798 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
801 /**********************************************
803 * Description: sets uboots idea of sdram size
804 **********************************************/
810 /*****************************************************************
811 * Routine: peripheral_enable
812 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
813 ******************************************************************/
814 void per_clocks_enable(void)
816 /* Enable GP2 timer. */
817 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
818 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
819 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
823 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
824 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
827 sr32(CM_FCLKEN_PER, 11, 1, 0x1);
828 sr32(CM_ICLKEN_PER, 11, 1, 0x1);
832 /* Enable GPIO 4, 5, & 6 clocks */
833 sr32(CM_FCLKEN_PER, 17, 3, 0x7);
834 sr32(CM_ICLKEN_PER, 17, 3, 0x7);
836 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
837 /* Turn on all 3 I2C clocks */
838 sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
839 sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
842 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
843 sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
845 sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
846 sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
847 sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
848 sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
849 sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
850 sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
851 sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
852 sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
853 sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
854 sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
855 sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
856 sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
861 /* Set MUX for UART, GPMC, SDRC, GPIO */
863 #define MUX_VAL(OFFSET,VALUE)\
864 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
866 #define CP(x) (CONTROL_PADCONF_##x)
869 * IDIS - Input Disable
870 * PTD - Pull type Down
872 * DIS - Pull type selection is inactive
873 * EN - Pull type selection is active
875 * The commented string gives the final mux configuration for that pin
877 #define MUX_DEFAULT()\
878 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
879 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
880 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
881 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
882 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
883 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
884 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
885 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
886 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
887 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
888 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
889 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
890 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
891 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
892 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
893 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
894 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
895 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
896 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
897 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
898 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
899 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
900 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
901 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
902 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
903 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
904 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
905 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
906 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
907 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
908 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
909 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
910 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
911 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
912 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
913 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
914 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
915 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
916 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
917 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
918 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
919 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
920 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
921 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
922 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
923 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
924 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
925 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
926 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
927 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
928 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
929 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
930 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
931 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
932 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
933 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
934 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
935 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
936 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
937 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
938 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
939 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
940 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
941 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
942 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
943 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
944 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
945 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
946 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
947 MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
948 MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
949 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
950 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
951 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
952 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
953 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
954 MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
955 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
956 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
957 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
958 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
959 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
960 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
961 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
962 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
963 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
964 MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
965 MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
966 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
968 MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
969 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
970 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
971 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
972 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
973 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
974 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
975 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
976 MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\
977 MUX_VAL(CP(MMC1_DAT5), (IEN | PTD | EN | M4)) /*GPIO_127*/\
978 MUX_VAL(CP(MMC1_DAT6), (IEN | PTD | EN | M4)) /*GPIO_128*/\
979 MUX_VAL(CP(MMC1_DAT7), (IEN | PTD | EN | M4)) /*GPIO_129*/\
980 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
981 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
982 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
983 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
984 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
985 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
986 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
987 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
988 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
989 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
990 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
991 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
992 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
993 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
994 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
995 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
996 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
997 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
998 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
999 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
1000 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
1001 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
1002 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
1003 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
1004 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
1005 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
1006 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
1007 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
1008 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
1009 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
1010 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
1011 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
1012 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
1013 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
1014 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
1015 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
1016 MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
1017 MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
1018 MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
1019 MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
1020 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
1021 MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
1022 MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
1023 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
1024 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
1026 /**********************************************************
1027 * Routine: set_muxconf_regs
1028 * Description: Setting up the configuration Mux registers
1029 * specific to the hardware. Many pins need
1030 * to be moved from protect to primary mode.
1031 *********************************************************/
1032 void set_muxconf_regs(void)
1037 /**********************************************************
1038 * Routine: nand+_init
1039 * Description: Set up nand for nand and jffs2 commands
1040 *********************************************************/
1044 /* global settings */
1045 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
1046 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
1047 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
1049 /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
1050 * We configure only GPMC CS0 with required values. Configiring other devices
1051 * at other CS is done in u-boot. So we don't have to bother doing it here.
1053 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
1056 #ifdef CFG_NAND_K9F1G08R0A
1057 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
1058 __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
1059 __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
1060 __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
1061 __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
1062 __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
1063 __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
1065 /* Enable the GPMC Mapping */
1066 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
1067 ((NAND_BASE_ADR>>24) & 0x3F) |
1068 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
1073 printf("Unsupported Chip!\n");
1081 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
1082 __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
1083 __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
1084 __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
1085 __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
1086 __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
1087 __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
1089 /* Enable the GPMC Mapping */
1090 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
1091 ((ONENAND_BASE>>24) & 0x3F) |
1092 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
1095 if (onenand_chip()) {
1097 printf("OneNAND Unsupported !\n");
1107 /* optionally do something like blinking LED */
1108 void board_hang(void)
1114 /******************************************************************************
1115 * Dummy function to handle errors for EABI incompatibility
1116 *****************************************************************************/
1121 /******************************************************************************
1122 * Dummy function to handle errors for EABI incompatibility
1123 *****************************************************************************/