2 * (C) Copyright 2004-2009
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/arch/cpu.h>
26 #include <asm/arch/bits.h>
27 #include <asm/arch/mux.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/sys_info.h>
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/mem.h>
33 #if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
34 #include <linux/mtd/nand_legacy.h>
37 /* EMIF and DMM registers */
38 #define EMIF1_BASE 0x4c000000
39 #define EMIF2_BASE 0x4d000000
40 #define DMM_BASE 0x4e000000
42 #define EMIF_MOD_ID_REV 0x0000
43 #define EMIF_STATUS 0x0004
44 #define EMIF_SDRAM_CONFIG 0x0008
45 #define EMIF_LPDDR2_NVM_CONFIG 0x000C
46 #define EMIF_SDRAM_REF_CTRL 0x0010
47 #define EMIF_SDRAM_REF_CTRL_SHDW 0x0014
48 #define EMIF_SDRAM_TIM_1 0x0018
49 #define EMIF_SDRAM_TIM_1_SHDW 0x001C
50 #define EMIF_SDRAM_TIM_2 0x0020
51 #define EMIF_SDRAM_TIM_2_SHDW 0x0024
52 #define EMIF_SDRAM_TIM_3 0x0028
53 #define EMIF_SDRAM_TIM_3_SHDW 0x002C
54 #define EMIF_LPDDR2_NVM_TIM 0x0030
55 #define EMIF_LPDDR2_NVM_TIM_SHDW 0x0034
56 #define EMIF_PWR_MGMT_CTRL 0x0038
57 #define EMIF_PWR_MGMT_CTRL_SHDW 0x003C
58 #define EMIF_LPDDR2_MODE_REG_DATA 0x0040
59 #define EMIF_LPDDR2_MODE_REG_CFG 0x0050
60 #define EMIF_L3_CONFIG 0x0054
61 #define EMIF_L3_CFG_VAL_1 0x0058
62 #define EMIF_L3_CFG_VAL_2 0x005C
63 #define IODFT_TLGC 0x0060
64 #define EMIF_PERF_CNT_1 0x0080
65 #define EMIF_PERF_CNT_2 0x0084
66 #define EMIF_PERF_CNT_CFG 0x0088
67 #define EMIF_PERF_CNT_SEL 0x008C
68 #define EMIF_PERF_CNT_TIM 0x0090
69 #define EMIF_READ_IDLE_CTRL 0x0098
70 #define EMIF_READ_IDLE_CTRL_SHDW 0x009c
71 #define EMIF_ZQ_CONFIG 0x00C8
72 #define EMIF_DDR_PHY_CTRL_1 0x00E4
73 #define EMIF_DDR_PHY_CTRL_1_SHDW 0x00E8
74 #define EMIF_DDR_PHY_CTRL_2 0x00EC
76 #define DMM_LISA_MAP_0 0x0040
77 #define DMM_LISA_MAP_1 0x0044
78 #define DMM_LISA_MAP_2 0x0048
79 #define DMM_LISA_MAP_3 0x004C
87 #define REF_EN 0x40000000
106 #define MR1_VALUE ((MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3) \
109 /* defines for MR2 */
110 #define MR2_RL3_WL1 1
111 #define MR2_RL4_WL2 2
112 #define MR2_RL5_WL2 3
113 #define MR2_RL6_WL3 4
115 /* defines for MR10 */
116 #define MR10_ZQINIT 0xFF
117 #define MR10_ZQRESET 0xC3
118 #define MR10_ZQCL 0xAB
119 #define MR10_ZQCS 0x56
122 /* TODO: FREQ update method is not working so shadow registers programming
123 * is just for same of completeness. This would be safer if auto
124 * trasnitions are working
126 #define FREQ_UPDATE_EMIF
127 /* EMIF Needs to be configured@19.2 MHz and shadow registers
128 * should be programmed for new OPP.
131 #define SDRAM_CONFIG_INIT 0x80800EB1
132 #define DDR_PHY_CTRL_1_INIT 0x849FFFF5
133 #define READ_IDLE_CTRL 0x000501FF
134 #define PWR_MGMT_CTRL 0x4000000f
135 #define PWR_MGMT_CTRL_OPP100 0x4000000f
136 #define ZQ_CONFIG 0x500b3215
138 #define CS1_MR(mr) ((mr) | 0x80000000)
151 const struct ddr_regs ddr_regs_380_mhz = {
155 .phy_ctrl_1 = 0x849FF408,
156 .ref_ctrl = 0x000005ca,
157 .config_init = 0x80000eb1,
158 .config_final = 0x80001ab1,
159 .zq_config = 0x500b3215,
165 * Unused timings - but we may need them later
166 * Keep them commented
169 const struct ddr_regs ddr_regs_400_mhz = {
173 .phy_ctrl_1 = 0x849FF408,
174 .ref_ctrl = 0x00000618,
175 .config_init = 0x80000eb1,
176 .config_final = 0x80001ab1,
177 .zq_config = 0x500b3215,
182 const struct ddr_regs ddr_regs_200_mhz = {
186 .phy_ctrl_1 = 0x849FF405,
187 .ref_ctrl = 0x0000030c,
188 .config_init = 0x80000eb1,
189 .config_final = 0x80000eb1,
190 .zq_config = 0x500b3215,
196 const struct ddr_regs ddr_regs_200_mhz_2cs = {
200 .phy_ctrl_1 = 0x849FF405,
201 .ref_ctrl = 0x0000030c,
202 .config_init = 0x80000eb9,
203 .config_final = 0x80000eb9,
204 .zq_config = 0xD00b3215,
209 const struct ddr_regs ddr_regs_400_mhz_2cs = {
210 /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/
214 .phy_ctrl_1 = 0x849FF408,
215 .ref_ctrl = 0x00000618,
216 .config_init = 0x80000eb9,
217 .config_final = 0x80001ab9,
218 .zq_config = 0xD00b3215,
223 /*******************************************************
225 * Description: spinning delay to use before udelay works
226 ******************************************************/
227 static inline void delay(unsigned long loops)
229 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
230 "bne 1b" : "=r" (loops) : "0"(loops));
234 void big_delay(unsigned int count)
237 for (i = 0; i < count; i++)
241 void reset_phy(unsigned int base)
243 __raw_writel(__raw_readl(base + IODFT_TLGC) | (1 << 10),
247 /* TODO: FREQ update method is not working so shadow registers programming
248 * is just for same of completeness. This would be safer if auto
249 * trasnitions are working
251 static int emif_config(unsigned int base)
253 unsigned int reg_value, rev;
254 const struct ddr_regs *ddr_regs = NULL;
255 rev = omap_revision();
257 if (rev == OMAP4430_ES1_0)
258 ddr_regs = &ddr_regs_380_mhz;
259 else if (rev == OMAP4430_ES2_0)
260 ddr_regs = &ddr_regs_200_mhz_2cs;
261 else if (rev >= OMAP4430_ES2_1)
262 ddr_regs = &ddr_regs_400_mhz_2cs;
265 * set SDRAM CONFIG register
266 * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
267 * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0
268 * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3
269 * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks
270 * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0
271 * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2 - 512- 9 column
272 * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8
274 __raw_writel(__raw_readl(base + EMIF_LPDDR2_NVM_CONFIG) & 0xbfffffff,
275 base + EMIF_LPDDR2_NVM_CONFIG);
276 __raw_writel(ddr_regs->config_init, base + EMIF_SDRAM_CONFIG);
278 /* PHY control values */
279 __raw_writel(DDR_PHY_CTRL_1_INIT, base + EMIF_DDR_PHY_CTRL_1);
280 __raw_writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1_SHDW);
283 * EMIF_READ_IDLE_CTRL
285 __raw_writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
286 __raw_writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
291 __raw_writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1);
292 __raw_writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1_SHDW);
297 __raw_writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2);
298 __raw_writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2_SHDW);
303 __raw_writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3);
304 __raw_writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3_SHDW);
306 __raw_writel(ddr_regs->zq_config, base + EMIF_ZQ_CONFIG);
311 //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL) = PWR_MGMT_CTRL;
312 //*(volatile int*)(base + EMIF_PWR_MGMT_CTRL_SHDW) = PWR_MGMT_CTRL_OPP100;
314 * poll MR0 register (DAI bit)
315 * REG_CS[31] = 0 -- Mode register command to CS0
316 * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW
317 * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW
320 __raw_writel(MR0_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
323 reg_value = __raw_readl(base + EMIF_LPDDR2_MODE_REG_DATA);
324 } while (reg_value & 1);
326 __raw_writel(CS1_MR(MR0_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
329 reg_value = __raw_readl(base + EMIF_LPDDR2_MODE_REG_DATA);
330 } while (reg_value & 1);
333 /* set MR10 register */
334 __raw_writel(MR10_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
335 __raw_writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
336 __raw_writel(CS1_MR(MR10_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
337 __raw_writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
339 /* wait for tZQINIT=1us */
342 /* set MR1 register */
343 __raw_writel(MR1_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
344 __raw_writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
345 __raw_writel(CS1_MR(MR1_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
346 __raw_writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
348 /* set MR2 register RL=6 for OPP100 */
349 __raw_writel(MR2_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
350 __raw_writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
351 __raw_writel(CS1_MR(MR2_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
352 __raw_writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
354 /* Set SDRAM CONFIG register again here with final RL-WL value */
355 __raw_writel(ddr_regs->config_final, base + EMIF_SDRAM_CONFIG);
356 __raw_writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1);
359 * EMIF_SDRAM_REF_CTRL
360 * refresh rate = DDR_CLK / reg_refresh_rate
361 * 3.9 uS = (400MHz) / reg_refresh_rate
363 __raw_writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL);
364 __raw_writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL_SHDW);
366 /* set MR16 register */
367 __raw_writel(MR16_ADDR | REF_EN, base + EMIF_LPDDR2_MODE_REG_CFG);
368 __raw_writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
369 __raw_writel(CS1_MR(MR16_ADDR | REF_EN),
370 base + EMIF_LPDDR2_MODE_REG_CFG);
371 __raw_writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
373 /* LPDDR2 init complete */
377 /*****************************************
379 * Description: Configure DDR
380 * EMIF1 -- CS0 -- DDR1 (256 MB)
381 * EMIF2 -- CS0 -- DDR2 (256 MB)
382 *****************************************/
383 static void ddr_init(void)
385 unsigned int base_addr, rev;
386 rev = omap_revision();
388 if (rev == OMAP4430_ES1_0) {
389 /* Configurte the Control Module DDRIO device */
390 __raw_writel(0x1c1c1c1c, 0x4A100638);
391 __raw_writel(0x1c1c1c1c, 0x4A10063c);
392 __raw_writel(0x1c1c1c1c, 0x4A100640);
393 __raw_writel(0x1c1c1c1c, 0x4A100648);
394 __raw_writel(0x1c1c1c1c, 0x4A10064c);
395 __raw_writel(0x1c1c1c1c, 0x4A100650);
396 /* LPDDR2IO set to NMOS PTV */
397 __raw_writel(0x00ffc000, 0x4A100704);
398 } else if (rev == OMAP4430_ES2_0) {
399 __raw_writel(0x9e9e9e9e, 0x4A100638);
400 __raw_writel(0x9e9e9e9e, 0x4A10063c);
401 __raw_writel(0x9e9e9e9e, 0x4A100640);
402 __raw_writel(0x9e9e9e9e, 0x4A100648);
403 __raw_writel(0x9e9e9e9e, 0x4A10064c);
404 __raw_writel(0x9e9e9e9e, 0x4A100650);
405 /* LPDDR2IO set to NMOS PTV */
406 __raw_writel(0x00ffc000, 0x4A100704);
413 /* Both EMIFs 128 byte interleaved*/
414 if (rev == OMAP4430_ES1_0)
415 __raw_writel(0x80540300, DMM_BASE + DMM_LISA_MAP_0);
417 __raw_writel(0x80640300, DMM_BASE + DMM_LISA_MAP_0);
419 /* EMIF2 only at 0x90000000 */
420 //*(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x90400200;
422 __raw_writel(0x00000000, DMM_BASE + DMM_LISA_MAP_2);
423 __raw_writel(0xFF020100, DMM_BASE + DMM_LISA_MAP_3);
425 /* DDR needs to be initialised @ 19.2 MHz
426 * So put core DPLL in bypass mode
427 * Configure the Core DPLL but don't lock it
429 configure_core_dpll_no_lock();
431 /* No IDLE: BUG in SDC */
432 /* sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
433 while(((*(volatile int *)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
435 __raw_writel(0, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
436 __raw_writel(0, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
439 base_addr = EMIF1_BASE;
440 emif_config(base_addr);
442 /* Configure EMIF24D */
443 base_addr = EMIF2_BASE;
444 emif_config(base_addr);
445 /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */
446 lock_core_dpll_shadow();
447 /* TODO: SDC needs few hacks to get DDR freq update working */
449 /* Set DLL_OVERRIDE = 0 */
450 __raw_writel(0, CM_DLL_CTRL);
454 /* Check for DDR PHY ready for EMIF1 & EMIF2 */
455 while (!(__raw_readl(EMIF1_BASE + EMIF_STATUS) & 4) ||
456 !(__raw_readl(EMIF2_BASE + EMIF_STATUS) & 4))
459 /* Reprogram the DDR PYHY Control register */
460 /* PHY control values */
462 sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
463 sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
465 /* Put the Core Subsystem PD to ON State */
467 /* No IDLE: BUG in SDC */
468 /* sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
469 while(((*(volatile int *)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
471 __raw_writel(0x80000000, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
472 __raw_writel(0x80000000, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
475 * In n a specific situation, the OCP interface between the DMM and
477 * 1. A TILER port is used to perform 2D burst writes of
478 * width 1 and height 8
479 * 2. ELLAn port is used to perform reads
480 * 3. All accesses are routed to the same EMIF controller
482 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
483 * be kept higher than default 0x7. As per recommondation 0x0A will
484 * be used for better performance with REG_LL_THRESH_MAX = 0x00
486 if (rev == OMAP4430_ES1_0) {
487 __raw_writel(0x0A0000FF, EMIF1_BASE + EMIF_L3_CONFIG);
488 __raw_writel(0x0A0000FF, EMIF2_BASE + EMIF_L3_CONFIG);
492 * DMM : DMM_LISA_MAP_0(Section_0)
493 * [31:24] SYS_ADDR 0x80
494 * [22:20] SYS_SIZE 0x7 - 2Gb
495 * [19:18] SDRC_INTLDMM 0x1 - 128 byte
496 * [17:16] SDRC_ADDRSPC 0x0
498 * [7:0] SDRC_ADDR 0X0
500 reset_phy(EMIF1_BASE);
501 reset_phy(EMIF2_BASE);
503 __raw_writel(0, 0x80000000);
504 __raw_writel(0, 0x80000000);
506 /* *((volatile int *)0x90000000) = 0; */
508 /*****************************************
509 * Routine: board_init
510 * Description: Early hardware init.
511 *****************************************/
517 /*************************************************************
518 * Routine: get_mem_type(void) - returns the kind of memory connected
519 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
520 *************************************************************/
521 u32 get_mem_type(void)
523 /* no nand, so return GPMC_NONE */
527 /*****************************************
528 * Routine: secure_unlock
529 * Description: Setup security registers for access
531 *****************************************/
532 void secure_unlock_mem(void)
534 /* Permission values for registers -Full fledged permissions to all */
535 #define UNLOCK_1 0xFFFFFFFF
536 #define UNLOCK_2 0x00000000
537 #define UNLOCK_3 0x0000FFFF
539 /* Protection Module Register Target APE (PM_RT)*/
540 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
541 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
542 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
543 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
545 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
546 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
547 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
549 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
550 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
551 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
552 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
555 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
556 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
557 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
559 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
562 /**********************************************************
563 * Routine: try_unlock_sram()
564 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
566 ***********************************************************/
567 void try_unlock_memory(void)
569 /* if GP device unlock device SRAM for general use */
570 /* secure code breaks for Secure/Emulation device - HS/E/T*/
574 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
575 static int scale_vcores(void)
577 unsigned int rev = omap_revision();
578 /* For VC bypass only VCOREx_CGF_FORCE is necessary and
579 * VCOREx_CFG_VOLTAGE changes can be discarded
581 /* PRM_VC_CFG_I2C_MODE */
582 __raw_writel(0, 0x4A307BA8);
584 /* PRM_VC_CFG_I2C_CLK */
585 __raw_writel(0x6026, 0x4A307BAC);
587 /* set VCORE1 force VSEL */
588 /* PRM_VC_VAL_BYPASS) */
589 if (rev == OMAP4430_ES1_0)
590 __raw_writel(0x3B5512, 0x4A307BA0);
592 __raw_writel(0x3A5512, 0x4A307BA0);
594 __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
595 while (__raw_readl(0x4A307BA0) & 0x1000000)
598 /* PRM_IRQSTATUS_MPU */
599 __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
601 /* FIXME: set VCORE2 force VSEL, Check the reset value */
602 /* PRM_VC_VAL_BYPASS) */
603 if (rev == OMAP4430_ES1_0)
604 __raw_writel(0x315B12, 0x4A307BA0);
606 __raw_writel(0x295B12, 0x4A307BA0);
608 __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
609 while (__raw_readl(0x4A307BA0) & 0x1000000)
612 /* PRM_IRQSTATUS_MPU */
613 __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
615 /*/set VCORE3 force VSEL */
616 /* PRM_VC_VAL_BYPASS */
619 __raw_writel(0x316112, 0x4A307BA0);
622 __raw_writel(0x296112, 0x4A307BA0);
625 __raw_writel(0x2A6112, 0x4A307BA0);
628 __raw_writel(__raw_readl(0x4A307BA0) | 0x1000000, 0x4A307BA0);
629 while (__raw_readl(0x4A307BA0) & 0x1000000)
632 /* PRM_IRQSTATUS_MPU */
633 __raw_writel(__raw_readl(0x4A306010), 0x4A306010);
639 /**********************************************************
641 * Description: Does early system init of muxing and clocks.
642 * - Called path is with SRAM stack.
643 **********************************************************/
647 unsigned int rev = omap_revision();
652 /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */
653 /* Currently SMI in Kernel on ES2 devices seems to have an isse
654 * Once that is resolved, we can postpone this config to kernel
656 /* setup_auxcr(get_device_type(), external_boot); */
660 /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
661 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
666 if (rev != OMAP4430_ES1_0) {
667 if (__raw_readl(0x4805D138) & (1<<22)) {
668 /* enable software ioreq */
669 sr32(0x4A30a31C, 8, 1, 0x1);
670 /* set for sys_clk (38.4MHz) */
671 sr32(0x4A30a31C, 1, 2, 0x0);
672 /* set divisor to 2 */
673 sr32(0x4A30a31C, 16, 4, 0x1);
674 /* set the clock source to active */
675 sr32(0x4A30a110, 0, 1, 0x1);
677 sr32(0x4A30a110, 2, 2, 0x3);
679 /* enable software ioreq */
680 sr32(0x4A30a314, 8, 1, 0x1);
681 /* set for PER_DPLL */
682 sr32(0x4A30a314, 1, 2, 0x2);
683 /* set divisor to 16 */
684 sr32(0x4A30a314, 16, 4, 0xf);
685 /* set the clock source to active */
686 sr32(0x4A30a110, 0, 1, 0x1);
688 sr32(0x4A30a110, 2, 2, 0x3);
694 /*******************************************************
695 * Routine: misc_init_r
696 * Description: Init ethernet (done here so udelay works)
697 ********************************************************/
698 int misc_init_r(void)
703 /******************************************************
704 * Routine: wait_for_command_complete
705 * Description: Wait for posting to finish on watchdog
706 ******************************************************/
707 void wait_for_command_complete(unsigned int wd_base)
711 pending = __raw_readl(wd_base + WWPS);
715 /*******************************************************************
717 * Description: take the Ethernet controller out of reset and wait
718 * for the EEPROM load to complete.
719 ******************************************************************/
721 /**********************************************
723 * Description: sets uboots idea of sdram size
724 **********************************************/
730 #define OMAP44XX_WKUP_CTRL_BASE 0x4A31E000
750 #define MV(OFFSET, VALUE)\
751 __raw_writew((VALUE), OMAP44XX_CTRL_BASE + (OFFSET));
752 #define MV1(OFFSET, VALUE)\
753 __raw_writew((VALUE), OMAP44XX_WKUP_CTRL_BASE + (OFFSET));
755 #define CP(x) (CONTROL_PADCONF_##x)
756 #define WK(x) (CONTROL_WKUP_##x)
759 * IDIS - Input Disable
760 * PTD - Pull type Down
762 * DIS - Pull type selection is inactive
763 * EN - Pull type selection is active
765 * The commented string gives the final mux configuration for that pin
768 #define MUX_DEFAULT_OMAP4() \
769 MV(CP(GPMC_AD0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \
770 MV(CP(GPMC_AD1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \
771 MV(CP(GPMC_AD2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \
772 MV(CP(GPMC_AD3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \
773 MV(CP(GPMC_AD4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \
774 MV(CP(GPMC_AD5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \
775 MV(CP(GPMC_AD6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \
776 MV(CP(GPMC_AD7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \
777 MV(CP(GPMC_AD8) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \
778 MV(CP(GPMC_AD9) , ( PTU | IEN | M3)) /* gpio_33 */ \
779 MV(CP(GPMC_AD10) , ( PTU | IEN | M3)) /* gpio_34 */ \
780 MV(CP(GPMC_AD11) , ( PTU | IEN | M3)) /* gpio_35 */ \
781 MV(CP(GPMC_AD12) , ( PTU | IEN | M3)) /* gpio_36 */ \
782 MV(CP(GPMC_AD13) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \
783 MV(CP(GPMC_AD14) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \
784 MV(CP(GPMC_AD15) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \
785 MV(CP(GPMC_A16) , ( M3)) /* gpio_40 */ \
786 MV(CP(GPMC_A17) , ( PTD | M3)) /* gpio_41 */ \
787 MV(CP(GPMC_A18) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \
788 MV(CP(GPMC_A19) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \
789 MV(CP(GPMC_A20) , ( IEN | M3)) /* gpio_44 */ \
790 MV(CP(GPMC_A21) , ( M3)) /* gpio_45 */ \
791 MV(CP(GPMC_A22) , ( M3)) /* gpio_46 */ \
792 MV(CP(GPMC_A23) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \
793 MV(CP(GPMC_A24) , ( PTD | M3)) /* gpio_48 */ \
794 MV(CP(GPMC_A25) , ( PTD | M3)) /* gpio_49 */ \
795 MV(CP(GPMC_NCS0) , ( M3)) /* gpio_50 */ \
796 MV(CP(GPMC_NCS1) , ( IEN | M3)) /* gpio_51 */ \
797 MV(CP(GPMC_NCS2) , ( IEN | M3)) /* gpio_52 */ \
798 MV(CP(GPMC_NCS3) , ( IEN | M3)) /* gpio_53 */ \
799 MV(CP(GPMC_NWP) , ( M3)) /* gpio_54 */ \
800 MV(CP(GPMC_CLK) , ( PTD | M3)) /* gpio_55 */ \
801 MV(CP(GPMC_NADV_ALE) , ( M3)) /* gpio_56 */ \
802 MV(CP(GPMC_NOE) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \
803 MV(CP(GPMC_NWE) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \
804 MV(CP(GPMC_NBE0_CLE) , ( M3)) /* gpio_59 */ \
805 MV(CP(GPMC_NBE1) , ( PTD | M3)) /* gpio_60 */ \
806 MV(CP(GPMC_WAIT0) , ( PTU | IEN | M3)) /* gpio_61 */ \
807 MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_62 */ \
808 MV(CP(C2C_DATA11) , ( PTD | M3)) /* gpio_100 */ \
809 MV(CP(C2C_DATA12) , ( PTD | IEN | M3)) /* gpio_101 */ \
810 MV(CP(C2C_DATA13) , ( PTD | M3)) /* gpio_102 */ \
811 MV(CP(C2C_DATA14) , ( M1)) /* dsi2_te0 */ \
812 MV(CP(C2C_DATA15) , ( PTD | M3)) /* gpio_104 */ \
813 MV(CP(HDMI_HPD) , ( M0)) /* hdmi_hpd */ \
814 MV(CP(HDMI_CEC) , ( M0)) /* hdmi_cec */ \
815 MV(CP(HDMI_DDC_SCL) , ( PTU | M0)) /* hdmi_ddc_scl */ \
816 MV(CP(HDMI_DDC_SDA) , ( PTU | IEN | M0)) /* hdmi_ddc_sda */ \
817 MV(CP(CSI21_DX0) , ( IEN | M0)) /* csi21_dx0 */ \
818 MV(CP(CSI21_DY0) , ( IEN | M0)) /* csi21_dy0 */ \
819 MV(CP(CSI21_DX1) , ( IEN | M0)) /* csi21_dx1 */ \
820 MV(CP(CSI21_DY1) , ( IEN | M0)) /* csi21_dy1 */ \
821 MV(CP(CSI21_DX2) , ( IEN | M0)) /* csi21_dx2 */ \
822 MV(CP(CSI21_DY2) , ( IEN | M0)) /* csi21_dy2 */ \
823 MV(CP(CSI21_DX3) , ( PTD | M7)) /* csi21_dx3 */ \
824 MV(CP(CSI21_DY3) , ( PTD | M7)) /* csi21_dy3 */ \
825 MV(CP(CSI21_DX4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dx4 */ \
826 MV(CP(CSI21_DY4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7)) /* csi21_dy4 */ \
827 MV(CP(CSI22_DX0) , ( IEN | M0)) /* csi22_dx0 */ \
828 MV(CP(CSI22_DY0) , ( IEN | M0)) /* csi22_dy0 */ \
829 MV(CP(CSI22_DX1) , ( IEN | M0)) /* csi22_dx1 */ \
830 MV(CP(CSI22_DY1) , ( IEN | M0)) /* csi22_dy1 */ \
831 MV(CP(CAM_SHUTTER) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \
832 MV(CP(CAM_STROBE) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \
833 MV(CP(CAM_GLOBALRESET) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \
834 MV(CP(USBB1_ULPITLL_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \
835 MV(CP(USBB1_ULPITLL_STP) , ( OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \
836 MV(CP(USBB1_ULPITLL_DIR) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \
837 MV(CP(USBB1_ULPITLL_NXT) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \
838 MV(CP(USBB1_ULPITLL_DAT0) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \
839 MV(CP(USBB1_ULPITLL_DAT1) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \
840 MV(CP(USBB1_ULPITLL_DAT2) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \
841 MV(CP(USBB1_ULPITLL_DAT3) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \
842 MV(CP(USBB1_ULPITLL_DAT4) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \
843 MV(CP(USBB1_ULPITLL_DAT5) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \
844 MV(CP(USBB1_ULPITLL_DAT6) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \
845 MV(CP(USBB1_ULPITLL_DAT7) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \
846 MV(CP(USBB1_HSIC_DATA) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \
847 MV(CP(USBB1_HSIC_STROBE) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \
848 MV(CP(USBC1_ICUSB_DP) , ( IEN | M0)) /* usbc1_icusb_dp */ \
849 MV(CP(USBC1_ICUSB_DM) , ( IEN | M0)) /* usbc1_icusb_dm */ \
850 MV(CP(SDMMC1_CLK) , ( PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \
851 MV(CP(SDMMC1_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \
852 MV(CP(SDMMC1_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \
853 MV(CP(SDMMC1_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \
854 MV(CP(SDMMC1_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \
855 MV(CP(SDMMC1_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \
856 MV(CP(SDMMC1_DAT4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \
857 MV(CP(SDMMC1_DAT5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \
858 MV(CP(SDMMC1_DAT6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \
859 MV(CP(SDMMC1_DAT7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \
860 MV(CP(ABE_MCBSP2_CLKX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \
861 MV(CP(ABE_MCBSP2_DR) , ( IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \
862 MV(CP(ABE_MCBSP2_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \
863 MV(CP(ABE_MCBSP2_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \
864 MV(CP(ABE_MCBSP1_CLKX) , ( IEN | M1)) /* abe_slimbus1_clock */ \
865 MV(CP(ABE_MCBSP1_DR) , ( IEN | M1)) /* abe_slimbus1_data */ \
866 MV(CP(ABE_MCBSP1_DX) , ( OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \
867 MV(CP(ABE_MCBSP1_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \
868 MV(CP(ABE_PDM_UL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_ul_data */ \
869 MV(CP(ABE_PDM_DL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_dl_data */ \
870 MV(CP(ABE_PDM_FRAME) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_frame */ \
871 MV(CP(ABE_PDM_LB_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_pdm_lb_clk */ \
872 MV(CP(ABE_CLKS) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_clks */ \
873 MV(CP(ABE_DMIC_CLK1) , ( M0)) /* abe_dmic_clk1 */ \
874 MV(CP(ABE_DMIC_DIN1) , ( IEN | M0)) /* abe_dmic_din1 */ \
875 MV(CP(ABE_DMIC_DIN2) , ( IEN | M0)) /* abe_dmic_din2 */ \
876 MV(CP(ABE_DMIC_DIN3) , ( IEN | M0)) /* abe_dmic_din3 */ \
877 MV(CP(UART2_CTS) , ( PTU | IEN | M0)) /* uart2_cts */ \
878 MV(CP(UART2_RTS) , ( M0)) /* uart2_rts */ \
879 MV(CP(UART2_RX) , ( PTU | IEN | M0)) /* uart2_rx */ \
880 MV(CP(UART2_TX) , ( M0)) /* uart2_tx */ \
881 MV(CP(HDQ_SIO) , ( M3)) /* gpio_127 */ \
882 MV(CP(I2C1_SCL) , ( PTU | IEN | M0)) /* i2c1_scl */ \
883 MV(CP(I2C1_SDA) , ( PTU | IEN | M0)) /* i2c1_sda */ \
884 MV(CP(I2C2_SCL) , ( PTU | IEN | M0)) /* i2c2_scl */ \
885 MV(CP(I2C2_SDA) , ( PTU | IEN | M0)) /* i2c2_sda */ \
886 MV(CP(I2C3_SCL) , ( PTU | IEN | M0)) /* i2c3_scl */ \
887 MV(CP(I2C3_SDA) , ( PTU | IEN | M0)) /* i2c3_sda */ \
888 MV(CP(I2C4_SCL) , ( PTU | IEN | M0)) /* i2c4_scl */ \
889 MV(CP(I2C4_SDA) , ( PTU | IEN | M0)) /* i2c4_sda */ \
890 MV(CP(MCSPI1_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \
891 MV(CP(MCSPI1_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \
892 MV(CP(MCSPI1_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \
893 MV(CP(MCSPI1_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \
894 MV(CP(MCSPI1_CS1) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* mcspi1_cs1 */ \
895 MV(CP(MCSPI1_CS2) , ( PTU | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \
896 MV(CP(MCSPI1_CS3) , ( PTU | IEN | M3)) /* gpio_140 */ \
897 MV(CP(UART3_CTS_RCTX) , ( PTU | IEN | M0)) /* uart3_tx */ \
898 MV(CP(UART3_RTS_SD) , ( M0)) /* uart3_rts_sd */ \
899 MV(CP(UART3_RX_IRRX) , ( IEN | M0)) /* uart3_rx */ \
900 MV(CP(UART3_TX_IRTX) , ( M0)) /* uart3_tx */ \
901 MV(CP(SDMMC5_CLK) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \
902 MV(CP(SDMMC5_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \
903 MV(CP(SDMMC5_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \
904 MV(CP(SDMMC5_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \
905 MV(CP(SDMMC5_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \
906 MV(CP(SDMMC5_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \
907 MV(CP(MCSPI4_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \
908 MV(CP(MCSPI4_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \
909 MV(CP(MCSPI4_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \
910 MV(CP(MCSPI4_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \
911 MV(CP(UART4_RX) , ( IEN | M0)) /* uart4_rx */ \
912 MV(CP(UART4_TX) , ( M0)) /* uart4_tx */ \
913 MV(CP(USBB2_ULPITLL_CLK) , ( IEN | M3)) /* gpio_157 */ \
914 MV(CP(USBB2_ULPITLL_STP) , ( IEN | M5)) /* dispc2_data23 */ \
915 MV(CP(USBB2_ULPITLL_DIR) , ( IEN | M5)) /* dispc2_data22 */ \
916 MV(CP(USBB2_ULPITLL_NXT) , ( IEN | M5)) /* dispc2_data21 */ \
917 MV(CP(USBB2_ULPITLL_DAT0) , ( IEN | M5)) /* dispc2_data20 */ \
918 MV(CP(USBB2_ULPITLL_DAT1) , ( IEN | M5)) /* dispc2_data19 */ \
919 MV(CP(USBB2_ULPITLL_DAT2) , ( IEN | M5)) /* dispc2_data18 */ \
920 MV(CP(USBB2_ULPITLL_DAT3) , ( IEN | M5)) /* dispc2_data15 */ \
921 MV(CP(USBB2_ULPITLL_DAT4) , ( IEN | M5)) /* dispc2_data14 */ \
922 MV(CP(USBB2_ULPITLL_DAT5) , ( IEN | M5)) /* dispc2_data13 */ \
923 MV(CP(USBB2_ULPITLL_DAT6) , ( IEN | M5)) /* dispc2_data12 */ \
924 MV(CP(USBB2_ULPITLL_DAT7) , ( IEN | M5)) /* dispc2_data11 */ \
925 MV(CP(USBB2_HSIC_DATA) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \
926 MV(CP(USBB2_HSIC_STROBE) , ( PTD | OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \
927 MV(CP(UNIPRO_TX0) , ( PTD | IEN | M3)) /* gpio_171 */ \
928 MV(CP(UNIPRO_TY0) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \
929 MV(CP(UNIPRO_TX1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \
930 MV(CP(UNIPRO_TY1) , ( OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \
931 MV(CP(UNIPRO_TX2) , ( PTU | IEN | M3)) /* gpio_0 */ \
932 MV(CP(UNIPRO_TY2) , ( PTU | IEN | M3)) /* gpio_1 */ \
933 MV(CP(UNIPRO_RX0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \
934 MV(CP(UNIPRO_RY0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \
935 MV(CP(UNIPRO_RX1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \
936 MV(CP(UNIPRO_RY1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \
937 MV(CP(UNIPRO_RX2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \
938 MV(CP(UNIPRO_RY2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \
939 MV(CP(USBA0_OTG_CE) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \
940 MV(CP(USBA0_OTG_DP) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \
941 MV(CP(USBA0_OTG_DM) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \
942 MV(CP(FREF_CLK1_OUT) , ( M0)) /* fref_clk1_out */ \
943 MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3)) /* gpio_182 */ \
944 MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0)) /* sys_nirq1 */ \
945 MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0)) /* sys_nirq2 */ \
946 MV(CP(SYS_BOOT0) , ( PTU | IEN | M3)) /* gpio_184 */ \
947 MV(CP(SYS_BOOT1) , ( M3)) /* gpio_185 */ \
948 MV(CP(SYS_BOOT2) , ( PTD | IEN | M3)) /* gpio_186 */ \
949 MV(CP(SYS_BOOT3) , ( M3)) /* gpio_187 */ \
950 MV(CP(SYS_BOOT4) , ( M3)) /* gpio_188 */ \
951 MV(CP(SYS_BOOT5) , ( PTD | IEN | M3)) /* gpio_189 */ \
952 MV(CP(DPM_EMU0) , ( IEN | M0)) /* dpm_emu0 */ \
953 MV(CP(DPM_EMU1) , ( IEN | M0)) /* dpm_emu1 */ \
954 MV(CP(DPM_EMU2) , ( IEN | M0)) /* dpm_emu2 */ \
955 MV(CP(DPM_EMU3) , ( IEN | M5)) /* dispc2_data10 */ \
956 MV(CP(DPM_EMU4) , ( IEN | M5)) /* dispc2_data9 */ \
957 MV(CP(DPM_EMU5) , ( IEN | M5)) /* dispc2_data16 */ \
958 MV(CP(DPM_EMU6) , ( IEN | M5)) /* dispc2_data17 */ \
959 MV(CP(DPM_EMU7) , ( IEN | M5)) /* dispc2_hsync */ \
960 MV(CP(DPM_EMU8) , ( IEN | M5)) /* dispc2_pclk */ \
961 MV(CP(DPM_EMU9) , ( IEN | M5)) /* dispc2_vsync */ \
962 MV(CP(DPM_EMU10) , ( IEN | M5)) /* dispc2_de */ \
963 MV(CP(DPM_EMU11) , ( IEN | M5)) /* dispc2_data8 */ \
964 MV(CP(DPM_EMU12) , ( IEN | M5)) /* dispc2_data7 */ \
965 MV(CP(DPM_EMU13) , ( IEN | M5)) /* dispc2_data6 */ \
966 MV(CP(DPM_EMU14) , ( IEN | M5)) /* dispc2_data5 */ \
967 MV(CP(DPM_EMU15) , ( IEN | M5)) /* dispc2_data4 */ \
968 MV(CP(DPM_EMU16) , ( M3)) /* gpio_27 */ \
969 MV(CP(DPM_EMU17) , ( IEN | M5)) /* dispc2_data2 */ \
970 MV(CP(DPM_EMU18) , ( IEN | M5)) /* dispc2_data1 */ \
971 MV(CP(DPM_EMU19) , ( IEN | M5)) /* dispc2_data0 */ \
972 MV1(WK(PAD0_SIM_IO) , ( IEN | M0)) /* sim_io */ \
973 MV1(WK(PAD1_SIM_CLK) , ( M0)) /* sim_clk */ \
974 MV1(WK(PAD0_SIM_RESET) , ( M0)) /* sim_reset */ \
975 MV1(WK(PAD1_SIM_CD) , ( PTU | IEN | M0)) /* sim_cd */ \
976 MV1(WK(PAD0_SIM_PWRCTRL) , ( M0)) /* sim_pwrctrl */ \
977 MV1(WK(PAD1_SR_SCL) , ( PTU | IEN | M0)) /* sr_scl */ \
978 MV1(WK(PAD0_SR_SDA) , ( PTU | IEN | M0)) /* sr_sda */ \
979 MV1(WK(PAD1_FREF_XTAL_IN) , ( M0)) /* # */ \
980 MV1(WK(PAD0_FREF_SLICER_IN) , ( M0)) /* fref_slicer_in */ \
981 MV1(WK(PAD1_FREF_CLK_IOREQ) , ( M0)) /* fref_clk_ioreq */ \
982 MV1(WK(PAD0_FREF_CLK0_OUT) , ( M2)) /* sys_drm_msecure */ \
983 MV1(WK(PAD1_FREF_CLK3_REQ) , ( PTU | IEN | M0)) /* # */ \
984 MV1(WK(PAD0_FREF_CLK3_OUT) , ( M0)) /* fref_clk3_out */ \
985 MV1(WK(PAD1_FREF_CLK4_REQ) , ( PTU | IEN | M0)) /* # */ \
986 MV1(WK(PAD0_FREF_CLK4_OUT) , ( M0)) /* # */ \
987 MV1(WK(PAD1_SYS_32K) , ( IEN | M0)) /* sys_32k */ \
988 MV1(WK(PAD0_SYS_NRESPWRON) , ( M0)) /* sys_nrespwron */ \
989 MV1(WK(PAD1_SYS_NRESWARM) , ( M0)) /* sys_nreswarm */ \
990 MV1(WK(PAD0_SYS_PWR_REQ) , ( PTU | M0)) /* sys_pwr_req */ \
991 MV1(WK(PAD1_SYS_PWRON_RESET) , ( M3)) /* gpio_wk29 */ \
992 MV1(WK(PAD0_SYS_BOOT6) , ( IEN | M3)) /* gpio_wk9 */ \
993 MV1(WK(PAD1_SYS_BOOT7) , ( IEN | M3)) /* gpio_wk10 */ \
994 MV1(WK(PAD1_FREF_CLK3_REQ), (M3)) /* gpio_wk30 */ \
995 MV1(WK(PAD1_FREF_CLK4_REQ), (M3)) /* gpio_wk7 */ \
996 MV1(WK(PAD0_FREF_CLK4_OUT), (M3)) /* gpio_wk8 */
998 #define MUX_DEFAULT_OMAP4_ALL() \
999 MV(CP(GPMC_AD0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \
1000 MV(CP(GPMC_AD1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \
1001 MV(CP(GPMC_AD2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \
1002 MV(CP(GPMC_AD3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \
1003 MV(CP(GPMC_AD4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \
1004 MV(CP(GPMC_AD5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \
1005 MV(CP(GPMC_AD6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \
1006 MV(CP(GPMC_AD7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \
1007 MV(CP(GPMC_AD8), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \
1008 MV(CP(GPMC_AD9), (M3_SAFE)) /* gpio_33 */ \
1009 MV(CP(GPMC_AD10), (M3_SAFE)) /* gpio_34 */ \
1010 MV(CP(GPMC_AD11), (M3_SAFE)) /* gpio_35 */ \
1011 MV(CP(GPMC_AD12), (M3_SAFE)) /* gpio_36 */ \
1012 MV(CP(GPMC_AD13), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \
1013 MV(CP(GPMC_AD14), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \
1014 MV(CP(GPMC_AD15), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \
1015 MV(CP(GPMC_A16), (M3_SAFE)) /* gpio_40 */ \
1016 MV(CP(GPMC_A17), (M3_SAFE)) /* gpio_41 */ \
1017 MV(CP(GPMC_A18), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \
1018 MV(CP(GPMC_A19), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \
1019 MV(CP(GPMC_A20), (M3_SAFE)) /* gpio_44 */ \
1020 MV(CP(GPMC_A21), (M3_SAFE)) /* gpio_45 */ \
1021 MV(CP(GPMC_A22), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col6 */ \
1022 MV(CP(GPMC_A23), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \
1023 MV(CP(GPMC_A24), (M3_SAFE)) /* gpio_48 */ \
1024 MV(CP(GPMC_A25), (M3_SAFE)) /* gpio_49 */ \
1025 MV(CP(GPMC_NCS0), (M0)) /* gpmc_ncs0 */ \
1026 MV(CP(GPMC_NCS1), (M3_SAFE)) /* gpio_51 */ \
1027 MV(CP(GPMC_NCS2), (M3_SAFE)) /* gpio_52 */ \
1028 MV(CP(GPMC_NCS3), (M3_SAFE)) /* gpio_53 */ \
1029 MV(CP(GPMC_NWP), (M0_SAFE)) /* gpmc_nwp */ \
1030 MV(CP(GPMC_CLK), (M3_SAFE)) /* gpio_55 */ \
1031 MV(CP(GPMC_NADV_ALE), (M0)) /* gpmc_nadv_ale */ \
1032 MV(CP(GPMC_NOE), (PTU | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \
1033 MV(CP(GPMC_NWE), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \
1034 MV(CP(GPMC_NBE0_CLE), (M0)) /* gpmc_nbe0_cle*/ \
1035 MV(CP(GPMC_NBE1), (M3_SAFE)) /* gpio_60 */ \
1036 MV(CP(GPMC_WAIT0), (M0)) /* gpmc_wait */ \
1037 MV(CP(GPMC_WAIT1), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \
1038 MV(CP(C2C_DATA11), (M3_SAFE)) /* gpio_100 */ \
1039 MV(CP(C2C_DATA12), (M1_SAFE)) /* dsi1_te0 */ \
1040 MV(CP(C2C_DATA13), (M3_SAFE)) /* gpio_102 */ \
1041 MV(CP(C2C_DATA14), (M1_SAFE)) /* dsi2_te0 */ \
1042 MV(CP(C2C_DATA15), (M3_SAFE)) /* gpio_104 */ \
1043 MV(CP(HDMI_HPD), (M0_SAFE)) /* hdmi_hpd */ \
1044 MV(CP(HDMI_CEC), (M0_SAFE)) /* hdmi_cec */ \
1045 MV(CP(HDMI_DDC_SCL), (M0_SAFE)) /* hdmi_ddc_scl */ \
1046 MV(CP(HDMI_DDC_SDA), (M0_SAFE)) /* hdmi_ddc_sda */ \
1047 MV(CP(CSI21_DX0), (M0_SAFE)) /* csi21_dx0 */ \
1048 MV(CP(CSI21_DY0), (M0_SAFE)) /* csi21_dy0 */ \
1049 MV(CP(CSI21_DX1), (M0_SAFE)) /* csi21_dx1 */ \
1050 MV(CP(CSI21_DY1), (M0_SAFE)) /* csi21_dy1 */ \
1051 MV(CP(CSI21_DX2), (M0_SAFE)) /* csi21_dx2 */ \
1052 MV(CP(CSI21_DY2), (M0_SAFE)) /* csi21_dy2 */ \
1053 MV(CP(CSI21_DX3), (M0_SAFE)) /* csi21_dx3 */ \
1054 MV(CP(CSI21_DY3), (M0_SAFE)) /* csi21_dy3 */ \
1055 MV(CP(CSI21_DX4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_75 */ \
1056 MV(CP(CSI21_DY4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_76 */ \
1057 MV(CP(CSI22_DX0), (M0_SAFE)) /* csi22_dx0 */ \
1058 MV(CP(CSI22_DY0), (M0_SAFE)) /* csi22_dy0 */ \
1059 MV(CP(CSI22_DX1), (M0_SAFE)) /* csi22_dx1 */ \
1060 MV(CP(CSI22_DY1), (M0_SAFE)) /* csi22_dy1 */ \
1061 MV(CP(CAM_SHUTTER), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \
1062 MV(CP(CAM_STROBE), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \
1063 MV(CP(CAM_GLOBALRESET), (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \
1064 MV(CP(USBB1_ULPITLL_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \
1065 MV(CP(USBB1_ULPITLL_STP), (PTU | OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \
1066 MV(CP(USBB1_ULPITLL_DIR), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \
1067 MV(CP(USBB1_ULPITLL_NXT), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \
1068 MV(CP(USBB1_ULPITLL_DAT0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \
1069 MV(CP(USBB1_ULPITLL_DAT1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \
1070 MV(CP(USBB1_ULPITLL_DAT2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \
1071 MV(CP(USBB1_ULPITLL_DAT3), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \
1072 MV(CP(USBB1_ULPITLL_DAT4), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \
1073 MV(CP(USBB1_ULPITLL_DAT5), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \
1074 MV(CP(USBB1_ULPITLL_DAT6), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \
1075 MV(CP(USBB1_ULPITLL_DAT7), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \
1076 MV(CP(USBB1_HSIC_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \
1077 MV(CP(USBB1_HSIC_STROBE), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \
1078 MV(CP(USBC1_ICUSB_DP), (M0_SAFE)) /* usbc1_icusb_dp */ \
1079 MV(CP(USBC1_ICUSB_DM), (M0_SAFE)) /* usbc1_icusb_dm */ \
1080 MV(CP(SDMMC1_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \
1081 MV(CP(SDMMC1_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \
1082 MV(CP(SDMMC1_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \
1083 MV(CP(SDMMC1_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \
1084 MV(CP(SDMMC1_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \
1085 MV(CP(SDMMC1_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \
1086 MV(CP(SDMMC1_DAT4), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \
1087 MV(CP(SDMMC1_DAT5), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \
1088 MV(CP(SDMMC1_DAT6), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \
1089 MV(CP(SDMMC1_DAT7), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \
1090 MV(CP(ABE_MCBSP2_CLKX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \
1091 MV(CP(ABE_MCBSP2_DR), (IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \
1092 MV(CP(ABE_MCBSP2_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \
1093 MV(CP(ABE_MCBSP2_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \
1094 MV(CP(ABE_MCBSP1_CLKX), (M1_SAFE)) /* abe_slimbus1_clock */ \
1095 MV(CP(ABE_MCBSP1_DR), (M1_SAFE)) /* abe_slimbus1_data */ \
1096 MV(CP(ABE_MCBSP1_DX), (OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \
1097 MV(CP(ABE_MCBSP1_FSX), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \
1098 MV(CP(ABE_PDM_UL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_ul_data */ \
1099 MV(CP(ABE_PDM_DL_DATA), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_dl_data */ \
1100 MV(CP(ABE_PDM_FRAME), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_frame */ \
1101 MV(CP(ABE_PDM_LB_CLK), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_lb_clk */ \
1102 MV(CP(ABE_CLKS), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_clks */ \
1103 MV(CP(ABE_DMIC_CLK1), (M0_SAFE)) /* abe_dmic_clk1 */ \
1104 MV(CP(ABE_DMIC_DIN1), (M0_SAFE)) /* abe_dmic_din1 */ \
1105 MV(CP(ABE_DMIC_DIN2), (M0_SAFE)) /* abe_dmic_din2 */ \
1106 MV(CP(ABE_DMIC_DIN3), (M0_SAFE)) /* abe_dmic_din3 */ \
1107 MV(CP(UART2_CTS), (PTU | IEN | M0)) /* uart2_cts */ \
1108 MV(CP(UART2_RTS), (M0)) /* uart2_rts */ \
1109 MV(CP(UART2_RX), (PTU | IEN | M0)) /* uart2_rx */ \
1110 MV(CP(UART2_TX), (M0)) /* uart2_tx */ \
1111 MV(CP(HDQ_SIO), (M3_SAFE)) /* gpio_127 */ \
1112 MV(CP(I2C1_SCL), (PTU | IEN | M0)) /* i2c1_scl */ \
1113 MV(CP(I2C1_SDA), (PTU | IEN | M0)) /* i2c1_sda */ \
1114 MV(CP(I2C2_SCL), (PTU | IEN | M0)) /* i2c2_scl */ \
1115 MV(CP(I2C2_SDA), (PTU | IEN | M0)) /* i2c2_sda */ \
1116 MV(CP(I2C3_SCL), (PTU | IEN | M0)) /* i2c3_scl */ \
1117 MV(CP(I2C3_SDA), (PTU | IEN | M0)) /* i2c3_sda */ \
1118 MV(CP(I2C4_SCL), (PTU | IEN | M0)) /* i2c4_scl */ \
1119 MV(CP(I2C4_SDA), (PTU | IEN | M0)) /* i2c4_sda */ \
1120 MV(CP(MCSPI1_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \
1121 MV(CP(MCSPI1_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \
1122 MV(CP(MCSPI1_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \
1123 MV(CP(MCSPI1_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \
1124 MV(CP(MCSPI1_CS1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* mcspi1_cs1 */ \
1125 MV(CP(MCSPI1_CS2), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \
1126 MV(CP(MCSPI1_CS3), (M3_SAFE)) /* gpio_140 */ \
1127 MV(CP(UART3_CTS_RCTX), (PTU | IEN | M0)) /* uart3_tx */ \
1128 MV(CP(UART3_RTS_SD), (M0)) /* uart3_rts_sd */ \
1129 MV(CP(UART3_RX_IRRX), (IEN | M0)) /* uart3_rx */ \
1130 MV(CP(UART3_TX_IRTX), (M0)) /* uart3_tx */ \
1131 MV(CP(SDMMC5_CLK), (PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \
1132 MV(CP(SDMMC5_CMD), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \
1133 MV(CP(SDMMC5_DAT0), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \
1134 MV(CP(SDMMC5_DAT1), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \
1135 MV(CP(SDMMC5_DAT2), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \
1136 MV(CP(SDMMC5_DAT3), (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \
1137 MV(CP(MCSPI4_CLK), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \
1138 MV(CP(MCSPI4_SIMO), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \
1139 MV(CP(MCSPI4_SOMI), (IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \
1140 MV(CP(MCSPI4_CS0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \
1141 MV(CP(UART4_RX), (IEN | M0)) /* uart4_rx */ \
1142 MV(CP(UART4_TX), (M0)) /* uart4_tx */ \
1143 MV(CP(USBB2_ULPITLL_CLK), (M3)) /* gpio_157 */ \
1144 MV(CP(USBB2_ULPITLL_STP), (M5)) /* dispc2_data23 */ \
1145 MV(CP(USBB2_ULPITLL_DIR), (M5)) /* dispc2_data22 */ \
1146 MV(CP(USBB2_ULPITLL_NXT), (M5)) /* dispc2_data21 */ \
1147 MV(CP(USBB2_ULPITLL_DAT0), (M5)) /* dispc2_data20 */ \
1148 MV(CP(USBB2_ULPITLL_DAT1), (M5)) /* dispc2_data19 */ \
1149 MV(CP(USBB2_ULPITLL_DAT2), (M5)) /* dispc2_data18 */ \
1150 MV(CP(USBB2_ULPITLL_DAT3), (M5)) /* dispc2_data15 */ \
1151 MV(CP(USBB2_ULPITLL_DAT4), (M5)) /* dispc2_data14 */ \
1152 MV(CP(USBB2_ULPITLL_DAT5), (M5)) /* dispc2_data13 */ \
1153 MV(CP(USBB2_ULPITLL_DAT6), (M5)) /* dispc2_data12 */ \
1154 MV(CP(USBB2_ULPITLL_DAT7), (M5)) /* dispc2_data11 */ \
1155 MV(CP(USBB2_HSIC_DATA), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \
1156 MV(CP(USBB2_HSIC_STROBE), (OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \
1157 MV(CP(UNIPRO_TX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col0 */ \
1158 MV(CP(UNIPRO_TY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \
1159 MV(CP(UNIPRO_TX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \
1160 MV(CP(UNIPRO_TY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \
1161 MV(CP(UNIPRO_TX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_0 */ \
1162 MV(CP(UNIPRO_TY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_1 */ \
1163 MV(CP(UNIPRO_RX0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \
1164 MV(CP(UNIPRO_RY0), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \
1165 MV(CP(UNIPRO_RX1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \
1166 MV(CP(UNIPRO_RY1), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \
1167 MV(CP(UNIPRO_RX2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \
1168 MV(CP(UNIPRO_RY2), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \
1169 MV(CP(USBA0_OTG_CE), (PTU | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \
1170 MV(CP(USBA0_OTG_DP), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \
1171 MV(CP(USBA0_OTG_DM), (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \
1172 MV(CP(FREF_CLK1_OUT), (M0_SAFE)) /* fref_clk1_out */ \
1173 MV(CP(FREF_CLK2_OUT), (M0_SAFE)) /* fref_clk2_out */ \
1174 MV(CP(SYS_NIRQ1), (PTU | IEN | M0)) /* sys_nirq1 */ \
1175 MV(CP(SYS_NIRQ2), (PTU | IEN | M0)) /* sys_nirq2 */ \
1176 MV(CP(SYS_BOOT0), (M3_SAFE)) /* gpio_184 */ \
1177 MV(CP(SYS_BOOT1), (M3_SAFE)) /* gpio_185 */ \
1178 MV(CP(SYS_BOOT2), (M3_SAFE)) /* gpio_186 */ \
1179 MV(CP(SYS_BOOT3), (M3_SAFE)) /* gpio_187 */ \
1180 MV(CP(SYS_BOOT4), (M3_SAFE)) /* gpio_188 */ \
1181 MV(CP(SYS_BOOT5), (M3_SAFE)) /* gpio_189 */ \
1182 MV(CP(DPM_EMU0), (M0_SAFE)) /* dpm_emu0 */ \
1183 MV(CP(DPM_EMU1), (M0_SAFE)) /* dpm_emu1 */ \
1184 MV(CP(DPM_EMU2), (M0_SAFE)) /* dpm_emu2 */ \
1185 MV(CP(DPM_EMU3), (M5)) /* dispc2_data10 */ \
1186 MV(CP(DPM_EMU4), (M5)) /* dispc2_data9 */ \
1187 MV(CP(DPM_EMU5), (M5)) /* dispc2_data16 */ \
1188 MV(CP(DPM_EMU6), (M5)) /* dispc2_data17 */ \
1189 MV(CP(DPM_EMU7), (M5)) /* dispc2_hsync */ \
1190 MV(CP(DPM_EMU8), (M5)) /* dispc2_pclk */ \
1191 MV(CP(DPM_EMU9), (M5)) /* dispc2_vsync */ \
1192 MV(CP(DPM_EMU10), (M5)) /* dispc2_de */ \
1193 MV(CP(DPM_EMU11), (M5)) /* dispc2_data8 */ \
1194 MV(CP(DPM_EMU12), (M5)) /* dispc2_data7 */ \
1195 MV(CP(DPM_EMU13), (M5)) /* dispc2_data6 */ \
1196 MV(CP(DPM_EMU14), (M5)) /* dispc2_data5 */ \
1197 MV(CP(DPM_EMU15), (M5)) /* dispc2_data4 */ \
1198 MV(CP(DPM_EMU16), (M5)) /* dispc2_data3/dmtimer8_pwm_evt */ \
1199 MV(CP(DPM_EMU17), (M5)) /* dispc2_data2 */ \
1200 MV(CP(DPM_EMU18), (M5)) /* dispc2_data1 */ \
1201 MV(CP(DPM_EMU19), (M5)) /* dispc2_data0 */ \
1202 MV1(WK(PAD0_SIM_IO), (M0_SAFE)) /* sim_io */ \
1203 MV1(WK(PAD1_SIM_CLK), (M0_SAFE)) /* sim_clk */ \
1204 MV1(WK(PAD0_SIM_RESET), (M0_SAFE)) /* sim_reset */ \
1205 MV1(WK(PAD1_SIM_CD), (M0_SAFE)) /* sim_cd */ \
1206 MV1(WK(PAD0_SIM_PWRCTRL), (M0_SAFE)) /* sim_pwrctrl */ \
1207 MV1(WK(PAD1_SR_SCL), (PTU | IEN | M0)) /* sr_scl */ \
1208 MV1(WK(PAD0_SR_SDA), (PTU | IEN | M0)) /* sr_sda */ \
1209 MV1(WK(PAD1_FREF_XTAL_IN), (M0_SAFE)) /* # */ \
1210 MV1(WK(PAD0_FREF_SLICER_IN), (M0_SAFE)) /* fref_slicer_in */ \
1211 MV1(WK(PAD1_FREF_CLK_IOREQ), (M0_SAFE)) /* fref_clk_ioreq */ \
1212 MV1(WK(PAD0_FREF_CLK0_OUT), (M0)) /* sys_drm_msecure */ \
1213 MV1(WK(PAD1_FREF_CLK3_REQ), (M0)) /* # */ \
1214 MV1(WK(PAD0_FREF_CLK3_OUT), (M0_SAFE)) /* fref_clk3_out */ \
1215 MV1(WK(PAD1_FREF_CLK4_REQ), (M0_SAFE)) /* # */ \
1216 MV1(WK(PAD0_FREF_CLK4_OUT), (M0_SAFE)) /* # */ \
1217 MV1(WK(PAD1_SYS_32K), (IEN | M0_SAFE)) /* sys_32k */ \
1218 MV1(WK(PAD0_SYS_NRESPWRON), (IEN | M0_SAFE)) /* sys_nrespwron */ \
1219 MV1(WK(PAD1_SYS_NRESWARM), (IEN | M0_SAFE)) /* sys_nreswarm */ \
1220 MV1(WK(PAD0_SYS_PWR_REQ), (M0_SAFE)) /* sys_pwr_req */ \
1221 MV1(WK(PAD1_SYS_PWRON_RESET), (M3_SAFE)) /* gpio_wk29 */ \
1222 MV1(WK(PAD0_SYS_BOOT6), (M3_SAFE)) /* gpio_wk9 */ \
1223 MV1(WK(PAD1_SYS_BOOT7), (M3_SAFE)) /* gpio_wk10 */ \
1224 MV1(WK(PAD1_JTAG_TCK), (IEN | M0)) /* jtag_tck */ \
1225 MV1(WK(PAD0_JTAG_RTCK), (M0)) /* jtag_rtck */ \
1226 MV1(WK(PAD1_JTAG_TMS_TMSC), (IEN | M0)) /* jtag_tms_tmsc */ \
1227 MV1(WK(PAD0_JTAG_TDI), (IEN | M0)) /* jtag_tdi */ \
1228 MV1(WK(PAD1_JTAG_TDO), (M0)) /* jtag_tdo */
1230 /**********************************************************
1231 * Routine: set_muxconf_regs
1232 * Description: Setting up the configuration Mux registers
1233 * specific to the hardware. Many pins need
1234 * to be moved from protect to primary mode.
1235 *********************************************************/
1236 void set_muxconf_regs(void)
1238 MUX_DEFAULT_OMAP4();
1241 /******************************************************************************
1242 * Routine: update_mux()
1243 * Description:Update balls which are different between boards. All should be
1244 * updated to match functionality. However, I'm only updating ones
1245 * which I'll be using for now. When power comes into play they
1246 * all need updating.
1247 *****************************************************************************/
1248 void update_mux(u32 btype, u32 mtype)
1253 /* optionally do something like blinking LED */
1254 void board_hang(void)