board/liebherr/display5/spl.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 DENX Software Engineering
   4  * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <image.h>
  11 #include <serial.h>
  12 #include <spl.h>
  13 #include <linux/libfdt.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/mx6-ddr.h>
  17 #include <asm/arch/mx6-pins.h>
  18 #include "asm/arch/crm_regs.h"
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/imx-regs.h>
  21 #include "asm/arch/iomux.h"
  22 #include <asm/mach-imx/iomux-v3.h>
  23 #include <asm/gpio.h>
  24 #include <fsl_esdhc_imx.h>
  25 #include <netdev.h>
  26 #include <bootcount.h>
  27 #include <watchdog.h>
  28 #include "common.h"
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
  33         .dram_sdclk_0 = 0x00000030,
  34         .dram_sdclk_1 = 0x00000030,
  35         .dram_cas = 0x00000030,
  36         .dram_ras = 0x00000030,
  37         .dram_reset = 0x00000030,
  38         .dram_sdcke0 = 0x00003000,
  39         .dram_sdcke1 = 0x00003000,
  40         .dram_sdba2 = 0x00000000,
  41         .dram_sdodt0 = 0x00000030,
  42         .dram_sdodt1 = 0x00000030,
  43
  44         .dram_sdqs0 = 0x00000030,
  45         .dram_sdqs1 = 0x00000030,
  46         .dram_sdqs2 = 0x00000030,
  47         .dram_sdqs3 = 0x00000030,
  48         .dram_sdqs4 = 0x00000030,
  49         .dram_sdqs5 = 0x00000030,
  50         .dram_sdqs6 = 0x00000030,
  51         .dram_sdqs7 = 0x00000030,
  52
  53         .dram_dqm0 = 0x00000030,
  54         .dram_dqm1 = 0x00000030,
  55         .dram_dqm2 = 0x00000030,
  56         .dram_dqm3 = 0x00000030,
  57         .dram_dqm4 = 0x00000030,
  58         .dram_dqm5 = 0x00000030,
  59         .dram_dqm6 = 0x00000030,
  60         .dram_dqm7 = 0x00000030,
  61 };
  62
  63 static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
  64         .grp_ddr_type = 0x000c0000,
  65         .grp_ddrmode_ctl = 0x00020000,
  66         .grp_ddrpke = 0x00000000,
  67         .grp_addds = 0x00000030,
  68         .grp_ctlds = 0x00000030,
  69         .grp_ddrmode = 0x00020000,
  70         .grp_b0ds = 0x00000030,
  71         .grp_b1ds = 0x00000030,
  72         .grp_b2ds = 0x00000030,
  73         .grp_b3ds = 0x00000030,
  74         .grp_b4ds = 0x00000030,
  75         .grp_b5ds = 0x00000030,
  76         .grp_b6ds = 0x00000030,
  77         .grp_b7ds = 0x00000030,
  78 };
  79
  80 /* 4x128Mx16.cfg */
  81 static const struct mx6_mmdc_calibration mx6_4x256mx16_mmdc_calib = {
  82         .p0_mpwldectrl0 = 0x002D0028,
  83         .p0_mpwldectrl1 = 0x0032002D,
  84         .p1_mpwldectrl0 = 0x00210036,
  85         .p1_mpwldectrl1 = 0x0019002E,
  86         .p0_mpdgctrl0 = 0x4349035C,
  87         .p0_mpdgctrl1 = 0x0348033D,
  88         .p1_mpdgctrl0 = 0x43550362,
  89         .p1_mpdgctrl1 = 0x03520316,
  90         .p0_mprddlctl = 0x41393940,
  91         .p1_mprddlctl = 0x3F3A3C47,
  92         .p0_mpwrdlctl = 0x413A423A,
  93         .p1_mpwrdlctl = 0x4042483E,
  94 };
  95
  96 /* MT41K128M16JT-125 (2Gb density) */
  97 static const struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  98         .mem_speed = 1600,
  99         .density = 2,
 100         .width = 16,
 101         .banks = 8,
 102         .rowaddr = 14,
 103         .coladdr = 10,
 104         .pagesz = 2,
 105         .trcd = 1375,
 106         .trcmin = 4875,
 107         .trasmin = 3500,
 108 };
 109
 110 iomux_v3_cfg_t const uart_console_pads[] = {
 111         /* UART5 */
 112         MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 113         MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 114         MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 115         MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 116 };
 117
 118 void displ5_set_iomux_uart_spl(void)
 119 {
 120         SETUP_IOMUX_PADS(uart_console_pads);
 121 }
 122
 123 iomux_v3_cfg_t const misc_pads_spl[] = {
 124         /* Emergency recovery pin */
 125         MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 126 };
 127
 128 void displ5_set_iomux_misc_spl(void)
 129 {
 130         SETUP_IOMUX_PADS(misc_pads_spl);
 131 }
 132
 133 #ifdef CONFIG_MXC_SPI
 134 iomux_v3_cfg_t const ecspi2_pads[] = {
 135         /* SPI2, NOR Flash nWP, CS0 */
 136         MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 137         MX6_PAD_CSI0_DAT9__ECSPI2_MOSI  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 138         MX6_PAD_CSI0_DAT8__ECSPI2_SCLK  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 139         MX6_PAD_CSI0_DAT11__GPIO5_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
 140         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL),
 141 };
 142
 143 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
 144 {
 145         if (bus != 1 || cs != 0)
 146                 return -EINVAL;
 147
 148         return IMX_GPIO_NR(5, 29);
 149 }
 150
 151 void displ5_set_iomux_ecspi_spl(void)
 152 {
 153         SETUP_IOMUX_PADS(ecspi2_pads);
 154 }
 155
 156 #else
 157 void displ5_set_iomux_ecspi_spl(void) {}
 158 #endif
 159
 160 #ifdef CONFIG_FSL_ESDHC_IMX
 161 iomux_v3_cfg_t const usdhc4_pads[] = {
 162         MX6_PAD_SD4_CLK__SD4_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 163         MX6_PAD_SD4_CMD__SD4_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 164         MX6_PAD_SD4_DAT0__SD4_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 165         MX6_PAD_SD4_DAT1__SD4_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 166         MX6_PAD_SD4_DAT2__SD4_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 167         MX6_PAD_SD4_DAT3__SD4_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 168         MX6_PAD_SD4_DAT4__SD4_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 169         MX6_PAD_SD4_DAT5__SD4_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 170         MX6_PAD_SD4_DAT6__SD4_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 171         MX6_PAD_SD4_DAT7__SD4_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 172         MX6_PAD_NANDF_ALE__SD4_RESET    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 173 };
 174
 175 void displ5_set_iomux_usdhc_spl(void)
 176 {
 177         SETUP_IOMUX_PADS(usdhc4_pads);
 178 }
 179
 180 #else
 181 void displ5_set_iomux_usdhc_spl(void) {}
 182 #endif
 183
 184 static void ccgr_init(void)
 185 {
 186         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 187
 188         writel(0x00C03F3F, &ccm->CCGR0);
 189         writel(0x0030FC3F, &ccm->CCGR1);
 190         writel(0x0FFFCFC0, &ccm->CCGR2);
 191         writel(0x3FF00000, &ccm->CCGR3);
 192         writel(0x00FFF300, &ccm->CCGR4);
 193         writel(0x0F0000C3, &ccm->CCGR5);
 194         writel(0x000003FF, &ccm->CCGR6);
 195 }
 196
 197 #ifdef CONFIG_MX6_DDRCAL
 198 static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
 199 {
 200         struct mx6_mmdc_calibration calibration = {0};
 201
 202         mmdc_read_calibration(sysinfo, &calibration);
 203
 204         debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
 205         debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
 206         debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
 207         debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
 208         debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
 209         debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
 210         debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
 211         debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
 212         debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
 213         debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
 214         debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
 215         debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
 216 }
 217
 218 static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
 219 {
 220         int ret;
 221
 222         /* Perform DDR DRAM calibration */
 223         udelay(100);
 224         ret = mmdc_do_write_level_calibration(sysinfo);
 225         if (ret) {
 226                 printf("DDR: Write level calibration error [%d]\n", ret);
 227                 return;
 228         }
 229
 230         ret = mmdc_do_dqs_calibration(sysinfo);
 231         if (ret) {
 232                 printf("DDR: DQS calibration error [%d]\n", ret);
 233                 return;
 234         }
 235
 236         spl_dram_print_cal(sysinfo);
 237 }
 238 #endif /* CONFIG_MX6_DDRCAL */
 239
 240 static void spl_dram_init(void)
 241 {
 242         struct mx6_ddr_sysinfo sysinfo = {
 243                 /* width of data bus:0=16,1=32,2=64 */
 244                 .dsize = 2,
 245                 /* config for full 4GB range so that get_mem_size() works */
 246                 .cs_density = 32, /* 32Gb per CS */
 247                 /* single chip select */
 248                 .ncs = 1,
 249                 .cs1_mirror = 0,
 250                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 251                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 252                 .walat = 1,     /* Write additional latency */
 253                 .ralat = 5,     /* Read additional latency */
 254                 .mif3_mode = 3, /* Command prediction working mode */
 255                 .bi_on = 1,     /* Bank interleaving enabled */
 256                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 257                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 258                 .pd_fast_exit = 1, /* enable precharge power-down fast exit */
 259                 .ddr_type = DDR_TYPE_DDR3,
 260                 .refsel = 1,    /* Refresh cycles at 32KHz */
 261                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 262         };
 263
 264         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 265         mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
 266
 267 #ifdef CONFIG_MX6_DDRCAL
 268         spl_dram_perform_cal(&sysinfo);
 269 #endif
 270 }
 271
 272 #ifdef CONFIG_SPL_SPI_SUPPORT
 273 static void displ5_init_ecspi(void)
 274 {
 275         displ5_set_iomux_ecspi_spl();
 276         enable_spi_clk(1, 1);
 277 }
 278 #else
 279 static inline void displ5_init_ecspi(void) { }
 280 #endif
 281
 282 #ifdef CONFIG_SPL_MMC_SUPPORT
 283 static struct fsl_esdhc_cfg usdhc_cfg = {
 284         .esdhc_base = USDHC4_BASE_ADDR,
 285         .max_bus_width = 8,
 286 };
 287
 288 int board_mmc_init(bd_t *bd)
 289 {
 290         displ5_set_iomux_usdhc_spl();
 291
 292         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 293         gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk;
 294
 295         return fsl_esdhc_initialize(bd, &usdhc_cfg);
 296 }
 297 #endif
 298
 299 void board_init_f(ulong dummy)
 300 {
 301         ccgr_init();
 302
 303         arch_cpu_init();
 304
 305         gpr_init();
 306
 307         /* setup GP timer */
 308         timer_init();
 309
 310         displ5_set_iomux_uart_spl();
 311
 312         /* UART clocks enabled and gd valid - init serial console */
 313         preloader_console_init();
 314
 315         displ5_init_ecspi();
 316
 317         /* DDR initialization */
 318         spl_dram_init();
 319
 320         /* Clear the BSS. */
 321         memset(__bss_start, 0, __bss_end - __bss_start);
 322
 323         displ5_set_iomux_misc_spl();
 324
 325         /* Initialize and reset WDT in SPL */
 326         hw_watchdog_init();
 327         WATCHDOG_RESET();
 328
 329         /* load/boot image from boot device */
 330         board_init_r(NULL, 0);
 331 }
 332
 333 #define EM_PAD IMX_GPIO_NR(3, 29)
 334 int board_check_emergency_pad(void)
 335 {
 336         int ret;
 337
 338         ret = gpio_direction_input(EM_PAD);
 339         if (ret)
 340                 return ret;
 341
 342         return !gpio_get_value(EM_PAD);
 343 }
 344
 345 void board_boot_order(u32 *spl_boot_list)
 346 {
 347         /* Default boot sequence SPI -> MMC */
 348         spl_boot_list[0] = spl_boot_device();
 349         spl_boot_list[1] = BOOT_DEVICE_MMC1;
 350         spl_boot_list[2] = BOOT_DEVICE_UART;
 351         spl_boot_list[3] = BOOT_DEVICE_NONE;
 352
 353         /*
 354          * In case of emergency PAD pressed, we always boot
 355          * to proper u-boot and perform recovery tasks there.
 356          */
 357         if (board_check_emergency_pad())
 358                 return;
 359
 360 #ifdef CONFIG_SPL_ENV_SUPPORT
 361         /* 'fastboot' */
 362         const char *s;
 363
 364         if (env_init() || env_load())
 365                 return;
 366
 367         s = env_get("BOOT_FROM");
 368         if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
 369                 spl_boot_list[0] = BOOT_DEVICE_MMC1;
 370                 spl_boot_list[1] = spl_boot_device();
 371         }
 372 #endif
 373 }
 374
 375 void reset_cpu(ulong addr) {}
 376
 377 #ifdef CONFIG_SPL_LOAD_FIT
 378 int board_fit_config_name_match(const char *name)
 379 {
 380         return 0;
 381 }
 382 #endif
 383
 384 #ifdef CONFIG_SPL_OS_BOOT
 385 /* Return: 1 - boot to U-Boot. 0 - boot OS (falcon mode) */
 386 int spl_start_uboot(void)
 387 {
 388         /* break into full u-boot on 'c' */
 389         if (serial_tstc() && serial_getc() == 'c')
 390                 return 1;
 391
 392 #ifdef CONFIG_SPL_ENV_SUPPORT
 393         if (env_get_yesno("boot_os") != 1)
 394                 return 1;
 395 #endif
 396         return 0;
 397 }
 398 #endif