3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * (C) Copyright 2005-2009
9 * Modified for InterControl digsyMTC MPC5200 board by
10 * Frank Bodammer, GCD Hard- & Software GmbH,
11 * frank.bodammer@gcd-solutions.de
14 * Grzegorz Bernacki, Semihalf, gjb@semihalf.com
16 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/processor.h>
26 #if defined(CONFIG_DIGSY_REV5)
27 #include "is45s16800a2.h"
28 #include <mtd/cfi_flash.h>
31 #include "is42s16800a-7t.h"
34 #include <fdt_support.h>
38 DECLARE_GLOBAL_DATA_PTR;
40 extern int usb_cpu_init(void);
42 #if defined(CONFIG_DIGSY_REV5)
44 * The M29W128GH needs a special reset command function,
45 * details see the doc/README.cfi file
47 void flash_cmd_reset(flash_info_t *info)
49 flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
53 #ifndef CONFIG_SYS_RAMBOOT
54 static void sdram_start(int hi_addr)
56 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
57 long control = SDRAM_CONTROL | hi_addr_bit;
59 /* unlock mode register */
60 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
62 /* precharge all banks */
63 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
66 out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
68 /* set mode register */
69 out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
71 /* normal operation */
72 out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
77 * ATTENTION: Although partially referenced initdram does NOT make real use
78 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
79 * CONFIG_SYS_SDRAM_BASE is something other than 0x00000000.
82 phys_size_t initdram(int board_type)
87 #ifndef CONFIG_SYS_RAMBOOT
90 /* setup SDRAM chip selects */
91 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001C); /* 512MB at 0x0 */
92 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
94 /* setup config registers */
95 out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
96 out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
98 /* find RAM size using SDRAM CS0 only */
100 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
102 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
110 /* memory smaller than 1MB is impossible */
111 if (dramsize < (1 << 20))
114 /* set SDRAM CS0 size according to the amount of RAM found */
116 out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
117 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
119 out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
122 /* let SDRAM CS1 start right after CS0 */
123 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize + 0x0000001C);
125 /* find RAM size using SDRAM CS1 only */
126 test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
130 /* memory smaller than 1MB is impossible */
131 if (dramsize2 < (1 << 20))
134 /* set SDRAM CS1 size according to the amount of RAM found */
136 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, (dramsize |
137 (0x13 + __builtin_ffs(dramsize2 >> 20) - 1)));
139 out_be32((void *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
142 #else /* CONFIG_SYS_RAMBOOT */
144 /* retrieve size of memory connected to SDRAM CS0 */
145 dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
146 if (dramsize >= 0x13)
147 dramsize = (1 << (dramsize - 0x13)) << 20;
151 /* retrieve size of memory connected to SDRAM CS1 */
152 dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
153 if (dramsize2 >= 0x13)
154 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
158 #endif /* CONFIG_SYS_RAMBOOT */
161 * On MPC5200B we need to set the special configuration delay in the
162 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
163 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
165 * "The SDelay should be written to a value of 0x00000004. It is
166 * required to account for changes caused by normal wafer processing
171 if ((SVR_MJREV(svr) >= 2) &&
172 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
173 out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
175 return dramsize + dramsize2;
181 int i = getenv_f("serial#", buf, sizeof(buf));
183 puts ("Board: InterControl digsyMTC");
184 #if defined(CONFIG_DIGSY_REV5)
196 #if defined(CONFIG_VIDEO)
198 #define GPIO_USB1_0 0x00010000 /* Power-On pin */
199 #define GPIO_USB1_9 0x08 /* PX_~EN pin */
201 #define GPIO_EE_DO 0x10 /* PSC6_0 (DO) pin */
202 #define GPIO_EE_CTS 0x20 /* PSC6_1 (CTS) pin */
203 #define GPIO_EE_DI 0x10000000 /* PSC6_2 (DI) pin */
204 #define GPIO_EE_CLK 0x20000000 /* PSC6_3 (CLK) pin */
206 #define GPT_GPIO_ON 0x00000034 /* GPT as simple GPIO, high */
208 static void exbo_hw_init(void)
210 struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
211 struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
212 struct mpc5xxx_wu_gpio *wu_gpio =
213 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
215 /* configure IrDA pins (PSC6 port) as gpios */
216 gpio->port_config &= 0xFF8FFFFF;
218 /* Init for USB1_0, EE_CLK and EE_DI - Low */
219 setbits_be32(&gpio->simple_ddr,
220 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
221 clrbits_be32(&gpio->simple_ode,
222 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
223 clrbits_be32(&gpio->simple_dvo,
224 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
225 setbits_be32(&gpio->simple_gpioe,
226 GPIO_USB1_0 | GPIO_EE_CLK | GPIO_EE_DI);
228 /* Init for EE_DO, EE_CTS - Input */
229 clrbits_8(&wu_gpio->ddr, GPIO_EE_DO | GPIO_EE_CTS);
230 setbits_8(&wu_gpio->enable, GPIO_EE_DO | GPIO_EE_CTS);
232 /* Init for PX_~EN (USB1_9) - High */
233 clrbits_8(&gpio->sint_ode, GPIO_USB1_9);
234 setbits_8(&gpio->sint_ddr, GPIO_USB1_9);
235 clrbits_8(&gpio->sint_inten, GPIO_USB1_9);
236 setbits_8(&gpio->sint_dvo, GPIO_USB1_9);
237 setbits_8(&gpio->sint_gpioe, GPIO_USB1_9);
239 /* Init for ~OE Switch (GPIO3) - Timer_0 GPIO High */
240 out_be32(&gpt[0].emsr, GPT_GPIO_ON);
241 /* Init for S Switch (GPIO4) - Timer_1 GPIO High */
242 out_be32(&gpt[1].emsr, GPT_GPIO_ON);
244 /* Power-On camera supply */
245 setbits_be32(&gpio->simple_dvo, GPIO_USB1_0);
248 static inline void exbo_hw_init(void) {}
249 #endif /* CONFIG_VIDEO */
251 int board_early_init_r(void)
254 * Now, when we are in RAM, enable flash write access for detection
255 * process. Note that CS_BOOT cannot be cleared when executing in
258 /* disable CS_BOOT */
259 clrbits_be32((void *)MPC5XXX_ADDECR, (1 << 25));
261 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 17));
263 setbits_be32((void *)MPC5XXX_ADDECR, (1 << 16));
265 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
266 /* Low level USB init, required for proper kernel operation */
273 void board_get_enetaddr (uchar * enet)
276 ushort addr_of_eth_addr = 0;
278 ushort len_sys_cfg = 0;
280 /* check identification word */
281 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, (uchar *)&read, 2);
282 if (read != EEPROM_IDENT)
285 /* calculate offset of config area */
286 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, (uchar *)&len_sys, 2);
287 eeprom_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG,
288 (uchar *)&len_sys_cfg, 2);
289 addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_ADDR_ETHADDR) << 1;
290 if (addr_of_eth_addr >= EEPROM_LEN)
293 eeprom_read(EEPROM_ADDR, addr_of_eth_addr, enet, 6);
296 int misc_init_r(void)
301 /* check if graphic extension board is present */
302 devbusfn = pci_find_device(PCI_VENDOR_ID_FUJITSU,
303 PCI_DEVICE_ID_CORAL_PA, 0);
307 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) {
308 board_get_enetaddr(enetaddr);
309 eth_setenv_enetaddr("ethaddr", enetaddr);
316 static struct pci_controller hose;
318 extern void pci_mpc5xxx_init(struct pci_controller *);
320 void pci_init_board(void)
322 pci_mpc5xxx_init(&hose);
326 #ifdef CONFIG_CMD_IDE
328 #ifdef CONFIG_IDE_RESET
330 void init_ide_reset(void)
332 debug ("init_ide_reset\n");
334 /* set gpio output value to 1 */
335 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
336 /* open drain output */
337 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
338 /* direction output */
339 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
341 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
345 void ide_set_reset(int idereset)
347 debug ("ide_reset(%d)\n", idereset);
349 /* set gpio output value to 0 */
350 clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
351 /* open drain output */
352 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
353 /* direction output */
354 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
356 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
360 /* set gpio output value to 1 */
361 setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, (1 << 25));
362 /* open drain output */
363 setbits_be32((void *)MPC5XXX_WU_GPIO_ODE, (1 << 25));
364 /* direction output */
365 setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, (1 << 25));
367 setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, (1 << 25));
369 #endif /* CONFIG_IDE_RESET */
370 #endif /* CONFIG_CMD_IDE */
372 #ifdef CONFIG_OF_BOARD_SETUP
373 static void ft_delete_node(void *fdt, const char *compat)
378 off = fdt_node_offset_by_compatible(fdt, -1, compat);
380 printf("Could not find %s node.\n", compat);
384 ret = fdt_del_node(fdt, off);
386 printf("Could not delete %s node.\n", compat);
388 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
389 static void ft_adapt_flash_base(void *blob)
391 flash_info_t *dev = &flash_info[0];
393 struct fdt_property *prop;
397 off = fdt_node_offset_by_compatible(blob, -1, "fsl,mpc5200b-lpb");
399 printf("Could not find fsl,mpc5200b-lpb node.\n");
403 /* found compatible property */
404 prop = fdt_get_property_w(blob, off, "ranges", &len);
406 reg = reg2 = (u32 *)&prop->data[0];
408 reg[2] = dev->start[0];
410 fdt_setprop(blob, off, "ranges", reg2, len);
412 printf("Could not find ranges\n");
415 extern ulong flash_get_size (phys_addr_t base, int banknum);
417 /* Update the Flash Baseaddr settings */
418 int update_flash_size (int flash_size)
420 volatile struct mpc5xxx_mmap_ctl *mm =
421 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
425 unsigned long base = 0x0;
426 u32 *cs_reg = (u32 *)&mm->cs0_start;
428 for (i = 0; i < 2; i++) {
429 dev = &flash_info[i];
432 /* calculate new base addr for this chipselect */
434 out_be32(cs_reg, START_REG(base));
436 out_be32(cs_reg, STOP_REG(base, dev->size));
438 /* recalculate the sectoraddr in the cfi driver */
439 size += flash_get_size(base, i);
442 flash_protect_default();
443 gd->bd->bi_flashstart = base;
446 #endif /* defined(CONFIG_SYS_UPDATE_FLASH_SIZE) */
448 int ft_board_setup(void *blob, bd_t *bd)
450 int phy_addr = CONFIG_PHY_ADDR;
451 char eth_path[] = "/soc5200@f0000000/mdio@3000/ethernet-phy@0";
453 ft_cpu_setup(blob, bd);
455 * There are 2 RTC nodes in the DTS, so remove
456 * the unneeded node here.
458 #if defined(CONFIG_DIGSY_REV5)
459 ft_delete_node(blob, "dallas,ds1339");
461 ft_delete_node(blob, "mc,rv3029c2");
463 #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
464 #ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
465 /* Update reg property in all nor flash nodes too */
466 fdt_fixup_nor_flash_size(blob);
468 ft_adapt_flash_base(blob);
470 /* fix up the phy address */
471 do_fixup_by_path(blob, eth_path, "reg", &phy_addr, sizeof(int), 0);
475 #endif /* CONFIG_OF_BOARD_SETUP */