3 * ISEE 2007 SL <www.iseebcn.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/cpu.h>
29 #include <asm/arch/bits.h>
30 #include <asm/arch/mux.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/sys_info.h>
33 #include <asm/arch/clocks.h>
34 #include <asm/arch/mem.h>
35 #include <asm/arch/gpio.h>
38 #define CORE_DPLL_PARAM_M2 0x09
39 #define CORE_DPLL_PARAM_M 0x360
40 #define CORE_DPLL_PARAM_N 0xC
42 /* Used to index into DPLL parameter tables */
50 typedef struct dpll_param dpll_param;
52 /* Following functions are exported from lowlevel_init.S */
53 extern dpll_param *get_mpu_dpll_param(void);
54 extern dpll_param *get_iva_dpll_param(void);
55 extern dpll_param *get_core_dpll_param(void);
56 extern dpll_param *get_per_dpll_param(void);
58 #define __raw_readl(a) (*(volatile unsigned int *)(a))
59 #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
60 #define __raw_readw(a) (*(volatile unsigned short *)(a))
61 #define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
63 static char *rev_s[CPU_3XX_MAX_REV] = {
73 /*******************************************************
75 * Description: spinning delay to use before udelay works
76 ******************************************************/
77 static inline void delay(unsigned long loops)
79 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
80 "bne 1b":"=r" (loops):"0"(loops));
83 void udelay (unsigned long usecs) {
87 /*************************************************************
88 * get_device_type(): tell if GP/HS/EMU/TST
89 *************************************************************/
90 u32 get_device_type(void)
93 mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
97 /************************************************
98 * get_sysboot_value(void) - return SYS_BOOT[4:0]
99 ************************************************/
100 u32 get_sysboot_value(void)
103 mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
107 /*************************************************************
108 * Routine: get_mem_type(void) - returns the kind of memory connected
109 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
110 *************************************************************/
111 u32 get_mem_type(void)
116 /******************************************
117 * get_cpu_type(void) - extract cpu info
118 ******************************************/
119 u32 get_cpu_type(void)
121 return __raw_readl(CONTROL_OMAP_STATUS);
124 /******************************************
125 * get_cpu_id(void) - extract cpu id
126 * returns 0 for ES1.0, cpuid otherwise
127 ******************************************/
133 * On ES1.0 the IDCODE register is not exposed on L4
134 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
136 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
137 if ((cpuid & 0xf) == 0x0) {
140 /* Decode the IDs on > ES1.0 */
141 cpuid = __raw_readl(CONTROL_IDCODE);
147 /*****************************************************************
148 * sr32 - clear & set a value in a bit range for a 32 bit address
149 *****************************************************************/
150 void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
155 tmp = __raw_readl(addr) & ~(msk << start_bit);
156 tmp |= value << start_bit;
157 __raw_writel(tmp, addr);
160 /*********************************************************************
161 * wait_on_value() - common routine to allow waiting for changes in
163 *********************************************************************/
164 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
169 val = __raw_readl(read_addr) & read_bit_mask;
170 if (val == match_value)
177 /******************************************
178 * get_cpu_family(void) - extract cpu info
179 ******************************************/
180 u32 get_cpu_family(void)
184 u32 cpuid = get_cpu_id();
189 hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
191 case HAWKEYE_OMAP34XX:
192 cpu_family = CPU_OMAP34XX;
195 cpu_family = CPU_AM35XX;
197 case HAWKEYE_OMAP36XX:
198 cpu_family = CPU_OMAP36XX;
201 cpu_family = CPU_OMAP34XX;
207 /******************************************
208 * get_cpu_rev(void) - extract version info
209 ******************************************/
210 u32 get_cpu_rev(void)
212 u32 cpuid = get_cpu_id();
217 return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
220 /******************************************
221 * Print CPU information
222 ******************************************/
223 int print_cpuinfo (void)
225 char *cpu_family_s, *cpu_s, *sec_s;
227 switch (get_cpu_family()) {
229 cpu_family_s = "OMAP";
230 switch (get_cpu_type()) {
250 switch (get_cpu_type()) {
263 cpu_family_s = "OMAP";
264 switch (get_cpu_type()) {
274 cpu_family_s = "OMAP";
278 switch (get_device_type()) {
295 printf("%s%s-%s ES%s\n",
296 cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]);
301 /*************************************************************
302 * get_sys_clk_speed - determine reference oscillator speed
303 * based on known 32kHz clock and gptimer.
304 *************************************************************/
305 u32 get_osc_clk_speed(void)
307 u32 start, cstart, cend, cdiff, val;
309 val = __raw_readl(PRM_CLKSRC_CTRL);
310 /* If SYS_CLK is being divided by 2, remove for now */
311 val = (val & (~BIT7)) | BIT6;
312 __raw_writel(val, PRM_CLKSRC_CTRL);
315 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
316 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
318 /* Enable I and F Clocks for GPT1 */
319 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
320 __raw_writel(val, CM_ICLKEN_WKUP);
321 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
322 __raw_writel(val, CM_FCLKEN_WKUP);
324 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
325 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
326 /* enable 32kHz source */
327 /* enabled out of reset */
328 /* determine sys_clk via gauging */
330 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
331 while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */
332 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
333 while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */
334 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
335 cdiff = cend - cstart; /* get elapsed ticks */
337 /* based on number of ticks assign speed */
340 else if (cdiff > 15200)
342 else if (cdiff > 13000)
344 else if (cdiff > 9000)
346 else if (cdiff > 7600)
352 /******************************************************************************
353 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
354 * -- input oscillator clock frequency.
356 *****************************************************************************/
357 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
359 if (osc_clk == S38_4M)
361 else if (osc_clk == S26M)
363 else if (osc_clk == S19_2M)
365 else if (osc_clk == S13M)
367 else if (osc_clk == S12M)
371 /******************************************************************************
372 * prcm_init() - inits clocks for PRCM as defined in clocks.h
373 * -- called from SRAM, or Flash (using temp SRAM stack).
374 *****************************************************************************/
377 u32 osc_clk = 0, sys_clkin_sel;
378 dpll_param *dpll_param_p;
379 u32 clk_index, sil_index;
381 /* Gauge the input clock speed and find out the sys_clkin_sel
382 * value corresponding to the input clock.
384 osc_clk = get_osc_clk_speed();
385 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
387 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
389 /* If the input clock is greater than 19.2M always divide/2 */
390 if (sys_clkin_sel > 2) {
391 sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
392 clk_index = sys_clkin_sel / 2;
394 sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
395 clk_index = sys_clkin_sel;
398 sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
400 /* The DPLL tables are defined according to sysclk value and
401 * silicon revision. The clk_index value will be used to get
402 * the values for that input sysclk from the DPLL param table
403 * and sil_index will get the values for that SysClk for the
404 * appropriate silicon rev.
406 sil_index = get_cpu_rev() - 1;
408 /* Unlock MPU DPLL (slows things down, and needed later) */
409 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
410 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
412 /* Getting the base address of Core DPLL param table */
413 dpll_param_p = (dpll_param *) get_core_dpll_param();
414 /* Moving it to the right sysclk and ES rev base */
415 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
417 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
418 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
419 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
421 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
422 work. write another value and then default value. */
423 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
424 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
425 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
426 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
427 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
428 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
429 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
430 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
431 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
432 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
433 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
434 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
435 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
436 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
437 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
439 /* Getting the base address to PER DPLL param table */
440 dpll_param_p = (dpll_param *) get_per_dpll_param();
441 /* Moving it to the right sysclk base */
442 dpll_param_p = dpll_param_p + clk_index;
444 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
445 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
446 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
447 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
448 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
449 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
451 if (get_cpu_family() == CPU_OMAP36XX) {
452 sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */
453 sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */
454 sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N); /* set n */
456 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
457 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
458 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
461 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
462 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
463 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
465 /* Getting the base address to MPU DPLL param table */
466 dpll_param_p = (dpll_param *) get_mpu_dpll_param();
468 /* Moving it to the right sysclk and ES rev base */
469 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
471 /* MPU DPLL (unlocked already) */
472 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
473 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
474 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
475 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
476 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
477 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
479 /* Getting the base address to IVA DPLL param table */
480 dpll_param_p = (dpll_param *) get_iva_dpll_param();
481 /* Moving it to the right sysclk and ES rev base */
482 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
483 /* IVA DPLL (set to 12*20=240MHz) */
484 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
485 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
486 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
487 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
488 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
489 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
490 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
491 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
493 /* Set up GPTimers to sys_clk source only */
494 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
495 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
500 /*****************************************
501 * Routine: secure_unlock
502 * Description: Setup security registers for access
504 *****************************************/
505 void secure_unlock(void)
507 /* Permission values for registers -Full fledged permissions to all */
508 #define UNLOCK_1 0xFFFFFFFF
509 #define UNLOCK_2 0x00000000
510 #define UNLOCK_3 0x0000FFFF
511 /* Protection Module Register Target APE (PM_RT) */
512 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
513 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
514 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
515 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
517 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
518 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
519 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
521 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
522 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
523 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
524 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
527 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
528 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
529 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
531 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
534 /**********************************************************
535 * Routine: try_unlock_sram()
536 * Description: If chip is GP type, unlock the SRAM for
538 ***********************************************************/
539 void try_unlock_memory(void)
543 /* if GP device unlock device SRAM for general use */
544 /* secure code breaks for Secure/Emulation device - HS/E/T */
545 mode = get_device_type();
546 if (mode == GP_DEVICE)
551 /*********************************************************************
552 * config_sdram_m65kx002am() - 2 dice of 2Gb, DDR x32 I/O, 4KB page
553 *********************************************************************/
554 void config_sdram_m65kx002am(void)
556 /* M65KX002AM - 2 dice of 2Gb */
557 /* reset sdrc controller */
558 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
559 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
560 __raw_writel(0, SDRC_SYSCONFIG);
562 /* setup sdrc to ball mux */
563 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
564 __raw_writel(0x2, SDRC_CS_CFG); /* 256 MB/bank */
566 /* CS0 SDRC Mode Register */
567 __raw_writel(MK65KX002AM_SDRC_MCDCFG, SDRC_MCFG_0);
569 /* CS1 SDRC Mode Register */
570 __raw_writel(MK65KX002AM_SDRC_MCDCFG, SDRC_MCFG_1);
573 __raw_writel(NUMONYX_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
574 __raw_writel(NUMONYX_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
575 __raw_writel(NUMONYX_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_1);
576 __raw_writel(NUMONYX_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_1);
578 __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL_0);
579 __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL_1);
581 __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
583 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
584 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
585 __raw_writel(CMD_NOP, SDRC_MANUAL_1);
589 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
590 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
592 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
593 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
595 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
596 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
599 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
600 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);
603 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
604 delay(0x2000); /* give time to lock */
607 /*********************************************************************
608 * config_onenand_nand0xgr4wxa() - 4-Gbit DDP or 2-Gbit OneNAND Flash
609 *********************************************************************/
610 void config_onenand_nand0xgr4wxa(void)
612 /* global settings */
613 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
614 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
615 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
617 /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
618 * We configure only GPMC CS0 with required values. Configuring other devices
619 * at other CS is done in u-boot. So we don't have to bother doing it here.
621 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
624 __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
625 __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
626 __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
627 __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
628 __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
629 __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
631 /* Enable the GPMC Mapping */
632 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
633 ((ONENAND_BASE>>24) & 0x3F) |
634 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
638 /**********************************************************
640 * Description: Does early system init of muxing and clocks.
641 * - Called at time when only stack is available.
642 **********************************************************/
652 config_sdram_m65kx002am();
655 /*****************************************
656 * Routine: board_init
657 * Description: Early hardware init.
658 *****************************************/
664 /*******************************************************
665 * Routine: misc_init_r
666 * Description: Init ethernet (done here so udelay works)
667 ********************************************************/
668 int misc_init_r(void)
670 omap_request_gpio(27);
671 omap_set_gpio_direction(27, 0);
672 omap_set_gpio_dataout(27, 1);
677 /******************************************************
678 * Routine: wait_for_command_complete
679 * Description: Wait for posting to finish on watchdog
680 ******************************************************/
681 void wait_for_command_complete(unsigned int wd_base)
685 pending = __raw_readl(wd_base + WWPS);
689 /****************************************
690 * Routine: watchdog_init
691 * Description: Shut down watch dogs
692 *****************************************/
693 void watchdog_init(void)
695 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
696 * either taken care of by ROM (HS/EMU) or not accessible (GP).
697 * We need to take care of WD2-MPU or take a PRCM reset. WD3
698 * should not be running and does not generate a PRCM reset.
700 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
701 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
702 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
704 #ifdef CONFIG_WATCHDOG
705 /* Enable WD2 watchdog */
706 __raw_writel(WD_UNLOCK3, WD2_BASE + WSPR);
707 wait_for_command_complete(WD2_BASE);
708 __raw_writel(WD_UNLOCK4, WD2_BASE + WSPR);
710 /* Disable WD2 watchdog */
711 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
712 wait_for_command_complete(WD2_BASE);
713 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
717 /**********************************************
719 * Description: sets uboots idea of sdram size
720 **********************************************/
726 /*****************************************************************
727 * Routine: peripheral_enable
728 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
729 ******************************************************************/
730 void per_clocks_enable(void)
732 /* Enable GP2 timer. */
733 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
734 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
735 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
739 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
740 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
743 sr32(CM_FCLKEN_PER, 11, 1, 0x1);
744 sr32(CM_ICLKEN_PER, 11, 1, 0x1);
748 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
749 /* Turn on all 3 I2C clocks */
750 sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
751 sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
754 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
755 sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
757 sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
758 sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
759 sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
760 sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
761 sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
762 sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
763 sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
764 sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
765 sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
766 sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
767 sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
768 sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
773 /* Set MUX for UART, GPMC, SDRC, GPIO */
775 #define MUX_VAL(OFFSET,VALUE)\
776 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
778 #define CP(x) (CONTROL_PADCONF_##x)
781 * IDIS - Input Disable
782 * PTD - Pull type Down
784 * DIS - Pull type selection is inactive
785 * EN - Pull type selection is active
787 * The commented string gives the final mux configuration for that pin
789 #define MUX_DEFAULT()\
790 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
791 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
792 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
793 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
794 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
795 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
796 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
797 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
798 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
799 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
800 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
801 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
802 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
803 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
804 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
805 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
806 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
807 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
808 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
809 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
810 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
811 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
812 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
813 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
814 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
815 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
816 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
817 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
818 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
819 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
820 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
821 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
822 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
823 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
824 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
825 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
826 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
827 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
828 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
829 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
830 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
831 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
832 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
833 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
834 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
835 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
836 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
837 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
838 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
839 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
840 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
841 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
842 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
843 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
844 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
845 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
846 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
847 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
848 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
849 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
850 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
851 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
852 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
853 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
854 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
855 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
856 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
857 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
858 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
859 MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
860 MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
861 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
862 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
863 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
864 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
865 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
866 MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\
867 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
868 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
869 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
870 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
871 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
872 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
873 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
874 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
875 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
876 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
877 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
878 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
879 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
880 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
881 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
882 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
883 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
884 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
885 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
886 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
887 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
888 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
889 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
890 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
891 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
892 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
893 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
894 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
895 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
896 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
897 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
898 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
899 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
900 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
901 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
902 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
903 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
904 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
905 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
906 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
907 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
908 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
909 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
910 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
911 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
912 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
913 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
914 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
915 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
916 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
917 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
918 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
919 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
920 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
921 MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
922 MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
923 MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
924 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
925 MUX_VAL(CP(ETK_D12), (IDIS | PTD | DIS | M4)) /*GPIO_26*/\
926 MUX_VAL(CP(ETK_D13), (IDIS | PTD | DIS | M4)) /*GPIO_27*/\
927 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
928 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\
929 MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
930 MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/
932 /**********************************************************
933 * Routine: set_muxconf_regs
934 * Description: Setting up the configuration Mux registers
935 * specific to the hardware. Many pins need
936 * to be moved from protect to primary mode.
937 *********************************************************/
938 void set_muxconf_regs(void)
943 /**********************************************************
945 * Description: Set up flash, NAND and OneNAND
946 *********************************************************/
950 config_onenand_nand0xgr4wxa();
951 if (onenand_chip()) {
953 printf("OneNAND Unsupported !\n");
962 /* optionally do something */
963 void board_hang(void)
967 /******************************************************************************
968 * Dummy function to handle errors for EABI incompatibility
969 *****************************************************************************/
974 /******************************************************************************
975 * Dummy function to handle errors for EABI incompatibility
976 *****************************************************************************/