board/gateworks/gw_ventana/gw_ventana.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Gateworks Corporation
   4  *
   5  * Author: Tim Harvey <tharvey@gateworks.com>
   6  */
   7
   8 #include <common.h>
   9 #include <net.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/iomux.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/arch/mxc_hdmi.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/gpio.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/sata.h>
  19 #include <asm/mach-imx/spi.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <asm/io.h>
  22 #include <asm/setup.h>
  23 #include <dm.h>
  24 #include <dm/platform_data/serial_mxc.h>
  25 #include <env.h>
  26 #include <hwconfig.h>
  27 #include <i2c.h>
  28 #include <fdt_support.h>
  29 #include <fsl_esdhc_imx.h>
  30 #include <jffs2/load_kernel.h>
  31 #include <linux/ctype.h>
  32 #include <miiphy.h>
  33 #include <mtd_node.h>
  34 #include <netdev.h>
  35 #include <pci.h>
  36 #include <linux/libfdt.h>
  37 #include <power/pmic.h>
  38 #include <power/ltc3676_pmic.h>
  39 #include <power/pfuze100_pmic.h>
  40 #include <fdt_support.h>
  41 #include <jffs2/load_kernel.h>
  42 #include <spi_flash.h>
  43
  44 #include "gsc.h"
  45 #include "common.h"
  46
  47 DECLARE_GLOBAL_DATA_PTR;
  48
  49
  50 /*
  51  * EEPROM board info struct populated by read_eeprom so that we only have to
  52  * read it once.
  53  */
  54 struct ventana_board_info ventana_info;
  55
  56 static int board_type;
  57
  58 /* ENET */
  59 static iomux_v3_cfg_t const enet_pads[] = {
  60         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  68                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  70                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  77                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
  78         /* PHY nRST */
  79         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  80 };
  81
  82 #ifdef CONFIG_CMD_NAND
  83 static iomux_v3_cfg_t const nfc_pads[] = {
  84         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  90         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
  91         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  92         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  93         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  94         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  95         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  96         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  97         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  98         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
  99 };
 100
 101 static void setup_gpmi_nand(void)
 102 {
 103         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 104
 105         /* config gpmi nand iomux */
 106         SETUP_IOMUX_PADS(nfc_pads);
 107
 108         /* config gpmi and bch clock to 100 MHz */
 109         clrsetbits_le32(&mxc_ccm->cs2cdr,
 110                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 111                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 112                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 113                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 114                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 115                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 116
 117         /* enable gpmi and bch clock gating */
 118         setbits_le32(&mxc_ccm->CCGR4,
 119                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 120                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 121                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 122                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 123                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 124
 125         /* enable apbh clock gating */
 126         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 127 }
 128 #endif
 129
 130 static void setup_iomux_enet(int gpio)
 131 {
 132         SETUP_IOMUX_PADS(enet_pads);
 133
 134         /* toggle PHY_RST# */
 135         gpio_request(gpio, "phy_rst#");
 136         gpio_direction_output(gpio, 0);
 137         mdelay(10);
 138         gpio_set_value(gpio, 1);
 139         mdelay(100);
 140 }
 141
 142 #ifdef CONFIG_USB_EHCI_MX6
 143 static iomux_v3_cfg_t const usb_pads[] = {
 144         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | DIO_PAD_CFG),
 145         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
 146         /* OTG PWR */
 147         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | DIO_PAD_CFG),
 148 };
 149
 150 int board_ehci_hcd_init(int port)
 151 {
 152         int gpio;
 153
 154         SETUP_IOMUX_PADS(usb_pads);
 155
 156         /* Reset USB HUB */
 157         switch (board_type) {
 158         case GW53xx:
 159         case GW552x:
 160         case GW5906:
 161                 gpio = (IMX_GPIO_NR(1, 9));
 162                 break;
 163         case GW54proto:
 164         case GW54xx:
 165                 gpio = (IMX_GPIO_NR(1, 16));
 166                 break;
 167         default:
 168                 return 0;
 169         }
 170
 171         /* request and toggle hub rst */
 172         gpio_request(gpio, "usb_hub_rst#");
 173         gpio_direction_output(gpio, 0);
 174         mdelay(2);
 175         gpio_set_value(gpio, 1);
 176
 177         return 0;
 178 }
 179
 180 int board_ehci_power(int port, int on)
 181 {
 182         /* enable OTG VBUS */
 183         if (!port && board_type < GW_UNKNOWN) {
 184                 if (gpio_cfg[board_type].otgpwr_en)
 185                         gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
 186         }
 187         return 0;
 188 }
 189 #endif /* CONFIG_USB_EHCI_MX6 */
 190
 191 #ifdef CONFIG_MXC_SPI
 192 iomux_v3_cfg_t const ecspi1_pads[] = {
 193         /* SS1 */
 194         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 195         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 196         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 197         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 198 };
 199
 200 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 201 {
 202         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 203 }
 204
 205 static void setup_spi(void)
 206 {
 207         gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
 208         gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
 209         SETUP_IOMUX_PADS(ecspi1_pads);
 210 }
 211 #endif
 212
 213 /* configure eth0 PHY board-specific LED behavior */
 214 int board_phy_config(struct phy_device *phydev)
 215 {
 216         unsigned short val;
 217
 218         /* Marvel 88E1510 */
 219         if (phydev->phy_id == 0x1410dd1) {
 220                 /*
 221                  * Page 3, Register 16: LED[2:0] Function Control Register
 222                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 223                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 224                  */
 225                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 226                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 227                 val &= 0xff00;
 228                 val |= 0x0017;
 229                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 230                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 231         }
 232
 233         /* TI DP83867 */
 234         else if (phydev->phy_id == 0x2000a231) {
 235                 /* configure register 0x170 for ref CLKOUT */
 236                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
 237                 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
 238                 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
 239                 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
 240                 val &= ~0x1f00;
 241                 val |= 0x0b00; /* chD tx clock*/
 242                 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
 243         }
 244
 245         if (phydev->drv->config)
 246                 phydev->drv->config(phydev);
 247
 248         return 0;
 249 }
 250
 251 #ifdef CONFIG_MV88E61XX_SWITCH
 252 int mv88e61xx_hw_reset(struct phy_device *phydev)
 253 {
 254         struct mii_dev *bus = phydev->bus;
 255
 256         /* GPIO[0] output, CLK125 */
 257         debug("enabling RGMII_REFCLK\n");
 258         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 259                    0x1a /*MV_SCRATCH_MISC*/,
 260                    (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
 261         bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
 262                    0x1a /*MV_SCRATCH_MISC*/,
 263                    (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
 264
 265         /* RGMII delay - Physical Control register bit[15:14] */
 266         debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
 267         /* forced 1000mbps full-duplex link */
 268         bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
 269         phydev->autoneg = AUTONEG_DISABLE;
 270         phydev->speed = SPEED_1000;
 271         phydev->duplex = DUPLEX_FULL;
 272
 273         /* LED configuration: 7:4-green (8=Activity)  3:0 amber (8=Link) */
 274         bus->write(bus, 0x10, 0, 0x16, 0x8088);
 275         bus->write(bus, 0x11, 0, 0x16, 0x8088);
 276         bus->write(bus, 0x12, 0, 0x16, 0x8088);
 277         bus->write(bus, 0x13, 0, 0x16, 0x8088);
 278
 279         return 0;
 280 }
 281 #endif // CONFIG_MV88E61XX_SWITCH
 282
 283 int board_eth_init(bd_t *bis)
 284 {
 285 #ifdef CONFIG_FEC_MXC
 286         struct ventana_board_info *info = &ventana_info;
 287
 288         if (test_bit(EECONFIG_ETH0, info->config)) {
 289                 setup_iomux_enet(GP_PHY_RST);
 290                 cpu_eth_init(bis);
 291         }
 292 #endif
 293
 294 #ifdef CONFIG_E1000
 295         e1000_initialize(bis);
 296 #endif
 297
 298 #ifdef CONFIG_CI_UDC
 299         /* For otg ethernet*/
 300         usb_eth_initialize(bis);
 301 #endif
 302
 303         /* default to the first detected enet dev */
 304         if (!env_get("ethprime")) {
 305                 struct eth_device *dev = eth_get_dev_by_index(0);
 306                 if (dev) {
 307                         env_set("ethprime", dev->name);
 308                         printf("set ethprime to %s\n", env_get("ethprime"));
 309                 }
 310         }
 311
 312         return 0;
 313 }
 314
 315 #if defined(CONFIG_VIDEO_IPUV3)
 316
 317 static void enable_hdmi(struct display_info_t const *dev)
 318 {
 319         imx_enable_hdmi_phy();
 320 }
 321
 322 static int detect_i2c(struct display_info_t const *dev)
 323 {
 324         return i2c_set_bus_num(dev->bus) == 0 &&
 325                 i2c_probe(dev->addr) == 0;
 326 }
 327
 328 static void enable_lvds(struct display_info_t const *dev)
 329 {
 330         struct iomuxc *iomux = (struct iomuxc *)
 331                                 IOMUXC_BASE_ADDR;
 332
 333         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 334         u32 reg = readl(&iomux->gpr[2]);
 335         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 336         writel(reg, &iomux->gpr[2]);
 337
 338         /* Enable Backlight */
 339         gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
 340         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 341         gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
 342         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
 343         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 344 }
 345
 346 struct display_info_t const displays[] = {{
 347         /* HDMI Output */
 348         .bus    = -1,
 349         .addr   = 0,
 350         .pixfmt = IPU_PIX_FMT_RGB24,
 351         .detect = detect_hdmi,
 352         .enable = enable_hdmi,
 353         .mode   = {
 354                 .name           = "HDMI",
 355                 .refresh        = 60,
 356                 .xres           = 1024,
 357                 .yres           = 768,
 358                 .pixclock       = 15385,
 359                 .left_margin    = 220,
 360                 .right_margin   = 40,
 361                 .upper_margin   = 21,
 362                 .lower_margin   = 7,
 363                 .hsync_len      = 60,
 364                 .vsync_len      = 10,
 365                 .sync           = FB_SYNC_EXT,
 366                 .vmode          = FB_VMODE_NONINTERLACED
 367 } }, {
 368         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 369         .bus    = 2,
 370         .addr   = 0x4,
 371         .pixfmt = IPU_PIX_FMT_LVDS666,
 372         .detect = detect_i2c,
 373         .enable = enable_lvds,
 374         .mode   = {
 375                 .name           = "Hannstar-XGA",
 376                 .refresh        = 60,
 377                 .xres           = 1024,
 378                 .yres           = 768,
 379                 .pixclock       = 15385,
 380                 .left_margin    = 220,
 381                 .right_margin   = 40,
 382                 .upper_margin   = 21,
 383                 .lower_margin   = 7,
 384                 .hsync_len      = 60,
 385                 .vsync_len      = 10,
 386                 .sync           = FB_SYNC_EXT,
 387                 .vmode          = FB_VMODE_NONINTERLACED
 388 } }, {
 389         /* DLC700JMG-T-4 */
 390         .bus    = 2,
 391         .addr   = 0x38,
 392         .detect = NULL,
 393         .enable = enable_lvds,
 394         .pixfmt = IPU_PIX_FMT_LVDS666,
 395         .mode   = {
 396                 .name           = "DLC700JMGT4",
 397                 .refresh        = 60,
 398                 .xres           = 1024,         /* 1024x600active pixels */
 399                 .yres           = 600,
 400                 .pixclock       = 15385,        /* 64MHz */
 401                 .left_margin    = 220,
 402                 .right_margin   = 40,
 403                 .upper_margin   = 21,
 404                 .lower_margin   = 7,
 405                 .hsync_len      = 60,
 406                 .vsync_len      = 10,
 407                 .sync           = FB_SYNC_EXT,
 408                 .vmode          = FB_VMODE_NONINTERLACED
 409 } }, {
 410         /* DLC800FIG-T-3 */
 411         .bus    = 2,
 412         .addr   = 0x14,
 413         .detect = NULL,
 414         .enable = enable_lvds,
 415         .pixfmt = IPU_PIX_FMT_LVDS666,
 416         .mode   = {
 417                 .name           = "DLC800FIGT3",
 418                 .refresh        = 60,
 419                 .xres           = 1024,         /* 1024x768 active pixels */
 420                 .yres           = 768,
 421                 .pixclock       = 15385,        /* 64MHz */
 422                 .left_margin    = 220,
 423                 .right_margin   = 40,
 424                 .upper_margin   = 21,
 425                 .lower_margin   = 7,
 426                 .hsync_len      = 60,
 427                 .vsync_len      = 10,
 428                 .sync           = FB_SYNC_EXT,
 429                 .vmode          = FB_VMODE_NONINTERLACED
 430 } }, {
 431         .bus    = 2,
 432         .addr   = 0x5d,
 433         .detect = detect_i2c,
 434         .enable = enable_lvds,
 435         .pixfmt = IPU_PIX_FMT_LVDS666,
 436         .mode   = {
 437                 .name           = "Z101WX01",
 438                 .refresh        = 60,
 439                 .xres           = 1280,
 440                 .yres           = 800,
 441                 .pixclock       = 15385,        /* 64MHz */
 442                 .left_margin    = 220,
 443                 .right_margin   = 40,
 444                 .upper_margin   = 21,
 445                 .lower_margin   = 7,
 446                 .hsync_len      = 60,
 447                 .vsync_len      = 10,
 448                 .sync           = FB_SYNC_EXT,
 449                 .vmode          = FB_VMODE_NONINTERLACED
 450         }
 451 },
 452 };
 453 size_t display_count = ARRAY_SIZE(displays);
 454
 455 static void setup_display(void)
 456 {
 457         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 458         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 459         int reg;
 460
 461         enable_ipu_clock();
 462         imx_setup_hdmi();
 463         /* Turn on LDB0,IPU,IPU DI0 clocks */
 464         reg = __raw_readl(&mxc_ccm->CCGR3);
 465         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 466         writel(reg, &mxc_ccm->CCGR3);
 467
 468         /* set LDB0, LDB1 clk select to 011/011 */
 469         reg = readl(&mxc_ccm->cs2cdr);
 470         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 471                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 472         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 473               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 474         writel(reg, &mxc_ccm->cs2cdr);
 475
 476         reg = readl(&mxc_ccm->cscmr2);
 477         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 478         writel(reg, &mxc_ccm->cscmr2);
 479
 480         reg = readl(&mxc_ccm->chsccdr);
 481         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 482                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 483         writel(reg, &mxc_ccm->chsccdr);
 484
 485         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 486              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 487              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 488              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 489              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 490              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 491              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 492              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 493              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 494         writel(reg, &iomux->gpr[2]);
 495
 496         reg = readl(&iomux->gpr[3]);
 497         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 498             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 499                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 500         writel(reg, &iomux->gpr[3]);
 501
 502         /* LVDS Backlight GPIO on LVDS connector - output low */
 503         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
 504         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 505 }
 506 #endif /* CONFIG_VIDEO_IPUV3 */
 507
 508 /* setup board specific PMIC */
 509 int power_init_board(void)
 510 {
 511         setup_pmic();
 512         return 0;
 513 }
 514
 515 #if defined(CONFIG_CMD_PCI)
 516 int imx6_pcie_toggle_reset(void)
 517 {
 518         if (board_type < GW_UNKNOWN) {
 519                 uint pin = gpio_cfg[board_type].pcie_rst;
 520                 gpio_request(pin, "pci_rst#");
 521                 gpio_direction_output(pin, 0);
 522                 mdelay(50);
 523                 gpio_direction_output(pin, 1);
 524         }
 525         return 0;
 526 }
 527
 528 /*
 529  * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
 530  * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
 531  * properly and assert reset for 100ms.
 532  */
 533 #define MAX_PCI_DEVS    32
 534 struct pci_dev {
 535         pci_dev_t devfn;
 536         unsigned short vendor;
 537         unsigned short device;
 538         unsigned short class;
 539         unsigned short busno; /* subbordinate busno */
 540         struct pci_dev *ppar;
 541 };
 542 struct pci_dev pci_devs[MAX_PCI_DEVS];
 543 int pci_devno;
 544 int pci_bridgeno;
 545
 546 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
 547                          unsigned short vendor, unsigned short device,
 548                          unsigned short class)
 549 {
 550         int i;
 551         u32 dw;
 552         struct pci_dev *pdev = &pci_devs[pci_devno++];
 553
 554         debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
 555               PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
 556
 557         /* store array of devs for later use in device-tree fixup */
 558         pdev->devfn = dev;
 559         pdev->vendor = vendor;
 560         pdev->device = device;
 561         pdev->class = class;
 562         pdev->ppar = NULL;
 563         if (class == PCI_CLASS_BRIDGE_PCI)
 564                 pdev->busno = ++pci_bridgeno;
 565         else
 566                 pdev->busno = 0;
 567
 568         /* fixup RC - it should be 00:00.0 not 00:01.0 */
 569         if (PCI_BUS(dev) == 0)
 570                 pdev->devfn = 0;
 571
 572         /* find dev's parent */
 573         for (i = 0; i < pci_devno; i++) {
 574                 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
 575                         pdev->ppar = &pci_devs[i];
 576                         break;
 577                 }
 578         }
 579
 580         /* assert downstream PERST# */
 581         if (vendor == PCI_VENDOR_ID_PLX &&
 582             (device & 0xfff0) == 0x8600 &&
 583             PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
 584                 debug("configuring PLX 860X downstream PERST#\n");
 585                 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
 586                 dw |= 0xaaa8; /* GPIO1-7 outputs */
 587                 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
 588
 589                 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
 590                 dw |= 0xfe;   /* GPIO1-7 output high */
 591                 pci_hose_write_config_dword(hose, dev, 0x644, dw);
 592
 593                 mdelay(100);
 594         }
 595 }
 596 #endif /* CONFIG_CMD_PCI */
 597
 598 #ifdef CONFIG_SERIAL_TAG
 599 /*
 600  * called when setting up ATAGS before booting kernel
 601  * populate serialnum from the following (in order of priority):
 602  *   serial# env var
 603  *   eeprom
 604  */
 605 void get_board_serial(struct tag_serialnr *serialnr)
 606 {
 607         char *serial = env_get("serial#");
 608
 609         if (serial) {
 610                 serialnr->high = 0;
 611                 serialnr->low = simple_strtoul(serial, NULL, 10);
 612         } else if (ventana_info.model[0]) {
 613                 serialnr->high = 0;
 614                 serialnr->low = ventana_info.serial;
 615         } else {
 616                 serialnr->high = 0;
 617                 serialnr->low = 0;
 618         }
 619 }
 620 #endif
 621
 622 /*
 623  * Board Support
 624  */
 625
 626 int board_early_init_f(void)
 627 {
 628         setup_iomux_uart();
 629
 630 #if defined(CONFIG_VIDEO_IPUV3)
 631         setup_display();
 632 #endif
 633         return 0;
 634 }
 635
 636 int dram_init(void)
 637 {
 638         gd->ram_size = imx_ddr_size();
 639         return 0;
 640 }
 641
 642 int board_init(void)
 643 {
 644         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 645
 646         clrsetbits_le32(&iomuxc_regs->gpr[1],
 647                         IOMUXC_GPR1_OTG_ID_MASK,
 648                         IOMUXC_GPR1_OTG_ID_GPIO1);
 649
 650         /* address of linux boot parameters */
 651         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 652
 653         /* read Gateworks EEPROM into global struct (used later) */
 654         setup_ventana_i2c(0);
 655         board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
 656
 657 #ifdef CONFIG_CMD_NAND
 658         if (gpio_cfg[board_type].nand)
 659                 setup_gpmi_nand();
 660 #endif
 661 #ifdef CONFIG_MXC_SPI
 662         setup_spi();
 663 #endif
 664         setup_ventana_i2c(1);
 665         setup_ventana_i2c(2);
 666
 667 #ifdef CONFIG_SATA
 668         setup_sata();
 669 #endif
 670
 671         setup_iomux_gpio(board_type, &ventana_info);
 672
 673         return 0;
 674 }
 675
 676 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
 677 /*
 678  * called during late init (after relocation and after board_init())
 679  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
 680  * EEPROM read.
 681  */
 682 int checkboard(void)
 683 {
 684         struct ventana_board_info *info = &ventana_info;
 685         unsigned char buf[4];
 686         const char *p;
 687         int quiet; /* Quiet or minimal output mode */
 688
 689         quiet = 0;
 690         p = env_get("quiet");
 691         if (p)
 692                 quiet = simple_strtol(p, NULL, 10);
 693         else
 694                 env_set("quiet", "0");
 695
 696         puts("\nGateworks Corporation Copyright 2014\n");
 697         if (info->model[0]) {
 698                 printf("Model: %s\n", info->model);
 699                 printf("MFGDate: %02x-%02x-%02x%02x\n",
 700                        info->mfgdate[0], info->mfgdate[1],
 701                        info->mfgdate[2], info->mfgdate[3]);
 702                 printf("Serial:%d\n", info->serial);
 703         } else {
 704                 puts("Invalid EEPROM - board will not function fully\n");
 705         }
 706         if (quiet)
 707                 return 0;
 708
 709         /* Display GSC firmware revision/CRC/status */
 710         gsc_info(0);
 711
 712         /* Display RTC */
 713         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
 714                 printf("RTC:   %d\n",
 715                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
 716         }
 717
 718         return 0;
 719 }
 720 #endif
 721
 722 #ifdef CONFIG_CMD_BMODE
 723 /*
 724  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
 725  * see Table 8-11 and Table 5-9
 726  *  BOOT_CFG1[7] = 1 (boot from NAND)
 727  *  BOOT_CFG1[5] = 0 - raw NAND
 728  *  BOOT_CFG1[4] = 0 - default pad settings
 729  *  BOOT_CFG1[3:2] = 00 - devices = 1
 730  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
 731  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
 732  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
 733  *  BOOT_CFG2[0] = 0 - Reset time 12ms
 734  */
 735 static const struct boot_mode board_boot_modes[] = {
 736         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
 737         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 738         { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
 739         { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
 740         { NULL, 0 },
 741 };
 742 #endif
 743
 744 /* late init */
 745 int misc_init_r(void)
 746 {
 747         struct ventana_board_info *info = &ventana_info;
 748         char buf[256];
 749         int i;
 750
 751         /* set env vars based on EEPROM data */
 752         if (ventana_info.model[0]) {
 753                 char str[16], fdt[36];
 754                 char *p;
 755                 const char *cputype = "";
 756
 757                 /*
 758                  * FDT name will be prefixed with CPU type.  Three versions
 759                  * will be created each increasingly generic and bootloader
 760                  * env scripts will try loading each from most specific to
 761                  * least.
 762                  */
 763                 if (is_cpu_type(MXC_CPU_MX6Q) ||
 764                     is_cpu_type(MXC_CPU_MX6D))
 765                         cputype = "imx6q";
 766                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
 767                          is_cpu_type(MXC_CPU_MX6SOLO))
 768                         cputype = "imx6dl";
 769                 env_set("soctype", cputype);
 770                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
 771                         env_set("flash_layout", "large");
 772                 else
 773                         env_set("flash_layout", "normal");
 774                 memset(str, 0, sizeof(str));
 775                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
 776                         str[i] = tolower(info->model[i]);
 777                 env_set("model", str);
 778                 if (!env_get("fdt_file")) {
 779                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 780                         env_set("fdt_file", fdt);
 781                 }
 782                 p = strchr(str, '-');
 783                 if (p) {
 784                         *p++ = 0;
 785
 786                         env_set("model_base", str);
 787                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 788                         env_set("fdt_file1", fdt);
 789                         if (board_type != GW551x &&
 790                             board_type != GW552x &&
 791                             board_type != GW553x &&
 792                             board_type != GW560x)
 793                                 str[4] = 'x';
 794                         str[5] = 'x';
 795                         str[6] = 0;
 796                         sprintf(fdt, "%s-%s.dtb", cputype, str);
 797                         env_set("fdt_file2", fdt);
 798                 }
 799
 800                 /* initialize env from EEPROM */
 801                 if (test_bit(EECONFIG_ETH0, info->config) &&
 802                     !env_get("ethaddr")) {
 803                         eth_env_set_enetaddr("ethaddr", info->mac0);
 804                 }
 805                 if (test_bit(EECONFIG_ETH1, info->config) &&
 806                     !env_get("eth1addr")) {
 807                         eth_env_set_enetaddr("eth1addr", info->mac1);
 808                 }
 809
 810                 /* board serial-number */
 811                 sprintf(str, "%6d", info->serial);
 812                 env_set("serial#", str);
 813
 814                 /* memory MB */
 815                 sprintf(str, "%d", (int) (gd->ram_size >> 20));
 816                 env_set("mem_mb", str);
 817         }
 818
 819         /* Set a non-initialized hwconfig based on board configuration */
 820         if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
 821                 buf[0] = 0;
 822                 if (gpio_cfg[board_type].rs232_en)
 823                         strcat(buf, "rs232;");
 824                 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
 825                         char buf1[32];
 826                         sprintf(buf1, "dio%d:mode=gpio;", i);
 827                         if (strlen(buf) + strlen(buf1) < sizeof(buf))
 828                                 strcat(buf, buf1);
 829                 }
 830                 env_set("hwconfig", buf);
 831         }
 832
 833         /* setup baseboard specific GPIO based on board and env */
 834         setup_board_gpio(board_type, info);
 835
 836 #ifdef CONFIG_CMD_BMODE
 837         add_board_boot_modes(board_boot_modes);
 838 #endif
 839
 840         /* disable boot watchdog */
 841         gsc_boot_wd_disable();
 842
 843         return 0;
 844 }
 845
 846 #ifdef CONFIG_OF_BOARD_SETUP
 847
 848 static int ft_sethdmiinfmt(void *blob, char *mode)
 849 {
 850         int off;
 851
 852         if (!mode)
 853                 return -EINVAL;
 854
 855         off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
 856         if (off < 0)
 857                 return off;
 858
 859         if (0 == strcasecmp(mode, "yuv422bt656")) {
 860                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
 861                              0x00, 0x00, 0x00 };
 862                 mode = "422_ccir";
 863                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 864                 fdt_setprop_u32(blob, off, "vidout_trc", 1);
 865                 fdt_setprop_u32(blob, off, "vidout_blc", 1);
 866                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 867                 printf("   set HDMI input mode to %s\n", mode);
 868         } else if (0 == strcasecmp(mode, "yuv422smp")) {
 869                 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
 870                              0x82, 0x81, 0x00 };
 871                 mode = "422_smp";
 872                 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
 873                 fdt_setprop_u32(blob, off, "vidout_trc", 0);
 874                 fdt_setprop_u32(blob, off, "vidout_blc", 0);
 875                 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
 876                 printf("   set HDMI input mode to %s\n", mode);
 877         } else {
 878                 return -EINVAL;
 879         }
 880
 881         return 0;
 882 }
 883
 884 #if defined(CONFIG_CMD_PCI)
 885 #define PCI_ID(x) ( \
 886         (PCI_BUS(x->devfn)<<16)| \
 887         (PCI_DEV(x->devfn)<<11)| \
 888         (PCI_FUNC(x->devfn)<<8) \
 889         )
 890 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
 891 {
 892         uint32_t reg[5];
 893         char node[32];
 894         int np;
 895
 896         sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
 897                 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
 898
 899         np = fdt_subnode_offset(blob, par, node);
 900         if (np >= 0)
 901                 return np;
 902         np = fdt_add_subnode(blob, par, node);
 903         if (np < 0) {
 904                 printf("   %s failed: no space\n", __func__);
 905                 return np;
 906         }
 907
 908         memset(reg, 0, sizeof(reg));
 909         reg[0] = cpu_to_fdt32(PCI_ID(dev));
 910         fdt_setprop(blob, np, "reg", reg, sizeof(reg));
 911
 912         return np;
 913 }
 914
 915 /* build a path of nested PCI devs for all bridges passed through */
 916 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
 917 {
 918         struct pci_dev *bridges[MAX_PCI_DEVS];
 919         int k, np;
 920
 921         /* build list of parents */
 922         np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
 923         if (np < 0)
 924                 return np;
 925
 926         k = 0;
 927         while (dev) {
 928                 bridges[k++] = dev;
 929                 dev = dev->ppar;
 930         };
 931
 932         /* now add them the to DT in reverse order */
 933         while (k--) {
 934                 np = fdt_add_pci_node(blob, np, bridges[k]);
 935                 if (np < 0)
 936                         break;
 937         }
 938
 939         return np;
 940 }
 941
 942 /*
 943  * The GW16082 has a hardware errata errata such that it's
 944  * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
 945  * of this normal PCI interrupt swizzling will not work so we will
 946  * provide an irq-map via device-tree.
 947  */
 948 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
 949 {
 950         int len;
 951         int host;
 952         uint32_t imap_new[8*4*4];
 953         const uint32_t *imap;
 954         uint32_t irq[4];
 955         uint32_t reg[4];
 956         int i;
 957
 958         /* build irq-map based on host controllers map */
 959         host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
 960         if (host < 0) {
 961                 printf("   %s failed: missing host\n", __func__);
 962                 return host;
 963         }
 964
 965         /* use interrupt data from root complex's node */
 966         imap = fdt_getprop(blob, host, "interrupt-map", &len);
 967         if (!imap || len != 128) {
 968                 printf("   %s failed: invalid interrupt-map\n",
 969                        __func__);
 970                 return -FDT_ERR_NOTFOUND;
 971         }
 972
 973         /* obtain irq's of host controller in pin order */
 974         for (i = 0; i < 4; i++)
 975                 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
 976
 977         /*
 978          * determine number of swizzles necessary:
 979          *   For each bridge we pass through we need to swizzle
 980          *   the number of the slot we are on.
 981          */
 982         struct pci_dev *d;
 983         int b;
 984         b = 0;
 985         d = dev->ppar;
 986         while(d && d->ppar) {
 987                 b += PCI_DEV(d->devfn);
 988                 d = d->ppar;
 989         }
 990
 991         /* create new irq mappings for slots12-15
 992          * <skt> <idsel> <slot> <skt-inta> <skt-intb>
 993          * J3    AD28    12     INTD      INTA
 994          * J4    AD29    13     INTC      INTD
 995          * J5    AD30    14     INTB      INTC
 996          * J2    AD31    15     INTA      INTB
 997          */
 998         for (i = 0; i < 4; i++) {
 999                 /* addr matches bus:dev:func */
1000                 u32 addr = dev->busno << 16 | (12+i) << 11;
1001
1002                 /* default cells from root complex */
1003                 memcpy(&imap_new[i*32], imap, 128);
1004                 /* first cell is PCI device address (BDF) */
1005                 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
1006                 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1007                 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1008                 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1009                 /* third cell is pin */
1010                 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1011                 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1012                 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1013                 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1014                 /* sixth cell is relative interrupt */
1015                 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1016                 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1017                 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1018                 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1019         }
1020         fdt_setprop(blob, np, "interrupt-map", imap_new,
1021                     sizeof(imap_new));
1022         reg[0] = cpu_to_fdt32(0xfff00);
1023         reg[1] = 0;
1024         reg[2] = 0;
1025         reg[3] = cpu_to_fdt32(0x7);
1026         fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1027         fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1028         fdt_setprop_string(blob, np, "device_type", "pci");
1029         fdt_setprop_cell(blob, np, "#address-cells", 3);
1030         fdt_setprop_cell(blob, np, "#size-cells", 2);
1031         printf("   Added custom interrupt-map for GW16082\n");
1032
1033         return 0;
1034 }
1035
1036 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
1037 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1038 {
1039         char *tmp, *end;
1040         char mac[16];
1041         unsigned char mac_addr[6];
1042         int j;
1043
1044         sprintf(mac, "eth1addr");
1045         tmp = env_get(mac);
1046         if (tmp) {
1047                 for (j = 0; j < 6; j++) {
1048                         mac_addr[j] = tmp ?
1049                                       simple_strtoul(tmp, &end,16) : 0;
1050                         if (tmp)
1051                                 tmp = (*end) ? end+1 : end;
1052                 }
1053                 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1054                             sizeof(mac_addr));
1055                 printf("   Added mac addr for eth1\n");
1056                 return 0;
1057         }
1058
1059         return -1;
1060 }
1061
1062 /*
1063  * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1064  * we will walk the PCI bus and add bridge nodes up to the device receiving
1065  * the fixup.
1066  */
1067 void ft_board_pci_fixup(void *blob, bd_t *bd)
1068 {
1069         int i, np;
1070         struct pci_dev *dev;
1071
1072         for (i = 0; i < pci_devno; i++) {
1073                 dev = &pci_devs[i];
1074
1075                 /*
1076                  * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1077                  * an EEPROM at i2c1-0x50.
1078                  */
1079                 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1080                     (dev->device == 0x8240) &&
1081                     (i2c_set_bus_num(1) == 0) &&
1082                     (i2c_probe(0x50) == 0))
1083                 {
1084                         np = fdt_add_pci_path(blob, dev);
1085                         if (np > 0)
1086                                 fdt_fixup_gw16082(blob, np, dev);
1087                 }
1088
1089                 /* ethernet1 mac address */
1090                 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1091                          (dev->device == 0x4380))
1092                 {
1093                         np = fdt_add_pci_path(blob, dev);
1094                         if (np > 0)
1095                                 fdt_fixup_sky2(blob, np, dev);
1096                 }
1097         }
1098 }
1099 #endif /* if defined(CONFIG_CMD_PCI) */
1100
1101 void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
1102 {
1103         int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1104
1105         if (off) {
1106                 fdt_delprop(blob, off, "ext-reset-output");
1107                 fdt_delprop(blob, off, "fsl,ext-reset-output");
1108         }
1109 }
1110
1111 /*
1112  * called prior to booting kernel or by 'fdt boardsetup' command
1113  *
1114  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1115  *  - mtd partitions based on mtdparts/mtdids env
1116  *  - system-serial (board serial num from EEPROM)
1117  *  - board (full model from EEPROM)
1118  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1119  */
1120 #define WDOG1_ADDR      0x20bc000
1121 #define WDOG2_ADDR      0x20c0000
1122 #define GPIO3_ADDR      0x20a4000
1123 #define USDHC3_ADDR     0x2198000
1124 #define PWM0_ADDR       0x2080000
1125 int ft_board_setup(void *blob, bd_t *bd)
1126 {
1127         struct ventana_board_info *info = &ventana_info;
1128         struct ventana_eeprom_config *cfg;
1129         static const struct node_info nodes[] = {
1130                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1131                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1132         };
1133         const char *model = env_get("model");
1134         const char *display = env_get("display");
1135         int i;
1136         char rev = 0;
1137
1138         /* determine board revision */
1139         for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1140                 if (ventana_info.model[i] >= 'A') {
1141                         rev = ventana_info.model[i];
1142                         break;
1143                 }
1144         }
1145
1146         if (env_get("fdt_noauto")) {
1147                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1148                 return 0;
1149         }
1150
1151         if (test_bit(EECONFIG_NAND, info->config)) {
1152                 /* Update partition nodes using info from mtdparts env var */
1153                 puts("   Updating MTD partitions...\n");
1154                 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1155         }
1156
1157         /* Update display timings from display env var */
1158         if (display) {
1159                 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1160                                       display) >= 0)
1161                         printf("   Set display timings for %s...\n", display);
1162         }
1163
1164         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1165
1166         /* board serial number */
1167         fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1168                     strlen(env_get("serial#")) + 1);
1169
1170         /* board (model contains model from device-tree) */
1171         fdt_setprop(blob, 0, "board", info->model,
1172                     strlen((const char *)info->model) + 1);
1173
1174         /* set desired digital video capture format */
1175         ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1176
1177         /*
1178          * Board model specific fixups
1179          */
1180         switch (board_type) {
1181         case GW51xx:
1182                 /*
1183                  * disable wdog node for GW51xx-A/B to work around
1184                  * errata causing wdog timer to be unreliable.
1185                  */
1186                 if (rev >= 'A' && rev < 'C') {
1187                         i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1188                                                           WDOG1_ADDR);
1189                         if (i)
1190                                 fdt_status_disabled(blob, i);
1191                 }
1192
1193                 /* GW51xx-E adds WDOG1_B external reset */
1194                 if (rev < 'E')
1195                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1196                 break;
1197
1198         case GW52xx:
1199                 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1200                 if (info->model[4] == '2') {
1201                         u32 handle = 0;
1202                         u32 *range = NULL;
1203
1204                         i = fdt_node_offset_by_compatible(blob, -1,
1205                                                           "fsl,imx6q-pcie");
1206                         if (i)
1207                                 range = (u32 *)fdt_getprop(blob, i,
1208                                                            "reset-gpio", NULL);
1209
1210                         if (range) {
1211                                 i = fdt_node_offset_by_compat_reg(blob,
1212                                         "fsl,imx6q-gpio", GPIO3_ADDR);
1213                                 if (i)
1214                                         handle = fdt_get_phandle(blob, i);
1215                                 if (handle) {
1216                                         range[0] = cpu_to_fdt32(handle);
1217                                         range[1] = cpu_to_fdt32(23);
1218                                 }
1219                         }
1220
1221                         /* these have broken usd_vsel */
1222                         if (strstr((const char *)info->model, "SP318-B") ||
1223                             strstr((const char *)info->model, "SP331-B"))
1224                                 gpio_cfg[board_type].usd_vsel = 0;
1225
1226                         /* GW522x-B adds WDOG1_B external reset */
1227                         if (rev < 'B')
1228                                 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1229                 }
1230
1231                 /* GW520x-E adds WDOG1_B external reset */
1232                 else if (info->model[4] == '0' && rev < 'E')
1233                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1234                 break;
1235
1236         case GW53xx:
1237                 /* GW53xx-E adds WDOG1_B external reset */
1238                 if (rev < 'E')
1239                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1240                 break;
1241
1242         case GW54xx:
1243                 /*
1244                  * disable serial2 node for GW54xx for compatibility with older
1245                  * 3.10.x kernel that improperly had this node enabled in the DT
1246                  */
1247                 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
1248                                         0);
1249
1250                 /* GW54xx-E adds WDOG2_B external reset */
1251                 if (rev < 'E')
1252                         ft_board_wdog_fixup(blob, WDOG2_ADDR);
1253                 break;
1254
1255         case GW551x:
1256                 /*
1257                  * isolate CSI0_DATA_EN for GW551x-A to work around errata
1258                  * causing non functional digital video in (it is not hooked up)
1259                  */
1260                 if (rev == 'A') {
1261                         u32 *range = NULL;
1262                         int len;
1263                         const u32 *handle = NULL;
1264
1265                         i = fdt_node_offset_by_compatible(blob, -1,
1266                                                 "fsl,imx-tda1997x-video");
1267                         if (i)
1268                                 handle = fdt_getprop(blob, i, "pinctrl-0",
1269                                                      NULL);
1270                         if (handle)
1271                                 i = fdt_node_offset_by_phandle(blob,
1272                                                         fdt32_to_cpu(*handle));
1273                         if (i)
1274                                 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1275                                                            &len);
1276                         if (range) {
1277                                 len /= sizeof(u32);
1278                                 for (i = 0; i < len; i += 6) {
1279                                         u32 mux_reg = fdt32_to_cpu(range[i+0]);
1280                                         u32 conf_reg = fdt32_to_cpu(range[i+1]);
1281                                         /* mux PAD_CSI0_DATA_EN to GPIO */
1282                                         if (is_cpu_type(MXC_CPU_MX6Q) &&
1283                                             mux_reg == 0x260 &&
1284                                             conf_reg == 0x630)
1285                                                 range[i+3] = cpu_to_fdt32(0x5);
1286                                         else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1287                                                  mux_reg == 0x08c &&
1288                                                  conf_reg == 0x3a0)
1289                                                 range[i+3] = cpu_to_fdt32(0x5);
1290                                 }
1291                                 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1292                                                     len);
1293                         }
1294
1295                         /* set BT656 video format */
1296                         ft_sethdmiinfmt(blob, "yuv422bt656");
1297                 }
1298
1299                 /* GW551x-C adds WDOG1_B external reset */
1300                 if (rev < 'C')
1301                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1302                 break;
1303         case GW5901:
1304         case GW5902:
1305                 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1306                 if (rev < 'B')
1307                         ft_board_wdog_fixup(blob, WDOG1_ADDR);
1308                 break;
1309         }
1310
1311         /* Configure DIO */
1312         for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1313                 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1314                 char arg[10];
1315
1316                 sprintf(arg, "dio%d", i);
1317                 if (!hwconfig(arg))
1318                         continue;
1319                 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1320                 {
1321                         phys_addr_t addr;
1322                         int off;
1323
1324                         printf("   Enabling pwm%d for DIO%d\n",
1325                                cfg->pwm_param, i);
1326                         addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1327                         off = fdt_node_offset_by_compat_reg(blob,
1328                                                             "fsl,imx6q-pwm",
1329                                                             addr);
1330                         if (off)
1331                                 fdt_status_okay(blob, off);
1332                 }
1333         }
1334
1335         /* remove no-1-8-v if UHS-I support is present */
1336         if (gpio_cfg[board_type].usd_vsel) {
1337                 debug("Enabling UHS-I support\n");
1338                 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1339                                                   USDHC3_ADDR);
1340                 if (i)
1341                         fdt_delprop(blob, i, "no-1-8-v");
1342         }
1343
1344 #if defined(CONFIG_CMD_PCI)
1345         if (!env_get("nopcifixup"))
1346                 ft_board_pci_fixup(blob, bd);
1347 #endif
1348
1349         /*
1350          * Peripheral Config:
1351          *  remove nodes by alias path if EEPROM config tells us the
1352          *  peripheral is not loaded on the board.
1353          */
1354         if (env_get("fdt_noconfig")) {
1355                 puts("   Skiping periperhal config (fdt_noconfig defined)\n");
1356                 return 0;
1357         }
1358         cfg = econfig;
1359         while (cfg->name) {
1360                 if (!test_bit(cfg->bit, info->config)) {
1361                         fdt_del_node_and_alias(blob, cfg->dtalias ?
1362                                                cfg->dtalias : cfg->name);
1363                 }
1364                 cfg++;
1365         }
1366
1367         return 0;
1368 }
1369 #endif /* CONFIG_OF_BOARD_SETUP */
1370
1371 static struct mxc_serial_platdata ventana_mxc_serial_plat = {
1372         .reg = (struct mxc_uart *)UART2_BASE,
1373 };
1374
1375 U_BOOT_DEVICE(ventana_serial) = {
1376         .name   = "serial_mxc",
1377         .platdata = &ventana_mxc_serial_plat,
1378 };